ES2046987T3 - Circuito integrado con autoverificacion de memoria. - Google Patents

Circuito integrado con autoverificacion de memoria.

Info

Publication number
ES2046987T3
ES2046987T3 ES87308454T ES87308454T ES2046987T3 ES 2046987 T3 ES2046987 T3 ES 2046987T3 ES 87308454 T ES87308454 T ES 87308454T ES 87308454 T ES87308454 T ES 87308454T ES 2046987 T3 ES2046987 T3 ES 2046987T3
Authority
ES
Spain
Prior art keywords
test
memory
integrated circuit
verification
self
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
ES87308454T
Other languages
English (en)
Inventor
Duane Rodney Aadsen
Sunil Kumar Jain
Charles Eugene Stroud
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
AT&T Corp
Original Assignee
American Telephone and Telegraph Co Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by American Telephone and Telegraph Co Inc filed Critical American Telephone and Telegraph Co Inc
Application granted granted Critical
Publication of ES2046987T3 publication Critical patent/ES2046987T3/es
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/10—Test algorithms, e.g. memory scan [MScan] algorithms; Test patterns, e.g. checkerboard patterns 

Landscapes

  • For Increasing The Reliability Of Semiconductor Memories (AREA)
  • Tests Of Electronic Circuits (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
  • Test And Diagnosis Of Digital Computers (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Semiconductor Memories (AREA)

Abstract

UNA SERIE DE MEMORIA INCLUIDA CON CIRCUITERIA LOGICA EN UN CIRCUITO INTEGRADO ES VERIFCADA POR UNA TECNIDCA QUE LEE Y ESCRIBE UNA SECUENCIA ESPECIFICADA DE BITS, DE TEST DENTRO DE UNA PALABRA DE MEMORIA DADA, ANTES DE PASAR A LA SIGUIENTE PALABRA. UN MODELO O PLANTILLA DE TARJETA DE CHEQUEO DE UNOS Y CEROS ES ESCRITA DENTRO DE LOCALIZACIONES FISICAS DE MEMORIA. ESO PROPORCIONA PARA EL PEOR DE LOS CASOS UN TEST MIENTRAS SE PERMITE FACIL IMPLANTACION DE LA CIRCUITERIA DEL TEST. RESULTADO DEL TEST DESDE UN CIRCUITO COMPARADOR PUEDE SER COMPRIMIDO PARA PROPORCIONAR UNAS POCAS SEÑALES DE ENSAYO, INDICANDO SI LA MEMORIA HA PASADO EL TEST, REQUIRIENDO UN NUMERO MINIMO DE TERMINALES PARA EL CHIP.
ES87308454T 1986-10-02 1987-09-24 Circuito integrado con autoverificacion de memoria. Expired - Lifetime ES2046987T3 (es)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US06/914,411 US4872168A (en) 1986-10-02 1986-10-02 Integrated circuit with memory self-test
SG21994A SG21994G (en) 1986-10-02 1994-02-07 Integrated circuit with memory self-test

Publications (1)

Publication Number Publication Date
ES2046987T3 true ES2046987T3 (es) 1994-02-16

Family

ID=26663870

Family Applications (1)

Application Number Title Priority Date Filing Date
ES87308454T Expired - Lifetime ES2046987T3 (es) 1986-10-02 1987-09-24 Circuito integrado con autoverificacion de memoria.

Country Status (7)

Country Link
US (1) US4872168A (es)
EP (1) EP0262867B1 (es)
JP (1) JPS63102098A (es)
DE (1) DE3788487T2 (es)
ES (1) ES2046987T3 (es)
HK (1) HK108294A (es)
SG (1) SG21994G (es)

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TW211094B (en) * 1992-04-30 1993-08-11 American Telephone & Telegraph Built-in self-test network
EP0573179A3 (en) * 1992-06-02 1996-06-05 American Telephone & Telegraph Non-fully-decoded test address generator
JP2768175B2 (ja) * 1992-10-26 1998-06-25 日本電気株式会社 半導体メモリ
JPH06242181A (ja) * 1992-11-23 1994-09-02 Texas Instr Inc <Ti> 集積回路の試験装置及び方法
US5442640A (en) * 1993-01-19 1995-08-15 International Business Machines Corporation Test and diagnosis of associated output logic for products having embedded arrays
US5375091A (en) * 1993-12-08 1994-12-20 International Business Machines Corporation Method and apparatus for memory dynamic burn-in and test
FR2718559B1 (fr) * 1994-04-08 1996-06-07 Sgs Thomson Microelectronics Mémoire non volatile modifiable électriquement incorporant des fonctions de test.
US5561765A (en) * 1994-07-27 1996-10-01 Siemens Rolm Communications, Inc. Algorithm for testing a memory
US5506959A (en) * 1994-08-04 1996-04-09 Telecommunication Research Laboratories Method and apparatus for testing electronic memories for the presence of multiple cell coupling faults
JP3301874B2 (ja) * 1994-12-19 2002-07-15 松下電器産業株式会社 半導体装置及びその検査方法
KR100234504B1 (ko) * 1995-09-18 1999-12-15 포만 제프리 엘 선택된 고장에 대한 고장정보를 포착하는 집적회로의 테스트 방법 및 내장된 자기 테스트 장치
JP3207727B2 (ja) * 1995-10-03 2001-09-10 株式会社東芝 半導体集積回路およびその応用装置
US5732047A (en) * 1995-12-12 1998-03-24 Advantest Corporation Timing comparator circuit for use in device testing apparatus
US5898701A (en) * 1995-12-21 1999-04-27 Cypress Semiconductor Corporation Method and apparatus for testing a device
US5825782A (en) * 1996-01-22 1998-10-20 Micron Technology, Inc. Non-volatile memory system including apparatus for testing memory elements by writing and verifying data patterns
JP3106947B2 (ja) * 1996-02-28 2000-11-06 日本電気株式会社 不揮発性半導体記憶装置
US5815510A (en) * 1996-03-28 1998-09-29 Cypress Semiconductor Corp. Serial programming of instruction codes in different numbers of clock cycles
US5768288A (en) * 1996-03-28 1998-06-16 Cypress Semiconductor Corp. Method and apparatus for programming a programmable logic device having verify logic for comparing verify data read from a memory location with program data
US5835503A (en) * 1996-03-28 1998-11-10 Cypress Semiconductor Corp. Method and apparatus for serially programming a programmable logic device
US5831988A (en) * 1997-01-23 1998-11-03 Unisys Corporation Fault isolating to a block of ROM
US5996106A (en) 1997-02-04 1999-11-30 Micron Technology, Inc. Multi bank test mode for memory devices
US5913928A (en) * 1997-05-09 1999-06-22 Micron Technology, Inc. Data compression test mode independent of redundancy
KR100468675B1 (ko) * 1997-07-25 2005-03-16 삼성전자주식회사 스태틱램자기테스트회로의어드레스발생기및어드레스발생방법
JP2000021193A (ja) * 1998-07-01 2000-01-21 Fujitsu Ltd メモリ試験方法及び装置並びに記憶媒体
US6233184B1 (en) 1998-11-13 2001-05-15 International Business Machines Corporation Structures for wafer level test and burn-in
FI109162B (fi) * 2000-06-30 2002-05-31 Nokia Corp Menetelmä ja järjestely konvoluutiokoodatun koodisanan dekoodaamiseksi
DE10041137A1 (de) * 2000-08-21 2002-03-21 Philips Corp Intellectual Pty Anordnung zum Testen von integrierten Schaltkreisen
US7978219B1 (en) 2000-08-30 2011-07-12 Kevin Reid Imes Device, network, server, and methods for providing digital images and associated processing information
US8326352B1 (en) 2000-09-06 2012-12-04 Kevin Reid Imes Device, network, server, and methods for providing service requests for wireless communication devices
ITRM20010104A1 (it) * 2001-02-27 2002-08-27 Micron Technology Inc Modo di lettura a compressione di dati per il collaudo di memorie.
US20020184557A1 (en) * 2001-04-25 2002-12-05 Hughes Brian William System and method for memory segment relocation
DE602004020887D1 (de) * 2003-05-22 2009-06-10 Nxp Bv Test von ram addressdekodierern auf widerstandsbehaftete leiterunterbrechungen
ITRM20040418A1 (it) * 2004-08-25 2004-11-25 Micron Technology Inc Modo di lettura a compressione di dati a piu' livelli per il collaudo di memorie.
US8166459B2 (en) * 2008-02-27 2012-04-24 Sap Ag Apparatus and method of generating self-debugging computer software
US10061672B2 (en) * 2013-03-07 2018-08-28 International Business Machines Corporation Implementing random content of program loops in random test generation for processor verification
JP6697993B2 (ja) * 2016-09-29 2020-05-27 ルネサスエレクトロニクス株式会社 半導体装置及び半導体装置の診断方法

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JPS58220296A (ja) * 1982-06-15 1983-12-21 Nec Corp スタテイツクｒａｍ制御方式
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EP0103654B1 (de) * 1982-09-22 1987-05-20 Deutsche ITT Industries GmbH Elektrisch programmierbare Speichermatrix
US4488300A (en) * 1982-12-01 1984-12-11 The Singer Company Method of checking the integrity of a source of additional memory for use in an electronically controlled sewing machine
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JPS61145799A (ja) * 1984-12-20 1986-07-03 Fujitsu Ltd メモリを内蔵した半導体集積回路

Also Published As

Publication number Publication date
EP0262867A3 (en) 1991-03-20
EP0262867B1 (en) 1993-12-15
US4872168A (en) 1989-10-03
EP0262867A2 (en) 1988-04-06
HK108294A (en) 1994-10-14
SG21994G (en) 1995-03-17
DE3788487D1 (de) 1994-01-27
JPS63102098A (ja) 1988-05-06
DE3788487T2 (de) 1994-06-23

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