ES2026924T3 - Procedimiento de memorizacion de un bit de informacion de una celda de memoria viva estatica del tipo mos y su correspondiente memoria. - Google Patents
Procedimiento de memorizacion de un bit de informacion de una celda de memoria viva estatica del tipo mos y su correspondiente memoria.Info
- Publication number
- ES2026924T3 ES2026924T3 ES198787401534T ES87401534T ES2026924T3 ES 2026924 T3 ES2026924 T3 ES 2026924T3 ES 198787401534 T ES198787401534 T ES 198787401534T ES 87401534 T ES87401534 T ES 87401534T ES 2026924 T3 ES2026924 T3 ES 2026924T3
- Authority
- ES
- Spain
- Prior art keywords
- procedure
- memorization
- memory cell
- information bit
- mos type
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 230000003068 static effect Effects 0.000 title abstract 2
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1025—Channel region of field-effect devices
- H01L29/1029—Channel region of field-effect devices of field-effect transistors
- H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/39—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using thyristors or the avalanche or negative resistance type, e.g. PNPN, SCR, SCS, UJT
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Semiconductor Memories (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Static Random-Access Memory (AREA)
Abstract
PROCEDIMIENTO DE MEMORIZACION DE UN BIT DE INFORMACION EN UNA CELULA DE MEMORIA ACTIVA INTEGRADA DE TIPO MOS, TRANSISTOR PARA LA EJECUCION DE TAL PROCEDIMIENTO Y MEMORIA RESULTANTE. UN TRANSISTOR MOS QUE PRESENTA UN FENOMENO DE ISTERESIS EN REGIMEN DE CONDUCCION BAJO LA SEÑAL. ESTE TRANSISTOR ES VENTAJOSAMENTE UTILIZADO COMO ELEMENTO DE MEMORIA EN UNA CELULA DE MEMORIA ACTIVA ESTATICA INTEGRADA.
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
FR8611029A FR2602367B1 (fr) | 1986-07-30 | 1986-07-30 | Procede de memorisation d'un bit d'information dans une cellule de memoire vive statique integree du type mos, transistor pour la mise en oeuvre du procede et memoire en resultant |
Publications (1)
Publication Number | Publication Date |
---|---|
ES2026924T3 true ES2026924T3 (es) | 1992-05-16 |
Family
ID=9337874
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
ES198787401534T Expired - Lifetime ES2026924T3 (es) | 1986-07-30 | 1987-07-01 | Procedimiento de memorizacion de un bit de informacion de una celda de memoria viva estatica del tipo mos y su correspondiente memoria. |
Country Status (6)
Country | Link |
---|---|
US (1) | US4843442A (es) |
EP (1) | EP0258075B1 (es) |
JP (1) | JPS6342094A (es) |
DE (1) | DE3773304D1 (es) |
ES (1) | ES2026924T3 (es) |
FR (1) | FR2602367B1 (es) |
Families Citing this family (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH03110253U (es) * | 1990-02-28 | 1991-11-12 | ||
US5863823A (en) * | 1993-07-12 | 1999-01-26 | Peregrine Semiconductor Corporation | Self-aligned edge control in silicon on insulator |
US5930638A (en) * | 1993-07-12 | 1999-07-27 | Peregrine Semiconductor Corp. | Method of making a low parasitic resistor on ultrathin silicon on insulator |
US5864162A (en) * | 1993-07-12 | 1999-01-26 | Peregrine Seimconductor Corporation | Apparatus and method of making a self-aligned integrated resistor load on ultrathin silicon on sapphire |
EP2075798A1 (en) * | 2007-12-25 | 2009-07-01 | TPO Displays Corp. | Storage data unit using hot carrier stressing |
Family Cites Families (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3733591A (en) * | 1970-06-24 | 1973-05-15 | Westinghouse Electric Corp | Non-volatile memory element |
US3974486A (en) * | 1975-04-07 | 1976-08-10 | International Business Machines Corporation | Multiplication mode bistable field effect transistor and memory utilizing same |
US4142111A (en) * | 1977-01-27 | 1979-02-27 | Texas Instruments Incorporated | One-transistor fully static semiconductor memory cell |
-
1986
- 1986-07-30 FR FR8611029A patent/FR2602367B1/fr not_active Expired
-
1987
- 1987-07-01 EP EP87401534A patent/EP0258075B1/fr not_active Expired - Lifetime
- 1987-07-01 DE DE8787401534T patent/DE3773304D1/de not_active Expired - Fee Related
- 1987-07-01 ES ES198787401534T patent/ES2026924T3/es not_active Expired - Lifetime
- 1987-07-29 US US07/079,040 patent/US4843442A/en not_active Expired - Fee Related
- 1987-07-30 JP JP62191509A patent/JPS6342094A/ja active Pending
Also Published As
Publication number | Publication date |
---|---|
EP0258075A1 (fr) | 1988-03-02 |
FR2602367A1 (fr) | 1988-02-05 |
EP0258075B1 (fr) | 1991-09-25 |
DE3773304D1 (de) | 1991-10-31 |
JPS6342094A (ja) | 1988-02-23 |
US4843442A (en) | 1989-06-27 |
FR2602367B1 (fr) | 1988-10-07 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
KR910005321A (ko) | 반도체 기억장치 | |
KR890001090A (ko) | 메모리 집적회로 | |
KR910010519A (ko) | 반도체 메모리 회로장치 | |
KR910003670A (ko) | 정적형 반도체 기억장치 | |
KR910013266A (ko) | 반도체 메모리 어레이의 구성방법 | |
KR890017706A (ko) | 다이나믹형 반도체 기억장치 | |
KR920015370A (ko) | 반도체 기억장치 | |
KR950009279A (ko) | 메모리 시험을 실시하는 반도체 메모리 장치 | |
BR7301488D0 (pt) | Para verificar vasamentos processo e aparelho para tester dispositivos com membrana | |
KR870011618A (ko) | 고속으로 데이타의 소거가 가능한 다이나믹 ram | |
ES2026924T3 (es) | Procedimiento de memorizacion de un bit de informacion de una celda de memoria viva estatica del tipo mos y su correspondiente memoria. | |
KR870008320A (ko) | 상이형 메모리셀로 구성되는 반도체 메모리장치 | |
KR880000960A (ko) | 반도체 메모리 | |
GB1509633A (en) | Memory device | |
KR860006790A (ko) | 반도체 기억장치 | |
ES395249A1 (es) | Un sistema de memoria de acceso al azar. | |
KR900019013A (ko) | 파셜 랜덤 액세스 메모리 | |
KR900002305A (ko) | 반도체 기억장치 | |
KR870009388A (ko) | 스태틱 반도체 기억장치 | |
KR900019047A (ko) | 반도체 기억장치 | |
JPS533747A (en) | Self-refresh dynamic memory circuit | |
JPS52149927A (en) | Beam addressable information memory unit | |
NO136237C (no) | Pastaer som inneholder syrer, aminer og fosforsyreestere. | |
KR880014569A (ko) | 반도체 기억장치 | |
ES2039251T3 (es) | Tratamiento del cabello. |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
FG2A | Definitive protection |
Ref document number: 258075 Country of ref document: ES |