EP4031489A1 - Bauelement zum initialisieren eines quantenpunkts - Google Patents

Bauelement zum initialisieren eines quantenpunkts

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Publication number
EP4031489A1
EP4031489A1 EP20792280.8A EP20792280A EP4031489A1 EP 4031489 A1 EP4031489 A1 EP 4031489A1 EP 20792280 A EP20792280 A EP 20792280A EP 4031489 A1 EP4031489 A1 EP 4031489A1
Authority
EP
European Patent Office
Prior art keywords
potential well
electronic component
gate electrode
quantum
static
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
EP20792280.8A
Other languages
German (de)
English (en)
French (fr)
Inventor
Matthias KÜNNE
Hendrik BLUHM
Lars SCHREIBER
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Forschungszentrum Juelich GmbH
Rheinisch Westlische Technische Hochschuke RWTH
Original Assignee
Forschungszentrum Juelich GmbH
Rheinisch Westlische Technische Hochschuke RWTH
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Forschungszentrum Juelich GmbH, Rheinisch Westlische Technische Hochschuke RWTH filed Critical Forschungszentrum Juelich GmbH
Publication of EP4031489A1 publication Critical patent/EP4031489A1/de
Pending legal-status Critical Current

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Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/778Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14Handling requests for interconnection or transfer
    • G06F13/20Handling requests for interconnection or transfer for access to input/output bus
    • BPERFORMING OPERATIONS; TRANSPORTING
    • B82NANOTECHNOLOGY
    • B82YSPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
    • B82Y10/00Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06NCOMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N10/00Quantum computing, i.e. information processing based on quantum-mechanical phenomena
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06NCOMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N10/00Quantum computing, i.e. information processing based on quantum-mechanical phenomena
    • G06N10/40Physical realisations or architectures of quantum processors or components for manipulating qubits, e.g. qubit coupling or qubit control
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/20Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
    • H01L29/201Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds including two or more compounds, e.g. alloys
    • H01L29/205Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds including two or more compounds, e.g. alloys in different semiconductor regions, e.g. heterojunctions
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40Electrodes ; Multistep manufacturing processes therefor
    • H01L29/401Multistep manufacturing processes
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312Gate electrodes for field effect devices
    • H01L29/42316Gate electrodes for field effect devices for field-effect transistors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66977Quantum effect devices, e.g. using quantum reflection, diffraction or interference effects, i.e. Bragg- or Aharonov-Bohm effects
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/7613Single electron transistors; Coulomb blockade devices
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K17/00Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/51Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
    • H03K17/92Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of superconductive devices
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10NELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N60/00Superconducting devices
    • H10N60/10Junction-based devices
    • H10N60/11Single-electron tunnelling devices
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10NELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N60/00Superconducting devices
    • H10N60/10Junction-based devices
    • H10N60/128Junction-based devices having three or more electrodes, e.g. transistor-like structures
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10NELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N69/00Integrated devices, or assemblies of multiple devices, comprising at least one superconducting element covered by group H10N60/00
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F2213/00Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F2213/40Bus coupling
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/762Charge transfer devices

Definitions

  • the invention relates to an electronic component for initializing the quantum mechanical state of a qubit, which is formed by a semiconductor component or a semiconductor-like structure with gate electrode arrangements.
  • the invention also relates to a method for such an electronic component.
  • These semiconductor components often consist of doped silicon elements in order to realize the circuits.
  • transistor circuits can be arranged in such semiconductor components and linked to form a logic circuit.
  • these semiconductor components can now be produced in ever more extreme compactness.
  • This compactness has reached its physical limits.
  • Both the density of the circuits and the temperature often lead to problems in such semiconductor components.
  • optimizations can be achieved through several layer models, higher switching clocks or the choice of semiconductor material.
  • the computing power is often insufficient for many applications, such as in cryptographic technology or when calculating weather or climate models, due to the enormous amount of data.
  • a quantum mechanical system with two states as the smallest unit for storing information is referred to as a “qubit”.
  • a qubit is defined, for example, by the quantum mechanical state spin “up” and spin “down”.
  • a semiconductor heterostructure serves as the substrate.
  • the semiconductor heterostructure contains a two-dimensional electron gas (2DEG).
  • Semiconductor heterostructures are monocrystalline layers of semiconductors with different compositions grown on top of one another. These layer structures provide numerous technically relevant quantization effects with regard to their electronic and optical properties. They are therefore particularly suitable for the production of microelectronic components.
  • the currently most important combination of materials for the production of semiconductor heterostructures is the GaAs / AlGaAs system.
  • Semiconductor heterostructures form so-called quantum films at the interfaces between different materials. These arise in particular because of different Energy ratios in the two materials.
  • the predetermined energy distribution has the consequence that charge carriers from the environment collect in the quantum film. There they are largely restricted in their freedom of movement to the layer and form the two-dimensional electron gas (2DEG).
  • a nanoscopic material structure is called a quantum dot.
  • Semiconductor materials are particularly suitable for this.
  • Charge carriers, both electrons and holes, are so limited in their mobility in a quantum dot that their energy can no longer assume continuous, but only discrete values.
  • 2DEG two-dimensional electron gas
  • a quantum dot device which comprises at least three conductive layers and at least two insulating layers.
  • the three conductive layers are electrically isolated from one another. It is described there that a conductive layer consists of a different material than the other two conductive layers.
  • the conductive layers can for example consist entirely and / or partially of aluminum, gold, copper or polysilicon.
  • the insulating layers consist, for example, of silicon oxide, silicon nitride and / or aluminum oxide.
  • quantum dot device an electron is quasi trapped in a potential well. Through quantum mechanical tunneling, an electron is moved from quantum dot to quantum dot. This can lead to inaccuracies or falsifications of the information content about the quantum mechanical state when an electron moves over longer distances.
  • WO 2017/020095 A1 discloses a scalable architecture for a processing device for performing quantum processing.
  • the architecture is based on an all-silicon CMOS manufacturing technology.
  • Transistor-based control circuits are used in conjunction with floating gates to drive a two-dimensional array of qubits.
  • the qubits are defined by the spin states of a single electron that is enclosed in a quantum dot.
  • a higher level is described here, i.e. how individual qubits can be controlled electrically, for example via transistors etc., including qubit operation and readout.
  • a "scalable architecture" is spoken of, but the array shown does not allow any real scaling, i.e. integration of cryogenic electronics, among other things, since no space can be created between the qubits.
  • US Pat. No. 8,164,082 B2 describes a spin bus quantum computer architecture which comprises a spin bus which consists of several strongly coupled qubits which are always based on qubits and which define a chain of spin qubits. A large number of information-carrying qubits are arranged next to a qubit of the spin bus. Electrodes are formed to the information-carrying qubits and the spin bus qubits to enable control of the establishment and break of the coupling between qubits to control the establishment and break of the coupling between each information-carrying qubit and the adjacent spin bus qubit enable.
  • the spin-bus architecture enables qubits to be coupled quickly and reliably over long distances.
  • EP 3 016 035 B1 describes a processing device and method for operating it, in particular, but not exclusively, the invention relates to a quantum processing device which can be controlled in order to carry out adiabatic quantum calculations.
  • a quantum processor has the following features: a plurality of qubit elements and a control structure which has a plurality of control components, each control component being arranged to control a plurality of qubit elements.
  • the control structure is controllable to perform a quantum calculation using the qubit elements, a quantum state of the qubit elements being encoded in the nuclear or electron spin of one or more donor atoms.
  • the donor atoms are arranged in a plane that is embedded in a semiconductor structure.
  • a first set of donor atoms is arranged to encode quantum information related to quantum computation.
  • a second set of donor atoms is arranged to enable electromagnetic coupling between one or more of the first set of donor atoms.
  • the donor atoms of the first set are arranged in a two-dimensional matrix arrangement.
  • the plurality of control members include a first set of elongate control members disposed in a first plane above the plane containing the donor atoms.
  • a second set of elongate control members are provided which are located in a second level below the level containing the donor atoms.
  • the qubits must be coupled over distances of at least a few micrometers, in particular to create space for local control electronics. Structures and structural elements have to be provided that allow a quantum dot to appear to transport different targets in order to be able to build logical circuits.
  • One or two-dimensional arrays were built from separate quantum dots through which electrons can then be transported. Due to the very large number of gate electrodes required and the voltages to be set with them, a coupling over several micrometers cannot be implemented without considerable effort or even not at all by means of this approach.
  • the object of the invention is therefore to eliminate the disadvantages of the prior art and to create an electronic component which allows logic circuits to be implemented with quantum dots, with a quantum mechanical state to be established for initializing a qubit, for example.
  • the object is achieved by the electronic component for initializing the quantum mechanical state of a qubit of the type mentioned at the beginning, comprising a) a substrate with a two-dimensional electron gas or electron hole gas; b) electrical contacts for connecting the gate electrode assemblies to voltage sources; c) gate electrode arrangements with gate electrodes, which are arranged on a surface of the electronic component for generating potential wells in the substrate; d) a reservoir, which is provided as a dispenser for charge carriers; e) the gate electrodes of the gate electrode arrangements have parallel electrode fingers, i. the gate electrodes of a first gate electrode arrangement in the substrate form a static potential well in which quantum dots are introduced from the reservoir; ii.
  • the gate electrodes of a second gate electrode arrangement form a movable potential well in the substrate, a charge carrier with its quantum mechanical state being translatable with this potential well; f) means for transferring two quantum dots from the reservoir into the static potential well; g) a stimulator for aligning or splitting the quantum dots; h) Means for transferring a charge carrier from the static potential well into the movable potential well.
  • the object is also achieved by a method for such an electronic component with the following method steps: a) introducing two charge carriers into the static potential well from the reservoir; b) bringing the movable potential well up to the static potential well; c) Exchange between the static potential well with the movable potential well so that a charge carrier is located in the movable potential well, d) Defined alignment of the quantum dots in the static potential well and the movable potential well by means of the
  • the invention is fundamentally based on the physical Pauli principle that an electronic level can never be filled with electrons with the same spin.
  • a static potential trough is generated and, on the other hand, a movable potential trough.
  • a pair of charge carriers of one energy level is introduced into the static potential well from the reservoir.
  • the pair of charge carriers is then split up.
  • One of the quantum dots is transferred to the moving potential well.
  • the stimulator With the stimulator, the quantum mechanical state of the quantum dots is aligned in a defined manner on the level - with an electron the spin.
  • the quantum dot in the movable potential well can now be transported away with the known quantum mechanical state, for example as an initialized qubit, with the movable potential well.
  • the quantum dot In order to bring the quantum dot with the movable potential well to the static potential well, the quantum dot must be able to be translated through the substrate over a longer distance without the quantum mechanical state changing.
  • the quantum dot is quasi trapped in the potential well, which is generated in a suitable manner by the gate electrode arrangement.
  • the potential well then moves continuously and directed through the substrate and takes the quantum dot with its quantum mechanical state with it over the distance.
  • the electrode fingers of the gate electrodes are connected accordingly.
  • the stimulator is designed as a magnet which generates a gradient magnetic field for initializing the quantum dots in the static potential well.
  • the quantum dots of an energy level are aligned in a defined manner.
  • micro-magnets can preferably be used, which can be easily integrated into the semiconductor component.
  • the gradient magnetic field thus serves to initialize the quantum dots in the static potential well.
  • An oscillating magnetic field can also be used as the gradient magnetic field. This gradient magnetic field moves the quantum dot into a desired quantum mechanical state. This allows the electronic component to be initialized so that it can then interact with the introduced quantum dot at the same level.
  • the gate electrodes of the first gate electrode form a static double potential well, means for translating a quantum dot from one static potential well into the next static potential well of the static double potential well.
  • each of the static potential wells has a quantum dot with different quantum mechanical states of the same level.
  • the defined alignment of the states is in turn determined by the stimulator.
  • the potential wells are each occupied with known quantum mechanical states - in the case of electrons, they are spins.
  • a corresponding advantageous embodiment of the method according to the invention for such an electronic component consists in that in a further step the static potential well is formed as a double potential well. Subsequently the two static potential wells of the double potential well are each occupied with charge carriers that have different quantum mechanical known states. The movable potential well is now brought up to the static double potential well. One charge carrier is exchanged between a static potential well and the movable potential well. The movable potential well with the quantum dot can then be led away. The movable potential well thus contains a quantum point whose quantum mechanical state is known, which can then be used to initialize a qubit, for example.
  • a gate electrode arrangement consists of two parallel gate electrodes which form a channel-like structure. This measure serves to ensure that the potential well can only move on a certain path in the substrate.
  • the substrate contains gallium arsenide (GaAs) and / or silicon germanium (SiGe). These materials are able to generate a two-dimensional electron gas in which quantum dots can be generated, held and moved. In the case of gallium arsenide, the quantum dots are occupied with electrons. In the case of silicon germanium, the quantum dots are filled with holes that are missing an electron.
  • GaAs gallium arsenide
  • SiGe silicon germanium
  • a further preferred embodiment of the electronic component can be achieved in that the respectively interconnected gate electrodes for the moving potential well can be periodically and / or out of phase with voltage. This measure enables the potential well to be guided continuously through the substrate. A quantum dot located in the potential well can thus be translated with the potential well through the substrate. In doing so, it does not lose its original quantum mechanical state.
  • a preferred embodiment of the electronic component consists in that in each case at least every third electrode finger of a gate electrode is connected together for the movable potential well. This is intended to ensure that the potential well is always guaranteed over at least one period over which the potential well is moved. This is the only way to enable continuous movement of the potential well with the quantum dot.
  • an advantageous embodiment for the method according to the invention for an electronic component results from the fact that in each case at least every third gate electrode is connected together and a voltage is periodically applied.
  • connection means are provided for connecting to a qubit of a quantum computer.
  • Translating the states of quantum dots over a greater distance is particularly suitable for quantum computers.
  • the electronic component must therefore have contact options in order to interconnect at least two qubits in order to transfer the quantum states of the quantum dots from one qubit to the other qubit.
  • Fig. 1 shows a schematic plan view of the electronic component for
  • Fig. 2 shows in section a schematic diagram of an inventive
  • Double potential well for initializing and reading out a qubit Double potential well for initializing and reading out a qubit.
  • Fig. 3 shows in section a schematic diagram of an inventive
  • Double potential well for initializing a qubit Double potential well for initializing a qubit.
  • Fig. 4 shows a schematic plan view of the electronic component for
  • Fig. 5 shows in section a schematic diagram of an inventive
  • FIG. 1 shows a first exemplary embodiment for an electronic component 10 according to the invention, which is again formed from a semiconductor heterostructure.
  • the structures of the component are preferably in a nanoscale dimension.
  • Undoped silicon germanium (SiGe) is used as substrate 12 for electronic component 10.
  • the electronic component 10 is designed in such a way that it contains a two-dimensional electron gas (2DEG).
  • Gate electrode assemblies 16, 18 are provided on surface 14 of substrate 12.
  • the gate electrode arrangement 16 has two gate electrodes 20, 22.
  • the individual gate electrodes 20, 22 are electrically isolated from one another by means of insulating layers 24 in a suitable manner.
  • gate electrode arrangements 16 are provided in layers, the insulating layer 24 being provided between each gate electrode 20, 22 of the gate electrode arrangement 16.
  • the gate electrodes 20, 22 furthermore include the electrode fingers 26, 28, which are arranged parallel to one another on the surface 14 of the substrate 12.
  • the gate electrode arrangements 16, 18 are supplied with a suitable voltage via electrical connections. By suitably applying sinusoidal voltages to the gate electrodes 20, 22 of the gate electrode arrangement 16, a movable potential well is generated in the substrate 12. A quantum dot 42 or charge carrier trapped in this potential well can thus be translated through the substrate.
  • the potential well is translated longitudinally through the substrate 12 by suitable control of electrode fingers 26, 28 of the gate electrodes 20, 22 with sinusoidal voltages.
  • the quantum dot 42 which is quasi trapped in such a potential well, can be translated with this potential well over a longer distance in the two-dimensional electron gas of the substrate 12 made of SiGe without experiencing a quantum mechanical change in state.
  • the gate electrode arrangement 18 forms a static double potential well.
  • the gate electrode arrangement 18 comprises the barrier gate electrodes 36, 38, 40 and, in addition to the pump gate electrode 42, a further pump gate electrode 44 which can set a quantum dot or a charge carrier in motion or oscillation.
  • the pump gate electrodes 42, 44 are arranged alternately between the barrier gate electrodes 36, 38 and 40.
  • the gate electrodes 36, 38, 40, 42, 44 each have electrode fingers 37, 39, 41, 43, 45.
  • the reservoir 49 for introducing changes in charge adjoins the barrier gate electrode arrangement 18.
  • FIG. 2 shows in section the first exemplary embodiment for the electronic component 10 according to the invention, which is formed from a semiconductor heterostructure.
  • the structures of the component are preferably in a nanoscale dimension.
  • Undoped silicon germanium (SiGe) is used as substrate 12 for electronic component 10.
  • the electronic component 10 is designed in such a way that it contains a two-dimensional electron gas (2DEG).
  • Gate electrode assemblies 16, 18 are provided on a surface 14 of the substrate 12.
  • the gate electrode arrangement 16 has two gate electrodes 20, 22.
  • the individual gate electrodes 20, 22 are electrically isolated from one another by means of insulating layers 24 in a suitable manner.
  • the gate electrode arrangements 16, 18 are provided in layers, the insulating layer 24 being provided between each gate electrode 20, 22.
  • the gate electrodes 20, 22 further comprise electrode fingers 26, 28 which are arranged parallel to one another on the surface 14 of the substrate 12.
  • the gate electrode arrangements 16, 18 are supplied with a suitable voltage via electrical connections.
  • a potential well 30 is generated in the substrate 12.
  • a quantum dot 32 or charge carrier trapped in this potential well 30 can thus pass through the substrate translate.
  • the potential well 30 is translated longitudinally through the substrate by suitable control of the electrode fingers 26, 28 with sinusoidal voltages.
  • the quantum dot 32 or the charge carrier, which is quasi trapped in such a potential well 30, can be translated with this potential well 30 over a longer distance in the two-dimensional electron gas of the SiGe substrate 12 without experiencing a quantum mechanical change in state.
  • the gate electrode arrangement 18 forms a static double trough 34.
  • the gate electrode arrangement 18 comprises barrier gate electrodes 36, 38, 40 and two pump gate electrodes 42, 44, which can set a quantum dot 32, 50, 54 or a charge carrier in motion or oscillation.
  • the pump gate electrodes 42, 44 are arranged between the barrier gate electrodes 36, 38, 40, respectively.
  • the gate electrodes 36, 38, 40, 42, 44 of the gate electrode arrangement 18 are each separated by an insulating layer 24.
  • the gate electrodes 36, 38, 40, 42, 44 each have electrode fingers 37, 39, 41, 43, 45.
  • the electrode fingers 37, 39, 41, 43, 45 can be seen in this sectional drawing.
  • the courses in the substrate 12 of the electronic component 10 for initializing a quantum state of a qubit in a quantum dot are shown schematically below the gate electrode arrangements 16, 18.
  • the sequences from A to F of the courses from the potential wells 30, 34 in the substrate 12 are shown to explain the function.
  • the electrode fingers 26, 28 of the gate electrode arrangements 16 form the movable potential wells 30 through the substrate 12.
  • the movement of the potential wells 30 takes place by suitable interconnection of the electrode fingers 26, 28.
  • the electrode fingers 26, 28 of the gate electrode arrangement 16 are periodically interconnected, which cause an almost continuous movement of the potential well 30 through the substrate 12.
  • the electronic component 10 is based on the physical Pauli principle that an electronic level can never be filled with electrons with the same spin.
  • a static double potential well 34 is generated and on the other hand with the gate electrodes 20, 22 the movable potential well 30.
  • a first potential well 46 of the static double potential well 34 two charge carriers 48 are created from a reservoir 49 introduced.
  • the charge carriers 48 are split up and aligned with a stimulator 51, for example with the aid of a gradient magnetic field and the pump gate electrodes 42, 44.
  • a split-off charge carrier 50 tunnels into a second static potential well 52 of the double potential well 34, which is indicated by arrow 53. Only one charge carrier 54 remains in the first static potential well.
  • the quantum states of the quantum dots 50, 54 in the potential wells 46, 48 are known from the alignment of an applied gradient magnetic field.
  • a further quantum dot 32 is brought up to the second static potential well 52 of the double potential well 34 at the same level.
  • the quantum mechanical state of the quantum dot 32 is not known.
  • Arrow 58 indicates the translation direction of the quantum dot 32 with the movable potential well 30.
  • the quantum dot 50 of the second static potential well 52 exchanges with the quantum dot 32 of the movable potential well 30.
  • the quantum mechanical state of the quantum dot 50 is known, is now located in the movable potential well 30 and initializes a qubit, for example.
  • the quantum dot 32 tunnels, provided it has the same spin as the quantum dot 50 now removed for initialization, into the first static potential well 46 of the double potential well 34.
  • a sensor element not shown here would therefore not detect any change in charge. If the quantum mechanical states of the quantum dot 50 and 32 are different, a change in charge can be detected.
  • the exchange is symbolized with arrow 60.
  • FIG 3 shows, in section, a further exemplary embodiment for the electronic component 10 according to the invention, which is formed from a semiconductor heterostructure.
  • the structures of the component 10 are preferably in a nanoscale dimension.
  • Undoped silicon germanium (SiGe) is used as substrate 12 for electronic component 10.
  • the electronic component 10 is designed in such a way that it contains a two-dimensional electron gas (2DEG).
  • the gate electrode assemblies 16, 18 are provided on the surface 14 of the substrate 12.
  • the gate electrode arrangement 16 also has the two gate electrodes 20, 22 here.
  • the individual gate electrodes 20, 22 are electrically isolated from one another by means of insulating layers 24 in a suitable manner.
  • the gate electrode arrangements 16, 18 are provided in layers for this purpose, the insulating layer 24 being provided between each gate electrode 20, 22.
  • the gate electrodes 20, 22 further comprise electrode fingers 26, 28 which are arranged parallel to one another on the surface 14 of the substrate 12.
  • the gate electrode arrangements 16, 18 are supplied with a suitable voltage via electrical connections.
  • a potential well 30 is generated in the substrate 12.
  • a quantum dot or charge carrier trapped in this potential well 30 can thus be translated through the substrate.
  • the potential well 30 is translated longitudinally through the substrate by suitable control of the electrode fingers 26, 28 with sinusoidal voltages.
  • the quantum dot or the charge carrier, which is quasi trapped in such a potential well 30, can be translated with this potential well 30 over a longer distance in the two-dimensional electron gas of the SiGe substrate 12 without experiencing a quantum mechanical change in state.
  • the gate electrode arrangement 18 forms a static double trough 34.
  • the gate electrode arrangement 18 comprises the barrier gate electrodes 36, 38, 40 and two pump gate electrodes 42, 44, which can set the quantum dot 32, 50, 54 or a charge carrier 48 in motion or oscillation.
  • the pump gate electrodes 42, 44 are arranged between the barrier gate electrodes 36, 38, 40, respectively.
  • the gate electrodes 36, 38, 40, 42, 44 of the Gate electrode assemblies 18 are each separated by an insulating layer 24.
  • the gate electrodes 36, 38, 40, 42, 44 each have electrode fingers 37, 39, 41, 43, 45.
  • the electrode fingers 37, 39, 41, 43, 45 can be seen in this sectional drawing.
  • the courses in the substrate 12 of the electronic component 10 for initializing a quantum state of a qubit in a quantum dot are shown schematically below the gate electrode arrangements 16, 18.
  • the sequences from A to D of the courses from the potential wells 30, 34 in the substrate 12 are shown to explain the function.
  • the electrode fingers 26, 28 of the gate electrode arrangement 16 form the movable potential wells 30 through the substrate 12.
  • the movement of the potential wells 30 takes place by suitable interconnection of the electrode fingers 26, 28.
  • the electrode fingers 26, 28 of the gate electrode arrangement 16 are periodically interconnected, which cause an almost continuous movement of the potential well 30 through the substrate 12.
  • the static double potential trough 34 is generated and, on the other hand, the movable potential trough 30 is generated with the gate electrodes 20, 22 49 introduced.
  • the charge carriers 48 are split up and aligned with the stimulator 51, for example with the aid of a gradient magnetic field.
  • the split-off charge carrier 50 tunnels quantum mechanically into the second static potential well 52 of the double potential well 34, which is indicated by arrow 53. Only the charge carrier 54 remains in the first static potential well 46.
  • the quantum states of the quantum dots 50, 54 in the potential wells 46, 48 are known from the alignment of an applied gradient magnetic field.
  • the movable potential well 30 is brought up to the second static potential well 52 of the double potential well 34.
  • the charge carrier 50 passes from the static potential well 52 into the movable potential well 30.
  • the quantum dot 50 can now be moved away with the movable potential well 30, arrow 58.
  • the quantum mechanical state of the quantum dot 50 is known, which creates a qubit for example can be initialized.
  • FIG. 4 shows a further exemplary embodiment for the electronic component 10 according to the invention, which is again formed from a semiconductor heterostructure.
  • the structures of the component 10 are preferably in a nanoscale dimension.
  • Undoped silicon germanium (SiGe) is used as substrate 12 for electronic component 10.
  • the electronic component 10 is designed in such a way that it contains a two-dimensional electron gas (2DEG).
  • the gate electrode assemblies 16, 18 are provided on the surface 14 of the substrate 12.
  • the gate electrode arrangement 16 has two gate electrodes 20, 22.
  • the individual gate electrodes 20, 22 are electrically isolated from one another by means of insulating layers 24 in a suitable manner.
  • gate electrode arrangements 16 are provided in layers, the insulating layer 24 being provided between each gate electrode 20, 22 of the gate electrode arrangement 16.
  • the gate electrodes 20, 22 furthermore include the electrode fingers 26, 28, which are arranged parallel to one another on the surface 14 of the substrate 12.
  • the gate electrode arrangements 16, 18 are supplied with a suitable voltage via electrical connections.
  • a movable potential well 30 is produced in the substrate 12.
  • a quantum dot 42 or charge carrier trapped in this potential well 30 can thus be translated through the substrate 12.
  • the potential well 30 is translated longitudinally through the substrate 12 by suitable control of the electrode fingers 26, 28 with sinusoidal voltages.
  • the quantum dot 42 which is quasi trapped in such a potential well, can be moved into the two-dimensional space over a longer distance with this potential well 30 Translate electron gas of the substrate 12 from SiGe without experiencing a quantum mechanical change of state.
  • the gate electrode arrangement 18 forms a static potential well.
  • the gate electrode arrangement 18 comprises the barrier gate electrodes 36, 40 and, in addition to the pump gate electrode 42, which can set a quantum dot or a charge carrier in motion or oscillation.
  • the pump gate electrode 42 is disposed between the barrier gate electrodes 36 and 40.
  • the gate electrodes 36, 40, 42 each have electrode fingers 37, 41, 43.
  • the reservoir 49 for introducing changes in charge adjoins the barrier gate electrode arrangement 18.
  • FIG. 5 shows in section a further exemplary embodiment for the electronic component 10 according to the invention, which is formed from a semiconductor heterostructure.
  • the structures of the component 10 are preferably in a nanoscale dimension.
  • Undoped silicon germanium (SiGe) is used as substrate 12 for electronic component 10.
  • the electronic component 10 is designed in such a way that it contains a two-dimensional electron gas (2DEG).
  • the gate electrode assemblies 16, 18 are provided on the surface 14 of the substrate 12.
  • the gate electrode arrangement 16 also has the two gate electrodes 20, 22 here.
  • the individual gate electrodes 20, 22 are electrically isolated from one another by means of insulating layers 24 in a suitable manner.
  • the gate electrode arrangements 16, 18 are provided in layers, the insulating layer 24 being provided between each gate electrode 20, 22.
  • the gate electrodes 20, 22 further comprise electrode fingers 26, 28 which are arranged parallel to one another on the surface 14 of the substrate 12.
  • the gate electrode arrangements 16, 18 are supplied with a suitable voltage via electrical connections.
  • a potential well 30 is generated in the substrate 12.
  • a quantum dot or charge carrier trapped in this potential well 30 can thus be translated through the substrate.
  • the potential well 30 is translated longitudinally through the substrate by suitable control of the electrode fingers 26, 28 with sinusoidal voltages.
  • the quantum dot or the charge carrier, which is quasi trapped in such a potential well 30, can be translated with this potential well 30 over a longer distance in the two-dimensional electron gas of the SiGe substrate 12 without experiencing a quantum mechanical change in state.
  • the gate electrode arrangement 18 forms a static potential well 70.
  • the gate electrode arrangement 18 comprises the barrier gate electrodes 36, 40 and a pump gate electrode 42, which can set the quantum dot 48 or a charge carrier in motion or oscillation.
  • the pump gate electrode 42 is arranged between the barrier gate electrodes 36, 40.
  • the gate electrodes 36, 40, 42 of the gate electrode arrangement 18 are each separated by an insulating layer 24.
  • the gate electrodes 36, 40, 42 each have electrode fingers 37, 41, 43.
  • the electrode fingers 37, 41, 43 can be seen in this sectional drawing.
  • the courses in the substrate 12 of the electronic component 10 for initializing a quantum state of a qubit in a quantum dot are shown schematically below the gate electrode arrangements 16, 18.
  • the sequences from A to D of the courses from the potential wells 30, 70 in the substrate 12 are shown to explain the function.
  • the electrode fingers 26, 28 of the gate electrode arrangement 16 form the movable potential wells 30 through the substrate 12.
  • the movement of the potential wells 30 takes place by suitable interconnection of the electrode fingers 26, 28.
  • the gate electrodes 36, 40 and 42 on the one hand the static potential well 70 and on the other hand the movable potential well 30 with the gate electrodes 20, 22.
  • Two charge carriers 48 from the reservoir 49 are introduced into the potential well 70.
  • the charge carriers 48 are split up and aligned with the stimulator 51, for example with the aid of a gradient magnetic field.
  • the split-off charge carrier 50 tunnels quantum mechanically into the movable potential well 30, which is indicated by arrow 53. Only the charge carrier 54 remains in the static potential well 70.
  • the quantum states of the quantum dots 50, 54 in the potential wells 70, 30 are created by the alignment of a
  • the quantum dot 50 can now be led away with the movable potential well 30, arrow 58.
  • the quantum mechanical state of the quantum dot 50 is known, as a result of which a qubit can be initialized, for example.

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EP20792280.8A 2019-09-20 2020-09-21 Bauelement zum initialisieren eines quantenpunkts Pending EP4031489A1 (de)

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US20220327072A1 (en) 2022-10-13
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CN114402440A (zh) 2022-04-26
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US12072819B2 (en) 2024-08-27
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