WO2024179675A1

WO2024179675A1 - Device for moving qubits for a semiconductor spin qubit quantum computer

Info

Publication number: WO2024179675A1
Application number: PCT/EP2023/055061
Authority: WO
Inventors: Inga SEIDLER; Lars Reiner SCHREIBER; Nils FOCKE; Jörg Hendrik BLUHM
Original assignee: Rheinisch-Westfälische Technische Hochschule (Rwth) Aachen
Priority date: 2023-02-28
Filing date: 2023-02-28
Publication date: 2024-09-06

Abstract

A shuttling element for a quantum computer comprises a plurality of gate electrodes arranged on a semiconductor heterostructure. The plurality of gate electrodes comprises screening gates to define at least one path in the semiconductor heterostructure. The plurality of gate electrodes comprises conveyor gates arranged at the at least one path. The conveyor gates comprise electrode subsets electrically disconnected from each other. The conveyor gates of any one of the electrode subsets are electrically connected with each other. The finger gates are configured to be supplied with at least one voltage V to move at least one qubit along the at least one path.

Description

Title: DEVICE FOR MOVING QUBITS FOR A SEMICONDUCTOR SPIN QUBIT QUANTUM COMPUTER

Field of the disclosure

[0001] The field of the present disclosure relates to the operation of quantum processors.

Background of the disclosure

[0002] Quantum processor architectures have to allow for scalability in order to achieve numbers of logical qubits sufficiently high to implement quantum computer chips that enable NISQ (noisy intermediate-scale quantum) era quantum computing or even universal quantum computing. In the case of spin qubit-based quantum computing, the qubits are arranged in a two-dimensional plane. A downside of this two-dimensional architecture is the so-called fan-out problem, i.e. , spatial requirements of the wiring for the control lines of the quantum processor between the quantum processor and a classical control circuit. These spatial requirements scale faster with the number of qubits than the size of the hitherto proposed spin qubitbased quantum processor architectures.

[0003] Recently, an architecture for spin-qubits based on direct electron shuttling in Si/SiGe semiconductor heterostructures was proposed. The architecture includes shuttling paths along which qubits are transportable across, in principle, arbitrary distances such as of up to about 50 pm. The shuttling paths allow to arrange components of the quantum processor, such as loading zones, readout zones, and manipulation zones, at a distance from each other, which lowers crosstalk. Providing shuttling paths also enables operations modes that require comparatively small operation frequencies and reduced local magnetic field gradients.

[0004] In these shuttling path-based architectures, high-fidelity shuttling is important for reliable computations. Such high-fidelity shuttling is compromised by, e.g., charge defects or low valley splitting along the shuttling path. The low valley splitting may lead to leakage out of the computational basis, e.g., two spin states, that is used for computation.

[0005] There is a need for identifying spots in the quantum processor, e.g., in the shuttling path or other components of the quantum processor, where the reliability of qubit handling is reduced, which ultimately impacts on the performance of the quantum processor.

Summary of the disclosure

[0006] A shuttling element for a quantum computer comprises a plurality of gate electrodes arranged on a semiconductor heterostructure, wherein the plurality of gate electrodes comprises screening gates to define at least one path in the semiconductor heterostructure. The plurality of gate electrodes comprises conveyor gates arranged at the at least one path. The conveyor gates comprise electrode subsets electrically disconnected from each other. The conveyor gates of any one of the electrode subsets are electrically connected with each other. The finger gates are configured to be supplied with at least one voltage V to move at least one qubit along the at least one path.

[0007] Ones of the plurality of electrode subsets may have a dielectric or insulating layer arranged between each other.

[0008] The conveyor gates may be arranged on a planarized dielectric or insulating layer.

[0009] The plurality of gate electrodes may be arranged on at least one surface of semiconductor heterostructure.

[0010] The manipulation zone may further comprise a top gate arranged above the conveyor gates.

[0011] A system comprises a shuttling element according to the disclosure and a magnet providing an external magnetic field Bo.

[0012] A method of moving at least one qubit along at least one path in a semiconductor heterostructure is disclosed, wherein the semiconductor heterostructure comprises a plurality of gate electrodes arranged thereon. The method comprises the step of providing an external magnetic field Bo. The method further comprises the step of generating at least one travelling potential well by applying at least one voltage to the plurality of gate electrodes, arranged at the at least one path, to move the at least one qubit.

[0013] The generating of the at least one travelling potential well may comprise applying at least one AC voltage to conveyor gates of the plurality of gate electrodes.

Brief description of the drawings

[0006] FIG. 1 shows a schematic top view of a quantum processor.

[0014] FIG. 2 shows a schematic top view of a unit cell of the quantum processor shown in FIG. 2.

[0015] FIG. 3A shows a top view of an aspect of a shuttling lane.

[0016] FIG. 3B shows a longitudinal cross-section of a further aspect the shuttling lane.

[0017] FIG. 3C shows an example of a grayscale-coded valley-splitting landscape of a shuttling lane as well as possible trajectories for a qubit along the shuttling lane which circumvent a series of fidelity-reducing loci with reduced valley splitting.

[0018] FIGS. 3D-3F show results of simulating an effect of disorder in a semiconductor heterostructure on the orbital splitting of the one or more qubits being moved along the at least one path of the shuttling element.

[0019] FIG. 4 shows a pair of path-defining gates arranged at a path for a qubit.

[0020] FIG. 5 shows a longitudinal cross-section of a further aspect of the shuttlinglane.

Detailed description

[0021] The present disclosure relates to a method of operating a quantum processor as well as to a method of manufacturing a quantum processor.

[0022] The quantum processor may operate based on spin qubits. A spin qubit is a two-level quantum system of a spin degree of freedom. An example of a spin qubit is the two-level quantum system of the spin of an electron confined in a quantum dot. Another example is a hole spin qubit. Furthermore, a group of electrons, for example two or three electrons, may be used to implement a spin qubit, such as an S-T0 singlet-triplet system of two electrons in a quantum double-dot. [0023] The method of the present disclosure is applicable to any type of electrically controllable spin qubit implemented in a semiconductor heterostructure 12. Using an electron-based spin qubit involves bringing the electron spin into a known state. To this end, the state of the electron is initialized. In one aspect, a selected qubit is associated with the same electron throughout the performing of a quantum algorithm. In another aspect, a qubit implemented by a first electron may be initialized and, subsequently to an operation on the qubit, the qubit may be implemented by means of a second electron. In a further aspect, there are situations in which it is impossible to tell whether the qubit is implemented by the first electron or by the second electron, without compromising the performing of quantum algorithms. Likewise, the method of the present disclosure may be applied on any type of hole spin qubit.

[0024] Using semiconductor materials to form the semiconductor heterostructure 12, for implementing the quantum processor facilitates manufacturing due to easy handling and low costs of the materials, such as in the case of silicon. There are established technologies for using silicon in computing hardware. A two-dimensional electron gas (2DEG) or a two-dimensional hole gas (2DHG) is confinable within the semiconductor heterostructure 12, formed from the semiconductor materials, in a quantum well 69 (see below and FIG. 5). The quantum well 69 is exemplarily shown in FIG. 5 only. However, the quantum well 69 will also be present in the semiconductor heterostructure 12 shown in FIGS. 3A, 3B. The 2DEG or the 2DHG may further be confined based on electrical potentials. The electric potentials may be static electric potentials or non-static electric potentials. The electrical potentials may form at least one quantum dot, in which at least one electron or hole of the 2DEG or 2DHG is trappable or confinable. The spin of the trapped (confined) at least one electron or hole is usable to implement spin qubits. Moving the electrical potentials results in moving the at least one quantum dot. The moving of the at least one quantum dot enables moving the trapped (confined) at least one electron/hole as well as the qubits associated with the trapped (confined) at least one electrons/holes. Altering a strength of the electrical potentials alters the degree of confinement of the trapped (confined) at least one electron or hole.

[0025] The quantum processor may comprise a plurality of unit cells. A unit cell of the plurality of unit cells comprises components that perform at least one action or operation on one or more qubits located in the unit cell. The at least one action on the one or more qubits includes: loading of the one or more qubits into the unit cell; unloading of the one or more qubits from the unit cell; moving (shuttling) the one or more qubits within the unit cell or beyond the unit cell (i.e. , to another one of the unit cell of the quantum processor); manipulating a quantum state of the one or more qubits; and readout of the quantum state of the one or more qubits. The manipulating of the one or more qubits may comprise manipulating a single qubit or manipulating two qubits. The manipulating of the single qubit comprises rotating the spins of the single qubit, e.g., for driving transitions between a plurality of spin states. The plurality of spin states may comprise, e.g., a spin-up state and a spin-down state. The manipulating of two qubits comprises implementing a CPHASE gate, a CNOT gate, and/or a SWAP gate.

[0026] In one aspect, several actions performed on the one or more qubits by the components of the unit cell may be performed one after another as a sequence of actions. For example, two actions may be performed one after another. In another aspect, the several actions performed on the one or more qubits by the components of the unit cell may be performed in parallel. For example, the two actions may be performed in parallel.

[0027] In one aspect, the several actions on the one or more qubits may be performed within a single one of the plurality of the unit cells or across several ones of the plurality of unit cells.

[0028] In one aspect, the several actions may be performed as part of determining a gate fidelity (see below for more details). For example, the determining of the gate fidelity may comprise performing the sequence of actions on the one or more qubits.

[0029] In another aspect, the several actions may be performed as part of performing an algorithm. For example, the performing of the algorithm may comprise performing the sequence of actions on the one or more qubits.

[0030] The components are arranged within the unit cell. Some of the components are connected with each other. The components and the connections of the components thus form a layout or structure of the unit cell. Ones of the plurality of unit cells may have substantially the same structure, in which the same components are arranged and connected with each other in substantially the same way. Other ones of the plurality of unit cells may have differing structures, in which the components and/or the connections of the components differ.

[0031] An aspect of the quantum processor is disclosed in international patent application no. WO 2021/052541 A1 , the disclosure of which is incorporated herein by reference in its entirety. In this aspect, shown in FIGS. 1 and 2, the quantum processor 10 comprises the semiconductor heterostructure 12. The semiconductor heterostructure 12 comprises several layers of differing material composition. The semiconductor heterostructure 12 may be a Si/SiGe or GaAs/AIGaAs heterostructure, however, the use of other materials in which a two-dimensional electron gas (2DEG) or a two-dimensional hole gas (2DHG) can be formed, such as Si-MOS or Ge/SiGe, is possible. The semiconductor heterostructure may be undoped and/or strained. The semiconductor heterostructure 12 may serve as a substrate of the quantum processor 10. The semiconductor heterostructure 12 may comprise the 2DEG. The 2DEG or the 2DHG may be arranged or located in the quantum well 69 (see FIG. 5). The one or more qubits may be arranged in the quantum well 69. The one or more qubits may be arranged in the at least one quantum dot formed in the quantum well 69. The one or more qubits may be generated from the 2DEG.

[0032] In one aspect, the semiconductor heterostructure 12 may further comprise a silicon cap 64, on which a dielectric or insulating layer 66 is arranged (see FIG. 5). The gate electrodes 50a, 50b may be arranged on top of the dielectric or insulating layer 66.

[0033] In a further aspect, the semiconductor heterostructure 12 may further comprise a layer of strained silicon 63 (see FIG. 5). In yet a further aspect, the semiconductor heterostructure 12 may further comprise a layer of silicon dioxide 62 (see FIG.5).

[0034] In the aspect of the quantum processor 10 shown in FIGS. 1 and 2, the components 16, 18, 20, 22, 24 are provided on at least one surface 14 of the semiconductor heterostructure 12. As can be seen in FIG. 1 , the shown aspect of the quantum processor 10 comprises one or more of each of the components 16, 18, 20, 22, 24. In another aspect, the quantum processor 10 may comprise one or more of only some of the component 16, 18, 20, 22, 24.

[0035] The quantum processor 10 shown in FIGS. 1 and 2 is a substantially two- dimensional device, as defined by the at least one surface 14. A third dimension of the quantum processor 10 is defined by a thickness of the semiconductor structure 12 and a thickness of the components 16, 18, 20, 22, 24.

[0036] The plurality of unit cells of the quantum processor 10 comprises several of the unit cell 26 (shown in FIG. 2). In the aspect shown in FIG.2, the unit cell 26 comprises the components 16, 18, 20, 22, 24. In another aspect of the disclosure, the unit cell 26 comprises merely some of the components 16, 18, 20, 22, 24. In yet a further aspect, the unit cell 26 may comprise more than one of at least one of the components 16, 18, 20, 22, 24.

[0037] The components 16, 18, 20, 22, 24 comprise a plurality of gate electrodes 50 (see FIGS. 3A and 3B) arranged on at least one surface 14 of the semiconductor heterostructure 12. The plurality of gate electrodes 50 may be arranged to define within the quantum well 69 of the associated one of the components 16, 18, 20, 22, 24 at least one path 45 (see FIGS. 1 , 2, 3A, 3C 4, 5) along which the one or more qubits may be moved (shuttled).

[0038] In FIGS. 1 and 2, the at least one path 45 is shown to substantially be directed in two directions on the surface 14 that are substantially perpendicular to one another, resulting in structure of a plurality of paths 45 that is grid-like. The plurality of paths 45 connect the components 16, 18, 20, 22, 24.

[0039] The plurality of gate electrodes 50 may further be arranged to move (shuttle) the one or more qubits along the at least one path 45. The movement (shuttling) may occur in either one of the two directions (back and forth) along the at least one path 45. The plurality of gate electrodes 50 may further be arranged for performing the at least one action on the one or more qubits, performed by the components 16, 18, 20, 22, 24.

[0040] The plurality of gate electrodes 50 may be provided with voltages. . The plurality of gate electrodes 50 may be made of metal. The plurality of gate electrodes 50 may be superconducting. The voltages may serve one or more purposes, such as defining the at least one path 45, moving (shuttling) the one or more qubits, and/or implementing the at least one action on the one or more qubits. The voltages may comprise DC (direct current) voltages and AC (alternating current) voltages. The voltages may comprise one or more stationary voltages and one or more non- stationary voltages. The voltages may be applied by means of DC lines, AC lines, and/or bias tees.

[0041 ] One or more of the components 16, 18, 20, 22, 24 may further comprise a magnet, such as a micromagnet. The micromagnet may be placed on top of the component 16, 18, 20, 22, 24. The micromagnet provides a magnetic field. The magnetic field may have a zero gradient or a non-zero gradient.

[0042] An external magnetic field splits the plurality of spin states (e.g., spin-up and spin-down) used as a computational basis for the one or more qubits into separated energy levels (Zeeman splitting). The external magnetic field may be provided by an external magnet, e.g., an electromagnet (not shown), that is placed in the vicinity of the quantum processor 10. The quantum processor 10 may at least partially be placed in the external magnetic field provided by the external magnet.

[0043] The one or more components 16, 18, 20, 22, 24 may further comprise means for providing electromagnetic radiation, e.g., microwaves, for manipulating the quantum state of the one or more qubits, e.g., rotating the spins of the one or more qubits between the plurality of spin states. The spins of the one or more qubits may thus be switched between, e.g., the spin-up and the spin-down state, or vice versa, by means of the electromagnetic radiation based on electron spin resonance (ESR). The frequency of the electromagnetic radiation may equal the energy difference of the separated energy levels. ESR provides a further way of manipulating the quantum state of the one or more qubits. The microwaves may have a frequency in the range of several hundred MHz to several hundred GHz. In one aspect, the frequency lies in the range of 9-10 GHz, but is not limited thereto.

[0044] Providing an inhomogeneous magnetic field, i.e., having a non-zero gradient, enables driving transitions between the plurality of spin states by means of displacements of the one or more qubits in the inhomogeneous magnetic field based on, e.g., an AC electric field. This effect is called electric dipole spin resonance (EDSR). The displacement makes the one or more qubits oscillate between the plurality of spin states (e.g., the spin states forming the computational basis such as the spin-up state and the spin-down state). For example, the one or more qubits may oscillate such that the spin-up state can be switched to the spin-down state, and vice versa. Alternatively, the EDSR may be achieved in one of the semiconductor heterostructure 12 in which spin-orbit coupling is present.

[0045] The plurality of gate electrodes 50 may be provided as one or more of gate electrode assemblies 50a, 50b, 50c, 50d. The plurality of gate electrodes 50 may comprise one or more laterally positioning gate electrodes (also termed "screening gates”) 50a (see FIG. 3A) arranged to define and/or modify a lateral position of a trajectory 80 (see FIG. 3C) in the quantum well 69 and/or at the at least one path 45 for moving (shuttling) the one or more qubits within the unit cell or beyond the unit cell. The trajectory 80 may be a trajectory of one or more potential wells (further described below), in which the one or more qubits are arrangeable. The one or more potential wells may thus be one or more travelling potential wells. The trajectory 80 of the one or more potential wells may thus correspond to a trajectory of the one or more qubits arranged at the least one path 45. Thus, the lateral position of the trajectory 80 may correspond to a lateral position of the one or more potential wells and/or of the one or more qubits. Arranging the one or more qubits at the least one path 45 is to be understood to mean that the one or more qubits are arranged within the quantum well 69.

[0046] The plurality of gate electrodes 50 may further comprise one or more shuttling gate electrodes (also termed “conveyor gates” or “finger gates” or “clavier gates”) 50b (see FIG. 3A) arranged to move (shuttle) the one or more qubits along the at least one path 45 for moving (shuttling) the one or more qubits within the unit cell or beyond the unit cell.

[0047] The plurality of gate electrodes 50 may further comprise at least one pitchenhancing gate electrode (also termed “top gate”) 50d arranged to enable enhancing a conveyor gate pitch or spacing of the conveyor gates 50b.

[0048] The plurality of gate electrodes 50 may further comprise at least one vertically positioning gate electrode (also termed “back gate”) 50c arranged to define and/or modify a vertical position of the trajectory 80 (see FIG. 5) in the quantum well 69 and/or at the at least one path 45 for moving (shuttling) the one or more qubits within the unit cell or beyond the unit cell. The vertical position of the trajectory 80 may correspond to a vertical position of the one or more potential wells and/or of the one or more qubits. [0049] The plurality of gate electrodes 50 may further comprise qubit-handling gate electrodes (not shown) arranged for performing the at least one action on the one or more qubits. The qubit-handling electrodes include plunger gates and barrier gates. The plunger gates may be used to control the occupation of a quantum dot, to control a detuning in a double quantum dot, and/or to perform an exchange of two qubits. The barrier gates may be used to form a potential double-well and/or to control the tunnel barrier in a double quantum dot.

[0050] The plurality of gate electrodes 50 may be arranged on the at least one surface 14 of the semiconductor heterostructure 12. The plurality of gate electrodes 50 may be arranged in layers that are separated by an insulating or dielectric layer 60 and the insulating or dielectric layer 66 (see FIG. 3B and 5). In one aspect, the layers may be arranged in a direction substantially perpendicular to the direction of the at least one path 45.

[0051] One or more of the insulating or dielectric layer 60, the insulating and dielectric layer 66, and/or the insulating or dielectric layer 67 may be planarized. A method of manufacturing the shuttling element 16 may comprise the step of planarizing one or more of the insulating or dielectric layer 60, the insulating and dielectric layer 66, and/or the insulating or dielectric layer 67. The insulating or dielectric layer 60 may be planarized during manufacturing before arranging the conveyor gates 50b on the insulating or dielectric layer 60. The planarizing facilitates using processes such as electron ray epitaxy, Deep UV, and/or spacer lithography.

[0052] The component 16 serves to move (shuttle) the one or more quantum dots in the semiconductor heterostructure 12 for moving (shuttling) the one or more qubits within the unit cell or beyond the unit cell. The component 16 is also termed “shuttling lane”. Aspects of the shuttling lane 16 is disclosed in international patent application no. WO 2021/052531 A1 , the disclosure of which is incorporated herein by reference in its entirety.

[0053] The component 18 provides a junction at which the one or more quantum dots may be diverted into at least one branch (at least one second one of the at least one path 45) that branches off of the at least one path 45 for moving (shuttling) the one or more qubits within the unit cell or beyond the unit cell. The component 18 is also termed “T-junction” . The at least one path 45 and the at least one branch of the T- junction 18 may be arranged perpendicular or non-perpendicular to one another. In one aspect, the at least one path 45 and the at least one branch of the T-junction 18 may substantially form a T-shape. Aspects of the T-junction 16 is disclosed in international patent application no. WO 2021/052539 A1 , the disclosure of which is incorporated herein by reference in its entirety.

[0054] The component 20 is provided for manipulating qubits in quantum dots. The component 20 is also termed “manipulation zone”. The manipulation zone 20 enables manipulating one or more current spin state of the one or more qubits. Any one qubit has a current spin state. In one aspect, the plurality of spin states may comprise the current spin state. In another aspect, the current spin state may be a linear combination of the plurality of spin states. During the manipulating, the one or more current spin states may be changed. Aspects of the manipulation zone 20 are disclosed in WO 2021/052537 A1 , the disclosure of which is incorporated herein by reference in its entirety.

[0055] The component 22 serves to initialize the one or more spin states of the one or more qubits. When the one or more spin states have been initialized, any one of the one or more current spin states is equal to one of the plurality of spin states. After initialization, the one or more current spin states may remain unchanged during a relaxation time. The relaxation time describes transitions between the spin-up state and the spin-down state due to interactions with the environment, such as the lattice of the semiconductor heterostructure 12. The component 22 is also termed “initialization zone”. Aspects of the initialization zone 22 are disclosed in WO 2021/052538 A1 , the disclosure of which is incorporated herein by reference in its entirety.

[0056] The component 24 serves to read out the one or more current spin states of the one or more qubits. When the one or more spin states have been read out, any one of the one or more current spin states prior to readout is known. The component 24 is also termed “readout zone”. Aspects of the readout zone 24 are disclosed in WO 2021/052536 A1 , the disclosure of which is incorporated herein by reference in its entirety.

[0057] The quantum processor 10 is operated to perform algorithms, such as quantum algorithms. The performing of the algorithms includes performing the sequence of actions on the one or more qubits, as explained above. The at least one action is performed by the components 16, 18, 20, 22, 24 of the unit cells 26.

[0058] The operating of the quantum processor 10 involves controlling the at least one action performed by the components 16, 18, 20, 22, 24. In one aspect of the disclosure, the at least one action is controlled by applying the voltages to the plurality of gate electrodes 50. The voltages may be set and/or adjusted to increase a fidelity F of the at least one action or of the sequence of actions. The fidelity F is a measure of how reliably the at least one action or the sequence of actions results in the outcome that is expected based on the design of the quantum processor 10 and on the voltages applied to the plurality of gate electrodes 50. To determine the fidelity F, the at least one action or the sequence of actions is repeated; subsequently the proportion of the repetitions is determined in which the actual outcome equals the expected outcome. The actual outcome includes the one or more current spin states that have been read out at the readout zone 24 after the at least one action or the sequence of actions. The expected outcome includes the one or more current spin states that are, based on known fidelities of the components 16, 18, 20, 22, 24 and/or the relaxation time of the one or more qubits, expected to be read out at the readout zone 24 after the at least one action or the sequence of actions.

[0059] For example, the at least one action may comprise the moving (shuttling) of the one or more qubits along the at least one path 45 of the shuttling lane 16. In this case, the fidelity F is a shuttling fidelity. The shuttling fidelity is understood to be a probability that the one or more current spin states of the one or more qubits are preserved during shuttling. The shuttling fidelity may be determined, for example, by repeatedly performing the sequence of actions: initialization of the one or more qubits, moving (shuttling) of the one or more qubits, and readout of the one or more qubits; followed by determining whether the initialized spin state of the one or more qubits are equal to the one or more current spin states after shuttling and prior to readout; and finally calculating the proportion of the repetitions in which the one or more current spin states were unaltered.

[0060] The fidelity F may further be a gate fidelity. The gate fidelity F is a measure of how closely the outcome of a gate operation (i.e. , the sequence of actions by means of the components 16, 18, 20, 22, 24 on the one or more qubits that are associated with a gate the quantum processor 10 is designed to implement) matches the expected, e.g., theoretical, outcome based on the design of the quantum processor 10 and the components 16, 18, 2022, 24. The gate fidelity F may be determined by randomized benchmarking.

[0061] As an example, increasing the shuttling fidelity F of a single qubit along a shuttling lane 16 will be described. FIG. 3A shows an aspect of the shuttling lane 16. The shuttling lane 16 comprises the screening gates 50a and the conveyor gates 50b arranged on the at least one surface 14 of the semiconductor heterostructure 12. In the aspect shown in FIG. 3A, the at least one surface 14 comprises a top surface 141 of the semiconductor heterostructure 12. In the aspect shown in FIG. 3B, the top surface 141 may be a top surface of the dielectric or insulating layer 66 (further described below).

[0062] The screening gates 50a are arranged to extend on either side of the at least one path 45 as screening gates 50a-1 and 50a-2 (see also FIG. 4). In one aspect, as shown in FIGS. 3A-3B, the screening gates 50a-1 and 50a-2 may extend continuously along the at least one path 45. The screening gates 50a-1 and 50a-2 may be spaced apart by approximately 200 nm. The screening gates 50a may be made from metal and may be manufactured by embedding the metal in the semiconductor heterostructure 12 or by local implantation of the semiconductor heterostructure 12. The screening gates 50a may be embedded in the dielectric or insulating layer 66 and/or in the dielectric or insulating layer 60.

[0063] The dielectric or insulating layer 66 and/or in the dielectric or insulating layer 60 may be structured in the lateral direction D3. In one aspect, the dielectric or insulating layer 66 and/or in the dielectric or insulating layer 60 may be provided as two separate portions (not shown), the separate portions enveloping the two screening gates 50a-1 and 50a-2, and the semiconductor heterostructure 12 extending into a space (not shown) between the two portions along the lateral (or transverse direction) D3. The semiconductor heterostructure 12 thus may form a ridge (not shown) in the space between the two portions of the dielectric or insulating layer 66 and/or in the dielectric or insulating layer 60.

[0064] The conveyor gates or finger gates 50b are arranged to extend transversely across the at least one path 45 (as shown in FIG. 3A). For example, the conveyor gates 50b may extend in a lateral direction D3. The conveyor gates or finger gates 50b are arranged along the at least one path 45.

[0065] In the aspect shown in Fig. 3A, the conveyor gates 50b are provided in electrode subsets 50b-1 , 50b-2, 50b-3, 50b-4 (indicated in FIGS. 3A and 3b by indices 1 , 2, 3, 4). The ones of the conveyor gates 50b that belong to one of the electrode subsets 50b-1 , 50b-2, 50b-3, 50b-4 are marked with the same index at the top of FIG. 3A, i.e. , the index 1 , 2, 3, or 4. The number of electrode subsets 50b-1 , 50b-2, 50b-3, 50b-4 shown in FIG. 3A is four. However, the number of the electrode subsets of the conveyor gates 50b may differ from this example and be, e.g., three or five. Any number of the electrode subsets of the conveyor gates 50b may be chosen, as long as the one or more travelling potential wells for moving (shuttling) the qubit or the one or more qubits (see below) can be generated. The one or more travelling potential wells provide the confinement to trap an electron or hole, the strength of which is sufficiently strong to overcome disorder during moving (shuttling) in the quantum well 69, and the height of which provide barriers between adjacent potential well to suppress tunnelling. The trapped one or more electrons or holes adiabatically follow a sufficiently slow translation of the potential.

[0066] In one aspect, the conveyor gates 50b may be arranged at the at least one path 45 in a manner, in which juxtaposed ones of the conveyor gates 50b extend differently far in the lateral (or transverse) direction D3 (as shown in FIG. 3A). In another aspect the conveyor gates 50b may extend equally far in the lateral (or transverse direction) D3.

[0067] The conveyor gates 50b may be arranged in a substantially equidistant manner with a substantially constant conveyor gate spacing between any two neighboring conveyor gates 50b. If a conveyor gate width, i.e., an extension of the conveyor gates 50b in the longitudinal direction D3, of the conveyor gates 50b is substantially constant, a conveyor gate pitch, which is the sum of the conveyor gate spacing and the conveyor gate width, is substantially constant. In one aspect of the disclosure, the conveyor gate pitch may be approximately 80 nm. The conveyor gates 50b may be arranged in a periodic manner. In one aspect, the conveyor gates 50b of any one of the electrode subsets 50b-1 , 50b-2, 50b-3, 50b-4 may be arranged in a substantially equidistant manner from each other based on a spatial period of the periodically arranged conveyor gates. In another aspect, any two conveyor gates 50b belonging to any selected one of the electrode subsets 50b-1 , 50b-2, 50b-3, 50b-4 have one conveyor gate of each of the other non-selected ones of the electrode subsets arranged therebetween. The periodical arrangement of the conveyor gates 50b facilitates industrial manufacturing of the shuttling path 16.

[0068] The conveyor gates 50b belonging to one of the four electrode subsets 50b-1 , 50b-2, 50b-3, 50b-4, shown in FIG. 3A, are electrically connected to each other by an electrical connection (not shown). The conveyor gates of any selected electrode subset from the electrode subsets 50b-1 , 50b-2, 50b-3, 50b-4 are electrically disconnected from (or not electrically connected to) the conveyor gates of the corresponding non-selected electrode subsets. In one aspect of the disclosure, the electrical connection may be provided by a metal strip (not shown) arranged parallel to the screening gates 50a. The metal strip may be arranged beyond the screening gates 50a in the lateral direction D3. For example, the metal strip connecting the electrodes subsets 50b-1 and 50b-3 may be arranged at the top of FIG. 3A, and the metal strip connecting the electrodes subsets 50b-2 and 50b-4 may be arranged at the bottom of FIG. 3A. The electrode subsets of the conveyor gates 50b with indices 1 and 3 may have the electrical connection on one side of the at least one path 45 (above the at least one path 45 as seen in FIG. 3A). The electrode subsets of the conveyor gates 50b with indices 2 and 4 may have the electrical connection on the other side of the at least one path 45 (below the at least one path 45 as seen in FIG. 3A). In one aspect of the disclosure, the electrode subsets 50b-1 , 50b-2, 50b-3, 50b- 4 may be arranged at different levels in the stacking direction D1 . For example, the metal strip connecting the conveyor gates of the electrode subset 50b-1 may be arranged on one side of the at least one path 45 at a higher level in the stacking direction D1 than the metal strip connecting the conveyor gates of the electrode subset 50b-3; and the metal strip connecting the conveyor gates of the electrode subset 50b-2 may be arranged on the other side of the at least one path 45 at a higher level in the stacking direction D1 than the metal strip connecting the conveyor gates of the electrode subset 50b-4. However, the metal strips may in another aspect be all arranged on one side of the at least one path 45. In a further aspect, ones of the metal strips connecting the conveyor gates of the electrode subsets 50b-1 , 50b-2, 50b-3, 50b-4 may be connected to the conveyor gates by vias; and the conveyor gates of the electrode subsets 50b-1 , 50b-2, 50b-3, 50b-4 may be arranged at substantially one level in the stacking direction D1.

[0069] The electrical connection of the conveyor gates of any one of the electrode subsets 50b-1 , 50b-2, 50b-3, 50b-4 enables providing a single voltage to the corresponding electrode subset. In other words, the number of voltage signals applied to the conveyor gates 50b is given by the number of electrode subsets chosen. As a result, the number voltage signals applied to screening gates 50a and the conveyor gates 50b is independent of a length of the shuttling element 16. In the example shown in FIGS. 3A and 3B, the number of electrode subsets is four. However, the number may be smaller or larger than four. For example, using three electrode subsets achieves moving the one or more qubits by means of the travelling potential well.

[0070] In a further aspect of the disclosure, the shuttling path 16 may comprise the top gate 50d (see FIG. 7). The top gate 50d may extend in the lateral (transverse) direction D3. The top gate may extend in the shuttling direction (or longitudinal direction) D2. The top gate 50d may cover at least part of the first path 451 and/or the second path 452. In one aspect, at least in the lateral (transverse) direction D3, the top gate 50d completely covers the first path 451 and/or the second path 452.

[0071] In yet another aspect of the disclosure, the top gate electrode 50d may be arranged on top of the conveyor gates 50b with a dielectric layer 67 arranged therebetween. The dielectric or insulating layer 67 may be partially arranged on the dielectric or insulating layer 60 (see FIG. 5). Sections of the dielectric or insulating layer 67, which are arranged between the electrodes of the conveyor gates 50b, may be arranged on the dielectric or insulating layer 60. The dielectric or insulating layer 67 may be structured, e.g., segmented or profiled, in the shuttling direction D2 (see FIG. 5). The dielectric or insulating layer 67 insulates the conveyor gates 50b that belong to different ones of the subsets 50b-1 , 50b-2, 50b-3, 50b-4 from each other. In one aspect of the disclosure, the dielectric or insulating layers 60 and 67 are a single dielectric or insulating layer 60, 67, in which the conveyor gates 50b are embedded.

[0072] The top gate 50d may be applied with a constant voltage. In a further aspect, the voltage applied to the top gate 50d may be modified on the one or more actions on the one or more qubits. For example, the voltage applied to the top gate 50d may be modified for shuttling the one or more qubits, for initializing the one or more qubits, for reading out of the one or more qubits, for manipulating the one or more qubits. In another example, the voltage applied to the top gate 50d may be modified according to sequence of actions on the one or more qubits, for instance as part of performing an algorithm. In yet a further aspect, the voltage applied to the top gate 50d may be modified periodically or non-periodically. The periodically modifying and/or the non- periodical ly modifying of the voltage applied to the top gate 50d may depend on the action performed on the one or more qubits. The periodically modifying of the voltage applied to the top gate 50d includes adding a square wave, a sawtooth wave, a superposition of sine waves. The periodically modifying of the voltage applied to the top gate 50d includes adding a stepwise increment to the voltage applied to the top gate 50d. The stepwise increment may depend on the one or more actions performed on the one or more qubits.

[0073] In one aspect, the top gate 50d may have a planar top surface (not shown). In another aspect of the disclosure, the top gate 50d may be structured. An example of the structured top gate 50d is a segmented top gate 50d. Another example of the structured top gate 50d is a top gate with a surface profile (or profiled top gate), as shown in FIG. 5. The structured top gate 50d may in one aspect be a segmented and profiled top gate. Additionally or alternatively to the longitudinal structuring, the top gate 50d may be structured, e.g., segmented and/or profiled, along the lateral direction (or transvers direction) D3.

[0074] The top gate 50d enables increasing the conveyor gate pitch between the conveyor gates 50b whilst maintaining the ability to shuttle the one or more qubits along the at least one path 45.

[0075] In an aspect of the disclosure, the at least one surface 14 may further comprise a back surface 142. The at least one back gate 50c may be arranged on the back surface 142 of the semiconductor heterostructure 12 opposite the top surface 141 (see FIG. 7). In the aspect shown in FIG. 5, the back surface 142 is arranged at a bottom of the semiconductor heterostructure. The back surface 142 is arranged opposite the top surface 141 . The back surface 142 may be a surface of the layer of silicon dioxide 62 (describe above). [0076] In the aspect shown in FIG. 5, the at least one back gate 50c extends along a shuttling direction or longitudinal direction D2 of the shuttling lane 16. The at least one back gate 50c may further extend laterally (or transversely to the at least one path 45). For example, the at least one back gate 50c may further extend along the lateral (or transverse) direction D3 of the shuttling lane 16 transverse to the at least one path 45. The at least one back gate 50c may overlap or intersect the screening gates 50a in the lateral direction D3. The at least one back gate 50c may be arranged opposite the screening gates 50a. A voltage may be applied to the at least one back gate 50c to provide an electrical potential to modify the confinement at the quantum well 69.

[0077] In one aspect of the disclosure, the at least one back gate 50c may be structured, e.g., segmented and/or profiled, along the shuttling direction (or longitudinal direction) D2. In another aspect of the disclosure, the at least one back gate 50c may be structured, e.g., segmented and/or profiled, along the lateral direction D3, i.e. , transverse to the at least one path 45. In a yet a further aspect of the disclosure, the at least one back gate may be structured, e.g., segmented and/or profiled, along the shuttling direction (or longitudinal direction) D2 and the lateral direction D3.

[0078] As shown in FIG. 3B, the screening gates 50a and the conveyor gates 50b are separated by the insulating or dielectric layer 60. As explained above, the insulating or dielectric layer 60 may be planarized during manufacturing before arranging the conveyor gates 50b on the insulating or dielectric layer 60. The four electrode subsets of the conveyor gates 50b may be separated by a further insulating or dielectric material (not shown). Furthermore, the dielectric or insulating layer 66 may be provided on the semiconductor heterostructure 12 (see FIG. 3B). The insulating or dielectric layer 66 separates the screening gates 50a and the semiconductor heterostructure 12. The screening gates 50a may be provided on the insulating layer 66.

[0079] The shuttling lane 16 is configured to move (shuttle) the one or more qubits along the at least one path 45. During the operation of the quantum processor 10, the shuttling lane 16 will be used to move the one or more qubits, e.g., from the initialization zone 22 to the manipulation zone 20 and thence to the readout zone 24. During this sequence of actions on the one or more qubits, the two screening gates (or “gates”) 50a-1 , 50a-2 (see FIGS. 3A and 4) of the screening gates 50a of the shuttling lane 16 may in one aspect of the disclosure be provided with the same voltage of, e.g., 0 V. When the voltage of 0V is applied to the two screening gates 50a-1 , 50a-2, the dielectric or insulating layer 66 may be omitted. The conveyor gates 50b are provided with AC voltages to provide the one or more travelling potential wells in which the one more qubits may be moved (shuttled). The AC voltages provided to the conveyor gates 50b may be sine-wave voltages. In another aspect, the AC voltages provided to the conveyor gates 50b may be non-sine-wave voltages. The non-sine wave voltages enable reducing varying orbital level splittings (see FIGS. 3D-3F and below). The AC voltages provided to the conveyor gates 50b may be phase-shifted between the electrode subsets of conveyor gates 50b-1 , 50b-2, 50b-3, 50b-4. The phase shifts of the conveyor gates 50b-2, 50b-3, 50b-4 with respect to the conveyor gates 50b-1 may be set to TT/2, IT, and 3TT/2, respectively. However, other settings for the phase shifts are conceivable. The phase shifts may deviate from being set to multiples of TT/2.

[0080] A lateral or transverse position in the lateral direction D3 of the trajectory 80 (see FIG. 3C) of the one or more qubits along the at least one path 45 (extending along the x-axis of FIG. 3C) is defined by the voltage applied to the two gates 50a-1 , 50a-2 (see, e.g., FIG. 4) of the screening gates 50a. If the voltage applied to the gate 50a-1 and the voltage applied to the gate 50a-2 are substantially equal, one or more lateral positions of the generated one or more potential wells (i.e. , of one or more minima of the one or more potential wells) will be substantially in the middle of the two gates 50a-1 , 50a-2. If on the other hand the voltage applied to the gate 50a-1 and the voltage applied to the gate 50a-2 differ, the lateral position of the generated one or more potential wells (i.e., of the one or more minima of the one or more potential wells) will be off the middle of the two gates 50a-1 , 50a-2. The differing voltages on the gates 50a-1 , 50a-2 may be the result of changing either the voltage applied to the gate 50a-1 or the voltage applied to the gate 50a-2 by the addition of an adjustment voltage AV. In other words, the voltage applied to either the gate 50a- 1 or the gate 50a is changed to V+AV. For example, in the case of the heterostructure 12 being an undoped Si/SiGe heterostructure, if the voltage applied to the gate 50a-1 is decreased relative to the voltage applied to the other gate 50a-2, the one or more positions of the generated one or more potential wells (i.e., of the one or more minima of the one or more potential wells) will be moved towards the other gate 50a-2. In case the heterostructure 12 is doped, such as when using GaAs/AIGaAs, increasing the voltage applied to the gate 50a-1 moves the one or more potential wells towards the other gate 50a-2. In this way, the trajectory 80 of the one or more qubits along the at least one path 45 may be shifted laterally (i.e. , in the lateral or transverse direction D3 with respect to the at least one path 45).

[0081] In one aspect of the disclosure, the lateral shifting of the trajectory 80 of the of the one or more qubits may be transient (termed “local shift” in FIG. 3C). The transient lateral shifting is the result of a time-varying adjustment voltage AV(t) being added to the voltage applied to the gate 50a-1 or the voltage applied to the gate 50a- 2. In other words, the trajectory 80 deviates only temporally from the lateral position that was initially set during a calibration (i.e., y-position of 0 nm in the example shown in FIG. 3C). The temporal lateral shifting results for example in the trajectory 80-1 shown in FIG. 3C.

[0082] In one aspect, the time-varying adjustment voltage AV(t) may be an AC voltage, such as a square pulse or a square wave. If several fidelity-reducing loci 70 are on average found to be distanced along the at least one path 45 (along the x-axis in FIG. 3C) from one another by an average distance of 1000 nm (or 1 pm), and a shuttling speed at which the one or more qubits are shuttled along the at least one path 45 is 10 nm/ns (or 10 m/s), then on average the one or more qubits take a time of 100 ns to travel a distance equal to the average distance. The time-varying adjustment voltage AV(t) may thus last for the time of 100 ns. For instance, half the period of the square wave may be chosen to be equal to the time of 100 ns. In other words the square wave may be chosen to have a frequency of 5 MHz.

[0083] In a further aspect of the disclosure, the adjustment voltage comprises a DC voltage that is added to the AC voltage applied to the conveyor gates 50b. The DC voltage may be applied to the conveyor gates 50b in addition to, or alternatively to the adjustment voltage AV(t) applied to the screening gates 50a. The further adjustment voltage may provide an alteration of the confinement provided by the conveyor gates 50b, e.g., enhance the confinement when the one or more qubits are in the vicinity of a fidelity-reducing locus 70 (see below). [0084] The lateral shifting of the lateral position of the trajectory 80-1 enables circumventing a fidelity-reducing locus 70 in the shuttling lane 16. When the one or more qubits pass the fidelity-reducing locus 70 in the shuttling lane 16, the shuttling fidelity F may be reduced. The reduced shuttling fidelity F results in a less reliable shuttling of the one or more qubits along the shuttling lane 16. The fidelity-reducing locus 70 may be the result of, for example, a manufacturing impurity, a manufacturing defect, a charge defect, a crystal defect, and/or a locally reduced valley splitting. FIG. 3C shows a greyscale-coded valley-splitting landscape with valley-splitting energies between 0 peV and 300 peV (lighter shaded areas corresponds to higher valleysplitting energies; darker shaded areas correspond to lower valley-splitting energies). Fidelity-reducing loci 70 are located where the valley-splitting energy is between 0 peV and approximately 30-50 peV (shown by the paler shaded areas within dark shaded areas) . In the example shown in FIG. 3C, the trajectory 80-1 circumvents several fidelity-reducing loci 70 positioned at the y-position of 0 nm. The fidelityreducing loci 70-1 , 70-2, 70-3, ... , 70-10 are indicated by arrows and in some cases additionally by white dotted elliptical markings. In the example shown, the deviation Ay from the lateral position of the trajectory 80 initially set during a calibration (i.e. , the y-position of 0 nm set during a calibration step described below) peaks at approximately 20 nm in the lateral direction D3 along the positive y-axis in FIG. 3C and at approximately -20 nm in the lateral direction D3 along the negative y-axis in FIG. 3C. In another case, the maximum values for the deviation Ay in the two lateral directions (along the positive and the negative y-axis, respectively) may differ from 20 nm and -20 nm, respectively.

[0085] The lateral shifting of the lateral position y of the trajectory 80-1 further enables continuous adjustment of the lateral position y of the trajectory 80-1 by means of a time-varying adjustment voltage AV(t). The time-varying adjustment voltage AV(t) results in a time-varying deviation Ay(t). The continuous adjustment may be required in the case of fluctuations in the voltages applied to the plurality of gate electrodes 50.

[0086] In an aspect of the disclosure, similar to the lateral shifting described above, one or more vertical positions of the one or more potential wells may be shifted vertically, i.e., in a stacking direction D1 (described below). Thereby, a vertical position of the trajectory 80-3 (a position along the stacking direction D1 ) may be altered. When the voltage applied to the at least one back gate 50c is changed, the confinement of the one or more potential wells is altered. The voltage applied to the at least one back gate 50c may be changed relative to the voltage applied to the screening gates 50a. Depending on the location of the at least one fidelity-reducing locus 70 (indicated by an asterisk in FIG. 5), the vertical position of the trajectory 80 may be altered upwards or downwards in the stacking direction D1 . Thereby, the at least one fidelity-reducing locus 70 may be circumvented, and the reliability (i.e. , the fidelity) of the shuttling lane 16 may be increased

[0087] FIGS. 3D-3F show results of simulating an effect of disorder in a semiconductor heterostructure 12 on the orbital splitting of the one or more qubits being moved along the at least one path 45 of the shuttling element 20. The disorder is due to one or more of defects at boundaries of the layers of the semiconductor heterostructure 12, defects within the layers of the heterostructure 12, and/or defects within the dielectric layers 60, 66 and/or 67. The defects at the boundaries of the layers of the semiconductor heterostructure 12 include charge defects at interfaces between layers made from semiconductor materials and the dielectric or insulating layers 60 and/or 66. These charge defects are randomly distributed, e.g., at the interfaces. A density of the charge defects was set to 5E10/cm². Transitions to excited orbital states of the electron confined in the one or more travelling potential wells are caused by the disorder. In a moving frame of the one or more travelling potential wells, the disorder that quasi-statically fluctuates turns into dynamic noise that couples the orbital/valley levels. Setting the shuttling velocity to v = 10 m/s results in a reduced orbital/valley excitation rate and a below-threshold phase error.

[0088] In FIGS. 3D-3F, the x-axis shows the distance by which the one or more qubits were simulated to be moved. The distance is measured in the spatial periods T and has a length of 10T. The spatial period T is four times the conveyor gate pitch, since every fourth conveyor gate 50b is applied with the same one of the voltage. In FIGS. 3D-3F, the y-axis indicates the orbital splitting in units of meV (millielectronvolts) resulting from the effect of material properties (including or not including defects) on the orbital splitting. The orbital splitting results from the confinement of the one or more qubits generated by the voltages applied to the gate electrodes 50. The wiggly horizontal line represents the ideal case of a semiconductor heterostructure 12 without any defects and shows the orbital splitting due to gate-generated confinement alone. The rugged line shows the effect on the orbital splitting of the presence of defects in the semiconductor heterostructure 12 and/or in the dielectric layers 60, 66, and/or 67. It can be seen that the orbital splitting gets reduced or increased depending on the spatially fluctuating material properties of the semiconductor heterostructure 12 and/or on spatially fluctuating material properties of the dielectric layers 60, 66 and/or 67. When the orbital splitting is only rarely reduced along the at least one path 45, the confinement of the moving quantum dot hosting one or more qubits along the at least one path 45 is increased, which results in increasing the shuttling fidelity F. In one aspect of the disclosure, the orbital splitting constantly exceeds 1 meV, in which case the shuttling velocity is set to 10 m/s.

[0089] A reduced thickness of one or more of the insulating or dielectric layers 60, 66, 67 enables screening the charge defects at the interfaces by the plurality of gate electrodes 50. The planarizing reduces the thickness of one or more of the dielectric or insulating layers 60, 66, 67. For instance, the insulating or dielectric layers 66 and/or 60 may be planarized before manufacturing of the conveyor gates 50b to reduce the thickness of the insulating or dielectric layer 66 and/or 60, respectively.

[0090] After planarization, the insulating or dielectric layers 66 and/or 60 are tightly placed on the semiconductor heterostructure 12. Planarizing the insulating or dielectric layers 66 and/or 60 results in the thickness of the insulating or dielectric layers 66 and/or 60 being reduced between the at least one path 45 and the conveyor gates 50b. In one aspect, the thickness of the insulating or dielectric layer 60 is required to cover a top surface and sides of the screening gates 50a.

[0091] In FIG. 3D, the dielectric or insulating layers 60 and 66 were simulated to have a thickness of 10 nm, the screening gates 50a-1 and 50a-2 were simulated to be spaced apart by 210 nm, the AC voltage applied to the conveyor gates in the phase- shifted manner was simulated to have an amplitude of 100 mV, and the voltage applied to the top gate 50d was simulated to be 170 mV.

[0092] In FIG. 3E, the dielectric or insulating layers 60 and 66 were simulated to have a thickness of 7 nm, the screening gates 50a-1 and 50a-2 were simulated to be spaced apart by 205 nm, the AC voltage applied to the conveyor gates in the phase- shifted manner was simulated to have an amplitude of 100 mV, and the voltage applied to the top gate 50d was simulated to be 150 mV.

[0093] In FIG. 3F, the dielectric or insulating layers 60 and 66 were simulated to have a thickness of 5 nm, the screening gates 50a-1 and 50a-2 were simulated to be spaced apart by 200 nm, the AC voltage applied to the conveyor gates in the phase- shifted manner was simulated to have an amplitude of 100 mV, and the voltage applied to the top gate 50d was simulated to be 140 mV.

[0094] It can be seen from FIGS. 3D-3F, that the conditions simulated in FIG. 3F achieve the smallest standard deviation of the orbital splitting along the at least one path 45.

[0095]The determination of the shuttling fidelity F enables identifying positions of the fidelity-reducing loci 70 at the trajectory 80-1 or 80-3 (e.g., along and/or in the vicinity of the trajectory 80-1 or 80-3). During the identification of the positions of the fidelityreducing loci 70, the applied voltages V are iteratively adjusted. Thereby, the lateral position of the trajectory 80-1 and/or the vertical position of the trajectory 80-3 is iteratively adjusted. The identification of the positions of the fidelity-reducing loci 70 results in a method of controlling the shuttling lane 16.

[0096] In a calibration step, the voltages V, which are applied to the plurality of gate electrodes 50, are calibrated. The calibration of the plurality of voltages V takes into account the target ranges for the plurality of voltages V. The target ranges may be predefined based on previously collected data from measurements and experiments. While the voltages V are calibrated, the voltages V are kept within the target ranges.

[0097] When the plurality of the voltages V are calibrated, at least one interaction between ones of the plurality of voltages among each other is accounted for. The at least one interaction may be expressed as a boundary condition or as a functional relationship. The functional relationship may take into account the target ranges.

[0098] For example, in the case of the shuttling lane 16 shown in FIGS. 3A and 3B, the voltages applied to the screening gates 50a and to the conveyor gates 50b generate electric fields (in the case of voltages V being DC voltages) and/or electromagnetic fields (in the case of voltages V being AC voltages). The generated fields superpose each other, e.g., at trajectory 80, and lead to a resultant electric field and/or a resultant electromagnetic field. The effect of this superposition, i.e., the interaction, needs to be considered with regard to the material composition as well as the targeted behaviors of the shuttling lane 16. Other interaction among the voltages applied to the gate electrodes 50 will be present and possibly depend on the actual design of the quantum processor 10.

Claims

1 . A shuttling element (16) for a quantum computer (10) comprising a plurality of gate electrodes (50) arranged on a semiconductor heterostructure (12) , wherein

- the plurality of gate electrodes (50) comprises screening gates (50a-1 , 50a-2) to define at least one path (45) in the semiconductor heterostructure (12);

- the plurality of gate electrodes (50) comprises conveyor gates (50b) arranged at the at least one path (45),

- the conveyor gates (50b) comprise electrode subsets (50b-1 , 50b-2, 50b-3, 50b-4) electrically disconnected from each other, the conveyor gates (50b) of any one of the electrode subsets (50b-1 , 50b-2, 50b-3, 50b-4) being electrically connected with each other;

- the finger gates (50b) are configured to be supplied with at least one voltage V to move at least one qubit along the at least one path (45).

2. The shuttling element (16) according to claim 1 , wherein ones of the plurality of electrode subsets (50b-1 , 50b-2, 50b-3, 50b-4) have a dielectric or insulating layer (67) arranged between each other.

3. The shuttling element (16) according to claim 1 or 2, wherein the conveyor gates (50b) are arranged on a planarized dielectric or insulating layer (60).

4. The manipulation zone (20) according to any one of claims 1 to 3, wherein the plurality of gate electrodes (50) is arranged on at least one surface (14) of semiconductor heterostructure (12).

5. The manipulation zone (20) according to any one of claims 1 to 4, further comprising a top gate (50d) arranged above the conveyor gates (50b).

6. A system comprising the shuttling element (16) according to any of claims 1 to 5 and a magnet providing an external magnetic field Bo.

7. A method of moving at least one qubit along at least one path (45) in a semiconductor heterostructure (12), the semiconductor heterostructure (12) comprising a plurality of gate electrodes (50) arranged thereon, the plurality of gate

- providing an external magnetic field Bo;

- generating at least one travelling potential well by applying at least one voltage to the plurality of gate electrodes (50), arranged at the at least one path (45), to move the at least one qubit.

8. The method of claim 7, wherein the generating of the at least one travelling potential well comprises applying at least one AC voltage to conveyor gates (50b) of the plurality of gate electrodes (50).

9. The method of claim 8, wherein the generating of the at least one travelling potential well comprises applying phase-shifted AC voltages to electrode subsets (50b-1 , 50b-2, 50b-3, 50b-4) of the conveyor gates (50b), the electrode subsets (50b-1 , 50b-2, 50b-3, 50b-4) being electrically disconnected from each other, and the conveyor gates (50b) of any one of the electrode subsets (50b-1 , 50b-2, 50b- 3, 50b-4) being electrically connected with each other.