EP2510538A2 - Élimination d'une matière de masquage - Google Patents

Élimination d'une matière de masquage

Info

Publication number
EP2510538A2
EP2510538A2 EP10836729A EP10836729A EP2510538A2 EP 2510538 A2 EP2510538 A2 EP 2510538A2 EP 10836729 A EP10836729 A EP 10836729A EP 10836729 A EP10836729 A EP 10836729A EP 2510538 A2 EP2510538 A2 EP 2510538A2
Authority
EP
European Patent Office
Prior art keywords
solution
ammonium
ceric
resist
cerium
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP10836729A
Other languages
German (de)
English (en)
Other versions
EP2510538A4 (fr
Inventor
Ali Afzali-Ardakani
Thomas H. Baum
Karl E. Boggs
Emanuel I. Cooper
Douglas Cywar
Matthew Kern
Mahmoud Khojasteh
George Gabriel Totir
Ronald W. Nunes
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Advanced Technology Materials Inc
International Business Machines Corp
Original Assignee
Advanced Technology Materials Inc
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US12/636,015 external-priority patent/US8367555B2/en
Application filed by Advanced Technology Materials Inc, International Business Machines Corp filed Critical Advanced Technology Materials Inc
Publication of EP2510538A2 publication Critical patent/EP2510538A2/fr
Publication of EP2510538A4 publication Critical patent/EP2510538A4/fr
Withdrawn legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31127—Etching organic layers
    • H01L21/31133—Etching organic layers by chemical means
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/3063—Electrolytic etching
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/26—Processing photosensitive materials; Apparatus therefor
    • G03F7/42—Stripping or agents therefor
    • G03F7/422—Stripping or agents therefor using liquids only
    • G03F7/423—Stripping or agents therefor using liquids only containing mineral acids or salts thereof, containing mineral oxidizing substances, e.g. peroxy compounds

Definitions

  • the present invention relates generally to removing a masking material and, more particularly, to removing a masking material using a solution comprising cerium.
  • Resist is a radiation sensitive (e.g., light radiation sensitive) material used to form a patterned layer on a substrate (e.g., a semiconductor wafer) during semiconductor device fabrication.
  • a radiation sensitive material e.g., light radiation sensitive
  • the exposed portion of the resist (for positive resist), or the unexposed portion of the resist (for negative resist) is removed to reveal the underlying surface of the substrate, leaving the rest of the surface of the substrate coated and protected by resist.
  • Resist may be more generally referred to as a masking material.
  • Other fabrication processes such as ion-implanting, etching, or depositing may be performed on the uncovered surface of the substrate and the remaining resist. After performing the other fabrication processes, the remaining resist is removed in a strip operation.
  • dopant ions e.g., ions of boron, boron difluoride, arsenic, indium, gallium, phosphorous, germanium, antimony, xenon or bismuth
  • the ions are implanted in the exposed regions of the substrate as well as in the remaining resist.
  • Ion-implantation may be used, for example, to form implanted regions in the substrate such as the channel region and source and drain regions of transistors. Ion- implantation may also be used to form lightly doped drain and double diffused drain regions.
  • ions implanted in the resist may deplete hydrogen from the surface of the resist causing the resist to form an outer layer or crust, which may be a carbonized layer that is harder than the underlying portion of the resist layer (i.e., the bulk portion of the resist layer).
  • the outer layer and the bulk portion have different thermal expansion rates and react to stripping processes at different rates.
  • High dose ion-implanted resist may cause severe hardening or crusting of the resist resulting in relatively large differences between the outer layer and bulk portion in, for example, differences in thermal expansion rates, solubilities and other chemical and physical characteristics.
  • FET field-effect-transistor
  • An FET may also be known as a metal-oxide-semiconductor FET (MOSFET), although MOSFET is a misnomer for FETs having a silicon gate instead of a metal gate.
  • FET transistors comprise a source region, a drain region, a channel region between the source and drain regions, a gate insulator above the channel region and a gate electrode above the gate insulator.
  • gate electrodes typically comprised metal.
  • gate electrodes typically comprised semiconductor silicon (e.g., in the form of polysilicon). Silicon was used because silicon is compatible with silicon dioxide used as the gate insulator, and because silicon could tolerate high temperatures that were useful for fabricating FETs and integrated circuits that included FETs.
  • metal gate electrodes Metal has the advantage of having less electrical resistance than polysilicon, thus reducing signal propagation times. Furthermore, in very recent technologies having transistor dimensions that are smaller that dimensions of preceding technologies, it is necessary to make the gate dielectric layer very thin (e.g., one nanometer). Very thin gate dielectric layers may cause a problem in polysilicon gate electrodes, called poly depletion, where a depletion layer is formed in the gate polysilicon electrode next to the gate dielectric when the channel region of the transistor is in inversion. To avoid poly depletion, a metal gate is desired. A variety of metal gates materials may be used, usually in conjunction with relatively high dielectric constant gate insulator materials, known as high-k dielectrics. Examples of metal gate materials include tantalum, tungsten, tantalum nitride, and titanium nitride (TiN).
  • Principles of the invention provide, for example, methods for removing a masking material and devices formed by removing a masking material.
  • a method for removing a masking material comprises contacting the masking material with a solution comprising cerium.
  • an electronic device is formed by removing a masking material by contacting the masking material with a solution comprising cerium.
  • a method for removing photoresist from a substrate comprises contacting the photoresist with a solution comprising cerium. Prior to contacting the photoresist with the solution, it is assumed that the photoresist has been ion- implanted by greater than approximately 5x10 14 ions per square centimeter, and/or ions having an average energy, before the ions impact the photoresist, greater than approximately five thousand electron volts (5 KeV).
  • the substrate comprises titanium nitride.
  • an electronic device is formed by removing photoresist from a substrate.
  • the photoresist is removed by contacting the photoresist with a solution comprising cerium.
  • the photoresist Prior to contacting the photoresist with the solution, the photoresist has been ion-implanted with greater than approximately 5x10 14 ions per square centimeter, and/or ions having an average energy, before the ions impact the photoresist, greater than approximately 5 KeV.
  • the electronic device comprises titanium nitride.
  • a method of forming an electronic device comprises forming a substrate comprising titanium nitride, ion-implanting photoresist by greater than approximately 5x10 14 ions per square centimeter, and/or ions having an average energy, before the ions impact the photoresist, greater than approximately 5 KeV, and contacting the photoresist with a solution comprising cerium.
  • the masking material comprises resist or photoresist
  • the solution used to remove the resist or photoresist comprises cerium ammonium nitrate.
  • a method for removing a masking material comprises contacting the masking material with a solution comprising cerium and at least one additional oxidant.
  • an electronic device is formed by removing a masking material by contacting the masking material with a solution comprising cerium and at least one additional oxidant.
  • a method for removing photoresist from a substrate comprises contacting the photoresist with a solution comprising cerium and at least one additional oxidant. Prior to contacting the photoresist with the solution, it is assumed that the photoresist has been ion- implanted by greater than approximately 5x10 14 ions per square centimeter, and/or ions having an average energy, before the ions impact the photoresist, greater than approximately five thousand electron volts (5 KeV).
  • the substrate comprises titanium nitride.
  • an electronic device is formed by removing photoresist from a substrate.
  • the photoresist is removed by contacting the photoresist with a solution comprising cerium and at least one additional oxidant.
  • a solution comprising cerium and at least one additional oxidant.
  • the photoresist Prior to contacting the photoresist with the solution, the photoresist has been ion- implanted with greater than approximately 5x10 14 ions per square centimeter, and/or ions having an average energy, before the ions impact the photoresist, greater than approximately 5 KeV.
  • the electronic device comprises titanium nitride.
  • a method of forming an electronic device comprises forming a substrate comprising titanium nitride, ion-implanting photoresist by greater than approximately 5x10 14 ions per square centimeter, and/or ions having an average energy, before the ions impact the photoresist, greater than approximately 5 KeV, and contacting the photoresist with a solution comprising cerium and at least one additional oxidant.
  • the masking material comprises resist or photoresist
  • the solution used to remove the resist or photoresist comprises cerium ammonium nitrate and at least one additional oxidant.
  • Further embodiments of the invention provide, for example, substantially complete removal of resist that has undergone ion-implantation whereby a hard or difficult to dissolve shell has been formed on the resist.
  • Additional embodiments of the invention provide, for example, a wet-only method of stripping a resist that has received high dose ion-implantation (e.g., high dose ion-implantation strip or HDIS), wherein the wet-only method does not require using any plasma-related steps or any vacuum-related steps.
  • high dose ion-implantation strip or HDIS high dose ion-implantation strip
  • FIG. 1 shows a method for removing a masking material from a substrate according to an exemplary embodiment of the invention.
  • FIG. 2 shows results of an x-ray photoelectron spectroscopy (XPS) analysis of a wafer that has been processed using a masking material removal method according to an exemplary embodiment of the invention.
  • FIG. 3 is a scanning electron microscope (SEM) image of a cross section of a silicon-on- insulator (SOI) wafer that has been processed using a masking material removal method according to an exemplary embodiment of the invention.
  • FIG. 4 shows results of an XPS analysis of a silicon-on-insulator wafer that has been processed using a masking material removal method according to an exemplary embodiment of the invention.
  • FIG. 5 shows a cross-sectional view of a packaged integrated circuit that has been processed using a masking material removal method according to an exemplary embodiment of the invention.
  • FIG. 6 shows the cleaning of a test wafer at various locations using a cerium-containing solution with and without manganese.
  • FIG. 7 shows the cleaning of a test wafer at various locations using dilute CAN solutions.
  • FIG. 8 shows the extent of masking material removal using a solution having a N3 ⁇ 4 to TFA ratio of 1.002:1.
  • FIG. 9 shows the extent of masking material removal using a solution having a N3 ⁇ 4 to TFA ratio of 3.826:1.
  • Ion-implantation is a process by which ions of a dopant material can be implanted into target material, usually a solid.
  • the physical properties of an ion-implanted material are usually different from the physical properties of the target material prior to implantation.
  • Ion- implantation is used in semiconductor device fabrication, for example, in the fabrication of integrated circuits and silicon semiconductor devices.
  • the implanted ions may introduce or cause a chemical change in the target due to the ions being a different element than the target, and/or a structural change, in that the target may be modified, damaged or even destroyed by ion- implantation.
  • elements that are typically used for implanted species in semiconductor fabrication include boron, boron difluoride, arsenic, indium, gallium, germanium, bismuth, xenon, phosphorus and antimony.
  • Boron is a p-type dopant in silicon because it donates or causes a "hole" (i.e., electron vacancy) in the silicon.
  • Arsenic is an n-type dopant in silicon because it donates or causes an extra electron in the silicon.
  • Dopants, such as boron and arsenic, implanted in intrinsic silicon may cause the intrinsic silicon to become conductive as a semiconductor.
  • One or more dopant materials may be implanted into a target material.
  • Ion-implantation is usually characterized by dose and energy.
  • the dose is the number of ions that are implanted per area of target material.
  • the energy is the energy of the ions being implanted. More advanced semiconductor processing or fabrication technologies typically use higher dose and/or higher energy than older technologies.
  • high dose ion-implantation HDII
  • the ion dose may be greater than about 5x10 ions/cm and/or the average energy of the ions, before the ions impact the target or substrate, may be from about five thousand electron volts (KeV) to greater than 100 KeV.
  • Resist including photoresist is a radiation sensitive material that is used to form a patterned coating on a surface, for example, the surface of a substrate or target. Resists are used in the fabrication of semiconductor devices, for example, integrated circuits and silicon semiconductor devices. One use of resists in the fabrication of semiconductor devices is as a mask for selective ion-implantation of dopants into a semiconductor substrate. A layer of resist is applied to the surface of the semiconductor substrate, or to the surface of a layer on or within the substrate, such as an insulator layer above a semiconductor layer.
  • a portion of the resist is exposed to the radiation, such portion of the resist corresponding to either the area of the semiconductor to be implanted (positive resist) or to the area of the semiconductor not to be implanted (negative resist).
  • the resist is then exposed to a developer which assists in removing a portion of the resist so that only the desired portion of the resist remains.
  • Positive resist is a type of resist in which the portion of the resist that is exposed to the radiation becomes soluble to, and removed by, the resist developer. The portion of the resist that is unexposed remains insoluble to, and is not removed by, the resist developer.
  • Negative resist is a type of resist in which the portion of the resist that is exposed to the radiation becomes insoluble to, and not removed by, the photoresist developer.
  • the portion of the resist that is not exposed to radiation remains soluble to, and is removed by, the resist developer.
  • the soluble portion of resist is dissolved by the resist developer.
  • Ion-implantation occurs after the resist is patterned by exposure to the radiation and developed by the developer.
  • the remaining portion of the resist blocks the implanted ions from reaching the semiconductor, or other material, below the resist.
  • the ions blocked by the resist are implanted into the resist instead of the underlying substrate.
  • the portions of the semiconductor not covered by resist are ion- implanted.
  • the radiation to which various resists are sensitive encompasses a relatively broad range.
  • the radiation may be within ultraviolet light (e.g., about 300 to 400 nm (nanometers)), deep ultra violet light (DUV; e.g., about 10 to 300 nm), G, H and I lines of mercury- vapor lamps (approximately 436 nm, 404.7 nm and 365.4 nm respectively), and x-rays (e.g., approximately 0.01 to 10 nm).
  • the radiation may alternately comprise electron beam (e- beam) radiation.
  • DUV light comprising a wavelength of approximately 193 nm and light comprising a wavelength of approximately 248 nm are often used for the radiation.
  • the photolithographic technologies comprising radiations of approximately 193 and 248 nm are called 193 nm lithography and 248 nm lithography, respectively,
  • the resist Because of the relatively high dose and/or high energy of the implanted ions blocked by the resist, the resist forms a crust or hard shell on the outer portions or outer sides of the resist where the ions impact and are absorbed.
  • the resist material that absorbs the ions is hardened by the ions.
  • the ions that are absorbed by the resist are ions that are blocked by the resist from being implanted into the semiconductor or other material below the resist.
  • the resist hardening may result from, or be referred to as, carbonization, polymerizing or polymer cross-linking.
  • the ions penetrating into the outer regions of the resist may cause the outer regions of the resist (e.g., top and sides of the resist) to become a crust, and chemical bonds in the inner regions of the resist close to the outer regions to become cross-linked.
  • the crust is known to be difficult to remove during a resist stripping process (e.g., the crust is insoluble in some known solvents used for stripping). Because the ions only penetrate a limited distance into the resist material, the crust is formed mostly on the outer portions of the resist. Because the bottom of the resist is covered by the implanted material or substrate, the crust may form on the top and side surfaces of the resist, but not on the bottom portion or in the interior portion of the resist.
  • the top crust is thicker than the side crust because the ions are usually implanted primarily with a downward direction of incidence.
  • the thickness of the resist crust is dependent upon the dosage of the implanted ions and the ion-implant energy.
  • the resist material that is inside or beneath the crust, that is, the portion of the resist that is generally unaffected by the ions, is referred to as bulk resist or bulk resist material.
  • the hardening or crusting of the resist for example, renders the outer portion of the resist insoluble, or less soluble, in water or in some other aqueous solutions (although, not necessarily in all other aqueous solutions or in all organic solvents).
  • Resist materials are often tailored for the wavelength of light, or the type of radiation, that they are meant to be exposed to. Such resist materials may be called with reference to the exposure wavelength, or to the type of radiation, for the resist material.
  • resist materials may be referred to as G-line, I-line, DUV (including 193 nm and 248 nm names), x-ray and e-beam.
  • High dose ion-implantation strip is the process of stripping exposed resist that has received HDII.
  • Some HDIS processes may include dry processes, such as plasma processes and vacuum processes.
  • Characteristics of an HDIS process may include, for example, strip rate, amount of residue, and loss of the exposed and underlying layer, such as the substrate, silicon substrate or layers above silicon. Residues are sometimes found on the substrate surface after an HDIS. The residues may result from, for example, sputtering during HDII, incomplete removal of the outer layer of resist, and/or oxidation of implanted ions in the resist. Optimally, after stripping and, optionally, rinsing, the surface should be substantially residue free to ensure high yield and eliminate the need for additional residue removal processing.
  • An example of additional residue removal processing is overstripping, such as a continuation of the strip process past the point nominally required to remove photoresist. Overstripping sometimes removes some of the underlying functional device structure which may adversely affect device performance and yield, especially for ultra shallow junction devices fabricated technologies at or below about 32 nanometers, and for metal gate transistor fabrication technologies.
  • a solution is a homogeneous mixture composed of two or more substances.
  • one or more solutes may be dissolved in a solvent.
  • Solutions may comprise, for example, liquids dissolved in other liquids.
  • the ability of one compound to dissolve in another compound is called solubility. Physical properties of compounds may change when other compounds are added.
  • metal gate or metal gate electrode includes gate electrodes of transistors (e.g., FET) comprising metal.
  • the metal may be in combination with other material.
  • Metals in the metal gates include, but are not limited to, Ti, Ta, W, Mo, Ru, Al, La, titanium nitride, tantalum nitride, tantalum carbide, titanium carbide, molybdenum nitride, tungsten nitride, ruthenium (IV) oxide, tantalum silicon nitride, titanium silicon nitride, tantalum carbon nitride, titanium carbon nitride, titanium aluminide, tantalum aluminide, titanium aluminum nitride, tantalum aluminum nitride, lanthanum oxide, or combinations thereof.
  • TiN titanium nitride
  • TiN x titanium nitride
  • TaN x tantalum nitride
  • Ashing is an exemplary stripping process for resist that has not undergone HDII. Ashing involves heating the resist to a sufficiently high temperature to cause the resist to be removed through volatilization, usually while interacting with an oxidizing plasma. Ashing is a problematic method for stripping resist material that has been used as an ion-implantation mask, especially for HDII, because the resulting resist crust is resistant to the ashing process. As temperature increases, the pressure of the volatile bulk resist, underneath or inside of the crust, increases causing the bulk resist to breakthrough or "pop" through the resist crust. Such popping causes fragments of the resist crust to be spread over the surface of the wafer, strongly adhering to the wafer surface.
  • Removal of resist crust fragments from the wafer surface may be difficult or impossible, causing, for example, severe yield degradation for devices being formed within a wafer substrate.
  • the removal of the resist crust should be performed at temperatures low enough to prevent popping. In general, using temperatures low enough to prevent popping may prolong the time required for resist removal, lowering wafer throughput (i.e., wafers processed per unit time).
  • a problem called "bulk resist undercut" may occur when a thinner side crust is removed before a thicker top crust, causing the bulk resist to be removed beneath the upper crust, which is not completely removed at the time. Bulk resist undercut may cause pieces of top crust to break free and contact the substrate, strongly adhering to the substrate and, for example, reducing yield of devices formed within the substrate.
  • complete or substantially complete removal of resist, including resist crust, from the wafer is needed to enable acceptable yield of devices being formed in or on the substrate (e.g., a semiconductor or silicon wafer).
  • resist stripping As outlined above, three important aspects of resist stripping are: (i) stripping at relatively low temperatures (e.g., low enough to prevent popping); (ii) relatively short times for resist stripping to allow for acceptable wafer throughput; and (iii) substantially complete removal of resist from the substrate surface.
  • a fourth important aspect of resist stripping concerns damage to the substrate, or undesirable removal of a portion of the substrate, that may result from resist stripping. Such damage is undesirable, for example, because it may cause structures and devices formed in or on the substrate (e.g., transistors or other electronic devices formed in or on a semiconductor wafer or silicon wafer) not to function or to function poorly.
  • Silicon may be defined to include, Si, polycrystalline Si, monocrystalline Si, and SiGe as well as other silicon-containing materials such as silicon oxide, thermal oxide, SiOH and SiCOH. Silicon is comprised in silicon-on-insulator (SOI) wafers that may be used, for example, as substrates or part of a substrate for electronic devices such as FETs and integrated circuits. Other types of wafers may also comprise silicon.
  • SOI silicon-on-insulator
  • damage to, or removal of, substrate material examples include, but are not limited to, damage to, or removal of, silicon or titanium nitride (Ti ), for example, Ti comprised in a metal gate of an FET or TiN comprised in a barrier between a semiconductor and a metal.
  • the damage for example, may involve dissolution (etching), conversion to different solid phases such as oxides, or a combination of both.
  • Embodiments of the invention are directed towards effective removal of post ion-implantation resist, which may be used, for example, as a block mask in silicon, other semiconductor technology and micro-electro-mechanical (MEM) technologies.
  • post ion-implantation resist which may be used, for example, as a block mask in silicon, other semiconductor technology and micro-electro-mechanical (MEM) technologies.
  • Commonly known processes for resist removal involves either a combination of dry etching (e.g., plasma etch, vacuum processes) and wet etch (e.g., chemical etch), or a wet etch using sulfuric-acid-based chemistries, such as a mixture of sulfuric acid and hydrogen peroxide (SPM).
  • SPM sulfuric-acid-based chemistries
  • a common drawback of many known resist strip methodologies currently used includes incomplete removal of crusted photoresist present on the wafer surface after ion-implantation.
  • Methods of the invention are useful for stripping resist that has been implanted with HDII, for example, implanted with about 5x10 14 or more ions/cm 2 and/or at energies above about 5 KeV.
  • methods of the invention are not so limited and may be useful for stripping resist that has been implanted with fewer than 5x10 14 ions/cm 2 and at energies below 5 KeV.
  • Methods of the invention may be useful for stripping resists that are patterned by procedures including exposed to one of the following types of radiation: e-beam, x-rays, and light of wavelengths corresponding to G-line, H-line, I-line DUV, about 248 nm and about 193nm.
  • Embodiments of the invention include methods for HDIS comprising, for example, temperatures lower than about 90 degrees centigrade (C) (e.g., about 35 to 90C, and/or low enough to prevent popping), reasonable times that are less than about 80 minutes to perform the HDIS (e.g., about 5 to 75 minutes), substantially complete removal of the resist (e.g., about 99% removal), and minimal or no damage to or removal of substrate material (e.g., less than approximately 50 angstroms removal of TiN, no or minimal silicon loss, and limited oxidation of components in a SOI wafer).
  • HDIS according to methods of the invention may result in little or no remaining resist or resist crust residue, for example, either in solution or deposited on the wafer.
  • Embodiments of the invention use oxidation chemistry to react with ion-implanted resist to make the resist soluble in common solvents (e.g., water).
  • the oxidation chemistry may include, for example, oxidation functional groups or chemical bonds.
  • the crusted portion, or polymer containing portion, of the resist is made completely or substantially soluble.
  • Embodiments of the invention as will be described herein, further provide stable aqueous solutions containing the lanthanoid element cerium, or a salt comprising cerium, which is capable of stripping high density ion-implanted resist.
  • Embodiments of the invention as will be described herein, are useful for many technologies including, but not limited to, integrated circuit fabrication technologies commonly known as 32 or less nanometer technologies.
  • Embodiments of the invention may be used, for example, to form electronic devices, such as FETs, or to form source, drain and channel regions of FETs by blocking dopants (e.g., ion-implanted dopants) from entering other than the source, drain or channel region that is being implanted.
  • Embodiments of the invention may be used, for example, to form conductors, by masking regions that are to be the conductors or are to be regions other than the conductors.
  • FIG. 1 generally shows a method 100 for the removal of a masking material from a substrate, according to an exemplary embodiment of the invention.
  • the method may be a method of HDIS.
  • Method 100 may, for example, involve wet chemistry without the use of plasmas or vacuum processes.
  • Method 100 may be considered a wet-only method not involving dry processing (i.e., processing involving plasma or vacuum processes), although it should be appreciated by those skilled in the art that further dry processing, before or after wet processing, is contemplated.
  • Step 110 of method 100 comprises providing the substrate.
  • the substrate may be a wafer, for example, a semiconductor wafer, upon or within which electronic devices are formed.
  • the electronic devices may comprise transistors, such as FETs, including FETs comprising a metal gate (e.g., a metal gate comprising Ti ).
  • Some of the electronic devices may be partially formed when the wafer is provided, for example, ion-implantation of source/drain regions or a channel region may have been done prior to providing the wafer. By way of another example only, deposition of a TiN layer may have occurred prior to providing the wafer.
  • the masking material may be adhered to the top surface of the wafer.
  • the masking material may comprise a resist material, for example, a photoresist material.
  • the masking material may have been ion- implanted (e.g., HDII) during ion-implantation of a portion of the wafer not covered by the masking material.
  • the ion-implantation of the masking material may have caused a hardened, crusted, polymerized and/or carbonized outer layer to form in the masking material.
  • the outer layer of the masking material may not be easily soluble, for example, not easily soluble in a rinse, such as rinses described below in step 130 and in Table 1.
  • Step 120 of method 100 comprises contacting the substrate, including the adhered masking material, with a solution.
  • the solution comprises the lanthanoid element cerium.
  • cerium is disclosed as being the active element employed in the solution, it is to be understood that elements with the same or similar chemical characteristics as cerium could be used.
  • other lanthanoid elements may have some characteristics similar to cerium.
  • Lanthanoid elements are generally known to be those elements with atomic numbers 57 through 71, i.e., lanthanum, cerium, praseodymium, neodymium, promethium, samarium, europium, gadolinium, terbium, dysprosium, holmium, erbium, thulium, ytterbium, and lutetium.
  • the solution may comprise at least one salt or coordination complex of the element cerium.
  • the salt of cerium may be, for example, cerium ammonium nitrate.
  • the chemical formula for cerium ammonium nitrate may be expressed as Ce( H4)2( 0 3 ) 6 or ( H4)2Ce( 0 3 ) 6 .
  • Cerium ammonium nitrate is also known as CAN, cerium (IV) ammonium nitrate, ceric ammonium nitrate and ammonium cerium nitrate.
  • CAN as used herein, refers to cerium ammonium nitrate.
  • CAN is an orange, water-soluble salt that may be used as an oxidizing agent.
  • the solution may comprise more than one of the above salts of cerium.
  • the cerium salt comprises cerium ammonium nitrate.
  • the effective range of concentrations for the cerium salt is from about 0.01% to about 70% by weight, preferably about 0.01% to about 30% by weight, based on the total weight of the solution.
  • ceric solutions in water tend to hydrolyze and generate precipitates over time, especially when kept above ambient temperature (i.e., above about 20 to 25°C)
  • acid or other compounds as stabilizing agents may be employed in order to stabilize the solution.
  • Concentrated solutions of ceric salts in water are generally stable, but at elevated temperatures around 70°C, ceric salts generate precipitates due to hydrolysis and/or redox reactions.
  • CAN may be formulated in acidic or other stabilizing media in order to stabilize the solution and prevent or limit precipitation of the cerium.
  • the stabilizing agents act to reduce precipitation, for example, by dissolving precipitant from the solution (e.g., precipitation or precipitant of CAN or one or more of the components of CAN).
  • precipitant e.g., precipitation or precipitant of CAN or one or more of the components of CAN.
  • a 20% CAN solution in water may generate large amounts of precipitate and becomes completely opaque after about 30-45 minutes, which is a relatively short period of time, at about 70°C.
  • the solvent comprises about 5.5% nitric acid and about 74.5% water, there is virtually no precipitate even after 24 hours.
  • Stabilizing agents contemplated include, but are not limited to, ammonium salts, strong acids, salts of weak bases, and any combination thereof.
  • One or more stabilizing agents may be used.
  • the solution may further comprise an ammonium salt, for example, in addition to the ammonium compound in CAN. Addition of ammonium salts can also help stabilize the solution.
  • Ammonium salts include, but are not limited to, at least one of ammonium chloride, ammonium nitrate, ammonium hydroxide (i.e., ammonia), ammonium sulfate
  • H ⁇ SC ammonium bisulfate, ammonium acetate, ammonium perchlorate (NH 4 CIO 4 ), ammonium trifluoro acetate (ATFA), ammonium methanesulfonate, ammonium carboxylate, ammonium ⁇ -diketonate, and ammonium trifiuoromethane sulfonate.
  • a solution comprising about 20% CAN and about 12% ammonium nitrate in water remains clear at 70°C for about 2.5 hours, compared with less than one hour for CAN alone.
  • Ammonium chloride ammonium bisulfate, ammonium acetate, ammonium perchlorate (NH 4 CIO 4 ), ammonium trifluoro acetate (ATFA), ammonium methanesulfonate, ammonium carboxylate, ammonium ⁇ -diketonate, and ammonium trifiuoromethane sulfonate.
  • the stabilizing agent comprises ammonium trifluoro acetate.
  • a 20% CAN solution containing 4% ammonium trifluoroacetate remains transparent for about 14 hours at 70°C.
  • Other compounds that are stabilizing agents for formulations of CAN and water include, but are not limited to, salts of weak bases and strong acids.
  • Acids contemplated include, but are not limited to, one or more of nitric acid, hydrochloric acid, sulfuric acid, perchloric acid, glacial acetic acid, periodic acid, methanesulfonic acid, trifluoromethanesulfonic acid, trifluoro acetic acid and polysulfonic acid (e.g., poly(4-styrenesulfonic acid).
  • polysulfonic acid e.g., poly(4-styrenesulfonic acid
  • other water soluble polymers may be added including, but not limited to, polyacrylic acid, polymethacrylic acid, and polymeric acid.
  • polymeric acid include, but are not limited to, polymaleic acid, polytetrafiourosulfonic acid, poly(ethylene-maleic) acid and polystyrene carboxylic acid.
  • the effective range of concentrations for these stabilizers is from about 0.01% to about 60% by weight, preferably about 0.5% to about 25% by weight, based on the total weight of the solution.
  • any combination of the aforementioned stabilizing agents is contemplated: ammonium salts only, strong acids only, salts of weak bases only, or any combination of ammonium salts, strong acids, and salts of weak bases.
  • the solution comprises CAN and perchloric acid
  • the solution preferably is not used to etch chromium films.
  • ammonium trifluoroacetate can be generated in situ by combining ammonia and trifluoro acetic acid (TFA).
  • TFA trifluoro acetic acid
  • the molar ratio of ammonia relative to TFA may be varied to increase stabilization of the solution.
  • the molar ratio of NH 3 to TFA is in a range from greater than about 0.8:1 to about 5:1, preferably about 2:1 to about 3: 1.
  • the molar ratio of ammonia to CAN is in a range from greater than about 1 : 1 to about 2:1, preferably about 1.2:1 to about 1.7:1. It should be appreciated that these ratios are exemplary and may be varied as necessary to effectively remove masking material, as readily determined by the skilled artisan.
  • the solution may further comprise other solutes or solvents.
  • the solution may further comprise water (H 2 O) as a solvent, such as deionized water (DI water).
  • DI water deionized water
  • Embodiments include about 1 wt% to about 40 wt% cerium salt and about 60 wt% to about 99 wt% DI water, preferably about 5 wt% to about 35 wt% cerium salt and about 65 wt% to about 95 wt% DI water, even more preferably about 10 wt% to about 30 wt% cerium salt and about 70 wt% to about 90 wt% DI water, and most preferably about 15 wt% to about 25 wt% cerium salt and about 75 wt% to about 85 wt% DI water, based on the total weight of the solution.
  • An exemplary formulation of the solution comprises approximately 20% by weight CAN and about 80% by weight DI water.
  • Alternate formulations are contemplated, for example, formulations comprising CAN and aqueous acidic solutions, including oxidation-resistant acids such as acetic, methanesulfonic, trifluoroacetic, and other fluorinated carboxylic acids.
  • Oxidation-resistant solvents are also contemplated as part of the formulation, e.g,. sulfolane and nitromethane.
  • the eerie solutions may further include at least one additional oxidant.
  • Additional oxidants contemplated include at least one of ruthenium (Ru), iridium (Ir), manganese (Mn) and osmium (Os) containing compounds.
  • oxidants including, but not limited to, Ru0 4 , Os0 4 , KMn0 4 , NH 4 Mn0 , RuCl 3 , OsCl 3 , Ru(N0 3 ) 3 , Os(N0 3 ) 3 , Mn(N0 3 ) 2 xH 2 0, MnC0 3 , MnSCvxFbO, Mn(C 2 H 3 0 2 ) 2 'xH 2 0, MnCl 2 , MnBr 2 , and combinations thereof.
  • the additional oxidant species may be generated in situ when in the presence of Ce(IV).
  • R11O4 is expensive and toxic, however, because it can be regenerated in situ in the presence of Ce(IV), lower concentrations of Ru0 4 and Ce(IV) can be used.
  • a lower valence Ru, Ir, or Os salt, e.g. RuCl 3 can be used as it will generate the oxidized form, e.g. RuO/t, in situ by reaction with Ce(IV).
  • Mn(II) salts are oxidized to a Mn(VII) salt, i.e., permanganate (Mn0 4 ⁇ )), which should enhance the oxidation activity of other oxidants present in the composition, e.g., cerium.
  • the additional oxidant can be ⁇ ( ⁇ 0 3 )2 ⁇ 2 0, MnC0 3 , MnSCVxF ⁇ O, or a combination thereof, wherein the Mn(II) ion is oxidized to Mn(VII) in the presence of Ce(IV).
  • the advantages associated with including an additional oxidant include the presence of two oxidants and the regeneration of reacted permanganate in the presence of Ce(IV).
  • the additional oxidant comprises ⁇ ( 0 3 )2 ⁇ 2 0, MnC0 3 , MnSCVxF ⁇ O, or a combination thereof.
  • the additional oxidant comprises ⁇ ( ⁇ 0 3 ) 2 ⁇ 2 ⁇ .
  • chromium added as a Cr 3+ salt, which is oxidized in situ to chromate or dichromate
  • vanadium added as a V0 2+ salt, which is oxidized in situ to V 5+
  • bromine added as a bromide, e.g., ammonium bromide or manganese bromide, which is oxidized to bromate, Br0 3 "
  • iodine which can be added, for instance, as ammonium iodate which is oxidized to periodate.
  • the high oxidation state can also be added directly to the initial solution, for example as ammonium dichromate for Cr, ammonium bromate for Br, periodic acid for I, and ammonium persulfate for active oxygen. It should be appreciated by those skilled in the art that the aforementioned compounds can be added either as the neat solid or as an aqueous solution, depending on solubility and ease of dissolution of the additive and on other process considerations.
  • the solutions of the invention can further include at least one surfactant selected from the group consisting of anionic, nonionic, cationic and zwitterionic surfactants, preferably at least one non-ionic surfactant.
  • suitable non-ionic surfactants may include fluorosurfactants, ethoxylated fluorosurfactants, polyoxyethylene- polyoxypropylene block co-polymers, alkylphenol ethoxylates, castor oil ethoxylates, fatty acid ethoxylates, alkyl ethoxylates, alkylphenyl ethoxylates, polyoxyethyleneglycol dodecyl ethers, fluorinated polyethers, as well as combinations comprising at least one of the foregoing.
  • the nonionic surfactant may be an ethoxylated fluoro surfactant such as ZONYL® FSO- 100 or FSN-100 fluoro surfactants (DuPont Canada Inc., Mississauga, Ontario, Canada), a polyoxyethylene-polyoxypropylene block co-polymers such as PLURONIC® 17R4 or 25R4 (BASF), a polyoxyethyleneglycol dodecyl ether such as BRIJ® 35P, a alkylphenol ethoxylate such as TRITON® X-100, a castor oil ethoxylate such as SURFONIC® CO (Huntsmen Chemical, Texas, USA), a fatty acid ethoxylate such as SURFONIC® E-400 MO (Huntsmen Chemical, Texas, USA), DYNOL® 604 (Air Products), a fiuorinated polyether such as POLYFOXTM PF-159 (Omnova Solutions, Inc.), and combinations thereof.
  • the nonionic surfactant may be ZONYL® FSO-100, FSN-100, PLURONIC® 17R4, PLURONIC® 25R4, BRIJ® 35P, SURFONIC® CO-42, SURFONIC® E-400 MO, POLYFOXTM PF-159, and combinations thereof.
  • Anionic fluoro surfactants can also be used, for example, fluoro surfactants such as ZONYL® UR and ZONYL® FS-62 (DuPont Canada Inc., Mississauga, Ontario, Canada), ammonium fluoroalkylsulfonates such as NOVECTM4300 (3M), perfluoroalkylsulfonic acids such as CAPSTONETM FS-10 (DuPont), sodium alkyl sulfates such as sodium ethylhexyl sulfate (NIAPROOF® 08), ammonium alkyl sulfates, alkyl (C] 0 -C 18 ) carboxylic acid ammonium salts, sodium sulfo succinates and esters thereof, e.g., dioctyl sodium sulfo succinate, alkyl (C 10 - C 18 ) sulfonic acid sodium salts, the di-anionic sulfonate surfactants Dow
  • Embodiments of the solution of the invention include, but are not limited to, (i) a solution comprising, consisting of, or consisting essentially of, cerium salt and solvent, (ii) a solution comprising, consisting of, or consisting essentially of, cerium salt, solvent, and ammonium salt, (i) a solution comprising, consisting of, or consisting essentially of, cerium salt, solvent and acid, (iv) a solution comprising, consisting of, or consisting essentially of, cerium salt, solvent, ammonium salt and acid, (v) a solution comprising, consisting of, or consisting essentially of, cerium salt, solvent, acid and additional oxidant(s), (vi) a solution comprising, consisting of, or consisting essentially of, cerium salt, solvent, acid and manganese (II) salt, (vii) a solution comprising, consisting of, or consisting essentially of, cerium salt, solvent, ATFA, and additional oxidant(s), (viii
  • Solution formulations that may be effective include, but are not limited to, solutions comprising about 2% to about 70% CAN and a solvent.
  • solvents include, but are not limited to, solvent compositions comprising about 1% to about 55% concentrated perchloric acid, about 5% to about 60% acetic acid, about 1% to about 50% nitric acid (HNO 3 ), about 1% to about 50% sulfuric acid, about 1% to about 50% methanesulfonic acid (CH3SO3H), about 1%) to about 55% trifluoromethanesulfonic acid (CF3SO3H), and/or about 1% to about 55% polysulfonic acid (e.g., polystyrenesulfonic acid).
  • solvent compositions comprising about 1% to about 55% concentrated perchloric acid, about 5% to about 60% acetic acid, about 1% to about 50% nitric acid (HNO 3 ), about 1% to about 50% sulfuric acid, about 1% to about 50% methanesulfonic acid (CH
  • the solutions may comprise only one or more than one acid.
  • a substrate may be immersed in an aqueous solution of about ten to about seventy-five percent polysulfonic acid.
  • concentration of the polysulfonic acid used may be from about ten to about fifty percent concentrated polysulfonic acid in water.
  • the polysulfonic acid may be, for example, polystyrenesulfonic acid.
  • the solution formulation is diluted to a CAN concentration less than about 10% by weight, preferably in a range from about 0.5% to about 8% by weight, even more preferably about 1% to about 6%, based on the total weight of the solution.
  • This "dilute solution” may be substantially devoid of stabilizing agent or alternatively, include stabilizing agent.
  • the dilute solution can comprise, consist of or consist essentially of CAN and water.
  • the dilute solution can comprise, consist of or consist essentially of CAN, at least one stabilizing agent, and water.
  • the dilute solution can be prepared by diluting a higher concentration CAN solution.
  • the dilute solution can be prepared by adding solid CAN to water, e.g., warm or boiling water as necessary to effectuate dissolution of the CAN therein. It should be appreciated that when the term "solution" is used in the process descriptions that it corresponds to any of the solutions described herein, dilute or otherwise.
  • the substrate may contact the solution by immersion of the substrate in the solution. Other methods of contact are also contemplated, for example, spraying, rinsing or washing the substrate with the solution, and agitating the substrate in the solution.
  • the substrate is typically contacted with the solution for a specific time duration. Time durations between about 5 and about 60 minutes are examples of effective time durations for the contacting the substrate with the solution.
  • the process of stripping resist can also be carried out in a spray batch tool or a single wafer apparatus, the latter of which would have several advantages including, but not limited to, the option to use low flash point solvents under a nitrogen atmosphere for the optional pre- treatment and/or post-treatment steps, more volatile oxidant-resistant components could be combined with the cerium-containing compound, and the temperature of the cerium-containing compound treatment step could be raised to closer to 100°C in order to shorten the process.
  • a process may be designed for a multiple- wafer spray tool, whereby a dilute solution as described herein is economically mist-sprayed (e.g., 1-2 liters/min) on a large batch of wafers (e.g., FSI's Zeta tool).
  • a hermetically closed chamber may be used that can take modest pressurization.
  • a similar process may be developed that would operate at higher temperatures (e.g., 130-150°C) and would be much faster, further saving both solution and processing time.
  • the solution and/or the substrate may be heated to and/or maintained at a specific temperature or within a specific temperature range. Temperatures low enough to prevent popping of the masking material are preferred. Other considerations may also dictate an upper limit on the temperature range, for example, the boiling point of water. Temperatures between about 35 and 90°C are examples of effective temperatures for the solution for the performance of step 120.
  • the solution may remove at least a portion, if not substantially all, of the masking material. In the best case, the solution may remove all (100%) of the masking material. Contact of the substrate and the adhered masking material to the solution may change one or more characteristics of the masking material. Contact of the substrate and the adhered masking material to the solution may make the masking material, especially the outer portion or the crust of the masking material, soluble, or more soluble than before contact with the solution. For example, the masking material may be made soluble, or more soluble, to the liquid or rinses of step 130 and Table 1 (see below). Consequently, the rinse described in step 130 may remove all or some of the remaining portion of the masking material by dissolving the masking material. The rinse may additionally or alternately mechanically remove (e.g., flush, rinse or wash off) masking material.
  • the rinse may additionally or alternately mechanically remove (e.g., flush, rinse or wash off) masking material.
  • Step 130 of method 100 is contacting the substrate, and any remaining masking material adhered to the substrate, with a rinse.
  • step 130 occurs after step 120.
  • the rinse removes some or all of the remaining masking material from the surface of the substrate.
  • the rinse removes substantially all of the remaining masking material, or at least enough of the remaining masking material to allow reasonable or desired yield of electronic devices that are being formed in or upon the substrate.
  • the remaining masking material may comprise all or a portion of the outer layer and/or all or a portion of the bulk material. All or a portion of the outer layer may have been previously made soluble to the rinse by step 120.
  • the substrate may contact the rinse by immersion of the substrate in the rinse. Other methods of contact are also contemplated, for example, spraying or washing the substrate with the rinse and agitating the substrate in the rinse.
  • the substrate is typically contacted with the rinse for a specific time duration. Exemplary time durations will be shown in later experimental descriptions of the method.
  • the rinse and/or the substrate may be heated to and/or maintained at a specific temperature or within a specific temperature range. Temperatures between approximately 55 and approximately 90°C are effective.
  • the rinse may comprise, for example, sulfuric acid (H2SO4) or sulfuric acid and water (e.g., DI water).
  • the rinse may comprise a single rinsing or a sequence of rinsing procedures.
  • the rinse may comprise a single rinsing in water, sulfuric acid or sulfuric acid and water.
  • An example of a sequence of rinsing procedures is an initial rinse in water followed by a rinse in sulfuric acid or sulfuric acid and water, and, optionally followed by another rinse in water. Additional rinses are contemplated. Drying may occur between rinses, after the final rinse, and between contacting the solution and the initial rinse. Drying may take place in an atmosphere comprising nitrogen (N 2 ).
  • the process of masking material removal comprises a pre-rinse of the substrate (e.g., with dilute or concentrated sulfuric acid), contact of the substrate with the solution (or dilute solution), and a post-rinse of the substrate (e.g., with dilute or concentrated sulfuric acid).
  • a pre-rinse of the substrate e.g., with dilute or concentrated sulfuric acid
  • a post-rinse of the substrate e.g., with dilute or concentrated sulfuric acid
  • a brief rinse with a dilute SCI solution is optional. In between the various chemical rinses, the substrate is rinsed with deionized water.
  • steps 120 and 130 are sufficient to remove all, nearly all, or substantially all (e.g., about 100%) of the masking material. Steps involving plasma, plasma etching or vacuum processes are not required, although may be used when preferred, as readily determinable by one skilled in the art.
  • the process described herein effectively and efficiently removes masking material from a substrate, wherein the masking material is comprised within a layer formed on at least a first portion of a substrate, and wherein the masking material blocks at least a first portion of dopant material from contacting the at least a first portion of the substrate.
  • the masking material comprises a resist exposed to at least one of: (i) light comprising one or more wavelengths between approximately 10 and approximately 400 nanometers; (ii) x-ray radiation, and (iii) electron beam radiation.
  • the first portion of the dopant material comprises ions implanted into the masking material, wherein the ions comprise at least one of: boron; boron trifluoride; indium; gallium; germanium; bismuth; arsenic; phosphorus; xenon and antimony.
  • the substrate may further include a second portion of dopant material which comprises ions implanted into a second portion of the substrate.
  • the process comprises the removal of at least a first portion of the masking material by the solution, and contacting the masking material with a liquid to remove a second portion of the masking material.
  • the liquid comprises at least one of: water; an acid; and sulfuric acid (H 2 SO 4 ).
  • the wafer and the tool may be contacted with a particle removal solution to dissolve and/or remove Ce(IV)-containing precipitates.
  • a particle removal solution may be contacted to the wafer before a rinsing step, after a rinsing step, or before and after a rinsing step.
  • Method 100 may be considered as a method for forming or fabricating, at least in part, an electronic device, for example an FET, an integrated circuit or a MEM, for example a micro- electro-mechanical system (MEMS).
  • an electronic device may be formed by forming a substrate (e.g., a substrate comprises titanium nitride), ion-implanting (e.g., HDII) photoresist, and contacting the photoresist with a solution comprising cerium (e.g., CAN) or a solution comprising cerium and at least one additional oxidant.
  • a substrate e.g., a substrate comprises titanium nitride
  • ion-implanting e.g., HDII
  • a MEM or a MEMS is a device fabricated with the integration of mechanical element (e.g., switches, sensors or actuators) and electronics (e.g., transistors, inductors, resistors, electronic memory elements, capacitors, and electronic conductors) on a common substrate (e.g., a substrate comprising silicon and/or TiN) through micro-fabrication technology.
  • the micro- mechanical components are fabricated, for example, using micro -machining processes that selectively etch away parts of the silicon wafer or add new structural layers.
  • a MEM is commonly fabricated on silicon substrates using processes compatible with complimentary- metal-oxide-semiconductor (CMOS) IC technology. Fabrication of a MEM may comprise resist removal according to embodiments of the present invention.
  • CMOS complimentary- metal-oxide-semiconductor
  • Method 100 and other methods of the invention may comprise, for example, reduction of water or acid soluble cerium (IV) compounds to cerium (III) compounds that sometimes are water insoluble.
  • Control of the acidity or the pH of the solution controls the solubility of cerium salts and when present, the at least one additional oxidant, that are in mixture or solution.
  • the acidity or the pH may be controlled, for example, by the amount of acid in an aqueous acid solution (i.e., a solution comprising acid and water as well as the cerium), such as the solutions of Examples 2 and 3 below. Even in the absence of added acid, partial hydrolysis of Ce(IV) ensures a low pH.
  • the pH of the solutions is less than 3, preferably less than 2, and most preferably less than 1 but not less than 0 since very high acid concentration can cause excessive etching of some gate materials, e.g., TiN.
  • Table 1 illustrates four examples of implementation of method 100. All examples are for the removal of resist (i.e., masking material) from a substrate to which the resist is adhered.
  • the resist is implanted with arsenic ions at the indicated dose and energy.
  • Step 110 of method 100 comprises providing the above described substrate with adhered resist.
  • Example 1 Example 2 Example 3 Example 4
  • the solution of method 100 comprises approximately 20% CAN and approximately 80% DI water.
  • the substrate is immersed in (i.e., contacts) the solution for approximately 30 minutes after the solution has been heated to approximately 70C. This immersion in the solution is comprised in step 120 of method 100.
  • the substrate is removed from the solution, rinsed by immersion for approximately 30 seconds in DI water, and dried in a nitrogen (N 2 ) containing atmosphere. This rinse is comprised in step 130 of method 100.
  • the solution of method 100 comprises approximately 15% CAN and approximately 85% solvent.
  • the solvent comprises approximately 10% of concentrated perchloric acid (HC10 4 ) in DI water (i.e., about 10% concentrated perchloric acid and about 90% water).
  • Concentrated perchloric acid comprises about 70% perchloric acid and, for example, about 30% water.
  • the substrate is immersed in the solution for about 30 minutes after the solution has been heated to approximately 60C. This immersion in the solution is comprised in step 120 of method 100.
  • the substrate is removed from the solution and undergoes a first rinsing procedure by immersion for about 30 seconds in DI water.
  • the substrate is then dried in a nitrogen containing atmosphere.
  • the substrate then undergoes a second rinsing procedure comprising immersion in concentrated sulfuric acid (i.e., about 96.5% sulfuric acid and about 3.5% DI water) for approximately 15 minutes after the sulfuric acid solution has been adjusted to a temperature of approximately 19C.
  • the substrate then undergoes a third rinsing procedure comprising a brief rinse in running DI water.
  • the running water may be at or near room temperature and the duration of the third rinsing procedure may be about 1 minute or less.
  • the substrate is then dried in a nitrogen containing atmosphere. This rinse, including the first, second and third rinsing procedures, is comprised in step 130 of method 100.
  • the solution of method 100 comprises approximately 20% CAN and approximately 80% solvent.
  • the solvent comprises approximately 50% glacial acetic acid (CH 3 COOH), in DI water (i.e., about 50% glacial acetic acid and about 50% DI water).
  • the substrate is immersed in the solution for approximately 60 minutes after the solution has been heated to approximately 70C. This immersion in the solution is comprised in step 120 of method 100.
  • the substrate is removed from the solution and undergoes a first rinsing procedure by immersion for about 30 seconds in DI water.
  • the substrate is then dried in a nitrogen containing atmosphere.
  • the substrate then undergoes a second rinsing procedure comprising immersion in concentrated sulfuric acid (i.e., about 96.5% sulfuric acid and about 3.5% DI water) for approximately 15 minutes after the sulfuric acid solution has been adjusted to a temperature of approximately 19C.
  • the substrate then undergoes a third rinsing procedure comprising a brief rinse in running DI water.
  • the running water may be at or near room temperature and the duration of the third rinsing procedure may be about 1 minute or less.
  • the substrate is then dried in a nitrogen containing atmosphere.
  • This rinse including the first, second and third rinsing procedures, comprises step 130 of method 100.
  • the solution of method 100 comprises approximately 55% CAN and approximately 45% DI water.
  • the substrate is immersed in the solution for approximately 15 minutes after the solution has been heated to approximately 80C. This immersion in the solution is comprised in step 120 of method 100.
  • the substrate is removed from the solution, rinsed by immersion for about 30 seconds in DI water, and dried in a nitrogen containing atmosphere. This rinse is comprised in step 130 of method 100.
  • TiN was chosen because TiN is comprised in metal gates of some FETs, for example, FETs formed, in part, using illustrative methods of the invention.
  • the experiment comprised exposing TiN deposited upon a wafer to a 20% aqueous solution of CAN for varying times at two temperatures and measuring the thickness of a titanium oxide (TiO x ) layer formed from titanium formerly within the TiN layer before the wafer and TiN were exposed to the CAN. The thicknesses of the remaining TiN layer and the remaining SiOxide layer were also measured (i.e., thicknesses remaining after immersion in CAN).
  • TiO x titanium oxide
  • step 110 comprised providing a silicon wafer coated with approximately ( ⁇ ) 2000 angstroms of silicon oxide (SiOxide) and a nominally (approximately) 130 angstrom layer of TiN over the layer of SiOxide.
  • SiOxide silicon oxide
  • step 110 comprised providing a silicon wafer coated with approximately ( ⁇ ) 2000 angstroms of silicon oxide (SiOxide) and a nominally (approximately) 130 angstrom layer of TiN over the layer of SiOxide.
  • the provided wafer as coated is called the original wafer. All temperatures, times and dimensions given in Table 2 are approximate.
  • Step 120 comprised immersion of the wafer in a solution of approximately 20% CAN and approximately 80% DI water for the times and temperatures indicated in the table.
  • Step 130 comprised rinsing the wafer in DI water after the immersion in the solution and drying in an atmosphere comprising nitrogen. Subsequent to immersing in CAN, rinsing and drying, the thicknesses of the remaining layers were measured by reflectometry. As shown in the table, the remaining layers comprise an upper layer of TiO x , a TiN layer that is a remaining portion of the original TiN layer before immersion in CAN, and the SiOxide layer that is substantially the original SiOxide layer before immersion in CAN. A control wafer was not immersed in CAN.
  • an approximately 4 angstrom thick TiO x layer was measured and an approximately 110 angstrom thick TiN layer was measured.
  • the measured approximately 4 angstroms thick TiO x layer and the measured apparent decrease from approximately 130 to approximately 110 angstroms in thickness (i.e., an approximately 20 angstrom thickness difference) of the TiN layer are not due to CAN, but have other causes, for example, oxidation of TiN not due to CAN or experimental error.
  • the table shows that for wafer 2, immersed in CAN at approximately 85°C for about 60 minutes, the TiN layer is reduced from a control wafer thickness of about 110 angstroms to about 80 angstroms and a TiOx layer has formed that is about 35 angstroms thick, that is, about 31 angstroms thicker than for the control wafer. Thicknesses of TiN layers and TiO x layers, as shown in the table, are acceptable for an HDIS strip and for device fabrication.
  • FIG. 2 shows the results of an x-ray photoelectron spectroscopy (XPS) analysis of the control wafer and wafer 5 of Table 2.
  • Trace 210 represents the control, that is, the wafer prior to immersion in the CAN solution.
  • Trace 220 represents wafer 5 after immersion.
  • the peak centered between binding energies of about 458 and 449 electron volts (EV) corresponds to oxidized titanium, most likely in the form of titanium oxide.
  • the peak that appears as a shoulder centered between binding energies of about 456 and 457 electron-volts corresponds to titanium nitride. From the XPS data the TiO x thickness can be qualitatively estimated to no less than about 20 to 30 angstroms.
  • Table 3 shows the effect of processing with a solution comprising CAN on samples of a silicon wafer, a portion of a silicon-on-insulator (SOI) wafer, a portion of a wafer coated with a 193 nm sensitive resist, and TiN. All temperatures and times given in Table 3 are approximate.
  • the samples were processed by immersion in a solution of approximately 20% CAN and approximately 80% DI water for the indicated times and at the indicated temperatures.
  • a sulfuric rinse for about 5 minutes at or near room temperature (RT).
  • Analysis of the samples after immersion and rinsing (if any) was by XPS, and for the silicon wafer sample, additionally by total reflection x-ray fluorescence analysis (TXRF).
  • Cerium was not detected in the post- processed samples, except for the sample of TiN.
  • the cerium was removed after a second part of a resist strip procedure consisting of immersion in cold sulfuric acid for about 5 to 15 minutes.
  • FIG. 3 is a scanning electron microscope (SEM) image with white lines drawn to highlight borders between layers of a cross section of a SOI wafer 300 after the wafer has been immersed in a solution of approximately 20% CAN and approximately 80% DI water for about 30 minutes at approximately 65°C.
  • the SOI wafer comprises a bulk silicon substrate 330, an insulating layer of silicon dioxide (S1O 2 ) 320 abutting the bulk silicon substrate 330, and an upper silicon layer 310 abutting the insulating layer 320.
  • the thickness of the upper silicon layer 310 was nominally (approximately) 70 nm.
  • the thickness of the upper silicon layer 310 measured by the SEM is approximately 69.22 nm. Therefore, there is no measurable thinning of the SOI wafer, or of the layers comprised within the SOI wafer, after immersion in the CAN solution.
  • FIG. 4 shows the results of an XPS analysis of the SOI wafer 300 after the wafer has been immersed in the CAN solution as described with reference to FIG. 3.
  • the leftmost peak having binding energy between about 103 and 104 electron volts (EV), corresponds to Si0 2 .
  • Trace 410 represents the control, that is, the wafer prior to immersion in the CAN solution.
  • Trace 420 represents the wafer after immersion.
  • At least a portion of the techniques of the present invention may be implemented in one or more integrated circuits.
  • die are typically fabricated in a repeated pattern on a surface of a semiconductor wafer. Individual die are cut or diced from the wafer, then packaged as integrated circuits. One skilled in the art would know how to dice wafers and package die to produce integrated circuits. Integrated circuits so manufactured are considered part of this invention.
  • FIG. 5 is a cross-sectional view depicting a packaged integrated circuit 500 according to an embodiment of the present invention.
  • the packaged integrated circuit 500 comprises a leadframe 502, a die 504 attached to the leadframe, and a plastic encapsulation mold 508.
  • FIG. 5 shows only one type of integrated circuit package, the invention is not so limited; the invention may comprise an integrated circuit die enclosed in any package type.
  • the die 504 includes a device described herein, for example, an FET or other electronic device formed according to methods of the invention, and may include other structures or circuits.
  • the die 504 may include at least one conductor, MEM device, FET, source, drain or channel region of an FET, or gate conductor of an FET, the formation of which comprises the removal of resist by methods of the invention.
  • An embodiment of the process of using the solutions of the invention to remove resist in batch mode is described. Specifically, a method of removing a masking material is described, the method comprising contacting the masking material with: (a) an optional pretreatment followed by a DI water rinse, (b) a solution comprising cerium as described herein followed by a DI water rinse, (c) a sulfuric acid post-treatment, (d) a DI water rinse, (e) dilute standard clean solution 1 (SC-1) treatment, (f) a DI water rinse, and (g) an IPA dry.
  • the conditions of the optional pretreatment (a) and the post-treatment (c) include using sulfuric acid and a solvent such as tetraglyme or gamma-butyro lactone at temperature from about 20 to about 70°C, more preferably about 40 to about 50°C, for time from about 5 to about 45 minutes.
  • concentration of the sulfuric acid is preferably in a range from about 80% to about 100%.
  • the cerium- containing treatment can include temperature in a range from about 60 to about 80°C for from about 15 to about 90 minutes using a solution having a cerium compound concentration of about 15 to about 25 wt% (e.g., about 15 to about 25 wt% CAN).
  • the dilute SC-1 treatment includes temperature in a range from about room temperature to about 50°C for time in a range from about 1 to 20 minutes, preferably about 1 to about 2 minutes.
  • An example of diluted SC-1 is a 1 : 1 :40 solution of concentrated ammonia, concentrated H 2 O 2 and DI water, by volume. Each water rinse preferably includes 1 to 10 rinse cycles, preferably about 3 to about 5 rinse cycles.
  • variables such as flow rate, jet pressure and mechanical force can be used to speed up the stripping process.
  • the time limits will be on the lower end or lower, e.g., about 0.5 to about 1 minute for the optional pretreatment and post-treatment steps, about 1 minute for the cerium-containing solution treatment, about 0.5 minutes of the dilute SC-1 treatment.
  • Mn(II) reacts very fast with Ce(IV) in well stirred solutions to form permanganate (Mn(VII) according to the reaction:
  • the reacted permanganate is likely to be regenerated by Ce(IV) ions.
  • An experiment was performed wherein a resist sample implanted with As at a dose of lxl0 16 /cm 2 at implant energy 25 keV was contacted with Formulations A-D at 65°C for 20 minutes, followed by a sulfuric acid rinse at room temperature for 15 min. Notably, a pretreatment step was not included so it would be easier to see if the addition of Mn had an effect. Pretreatment steps are contemplated herein.
  • Formulation A 20 wt% CAN, 3 wt% cone. HN0 3 , 77 wt % DI water
  • Formulation B 20 wt% CAN, 3 wt% cone. HN0 3 , 0.1 wt% Mn(N0 3 ) 2 -4H 2 0 (-200 ppm Mn), 76.9 wt % DI water
  • Formulation C 20 wt% CAN, 3 wt% cone. HN0 3 , 0.3 wt% Mn(N0 3 ) 2 -4H 2 0, 76.7 wt % DI water
  • Formulation D 20 wt% CAN, 3 wt% cone. HN0 3 , 1 wt% ⁇ ( ⁇ 0 3 ) 2 ⁇ 4 ⁇ 2 0, 76 wt % DI water
  • Formulation E 20 wt% CAN, 4 wt% ATFA, 76 wt % DI water
  • Formulation F 20 wt% CAN, 4 wt% ATFA, 20 ppm Mn from ⁇ ( ⁇ 0 3 ) 2 ⁇ 4 ⁇ 2 0, remainder DI water
  • Formulation G 20 wt% CAN, 4 wt% ATFA, 60 ppm Mn from ⁇ ( ⁇ 0 ) 2 ⁇ 4 ⁇ 2 0, remainder DI water
  • Example D An experiment was performed wherein a resist sample implanted with As at a dose of lxl0 16 /cm 2 at implant energy 25 keV was contacted with a sulfuric acid pretreatment at 40°C for 10 min, followed by contact with Formulations H and I at 70°C for 50 minutes, followed by a sulfuric acid rinse at 40°C for 10 min.
  • Formulation H 20 wt% CAN, 6 wt% ATFA, 73 wt % DI water
  • Formulation I 20 wt% CAN, 6 wt% ATFA, 50 ppm Mn from ⁇ ( ⁇ 0 3 ) 2 ⁇ 4 ⁇ 2 0, balance DI water
  • test area was optically imaged following the cleaning protocol and the results reported based on grading of specific test mask locations. Each location has a different property, e.g., spacing, thickness, area, etc. The results were reported numerically wherein a "10" signifies complete cleaning and a "0" signifies no cleaning. The results can be seen in FIG. 6. It can be seen that locations where formulation H was not effective, the presence of manganese in Formulation I substantially improved the cleaning of the wafer.
  • a series of 1%, 3%, and 5% by weight CAN in water solutions were prepared without any stabilizing agent and heated in an open flask to 90-95°C.
  • the 1% and 3% solutions showed no precipitate after -70 min, while the 5% solution started precipitating after -20 min.
  • a 5% by weight CAN solution without stabilizing agent was prepared by adding solid CAN to stirred boiling DI water in a 250- ml Erlenmeyer flask. The solution was boiled ( ⁇ 100°C) for about 20 minutes and remained precipitate-free.
  • Table 4 Stability of solutions having various NH3/CAN ratios over time.
  • integrated circuits and integrated circuit assemblies formed in accordance with the present invention described herein and shown in the figures may be employed in applications, hardware and/or electronic systems, e.g., one or more digital computers with associated memory, implementation-specific integrated circuit(s), functional circuitry, etc.
  • Other suitable hardware and systems for comprising or using components of the invention may include, but are not limited to, personal computers, communication networks, electronic commerce systems, portable communications devices (e.g., cell phones), and solid- state media storage devices. Systems and hardware incorporating such integrated circuits are considered part of this invention. Given the teachings of the invention provided herein, one of ordinary skill in the art will be able to contemplate other implementations and applications of the techniques of the invention.
  • embodiments of the invention are also applicable for removal and stripping of photoresists that are not ion implanted, or at least not heavily ion implanted.
  • photoresists include photoresists that may not be soluble in conventional organic solvents, for example, negative photoresist that due to polymer cross-linking are not soluble in conventional organic solvents.
  • photoresists may be remove or stripped using techniques of the present invention.

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Cleaning Or Drying Semiconductors (AREA)
  • Photosensitive Polymer And Photoresist Processing (AREA)
  • ing And Chemical Polishing (AREA)
  • Detergent Compositions (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)

Abstract

La présente invention porte sur des procédés d'élimination d'une matière de masquage, par exemple, un photorésist, et sur des dispositifs électroniques formés par l'élimination d'une matière de masquage. Par exemple, un procédé pour éliminer une matière de masquage comprend la mise en contact de la matière de masquage avec une solution comprenant du cérium et au moins un oxydant supplémentaire. Le cérium peut être compris dans un sel. Le sel peut être du nitrate de cérium et d'ammonium. Le au moins un oxydant supplémentaire peut être un composé contenant du manganèse, du ruthénium et/ou de l'osmium.
EP10836729.3A 2009-12-11 2010-12-10 Élimination d'une matière de masquage Withdrawn EP2510538A4 (fr)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US12/636,015 US8367555B2 (en) 2009-12-11 2009-12-11 Removal of masking material
US35624210P 2010-06-18 2010-06-18
PCT/US2010/059800 WO2011072188A2 (fr) 2009-12-11 2010-12-10 Élimination d'une matière de masquage

Publications (2)

Publication Number Publication Date
EP2510538A2 true EP2510538A2 (fr) 2012-10-17
EP2510538A4 EP2510538A4 (fr) 2014-03-26

Family

ID=44146190

Family Applications (1)

Application Number Title Priority Date Filing Date
EP10836729.3A Withdrawn EP2510538A4 (fr) 2009-12-11 2010-12-10 Élimination d'une matière de masquage

Country Status (7)

Country Link
EP (1) EP2510538A4 (fr)
JP (1) JP2013513824A (fr)
KR (1) KR20120108984A (fr)
CN (1) CN103119694A (fr)
SG (1) SG181642A1 (fr)
TW (1) TW201140254A (fr)
WO (1) WO2011072188A2 (fr)

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR102064487B1 (ko) 2011-01-13 2020-01-10 엔테그리스, 아이엔씨. 세륨-함유 용액에 의해 발생된 입자의 제거를 위한 배합물
US8367556B1 (en) * 2011-12-01 2013-02-05 International Business Machines Corporation Use of an organic planarizing mask for cutting a plurality of gate lines
EP2850495A4 (fr) * 2012-05-18 2016-01-20 Entegris Inc Composition et processus permettant d'arracher un enduit photorésistant d'une surface comprenant du nitrure de titane
CN103235491A (zh) * 2013-04-07 2013-08-07 北京七星华创电子股份有限公司 一种抗蚀剂剥离液及其应用
KR102166974B1 (ko) * 2013-11-11 2020-10-16 도쿄엘렉트론가부시키가이샤 에칭 후 폴리머의 제거 및 하드마스크 제거의 향상을 위한 방법 및 하드웨어
TWI595332B (zh) * 2014-08-05 2017-08-11 頎邦科技股份有限公司 光阻剝離方法
CN106435616B (zh) * 2016-10-10 2018-09-07 深圳大学 一种TiNC膜的退镀液及退镀工艺
KR101971459B1 (ko) * 2017-06-05 2019-04-23 재원산업 주식회사 유기발광소자 제조용 도전 부재 세정용 조성물 및 이를 이용한 세정방법
JP6992095B2 (ja) * 2018-02-05 2022-01-13 富士フイルム株式会社 基板の処理方法、半導体装置の製造方法、基板処理用キット
CN115066104A (zh) * 2022-07-09 2022-09-16 南通群安电子材料有限公司 针对厚光阻抗蚀剂的剥除液

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2006113621A2 (fr) * 2005-04-15 2006-10-26 Advanced Technology Materials, Inc. Formulations pour le nettoyage de couches de photoresine implantees d'ions a partir de dispositifs microelectroniques
US20080283090A1 (en) * 2007-05-18 2008-11-20 Dekraker David Process for treatment of substrates with water vapor or steam

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE19639093A1 (de) * 1996-09-24 1998-03-26 Bosch Gmbh Robert Verfahren zur drahtlosen Übertragung von Ortsinformationen und Nutzinformationen und Sende-/Empfangseinrichtung
US6162565A (en) * 1998-10-23 2000-12-19 International Business Machines Corporation Dilute acid rinse after develop for chrome etch
JP2002064101A (ja) * 2000-08-21 2002-02-28 Casio Comput Co Ltd クロム層を有する配線の形成方法
US6599370B2 (en) * 2000-10-16 2003-07-29 Mallinckrodt Inc. Stabilized alkaline compositions for cleaning microelectronic substrates
JP2003017465A (ja) * 2001-06-29 2003-01-17 Mitsubishi Electric Corp 半導体装置の製造方法および半導体装置
US7247567B2 (en) * 2004-06-16 2007-07-24 Cabot Microelectronics Corporation Method of polishing a tungsten-containing substrate

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2006113621A2 (fr) * 2005-04-15 2006-10-26 Advanced Technology Materials, Inc. Formulations pour le nettoyage de couches de photoresine implantees d'ions a partir de dispositifs microelectroniques
US20080283090A1 (en) * 2007-05-18 2008-11-20 Dekraker David Process for treatment of substrates with water vapor or steam

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See also references of WO2011072188A2 *

Also Published As

Publication number Publication date
SG181642A1 (en) 2012-07-30
EP2510538A4 (fr) 2014-03-26
JP2013513824A (ja) 2013-04-22
WO2011072188A3 (fr) 2011-09-15
KR20120108984A (ko) 2012-10-05
WO2011072188A2 (fr) 2011-06-16
CN103119694A (zh) 2013-05-22
TW201140254A (en) 2011-11-16

Similar Documents

Publication Publication Date Title
WO2011072188A2 (fr) Élimination d'une matière de masquage
US8367555B2 (en) Removal of masking material
US10446389B2 (en) Formulations for the removal of particles generated by cerium-containing solutions
KR102266832B1 (ko) ＴｉＮ 하드 마스크 및 에치 잔류물 제거
US6248704B1 (en) Compositions for cleaning organic and plasma etched residues for semiconductors devices
EP1212150B1 (fr) Compositions a base de lactame destinees au nettoyage de residus organiques et de gravure au plasma sur des dispositifs a semi-conducteurs
JP4755060B2 (ja) 残留物を除去するための水性洗浄組成物及びそれを使用する方法
TWI441902B (zh) 光阻殘渣及聚合物殘渣的除去液組成物
US9678430B2 (en) Composition and process for stripping photoresist from a surface including titanium nitride
KR101339749B1 (ko) 다제형 반도체 기판용 세정 키트, 그것을 사용한 세정 방법 및 반도체 소자의 제조 방법
EP2460177B1 (fr) Methode de retrait de photoresist pour application en semiconducteurs
IL269490A (en) Methods of surface treatment and preparations for the same purpose
TWI654340B (zh) Ｎｉ：ＮｉＧｅ：Ｇｅ選擇性蝕刻配方及其使用方法
CN110777021A (zh) 蚀刻后残留物清洁组合物及其使用方法
US7252718B2 (en) Forming a passivating aluminum fluoride layer and removing same for use in semiconductor manufacture
US8853081B2 (en) High dose ion-implanted photoresist removal using organic solvent and transition metal mixtures
US20140187460A1 (en) Removal of masking material
KR102321217B1 (ko) 에칭 후 잔여물 세정 조성물 및 이의 사용 방법
CN116568743A (zh) 清洁组成物
Reinhardt et al. High Dose Implant Stripping
JP5125636B2 (ja) 半導体ドライプロセス後の残渣除去液及びそれを用いた残渣除去方法

Legal Events

Date Code Title Description
PUAI Public reference made under article 153(3) epc to a published international application that has entered the european phase

Free format text: ORIGINAL CODE: 0009012

17P Request for examination filed

Effective date: 20120704

AK Designated contracting states

Kind code of ref document: A2

Designated state(s): AL AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HR HU IE IS IT LI LT LU LV MC MK MT NL NO PL PT RO RS SE SI SK SM TR

RIN1 Information on inventor provided before grant (corrected)

Inventor name: CYWAR, DOUGLAS

Inventor name: BOGGS, KARL E.

Inventor name: KERN, MATTHEW

Inventor name: BAUM, THOMAS H.

Inventor name: TOTIR, GEORGE GABRIEL

Inventor name: AFZALI-ARDAKANI, ALI

Inventor name: NUNES, RONALD W.

Inventor name: COOPER, EMANUEL I.

Inventor name: KHOJASTEH, MAHMOUD

RIN1 Information on inventor provided before grant (corrected)

Inventor name: NUNES, RONALD W.

Inventor name: AFZALI-ARDAKANI, ALI

Inventor name: TOTIR, GEORGE GABRIEL

Inventor name: KHOJASTEH, MAHMOUD

Inventor name: COOPER, EMANUEL I.

Inventor name: BOGGS, KARL E.

Inventor name: BAUM, THOMAS H.

Inventor name: CYWAR, DOUGLAS

Inventor name: KERN, MATTHEW

DAX Request for extension of the european patent (deleted)
A4 Supplementary search report drawn up and despatched

Effective date: 20140225

RIC1 Information provided on ipc code assigned before grant

Ipc: H01L 21/311 20060101AFI20140219BHEP

Ipc: G03F 7/42 20060101ALI20140219BHEP

STAA Information on the status of an ep patent application or granted ep patent

Free format text: STATUS: THE APPLICATION IS DEEMED TO BE WITHDRAWN

18D Application deemed to be withdrawn

Effective date: 20140701