EP2400527A1 - Siliciumcarbidsubstrat und verfahren zu seiner herstellung - Google Patents

Siliciumcarbidsubstrat und verfahren zu seiner herstellung Download PDF

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Publication number
EP2400527A1
EP2400527A1 EP10743665A EP10743665A EP2400527A1 EP 2400527 A1 EP2400527 A1 EP 2400527A1 EP 10743665 A EP10743665 A EP 10743665A EP 10743665 A EP10743665 A EP 10743665A EP 2400527 A1 EP2400527 A1 EP 2400527A1
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EP
European Patent Office
Prior art keywords
main surface
less
plane
silicon carbide
sic substrate
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EP10743665A
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English (en)
French (fr)
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EP2400527A4 (de
Inventor
Makoto Sasaki
Takeyoshi Masuda
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Sumitomo Electric Industries Ltd
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Sumitomo Electric Industries Ltd
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Publication of EP2400527A1 publication Critical patent/EP2400527A1/de
Publication of EP2400527A4 publication Critical patent/EP2400527A4/de
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • C—CHEMISTRY; METALLURGY
    • C30—CRYSTAL GROWTH
    • C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
    • C30B29/00—Single crystals or homogeneous polycrystalline material with defined structure characterised by the material or by their shape
    • C30B29/10—Inorganic compounds or compositions
    • C30B29/36—Carbides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/544—Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/04—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their crystalline structure, e.g. polycrystalline, cubic or particular orientation of crystalline planes
    • H01L29/045—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their crystalline structure, e.g. polycrystalline, cubic or particular orientation of crystalline planes by their particular orientation of crystalline planes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66053—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide
    • H01L29/66068—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/544—Marks applied to semiconductor devices or parts
    • H01L2223/54406—Marks applied to semiconductor devices or parts comprising alphanumeric information
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/544—Marks applied to semiconductor devices or parts
    • H01L2223/5442—Marks applied to semiconductor devices or parts comprising non digital, non alphanumeric information, e.g. symbols
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/544—Marks applied to semiconductor devices or parts
    • H01L2223/54433—Marks applied to semiconductor devices or parts containing identification or tracking information
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/544—Marks applied to semiconductor devices or parts
    • H01L2223/54493—Peripheral marks on wafers, e.g. orientation flats, notches, lot number
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
    • H01L29/1608—Silicon carbide
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T83/00—Cutting
    • Y10T83/04—Processes

Definitions

  • the present invention relates to a silicon carbide substrate and a method of manufacturing a silicon carbide substrate.
  • Non-Patent Document 1 One of such semiconductor devices known is a MOSFET (Metal Oxide Semiconductor Field Effect Transistor) of SiC (Non-Patent Document 1, for example).
  • MOSFET Metal Oxide Semiconductor Field Effect Transistor
  • Non-Patent Document 1 discloses that, when MOSFETs are fabricated on the (11-20) plane of a SiC substrate, a drain current along the ⁇ 1-100> direction is 3 times larger than along the ⁇ 0001> direction. It is known that a crystal orientation (plane orientation) has a strong influence on electron mobility even when MOSFETs are fabricated on the same plane, as described above.
  • a semiconductor substrate has an orientation flat (hereinafter also referred to as ori-fla) formed in a portion of its periphery in order to facilitate alignment and identification of crystal orientation. It is known to form an ori-fla for identifying the ⁇ 0001> direction on the (11-20) plane of the SiC substrate in Non-Patent Document 1.
  • ori-fla orientation flat
  • the present inventors notice the use of a SiC substrate in which a plane orientation of a main surface is substantially ⁇ 03-38 ⁇ in a semiconductor device process.
  • a method of forming an ori-fla on a SiC substrate having a substantially ⁇ 03-38 ⁇ plane as a main surface is unknown, however. Without an ori-fla, it is difficult to determine a plane direction, a polarity plane and the like, which may result in fabrication of a semiconductor device in an unexpected direction.
  • the present invention provides a SiC substrate in which a plane orientation is defined and a method of manufacturing the SiC substrate.
  • a SiC substrate includes a first orientation flat (first ori-fla) parallel to the ⁇ 11-20> direction, and a second orientation flat (second ori-fla) being in a direction intersecting the first orientation flat and being different from the first orientation flat in length.
  • first ori-fla first orientation flat
  • second ori-fla second orientation flat
  • the SiC substrate according to the one aspect of the present invention includes the first ori-fla and the second ori-fla.
  • the first ori-fla can be identified by determining whether the first ori-fla is relatively short or long. Since the first ori-fla indicates the ⁇ 11-20> direction of high channel mobility, a direction of high channel mobility can be identified in the SiC substrate by the first ori-fla. Namely, a plane orientation can be defined. When a semiconductor device is fabricated with the SiC substrate in which the plane orientation is defined in this manner, a channel can be formed in the direction of high mobility, which leads to fabrication of a semiconductor device with improved properties.
  • the second orientation flat is orthogonal to the first orientation flat.
  • the first ori-fla indicating the direction of high channel mobility can be defined more clearly.
  • side surfaces including the first and second orientation flats, respectively are inclined at not less than -10° and not more than 10° in a direction perpendicular to the main surface.
  • the side surfaces are substantially perpendicular to the main surface, and are therefore easy to handle with improved workability.
  • a SiC substrate includes a main surface having a rectangular plane shape and being inclined at not less than 50° and not more than 65° in the ⁇ 1-100> direction as well as at not less than -10° and not more than 10° in the ⁇ 11-20> direction with respect to the ⁇ 0001 ⁇ plane.
  • the main surface includes a first side parallel to the ⁇ 11-20> direction, a second side in a direction perpendicular to the first side, and a third side connecting the first side to the second side.
  • a length of the third side projected in a direction in which the first side extends is different from a length of the third side projected in a direction in which the second side extends.
  • the main surface includes the third side, with the length of the third side projected in the direction in which the first side extends being different from the length of the third side projected in the direction in which the second side extends.
  • the first side can be identified by determining whether the length of the third side projected along the first side is relatively short or long. Since the first side indicates the ⁇ 11-20> direction of high channel mobility, a direction of high channel mobility can be identified in the SiC substrate. Namely, a plane orientation can be defined. When a semiconductor device is fabricated with the SiC substrate in which the plane orientation is defined in this manner, a channel can be formed in the direction of high mobility, which leads to fabrication of a semiconductor device with improved properties.
  • a SiC substrate includes a main surface having a rectangular plane shape and being inclined at not less than 50° and not more than 65° in the ⁇ 1-100> direction as well as at not less than -10° and not more than 10° in the ⁇ 11-20> direction with respect to the ⁇ 0001 ⁇ plane.
  • the main surface includes a first side parallel to the ⁇ 11-20> direction, a second side in a direction perpendicular to the first side, and a mark formed in vicinity of a corner where the first side is connected to the second side.
  • the main surface includes the mark in vicinity of the corner where the first side is connected to the second side. Accordingly, the first side can be identified by determining a position where the mark is to be formed with respect to the first side. Since the first side indicates the ⁇ 11-20> direction of high channel mobility, a direction of high channel mobility can be identified in the SiC substrate. Namely, a plane orientation can be defined. When a semiconductor device is fabricated with the SiC substrate in which the plane orientation is defined in this manner, a channel can be formed in the direction of high mobility, which leads to fabrication of a semiconductor device with improved properties.
  • the mark is a laser-irradiated mark, or a scratch by a diamond pen. Accordingly, the mark can be readily formed.
  • the first side is different from the second side in length.
  • the first side can be readily identified by determining whether the first side is relatively short or long.
  • side surfaces including the first and second sides, respectively are inclined at not less than -10° and not more than 10° in a direction perpendicular to the main surface.
  • the side surfaces are substantially perpendicular to the main surface, and are therefore easy to handle with improved workability.
  • a manufacturing method includes the following steps.
  • a SiC ingot is prepared.
  • a SiC substrate including a main surface having a circular or elliptical plane shape and being inclined at not less than 50° and not more than 65° in the ⁇ 1-100> direction as well as at not less than -10° and not more than 10° in the ⁇ 11-20> direction with respect to the ⁇ 0001 ⁇ plane is cut from the ingot.
  • a first orientation flat parallel to the ⁇ 11-20> direction and a second orientation flat being in a direction intersecting the first orientation flat and being different from the first orientation flat in length are formed on the SiC substrate.
  • the SiC substrate including the first ori-fla parallel to the ⁇ 11-20> direction of high channel mobility and the second ori-fla different from the first ori-fla in length can be manufactured. Accordingly, the SiC substrate in which the plane orientation is defined according to the one aspect of the present invention described above can be manufactured.
  • a manufacturing method includes the following steps.
  • a SiC ingot is prepared.
  • the ingot is processed to include a first side parallel to a ⁇ 11-20> direction, a second side in a direction perpendicular to the first side, and a third side connecting the first side to the second side, with a length of the third side projected in a direction in which the first side extends being different from a length of the third side projected in a direction in which the second side extends, on a plane inclined at not less than 50° and not more than 65° in the ⁇ 1-100> direction as well as at not less than -10° and not more than 10° in the ⁇ 11-20> direction with respect to the ⁇ 0001 ⁇ plane.
  • a method of manufacturing the SiC substrate according to the still another aspect includes the following steps.
  • a SiC ingot is prepared.
  • a SiC substrate including a main surface having a rectangular plane shape and being inclined at not less than 50° and not more than 65° in the ⁇ 1-100> direction as well as at not less than -10° and not more than 10° in the ⁇ 11-20> direction with respect to the ⁇ 0001 ⁇ plane is cut.
  • the cutting step includes the steps of cutting the SiC substrate from the ingot such that the substrate includes a first side parallel to the ⁇ 11-20> direction and a second side in a direction perpendicular to the first side, and forming a mark in vicinity of a corner where the first side is connected to the second side in the main surface.
  • the SiC substrate including the first side parallel to the ⁇ 11-20> direction of high channel mobility and the mark that can be used to identify the first side can be manufactured. Accordingly, the SiC substrate in which the plane orientation is defined according to the still another aspect of the present invention described above can be manufactured.
  • Main surface 11 has a circular or elliptical plane shape.
  • the circular or elliptical shape partially includes straight portions due to first and second ori-flas 12 and 13.
  • the phrase "main surface 11 has a circular or elliptical plane shape" is used herein to include the case where the circular or elliptical shape is partially chipped in plane shape.
  • Lengths L12 and L13 of first and second ori-flas 12 and 13 refer to lengths of the straight portions when SiC substrate 10 is viewed from above, as shown in Fig. 2 .
  • Side surfaces including first and second ori-flas 12 and 13, respectively preferably are inclined at not less than -10° and not more than 10° in a direction perpendicular to main surface 11, more preferably are inclined at not less than -5° and not more than 5° in the direction, and still more preferably are perpendicular to main surface 11.
  • main surface 11 is the (03-38) plane
  • the side surfaces including first and second ori-flas 12 and 13 are preferably orthogonal to a plane inclined at not less than 54° and not more than 55° in the ⁇ 1-100> direction with respect to the (0001) plane. In this case, SiC substrate 10 is easy to handle with improved workability.
  • a SiC ingot 22 is prepared (step S1).
  • SiC ingot 22 is grown on a main surface 21a of a base substrate 21, as shown in Fig. 5 , for example.
  • Main surface 21a is inclined at not less than 50° and not more than 65° in the ⁇ 1-100> direction as well as at not less than -10° and not more than 10° in the ⁇ 11-20> direction with respect to the ⁇ 0001 ⁇ plane.
  • a growth direction of ingot 22 is direction X
  • a growth surface of ingot 22 is the same as main surface 21a of base substrate 21.
  • a growth method is not particularly limited, and an HVPE (Hydride Vapor Phase Epitaxy) method, an MBE (Molecular Beam Epitaxy) method, an OMVPE (OrganoMetallic Vapor Phase Epitaxy) method, a sublimation method, a vapor phase epitaxy method such as a CVD (Chemical Vapor Deposition) method, a flux method, or a liquid phase epitaxy method such as a high nitrogen pressure solution method may be employed, for example.
  • HVPE Hydride Vapor Phase Epitaxy
  • MBE Molecular Beam Epitaxy
  • OMVPE Organic Vapor Phase Epitaxy
  • sublimation method a vapor phase epitaxy method
  • a vapor phase epitaxy method such as a CVD (Chemical Vapor Deposition) method
  • a flux method or a liquid phase epitaxy method such as a high nitrogen pressure solution method
  • Base substrate 21 is removed as necessary, such as when base substrate 21 is different from SiC in composition.
  • first ori-fla 12 parallel to the ⁇ 11-20> direction, and second ori-fla 13 being in the direction intersecting first ori-fla 12 and being different from first ori-fla 12 in length are formed on ingot 22 (step S2).
  • first ori-fla 12 and second ori-fla 13 intersect with each other.
  • a SiC substrate including main surface 11 having a circular or elliptical plane shape and being inclined at not less than 50° and not more than 65° in the ⁇ 1-100> direction as well as at not less than -10° and not more than 10° in the ⁇ 11-20> direction with respect to the ⁇ 0001 ⁇ plane is cut from ingot 22 including first and second ori-flas 12 and 13 (step S3).
  • the side surfaces including first and second ori-flas 12 and 13, respectively preferably are inclined at not less than -10° and not more than 10° in a direction perpendicular to main surface 11, more preferably are inclined at not less than -5° and not more than 5° in the direction, and still more preferably are perpendicular to main surface 11.
  • SiC substrate 10 shown in Figs. 1 and 2 can be manufactured.
  • Step S2 and step S3 may be performed simultaneously or separately.
  • a SiC substrate including main surface 11 having a circular or elliptical plane shape and being inclined at not less than 50° and not more than 65° in the ⁇ 1-100> direction as well as at not less than -10° and not more than 10° in the ⁇ 11-20> direction with respect to the ⁇ 0001 ⁇ plane is cut from ingot 22 (step S3).
  • SiC substrate 10 shown in Figs. 1 and 2 can be manufactured.
  • a SiC substrate including main surface 11 having a circular or elliptical plane shape and being inclined at not less than 50° and not more than 65° in the ⁇ 1-100> direction as well as at not less than -10° and not more than 10° in the ⁇ 11-20> direction with respect to the ⁇ 0001 ⁇ plane is cut from ingot 22 (step S3). If the SiC substrate is sliced parallel to main surface 21a of base substrate 21 at step S3, main surface 11 described above is not obtained because the growth surface of SiC ingot 22 is the same as main surface 21a of base substrate 21.
  • the SiC substrate is cut along a plane C2 parallel to a plane inclined at not less than 50° and not more than 65° in the ⁇ 1-100> direction as well as at not less than -10° and not more than 10° in the ⁇ 11-20> direction with respect to the ⁇ 0001 ⁇ plane, in order to obtain main surface 11 described above.
  • first ori-fla 12 parallel to the ⁇ 11-20> direction, and second ori-fla 13 being in the direction intersecting first ori-fla 12 and being different from first ori-fla 12 in length are formed on the SiC substrate (step S4).
  • SiC substrate 10 shown in Figs. 1 and 2 can be manufactured.
  • SiC substrate 10 according to the present embodiment includes first ori-fla 12 parallel to the ⁇ 11-20> direction, and second ori-fla 13 being in the direction intersecting first ori-fla 12 and being different from first ori-fla 12 in length.
  • SiC substrate 10 includes first ori-fla 12 and second ori-fla 13.
  • First ori-fla 12 can be identified by determining whether first ori-fla 12 is relatively short or long. Since first ori-fla 12 indicates the ⁇ 11-20> direction of high channel mobility, a direction of high channel mobility can be identified in SiC substrate 10. Namely, a plane orientation of high mobility can be defined in SiC substrate 10 according to the present embodiment. Accordingly, when a semiconductor device is fabricated with SiC substrate 10, the ⁇ 11-20> direction can be identified, which facilitates setting of a wafer of SiC substrate 10 during a semiconductor device process. As a result, a channel can be formed in the direction of high mobility, which leads to fabrication of a semiconductor device with improved properties.
  • the ⁇ 03-38 ⁇ plane is a forbidden plane with X-ray diffraction during processing, and is thus inappropriate as a reference plane.
  • the (11-20) plane which is a low-index plane can be readily used as a reference.
  • the (11-20) plane can be readily used as a reference for enhancing processing accuracy as well.
  • SiC substrate 10 according to the present embodiment in which a direction of high channel mobility can be clearly identified as described above, can be appropriately employed in electronic devices such as a bipolar transistor, a field effect transistor (FET), and a spin FET.
  • electronic devices such as a bipolar transistor, a field effect transistor (FET), and a spin FET.
  • SiC substrate 30 includes a main surface 31 having a rectangular plane shape and being inclined at not less than 50° and not more than 65° in the ⁇ 1-100> direction as well as at not less than -10° and not more than 10° in the ⁇ 11-20> direction with respect to the ⁇ 0001 ⁇ plane.
  • main surface 31 has a shape with a notch formed in one corner of the quadrangle when SiC substrate 30 is viewed from above.
  • Main surface 31 includes a first side 31a, a second side 31b, and a third side 31c.
  • First side 31a is parallel to the ⁇ 11-20> direction.
  • Second side 31b is in a direction perpendicular to first side 31a.
  • second side 31b is parallel to direction X shown in Fig. 3 .
  • Third side 31c connects first side 31a to second side 31b.
  • a length L31a of third side 31c projected in a direction in which first side 31a extends is different from a length L31b of third side 31c projected in a direction in which second side 31b extends.
  • length L31a is a width of the notch in the ⁇ 11-20> direction
  • length L31b is a width of the notch in direction X.
  • length L31a is longer than length L31b in the present embodiment, this is not restrictive. Namely, any relation in terms of size between length L31a and length L32a is acceptable. It is preferable that length L31a and length L31b be different from each other to such a degree that one can visually discern the size relation.
  • first side 31a be different from a length of second side 31b.
  • first side 31a and second side 31b can be recognized more readily.
  • Side surfaces 32 and 33 including first and second sides 31a and 31b, respectively, preferably are inclined at not less than -10° and not more than 10° in a direction perpendicular to main surface 31, more preferably are inclined at not less than -5° and not more than 5° in the direction, and still more preferably are perpendicular to main surface 31.
  • a side surface 34 including the third side preferably is inclined at not less than -10° and not more than 10° in the direction perpendicular to main surface 31, and more preferably is perpendicular to main surface 31.
  • SiC substrate 10 is easy to handle with improved workability.
  • SiC ingot 22 is prepared in a manner similar to the first embodiment (step S1).
  • ingot 22 is processed to include first side 31a parallel to the ⁇ 11-20> direction, second side 31b in the direction perpendicular to first side 31a, and third side 31c connecting first side 31a to second side 31b, with the length of third side 31c projected in the direction in which first side 31a extends being different from the length of third side 31c projected in the direction in which second side 31b extends, on a plane inclined at not less than 50° and not more than 65° in the ⁇ 1-100> direction as well as at not less than -10° and not more than 10° in the ⁇ 11-20> direction with respect to the ⁇ 0001 ⁇ plane (step S5).
  • SiC substrate 30 including main surface 31 having a rectangular plane shape and being inclined at not less than 50° and not more than 65° in the ⁇ 1-100> direction as well as at not less than -10° and not more than 10° in the ⁇ 11-20> direction with respect to the ⁇ 0001 ⁇ plane is cut from ingot 22 shown in Fig. 13 (step S3).
  • main surface 31 of ingot 22 is in a direction perpendicular to direction X
  • SiC substrate 30 is cut along a plane parallel to a plane orthogonal to direction X.
  • SiC substrate 30 shown in Figs. 10 and 11 can be manufactured.
  • a method of manufacturing SiC substrate 30 according to the variation is basically similar to the method of manufacturing SiC substrate 30 according to the embodiment described above, except that step S5 for forming first to third sides 31a, 31b, 31c and step S3 for cutting are performed simultaneously.
  • SiC ingot 22 as shown in Figs. 5 and 15 is prepared in a manner similar to the first embodiment (step S 1).
  • SiC substrate 30 is cut from ingot 22 shown in Fig. 15 such that SiC substrate 30 includes first to third sides 31a, 31b, and 31c (step S3).
  • SiC substrate 30 shown in Figs. 10 and 11 can be manufactured.
  • main surface 31 has third side 31c, with length L31a of third side 31c projected in the direction in which first side 31a extends being different from length L31b of third side 31c projected in the direction in which second side 31b extends.
  • First side 31a can be identified by determining whether length L31a of third side 31c projected along first side 31a is relatively short or long. Since first side 31a indicates the ⁇ 11-20> direction of high channel mobility, a direction of high channel mobility can be identified in SiC substrate 30. Namely, a plane orientation of high mobility can be defined in SiC substrate 30 according to the present embodiment. Therefore, when a semiconductor device is fabricated with SiC substrate 30, a channel can be formed in the direction of high mobility, which leads to fabrication of a semiconductor device with improved properties.
  • SiC substrate 40 according to the present embodiment includes a main surface 41 having a rectangular plane shape and being inclined at not less than 50° and not more than 65° in the ⁇ 1-100> direction as well as at not less than -10° and not more than 10° in the ⁇ 11-20> direction with respect to the ⁇ 0001 ⁇ plane.
  • main surface 31 is quadrangular when SiC substrate 30 is viewed from above.
  • a quadrangle is preferable from the viewpoint of increasing the area of main surface 41.
  • Main surface 41 includes a first side 41a, a second side 41b, and a mark (marking) 45.
  • First side 41a is parallel to the ⁇ 11-20> direction.
  • Second side 41b is in a direction perpendicular to first side 41b.
  • second side 41b is parallel to direction X shown in Fig. 3 .
  • first side 41a be different from a length of second side 41b.
  • any relation in terms of size between the length of first side 41a and the length of second side 41b is acceptable, it is preferable that these lengths be different from each other to such a degree that one can visually discern the size relation. Accordingly, first side 41a can be readily identified by determining whether first side 41a is relatively short or long.
  • Mark 45 is formed in the vicinity of a corner where first side 41a is connected to second side 41b. It is preferable that mark 45 be a laser-irradiated mark, or a scratch by a diamond pen. Accordingly, mark 45 can be readily formed, and processing accuracy of mark 45 can be improved.
  • mark 45 it is preferable to form mark 45 in different sizes and numbers between the ⁇ 11-20> direction and direction X. In the present embodiment, a larger number of marks 45 are formed in the ⁇ 11-20> direction. Accordingly, first side 41a can be identified more readily.
  • mark 45 be a sign vertically and bilaterally asymmetric, a number, or the like. Accordingly, it is easy to determine a polarity plane, and a crystal axis direction to which the direction of first side 41a corresponds.
  • mark 45 is also preferable to form mark 45 on one of the Si face (main surface) side and the C face (rear surface) side, which is opposite to a surface utilized in the device process.
  • SiC has light transmission properties. Accordingly, even if mark 45 is formed on the rear surface and a metal film without light transmission properties or the like is formed, for example, mark 45 formed on the rear surface can be readily recognized with a microscope by polishing the main surface.
  • SiC substrate 10 is easy to handle with improved workability.
  • SiC ingot 22 is prepared in a manner similar to the first embodiment (step S1).
  • SiC substrate 40 including main surface 41 having a rectangular plane shape and being inclined at not less than 50° and not more than 65° in the ⁇ 1-100> direction as well as at not less than -10° and not more than 10° in the ⁇ 11-20> direction with respect to the ⁇ 0001 ⁇ plane is cut.
  • a substrate 47 made of SiC is cut from ingot 22 such that substrate 47 includes first side 41a parallel to the ⁇ 11-20> direction and second side 41b in the direction perpendicular to first side 41a (step S2). Then, mark 45 is formed in the vicinity of the corner where first side 41a is connected to second side 41b in main surface 41 of substrate 47 (step S6).
  • a method of forming a laser-irradiated mark by laser irradiation, a method of forming a scratch by a diamond pen, or the like may be employed as a method of forming mark 45 at step S6.
  • SiC substrate 40 shown in Figs. 16 and 17 can be manufactured.
  • main surface 41 includes mark 45 in the vicinity of the corner where first side 41a is connected to second side 41b.
  • First side 41a can be identified by determining a position where mark 45 is to be formed with respect to first side 41a.
  • mark 45 is formed on the right edge of first side 41a.
  • the number of marks 45 formed in a direction parallel to first side 41a is larger than the number of marks 45 formed in a direction parallel to second side 41b.
  • first side 41a can be identified in the present embodiment. Since first side 41a indicates the ⁇ 11-20> direction of high channel mobility, a direction of high channel mobility can be identified in SiC substrate 40.
  • a plane orientation of high channel mobility can be defined in SiC substrate 40 according to the present embodiment. Therefore, when a semiconductor device is fabricated with SiC substrate 40, a channel can be formed in the direction of high mobility, which leads to fabrication of a semiconductor device with improved properties.
  • vertical DMOSFETs Double Implanted Metal Oxide Semiconductor Field Effect Transistors 100 shown in Fig. 21 each having a channel in a range of not more than -90° from the ⁇ 11-20> direction were manufactured.
  • an n type SiC substrate of the 4H polytype was prepared as a SiC substrate 110.
  • a main surface 111 of SiC substrate 110 was inclined at not less than 50° and not more than 65° in the ⁇ 1-100> direction as well as at not less than -10° and not more than 10° in the ⁇ 11-20> direction with respect to the ⁇ 0001 ⁇ plane.
  • a semiconductor layer 112 made of n type SiC containing an n type impurity of higher concentration than SiC substrate 110 was formed on main surface 111 of SiC substrate 110 with the CVD method.
  • a main surface 112a of semiconductor layer 112 was inclined at not less than 50° and not more than 65° in the ⁇ 1-100> direction as well as at not less than -10° and not more than 10° in the ⁇ 11-20> direction with respect to the ⁇ 0001 ⁇ plane.
  • an oxide film having been patterned by photolithography and etching was formed as an ion implantation prevention mask in a region other than a region where semiconductor layer 112 had been formed.
  • p type impurity ions were implanted into main surface 112a of semiconductor layer 112. Consequently, a p type impurity diffusion layer 114 was formed in main surface 112a of semiconductor layer 112.
  • P type impurity diffusion layer 114 had a stripe shape extending in the ⁇ 11-20> direction.
  • N type impurity diffusion layer 115 had a stripe shape extending in the ⁇ 11-20> direction.
  • semiconductor layer 112 including p type impurity diffusion layer 114 and n type impurity diffusion layer 115 was subjected to an activation annealing process.
  • semiconductor layer 112 including p type impurity diffusion layer 114 and n type impurity diffusion layer 115 was heated at a temperature of about 1700°C for about 30 minutes in an atmosphere of argon gas. Consequently, the p type impurity ions in p type impurity diffusion layer 114 and the n type impurity ions in n type impurity diffusion layer 115 that had been implanted as described above were activated.
  • an insulating film 13 was formed with dry oxidation (thermal oxidation) to be in contact with the entire main surface 112a of semiconductor layer 112 including p type impurity diffusion layer 114 and n type impurity diffusion layer 115.
  • dry oxidation thermal oxidation
  • main surface 112a of semiconductor layer 112 including p type impurity diffusion layer 114 and n type impurity diffusion layer 115 was heated at a temperature of about 1200°C for about 30 minutes in the air.
  • semiconductor layer 112 including insulating film 13 was subjected to a nitrogen annealing process.
  • semiconductor layer 112 including insulating film 13 was heated at a temperature of about 1100°C for about 120 minutes in an atmosphere of nitrogen monoxide (NO) gas. Consequently, a maximum value of nitrogen concentration in a region of not more than 10 nm from an interface between semiconductor layer 112 and insulating film 13 was set to be not less than 1 ⁇ 10 21 cm -3 .
  • NO nitrogen monoxide
  • Semiconductor layer 112 having been subjected to the nitrogen annealing process was further subjected to an inert gas annealing process in an atmosphere of argon gas.
  • semiconductor layer 112 having been subjected to the nitrogen annealing process was heated at a temperature of about 1100°C for about 60 minutes in an atmosphere of argon gas.
  • Insulating film 113 formed as described above was patterned by removing a portion of insulating film 113.
  • Insulating film 113 was patterned in each case such that a channel direction was included in a range of ⁇ 90° from the ⁇ 11-20> direction in main surface 112a of semiconductor layer 112. That is, insulating film 113 was patterned in each case such that the channel direction is parallel to any direction in a range of ⁇ 11-20> direction - 90° to ⁇ 11-20> direction + 90° in main surface 112a of semiconductor layer 112.
  • the portion of insulating film 113 was removed as follows. An etching mask having been patterned by photolithography and etching to expose a portion where insulating film 113 was removed was formed on a main surface of insulating film 113. Thereafter, the exposed portion of insulating film 113 was removed by etching, to form insulating film 113 shown in Fig. 21 .
  • Source electrode 116 was formed to be in contact with a main surface of n type impurity diffusion layer 115 in main surface 112a of semiconductor layer 112 exposed through the portion where insulating film 113 had been removed.
  • Source electrode 116 was formed by forming a conducting film made of nickel by sputtering on main surface 112a of semiconductor layer 112 exposed after etching of insulating film 113 described above and on a main surface of the etching mask, and then removing the etching mask. That is, the conducting film formed on the main surface of the etching mask was removed (lifted off) along with the etching mask, leaving only the conducting film formed on main surface 112a of semiconductor layer 112 as source electrode 116.
  • Semiconductor layer 112 including source electrode 116 was subjected to heat treatment for alloyzation. During the heat treatment for alloyzation, semiconductor layer 112 including source electrode 116 was heated at a temperature of about 950°C for about 2 minutes in an atmosphere of argon gas,
  • Gate electrode 117 was formed on the main surface of insulating film 113.
  • Gate electrode 117 was formed as follows. A resist mask having an opening in a portion where gate electrode 17 was to be formed was formed by photolithography and etching to cover the entire main surface of insulating film 113 and the entire main surface of source electrode 116. A conducting film made of aluminum was formed by sputtering on a main surface of the resist mask and on the main surface of insulating film 113 exposed through the opening of the resist mask. The resist mask was then removed. That is, the conducting film formed on the main surface of the resist mask was removed (lifted off) along with the resist mask, leaving only the conducting film formed on the main surface of insulating film 113 as gate electrode 117.
  • drain electrode 118 was formed on a rear surface of SiC substrate 110.
  • drain electrode 118 a conducting film made of nickel was formed by sputtering on the rear surface of SiC substrate 110.
  • various DMOSFETs 100 shown in Fig. 21 each having a channel in a range of not more than -90° from the ⁇ 11-20> direction were manufactured. Relation between an angle (°) with respect to the ⁇ -2110> direction in main surface 112a (crystallographic plane inclined at not less than 50° and not more than 65° in the ⁇ 1-100> direction as well as at not less than -10° and not more than 10° in the ⁇ 11-20> direction with respect to the ⁇ 0001 ⁇ plane) of semiconductor layer 112 in DMOSFETs 100 having the various channel directions and channel mobility (relative value) was determined. The results are shown in Fig. 22 .
  • a vertical axis represents the channel mobility (relative value), while a horizontal axis represents the angle (°) with respect to the ⁇ 11-20> direction in main surface 112a of semiconductor layer 112.
  • the angle (°) on the horizontal axis in Fig. 22 does not limit a direction of inclination with respect to the ⁇ 11-20> direction. Accordingly, -10° on the horizontal axis refers to both a direction inclined at +10° and a direction inclined at -10° with respect to the ⁇ 11-20> direction.
  • the channel mobility (relative value) on the vertical axis in Fig. 22 is represented in a relative value, with channel mobility in the ⁇ 11-20> direction in main surface 112a of semiconductor layer 112 being assumed as 1.
  • a portion corresponding to an angle (°) of 0° on the horizontal axis in Fig. 22 indicates the ⁇ 11-20> direction in main surface 112a of semiconductor layer 112.
  • the channel mobility is the highest when the channel direction is in the direction of an angle of 0° with respect to the ⁇ 11-20> direction ( ⁇ 11-20 direction>) in main surface 112a of semiconductor layer 112, and that the channel mobility tends to be lower with increase in deviation from the ⁇ 11-20> direction in main surface 112a of semiconductor layer 112.
  • main surface 112a of semiconductor layer 112 is a crystallographic plane inclined at not less than 50° and not more than 65° in the ⁇ 1-100> direction as well as at not less than -10° and not more than 10° in the ⁇ 11-20> direction with respect to the ⁇ 0001 ⁇ plane.
  • the channel direction being in the ⁇ 11-20> direction in main surface 112a of semiconductor layer 112 is considered most preferable.
  • the channel direction is in a direction having an angle of not less than -10° and not more than 0° with respect to the ⁇ 11-20> direction in main surface 112a of semiconductor layer 112 (i.e., a direction inclined at ⁇ 10° in the ⁇ 11-20> direction)
  • the channel mobility (relative value) is higher than 0.99, as shown in Fig. 22 . Accordingly, variation to some extent in channel mobility of DMOSFET 100 is unlikely to cause significant reduction in channel mobility.
  • DMOSFET 100 has a channel direction in a range of inclination of ⁇ 10° in the ⁇ 11-20> direction in main surface 112a of semiconductor layer 112.
  • the ⁇ 11-20> direction in main surface 112a of semiconductor layer 112 needs to be identified. Since main surface 112a of semiconductor layer 112 has the same crystal orientation as that of main surface 111 of SiC substrate 110, the ⁇ 11-20> direction needs to be identified in main surface 111 of SiC substrate 110.
  • SiC substrates 10, 30 and 40 according to the present invention include first ori-fla 12, third side 31c, and mark 45 for identifying the ⁇ 11-20> direction, respectively. Accordingly, the ⁇ 11-20> direction can be identified in main surface 112a of semiconductor layer 112, so that a channel can be formed to have high mobility.
  • channel mobility was high in the direction inclined at not less than -10° and not more than 10° in the ⁇ 11-20> direction in a semiconductor device fabricated on the plane inclined at not less than 50° and not more than 65° in the ⁇ 1-100> direction with respect to the ⁇ 0001 ⁇ plane.
  • SiC substrates 10, 30 and 40 of the present invention including first ori-fla 12, third side 31c, and mark 45 for identifying the ⁇ 11-20> direction, respectively, allow fabrication of a SiC semiconductor of high channel mobility.

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JP2012089613A (ja) * 2010-10-18 2012-05-10 Sumitomo Electric Ind Ltd 炭化珪素基板を有する複合基板の製造方法
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JP2012089639A (ja) * 2010-10-19 2012-05-10 Sumitomo Electric Ind Ltd 単結晶炭化珪素基板を有する複合基板
JP6119100B2 (ja) * 2012-02-01 2017-04-26 住友電気工業株式会社 炭化珪素半導体装置
JP6930640B2 (ja) * 2017-03-08 2021-09-01 住友電気工業株式会社 炭化珪素単結晶基板、炭化珪素エピタキシャル基板および炭化珪素半導体装置の製造方法
JP7352058B2 (ja) * 2017-11-01 2023-09-28 セントラル硝子株式会社 炭化ケイ素単結晶の製造方法
JP6974133B2 (ja) * 2017-11-22 2021-12-01 株式会社ディスコ ＳｉＣインゴットの成型方法
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