EP1794821A1 - Memoire a semi-conducteurs a connexion resistive - Google Patents

Memoire a semi-conducteurs a connexion resistive

Info

Publication number
EP1794821A1
EP1794821A1 EP05782602A EP05782602A EP1794821A1 EP 1794821 A1 EP1794821 A1 EP 1794821A1 EP 05782602 A EP05782602 A EP 05782602A EP 05782602 A EP05782602 A EP 05782602A EP 1794821 A1 EP1794821 A1 EP 1794821A1
Authority
EP
European Patent Office
Prior art keywords
layer
gese
electrode
memory cell
matrix material
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP05782602A
Other languages
German (de)
English (en)
Inventor
Klaus-Dieter Ufert
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Infineon Technologies AG
Original Assignee
Infineon Technologies AG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Infineon Technologies AG filed Critical Infineon Technologies AG
Publication of EP1794821A1 publication Critical patent/EP1794821A1/fr
Withdrawn legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/20—Multistable switching devices, e.g. memristors
    • H10N70/24—Multistable switching devices, e.g. memristors based on migration or redistribution of ionic species, e.g. anions, vacancies
    • H10N70/245—Multistable switching devices, e.g. memristors based on migration or redistribution of ionic species, e.g. anions, vacancies the species being metal cations, e.g. programmable metallization cells
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0004—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements comprising amorphous/crystalline phase transition cells
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B63/00—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices
    • H10B63/80—Arrangements comprising multiple bistable or multi-stable switching components of the same type on a plane parallel to the substrate, e.g. cross-point arrays
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/011—Manufacture or treatment of multistable switching devices
    • H10N70/041—Modification of switching materials after formation, e.g. doping
    • H10N70/046—Modification of switching materials after formation, e.g. doping by diffusion, e.g. photo-dissolution
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/801—Constructional details of multistable switching devices
    • H10N70/821—Device geometry
    • H10N70/826—Device geometry adapted for essentially vertical current flow, e.g. sandwich or pillar type devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/801—Constructional details of multistable switching devices
    • H10N70/821—Device geometry
    • H10N70/826—Device geometry adapted for essentially vertical current flow, e.g. sandwich or pillar type devices
    • H10N70/8265—Device geometry adapted for essentially vertical current flow, e.g. sandwich or pillar type devices on sidewalls of dielectric structures, e.g. mesa-shaped or cup-shaped devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/801—Constructional details of multistable switching devices
    • H10N70/881—Switching materials
    • H10N70/882—Compounds of sulfur, selenium or tellurium, e.g. chalcogenides
    • H10N70/8825—Selenides, e.g. GeSe

Definitions

  • the invention relates to a semiconductor memory with resistively switching memory cells.
  • the invention further relates to a method for producing a semiconductor memory device with nonvolatile, resistively switching memory cells.
  • a cell array is usually constructed consisting of a plurality of memory cells and a matrix of column and row inlets or word and bit lines.
  • the actual memory cell is located at the crossing points of the leads made of electrically conductive material.
  • the column and row inlets or word and bit lines are in each case electrically connected to the memory cell via an upper electrode or top electrode and a lower electrode or bottom electrode.
  • the respective word and bit lines are selected and subjected to either a write current or a read current.
  • the word and bit lines are controlled by appropriate control devices.
  • RAM Random Access Memory
  • a RAM memory device is a random access memory, that is, data can be stored under a certain address and later read out again at the same address.
  • DRAMs Dynamic Random Access Memory
  • a single, appropriately driven capacitive element such as e.g. a trench capacitor
  • this charge remains in a DRAM memory cell for only a relatively short time, which is why regular charging, e.g. approximately every 64 ms, a so-called "refresh" must be performed, the information content is written again in the memory cell.
  • SRAMs Static Random Access Memories
  • DRAMs Dynamic Random Access Memories
  • SRAMs do not need to be "refreshed", since the data stored in the transistors of the memory cell are preserved as long as a corresponding supply voltage is supplied to the SRAM.
  • NVMs or non-volatile memories such as EPROMs, EEPROMs and flash memories, the stored data remain stored even when the supply voltage is switched off.
  • CMOS complementary metal oxide semiconductor
  • the flash memory concept is faced with the problem of limited write and read cycles with barrier layers, but no optimal solution has yet been found for the high voltages and slow read and write cycles.
  • CB Conductive Bridging RAM
  • CB Conductive Bridging RAM
  • the CBRAM memory cell can be switched by bipolar electrical pulses between different electrical resistance values.
  • such an element can be switched by applying short current or voltage pulses between a very high (eg in the GOhm range) and a significantly lower resistance value (eg in the kOhm range).
  • the switching speeds can be less than a microsecond.
  • CBRAM memory cells in a volume between an upper electrode and a lower electrode or bottom electrode, there is an electrochemically active material, e.g. so-called chalcogenide material of germanium (Ge), selenium (Se), copper (Cu), sulfur (S) and / or silver (Ag), for example, in a GeSe, GeS, AgSe or CuS compound.
  • an electrochemically active material e.g. so-called chalcogenide material of germanium (Ge), selenium (Se), copper (Cu), sulfur (S) and / or silver (Ag), for example, in a GeSe, GeS, AgSe or CuS compound.
  • the above-mentioned switching process is based in the CBRAM memory cell in principle that by applying appropriate current or voltage pulses of certain intensity or height and duration at the electrodes in the electrode disposed between the active material elements of a so-called separation clusters in volume always continue to grow until the two electrodes finally bridged electrically conductive, ie electrically connected to each other, which corresponds to the electrically conductive state of the CBRAM cell.
  • this process can be reversed again, whereby the relevant CBRAM cell can be brought back into a non-conductive state again.
  • a switch between a state with a higher electrical conductivity of the CBRAM memory cell and a state with a lower electrical conductivity of the CBRAM memory cell can be achieved.
  • the switching process in the CBRAM memory cell is based essentially on the modulation of the chemical
  • composition and the local nanostructure of the doped with a metal chalcogenide material which serves as a solid electrolyte and diffusion matrix.
  • the pure chalcogenide material typically exhibits a semiconductive behavior and has a very high electrical resistance at room temperature that is orders of magnitude, i. E. Powers of ten of the ohmic resistance value is higher than that of an electrically conductive metal.
  • the current or voltage pulses applied across the electrodes change the steric arrangement and the local concentration of the ionic and metallic constituents of the element which is mobile in the diffusion matrix. Thereby, the so-called bridging, i. an electrical bridging of the volume between the electrodes of metal-rich precipitates, be caused that the electrical
  • Resistor of CBRAM memory cell changed by several orders of magnitude by the ohmic resistance value is lowered by several orders of magnitude.
  • the surface of glassy sputter deposited GeSe layers of the chalcogenide material also always has an amorphous structure and often contains excess and selenium poorly bound to valence bond with germanium.
  • an annealing process at 250 0 C in an oxygen atmosphere is carried out to oxidize the selenium layer on the surface of the GeSe layer and evaporate.
  • the disadvantage of this method is that that during this annealing, the entire storage element is heated, so that it can lead to an undesirable modification of the layer properties or interfacial interdiffusion.
  • the thermal energies used in this method for the resolution of Selenstromronne lie in the meV range.
  • the general aim of the present invention is to provide a non-volatile semiconductor memory which is characterized by good scalability (nanoscale dimensions).
  • An object of the present invention is to provide a non-volatile semiconductor memory device which ensures low switching voltages at low switching times and enables a high number of switching cycles with good temperature stability.
  • a further object of the present invention is to provide a CBRAM memory cell in which a chemically inert barrier layer is present between the Ag-doped GeSe layer and the Ag top electrode, which improves the switching characteristics of the CBRAM memory cell.
  • the objects are achieved according to the present invention by a resistively switching CBRAM semiconductor memory having the features specified in claim 1.
  • the objects are further achieved by a method for producing a non-volatile, resistively switching CBRAM memory cell having the features specified in claim 10.
  • Advantageous embodiments of the invention are defined in the subclaims.
  • a semiconductor memory with resistive switching, nonvolatile memory cells which are respectively arranged at the intersections of a memory cell array of electrical leads, which are respectively connected via a first electrode and a second electrode to the memory cell
  • the memory cell comprises a plurality of material layers having at least one active matrix material layer serving as an ion conductor of the memory cell utilizing the ion drift in the
  • the matrix material layer has a resistively switching property between two stable states
  • the memory cell comprising a GeSe / Ge: H double layer with a glassy GeSe layer and an amorphous Ge: H layer and the amorphous Ge: H layer between the GeSe layer and the second electrode is arranged.
  • the solution according to the invention is therefore based on the special structure of the layer matrix of a CBRAM memory cell arranged between the electrodes of the column and row inlets and bit lines, wherein the ion conductor of the CBRAM memory cell is designed as a GeSe / Ge: H double layer system a glassy GeSe layer and an overlying amorphous Ge: H layer comprises.
  • the resistive non-volatile storage effect of the CBRAM memory cell is obtained on the one hand, and on the other hand, by means of the thin Ge: H layer containing germanium (Ge) and hydrogen (H) ensured chemical stability of the overlying top electrode, which is preferably made of silver (Ag) in one of the last coating processes.
  • the GeSe / Ge: H double layer system according to the present invention formation of AgSe conglomerates in the Ag doping and / or electrode layer is prevented so that precipitations are prevented and homogeneous deposition of the silver doping layer is made possible.
  • a memory cell comprising an active material, which is displaceable by electrochemical switching operations in a more or less electrically conductive state, wherein the The method comprises at least the following steps:
  • the GeSe / Ge: H double layer is deposited before the Ag doping process step and thus forms the entire active memory layer matrix, into which the Ag ion conductor is then preferably subsequently is incorporated by photodiffusion.
  • the surface layer of the double layer consists of an amorphous Ge: H compound, which is temperature-stable and chemically inert to silver.
  • the method according to the invention for producing a CBRAM memory cell avoids the implementation of an annealing process step in which the doped silver can uncontrollably diffuse through the GeSe matrix and thus short-circuit the CBRAM memory cell.
  • Another advantage of the GeSe / Ge: H double layer produced by the method according to the invention is that the double layer in the same system and without intermediate aeration in a process step by reactive sputtering of a GeSe and Ge target in a noble gas or noble gas / hydrogen mixture can be produced.
  • the GeSe / Ge: H bilayer system can be deposited on the GeSe layer in a common process step, without the need for intermediate filling or the use of another system.
  • the passivation layer is only deposited after the photodiffusion or subsequently carried out in an annealing process in an oxygen atmosphere.
  • deposition of the Ge: H layer onto the already Ag-doped GeSe layer is fundamentally possible since the Ag-doped GeSe layer is not an oxide layer.
  • the advantage of the GeSe / Ge: H double-layer system lies in the chemically inert nature of the interface, the electronically undisturbed connection between the top electrode and the ion conductor in the GeSe / Ge: H matrix layer and in the improved temperature resistance and in the reduced production costs.
  • Double layer matrix into which the Ag ion conductor is diffused Due to the similarity of the structure of the amorphous, glassy GeSe layer and the amorphous Ge: H layer, the subsequent photodiffusion process, with which the silver is incorporated into the GeSe / Ge: H bilayer matrix, is not affected. Due to the spatial separation of the GeSe layer to the Ag top electrode due to the chemical barrier formed by the Ge: H layer to the Ag top electrode, no reaction partner for the silver, in particular no selenium is present, so that the formation of conglomerates in the Ag - Electrode layer is prevented.
  • the switching properties of the GeSe layer matrix described above, on which the resistive non-volatile memory effect of the CBRAM memory cell is based, are not modified by the thin, amorphous Ge: H layer.
  • the amorphous Ge: H layer is more stable in temperature than the GeSe layer or an additional oxide passivation layer and thus improves the temperature resistance of the CBRAM memory element according to the invention during subsequent process steps.
  • the advantages of the GeSe / Ge: H bilayer explained above are significant for the stable operation of the CBRAM memory element.
  • the formation of the GeSe / Ge: H bilayer can be achieved by modifying known processes for making a GeSe: Ag resistive, nonvolatile CBRAM memory element.
  • a sputter coating plant such as in the system ZV 6000 Fa. Leybold or similar systems of the Fa. KDF, without interruption of the vacuum three different sputtering targets are used.
  • To produce the GeSe / Ge: H: Ag storage element for example, a GeSe, Ge and Ag target are installed in a sputtering system of this type.
  • the GeSe layer is deposited by means of rf magnetron sputtering of a GeSe compound target into the prefabricated vias of the memory element.
  • argon is usually used as the sputtering gas at a pressure of about 4 to 5 ⁇ 10 -3 mbar and an RF sputtering power in the range of 1 to 2 kW.
  • the generated layer thickness is about 40 nm to 45 nm.
  • the elementary Ge target is atomized instead of the GeSe target.
  • a reactive noble gas / hydrogen mixture is used, wherein the hydrogen reacts with the germanium to Ge: H on the layer surface.
  • the same pressure and the same rf power can be used as in the first second sub-step, wherein the second
  • Sub-step generated layer thickness should be in the range of 5 nm to 10 nm.
  • a similar sputtering process as for the deposition of absorber material for thin-film solar cells can be used.
  • a GeSe / Ge: H bilayer matrix is generated according to the present invention.
  • the Ag top electrode is deposited by dc magnetron sputtering from the Ag element target in a noble gas.
  • FIG. 1 shows the schematic structure of a CBRAM
  • Memory cell with a GeSe / Ge: H bilayer matrix in a preferred embodiment of the invention.
  • the incorporation of the GeSe / Ge: H double layer into the via of the CBRAM memory element according to the invention is shown schematically in FIG.
  • the wafers used preferably already have structures for a W bottom electrode and corresponding vias in the insulator layer with the required dimensions.
  • the CBRAM memory cell shown in the figure comprises a layer stack of material layers which is built up on a substrate.
  • the layers are prepared in several process steps according to the present invention in the manner described above.
  • the lowermost layer represents a first electrode or bottom electrode 1, while the uppermost layer consists of a second electrode or top electrode 2.
  • the layer stack of the CBRAM memory cell is connected to the electrical leads, the column and row inlets or word and bit lines of the semiconductor memory via the two electrodes 1 and 2.
  • the electrodes 1, 2 are each fabricated in a sputtering process using an Ag sputtering target of silver. Between the electrodes 1, 2 there is an active matrix material layer 3, which contains a GeSe / Ge: H double layer.
  • the matrix material layer 3 is doped with silver ions and has an amorphous, micromorphic or microcrystalline structure.
  • a doping layer (not shown) which serves to doping the matrix material layer 3 with silver ions, and on the doping layer is the layer of the second electrode 2.
  • a contact hole 6 is provided, which enables a contacting of the bottom electrode 1 from above.
  • the material layers of the memory cell are bounded laterally by a dielectric 4, 5, which is arranged between the contact hole 6 and the material layers of the memory cell.
  • the GeSe / Ge: H double layer comprises a GeSe layer and a Ge: H layer arranged above it, so that the Ge: H
  • the GeSe / Ge: H double-layer matrix is first produced, into which the Ag ion conductor is subsequently diffused by a photodiffusion process. Due to the similarity of the structure of the amorphous, glassy GeSe layer and the amorphous Ge: H layer, the subsequent photodiffusion process, with which the silver is incorporated into the GeSe / Ge: H bilayer matrix, is unaffected.
  • the Ge: H layer Due to the spatial separation of the GeSe layer from the Ag top electrode due to the chemical barrier of the thin, amorphous Ge: H layer, the formation of silver Conglomerates on the active matrix material layer 3 effectively prevented, whereby the switching characteristics of the CBRAM memory cell can be improved.
  • the Ge: H layer is more stable in temperature than the GeSe layer and thus improves the temperature resistance of the CBRAM memory element according to the invention during subsequent process steps.

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  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Semiconductor Memories (AREA)

Abstract

L'objet de la présente invention est la mise au point d'une mémoire à semi-conducteurs rémanente pourvue de cellules de RAM à pontage conducteur (CBRAM) possédant entre la couche GeSe à dopage Ag et l'électrode supérieure Ag une couche frontière chimiquement inerte qui améliore les propriétés de connexion de la cellule de mémoire CBRAM. A cet effet, la couche de matière de matrice active de la cellule de mémoire comporte une double couche GeSe/Ge:H (3) constituée d'une couche GeSe vitreuse et d'une couche Ge:H amorphe, la couche Ge:H amorphe étant située entre la couche GeSe et la deuxième électrode (2). La formation d'agglomérats de AgSe dans la couche à dopage Ag et / ou dans la couche électrode est ainsi évitée, ce qui empêche les séparations et permet un dépôt homogène de la couche dopée à l'argent. Grâce au système de double couche GeSe/Ge:H, il est possible d'une part de conserver l'action rémanente et résistive de la cellule de mémoire CBRAM et d'autre part de garantir, à l'aide de la couche mince Ge:H, la stabilité chimique de l'électrode supérieure située au-dessus de ladite couche mince.
EP05782602A 2004-09-27 2005-09-07 Memoire a semi-conducteurs a connexion resistive Withdrawn EP1794821A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE102004046804A DE102004046804B4 (de) 2004-09-27 2004-09-27 Resistiv schaltender Halbleiterspeicher
PCT/EP2005/054410 WO2006034946A1 (fr) 2004-09-27 2005-09-07 Memoire a semi-conducteurs a connexion resistive

Publications (1)

Publication Number Publication Date
EP1794821A1 true EP1794821A1 (fr) 2007-06-13

Family

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Family Applications (1)

Application Number Title Priority Date Filing Date
EP05782602A Withdrawn EP1794821A1 (fr) 2004-09-27 2005-09-07 Memoire a semi-conducteurs a connexion resistive

Country Status (8)

Country Link
US (1) US20090045387A1 (fr)
EP (1) EP1794821A1 (fr)
JP (1) JP2007509509A (fr)
KR (1) KR20060082868A (fr)
CN (1) CN1879233A (fr)
DE (1) DE102004046804B4 (fr)
TW (1) TWI292191B (fr)
WO (1) WO2006034946A1 (fr)

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FR2880177B1 (fr) 2004-12-23 2007-05-18 Commissariat Energie Atomique Memoire pmc ayant un temps de retention et une vitesse d'ecriture ameliores
FR2895531B1 (fr) 2005-12-23 2008-05-09 Commissariat Energie Atomique Procede ameliore de realisation de cellules memoires de type pmc
US20070210297A1 (en) * 2006-03-13 2007-09-13 Ralf Symanczyk Electrical structure with a solid state electrolyte layer, memory with a memory cell and method for fabricating the electrical structure
KR100833903B1 (ko) * 2006-06-13 2008-06-03 광주과학기술원 비휘발성 기억소자, 그 제조방법 및 그 제조장치
US8038850B2 (en) * 2006-06-23 2011-10-18 Qimonda Ag Sputter deposition method for forming integrated circuit
US8178379B2 (en) * 2007-04-13 2012-05-15 Qimonda Ag Integrated circuit, resistivity changing memory device, memory module, and method of fabricating an integrated circuit
FR2922368A1 (fr) 2007-10-16 2009-04-17 Commissariat Energie Atomique Procede de fabrication d'une memoire cbram ayant une fiabilite amelioree
FR2934711B1 (fr) * 2008-07-29 2011-03-11 Commissariat Energie Atomique Dispositif memoire et memoire cbram a fiablilite amelioree.
TWI401796B (zh) * 2008-12-30 2013-07-11 Ind Tech Res Inst 導通微通道記憶體元件及其製造方法
US20110084248A1 (en) * 2009-10-13 2011-04-14 Nanya Technology Corporation Cross point memory array devices
TWI625874B (zh) * 2015-11-05 2018-06-01 華邦電子股份有限公司 導電橋接式隨機存取記憶體

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US6635914B2 (en) * 2000-09-08 2003-10-21 Axon Technologies Corp. Microelectronic programmable device and methods of forming and programming the same
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Also Published As

Publication number Publication date
US20090045387A1 (en) 2009-02-19
JP2007509509A (ja) 2007-04-12
TW200618114A (en) 2006-06-01
WO2006034946A1 (fr) 2006-04-06
DE102004046804B4 (de) 2006-10-05
CN1879233A (zh) 2006-12-13
KR20060082868A (ko) 2006-07-19
DE102004046804A1 (de) 2006-04-06
TWI292191B (en) 2008-01-01

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