Classifications

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  • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
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  • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
  • H01L29/76—Unipolar devices, e.g. field effect transistors
  • H01L29/772—Field effect transistors
  • H01L29/78—Field effect transistors with field effect produced by an insulated gate
  • H01L29/792—Field effect transistors with field effect produced by an insulated gate with charge trapping gate insulator, e.g. MNOS-memory transistors
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  • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
  • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
  • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
  • H01L29/76—Unipolar devices, e.g. field effect transistors
  • H01L29/772—Field effect transistors
  • H01L29/78—Field effect transistors with field effect produced by an insulated gate
  • H01L29/792—Field effect transistors with field effect produced by an insulated gate with charge trapping gate insulator, e.g. MNOS-memory transistors
  • H01L29/7923—Programmable transistors with more than two possible different levels of programmation
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  • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
  • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
  • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
  • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
  • H01L21/84—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body
  • H01L21/845—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body including field-effect transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
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  • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
  • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
  • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
  • H01L27/1203—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI
  • H01L27/1211—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI combined with field-effect transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
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  • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
  • H01L29/66007—Multistep manufacturing processes
  • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
  • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
  • H01L29/66409—Unipolar field-effect transistors
  • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
  • H01L29/66833—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a charge trapping gate insulator, e.g. MNOS transistors
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  • H10B—ELECTRONIC MEMORY DEVICES
  • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
  • H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
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  • H10B—ELECTRONIC MEMORY DEVICES
  • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
  • H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
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  • H10B—ELECTRONIC MEMORY DEVICES
  • H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
  • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
  • H01L29/66007—Multistep manufacturing processes
  • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
  • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
  • H01L29/66409—Unipolar field-effect transistors
  • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
  • H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
  • H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
  • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
  • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
  • H01L29/76—Unipolar devices, e.g. field effect transistors
  • H01L29/772—Field effect transistors
  • H01L29/78—Field effect transistors with field effect produced by an insulated gate
  • H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

Definitions

• Bridge field effect transistor memory cell Bridge field effect transistor memory cell arrangement and method for producing a bridge field effect transistor memory cell
• the invention relates to a fin field effect transistor memory cell, a fin field effect transistor memory cell arrangement and a method for producing a fin field effect transistor memory cell.
• a floating gate memory is known from the prior art, in which an electrically conductive floating gate region is arranged above a gate-insulating layer of a field effect transistor integrated in a substrate and in which electrical charge carriers are permanent by means of Fowler-Nordheim tunnels can be introduced. Due to the field effect, the value of the threshold voltage of such a transistor depends on whether charge carriers are stored in the floating gate or not. Thus, in the presence or absence of electrical charge carriers in the floating gate layer, storage information can be encoded.
• a high voltage of typically 15V to 20V is required to introduce electrical charge carriers into a floating gate. This can damage sensitive integrated components and is also unattractive for energy-saving (e.g. low-power applications) or mobile applications (e.g. mobile phones, personal digital assistants, PDAs).
• energy-saving e.g. low-power applications
• mobile applications e.g. mobile phones, personal digital assistants, PDAs.
• a silicon nitride trapping layer is used as the gate-insulating layer of a field-effect transistor, it being possible for channel carriers to be introduced permanently into the silicon nitride layer as a charge-receiving layer by means of channel hot electron injection (tunneling of hot electrons) , Typical programming voltages in this case are approximately 9V, and write times of 150ns are achieved on a single cell.
• a NROM memory cell is known in which two bits of memory information can be stored in a transistor.
• NROM memory cell has the disadvantage of high power consumption. Furthermore, the scalability of NROM memory cells is poor due to short-channel effects, such as the "punch through” effect, which occur in particular with a channel length of typically less than 200 nm. In addition, with a small width of transistors of NROM memory cells, the read current is very small. This also stands in the way of continued scaling.
• Memory cell arrangements known from the prior art are a NAND arrangement with planar floating gate memory cells or so-called “virtual ground arrays" with NROM memory cells for storing two bits of information per memory cell. With these memory cell arrangements, storage capacities of approximately 1 Gbit can be achieved. However, for technological reasons, a continuous increase in the storage density is difficult due to the poor scalability of these memory cell arrangements.
• [2] describes non-volatile fin field effect transistor memory cells in which the material of the gate electrodes is present on the two side walls of the fin. The gate electrodes are made of metal or polysilicon.
• [3] describes a process for applying a polycarbonate layer to a planar oxidized silicon substrate by means of a deposition process using methane as the hydrocarbon precursor material. It is further disclosed in [3] that this poly-carbon layer can be used as a gate material for a planar MOS field-effect transistor.
• [4] discloses a planar field effect transistor in which the gate insulating layer has a carbon layer which covers the gate electrode.
• [5] also describes a planar chemical field effect transistor with a source region and drain region arranged on a semiconductor substrate, which are connected to one another by means of a conductive channel.
• the gate electrode of the planar chemical field effect transistor is formed by a carbon electrode.
• [6] describes a non-volatile memory cell arrangement with a carbon layer as an electrode
• the invention is based on the problem of providing a memory cell which can also be scaled down to small dimensions.
• the problem is solved by a fin field effect transistor memory cell, by a fin field effect transistor memory cell arrangement and by a method for
• the fin field effect transistor memory cell according to the invention contains a first and a second source / drain region and a channel region arranged between them, which source / drain and channel regions are formed in a semiconductor fin. Furthermore, a charge storage layer is provided, which is arranged at least partially on the semiconductor bridge.
• the land field effect transistor memory cell contains a metallically conductive gate region on at least part of the charge storage layer, the charge storage layer being set up in such a way that predeterminable electrical potentials are applied to the land field effect transistor memory cell in the
• Charge storage layer electrical charge carriers can be selectively introduced or removed therefrom.
• the bridge field effect transistor memory cell arrangement according to the invention contains a plurality of bridge field effect transistor memory cells with the features described above.
• Bridge field effect transistor memory cell a first and a second source / drain region and a channel region arranged between them are formed in a semiconductor bridge. Furthermore, a charge storage layer is at least partially formed on the semiconductor bridge. A metallic conductive gate region is formed on at least part of the charge storage layer.
• the charge storage layer is set up in such a way that by applying! Predefinable electrical potentials on the fin field effect transistor memory cell in the charge storage layer can be selectively introduced or removed from electrical charge carriers.
• the gate region of a fin field effect transistor memory cell (or the word line region of a fin field effect transistor memory cell arrangement) is formed from a metallically conductive material, i.e. a material that has an electrical conductivity that is characteristic of a metallic material.
• metallically conductive material i.e. a material that has an electrical conductivity that is characteristic of a metallic material.
• metallic material, doped polycrystalline silicon material or carbon-containing material is introduced between adjacent semiconductor webs or semiconductor fins.
• the metallically conductive material is preferably at least partially arranged on the side walls of the semiconductor webs or semiconductor fins.
• gate region or word line made of a metallically conductive material leads to low-resistance control of the memory cell and brings about an improved erase performance, in particular when used as a material P-type dopant provided polycrystalline
• Silicon is used, or a metal with a work function of preferably greater than 4.1 eV.
• This improved erasure performance results from a particularly advantageous potential profile between the channel area, the charge storage layer (e.g. provided as an ONO layer sequence) and the gate area in a realization from a metallically conductive material.
• the web field-effect transistor memory cell according to the invention combines a high storage density of, for example, 8 Gbit / cm 2 and more with a high readout rate.
• An aspect ratio is understood to mean the ratio of height to width of the area between adjacent fins of a memory cell arrangement. Such a distance can be on the order of 10 nm, the height of a fin can be 50 nm, for example.
• Charge storage layer can be executed.
• Memory cells with an electrically insulating charge storage layer enable lower programming voltages than those with Floating gate.
• Charge storage layer can also be referred to as a trapping layer, since electrical charge carriers are clearly captured in the electrically insulating layer.
• the charge storage layer can for example be a silicon oxide-silicon nitride-silicon oxide layer sequence (ONO layer sequence), aluminum oxide, yttrium oxide,
• the gate region of the land field effect transistor memory cell according to the invention or a word line region of the land field effect transistor memory cell arrangement can have carbon material or consist of carbon material.
• the gate region is made of a carbon-containing material, even with fins or webs that have a very small dimension or a very small distance from one another, gaps between adjacent fins can be made safely and with avoidance of air holes with material that impair the electrical controllability of the storage cell Gate area to be filled form-fitting.
• the homogeneous covering of the semiconductor webs provided with the charge storage layer with the carbon-containing gate region achieved according to the invention has the effect that when an electrical voltage is applied to the gate region, the electrical properties of the memory cell can be precisely controlled or set by means of the field effect. This enables the memory cell to function properly even at high storage densities.
• a low-resistance, high-quality and miniaturized electrical control line for a transistor memory cell can also be wetted with material using carbon material for the gate regions or word line regions.
• the carbon material also has good electrical conductivity even with small thicknesses.
• the carbon layer of the web field effect transistor memory cell according to the invention has good adhesion properties, in particular on a silicon oxide layer, so that undesired detachment of such layers from one another is avoided.
• the carbon layer can be structured, for example, using an oxygen plasma or nitrogen plasma etching method with high quality and at reasonable cost.
• the deposition of silicon nitride material (for example as a cover or passivation layer) on the carbon-containing layer is technologically possible without any problems.
• Doping material can be introduced into the carbon material in order to increase the electrical conductivity of the gate region.
• boron, aluminum, indium, phosphorus or arsenic can be used as the doping material.
• Such doping material can, for example, be introduced or injected into the gate region during the manufacture of the carbon-containing gate region, for example by feeding an additional precursor comprising doping material into the process chamber during a chemical vapor deposition (CVD) process.
• an additional precursor for providing boron doping material is, for example, diborane (B 2 H S ). •
• the semiconductor web can be formed from a bulk silicon substrate or from a silicon-on-insulator substrate.
• the memory cell according to the invention can be implemented in bulk silicon technology or in SOI technology.
• the Gate area preferably polycrystalline silicon or a
• the gate region can have doped polycrystalline silicon, it being possible for the doping atoms to be of the n-conductivity type or of the p-conductivity type.
• the polycrystalline silicon preferably has p-type dopant, for example boron,
• the polycrystalline silicon is p + -doped (ie has a very strong p-doping), a particularly effective quenching performance can be obtained on the basis of the advantageous energy band profile then obtained (cf. FIG. 9 and associated description).
• metals' a sufficiently high work function As in the case of a p-doped gate material, the gate current is reduced by a high barrier to the top oxide, so that efficient deletion is achieved by the hole current from the substrate.
• the gate region can have a metal with a work function that is sufficiently high to keep a gate current required for erasing the memory cell low.
• the gate region can have a metal with a work function of at least 4.1 electron volts.
• the fin field effect transistor memory cells of the fin field effect transistor memory cell arrangement can be arranged essentially in the form of a matrix.
• Bridge field effect transistor memory cells arranged along a first direction can have common word line regions which are coupled to the gate regions of the associated bridge field effect transistor memory cells and are formed from the same material as the gate regions.
• the gate regions and the word line regions of a row or column of fin field effect transistor memory cells of the memory cell arrangement can clearly consist of a one-piece and one-material carbon structure.
• the fin field effect transistor memory cell arrangement can be set up as a NAND memory cell arrangement.
• the fins can be arranged to run essentially orthogonally to the word line regions.
• the word line regions can be used as a mask for forming the source / drain regions of the fin field effect transistor memory cells.
• NAND architecture it is possible to clearly use a semiconductor fin as part of the bit line.
• vias are preferably formed at a distance of a predetermined number (typically eight or sixteen) of memory cells of a semiconductor fin, by means of which the source / drain regions are coupled to metallic bit lines of a wiring level.
• the land field effect transistor memory cell arrangement according to the invention can be set up in such a way that charge carriers enter the at least one gate region and at least part of the source / drain regions by means of the application of predeterminable electrical potentials
• Charge storage layer of a selected bridge field effect transistor memory cell can be selectively introduced or removed by means of Fowler-Nordheim tunnels.
• the bridge field effect transistor memory cell arrangement can have at least a first bit line region and at least a second bit line region, the first source / drain region of a respective Steoj field effect transistor memory cell is coupled to an assigned first bit line area and the second source / drain area of a respective fin field effect transistor memory cell is coupled to an assigned second bit line area.
• bit line areas can be in a wiring level above
• Gate areas or the word line areas may be provided, wherein a memory cell in a crossing area of a word line and a bit line is controlled by means of an associated word line and is read out or programmed by means of associated bit lines.
• the first and second bit line regions can be arranged essentially running in a second direction, which second direction is arranged obliquely to the first direction.
• the semiconductor fin is preferably in the
• bit line areas Arranged essentially orthogonal to the word line or the coupled gate regions.
• bit line areas To be provided, for example, in a wiring level arranged above the word line level, at an angle to the word lines, for example at a 45 ° angle.
• the first and second bit line regions can run in a straight line or have a zigzag or sawtooth structure. If a bit line region is provided as a zigzag or sawtooth-like structure which extends essentially obliquely to the word line regions along the second course direction, it is possible to add bit line regions of essentially the same length and thus having essentially the same ohmic resistance form with which source / drain regions of fin field effect transistor memory cells can be controlled.
• the semiconductor fins of the fin field effect transistor memory cells and the word line regions can be arranged running in a third direction, and first and second bit line regions can be arranged running in a fourth direction, which third direction is arranged perpendicular to the fourth direction ,
• charge carriers can be selectively introduced or removed from the charge storage layer in a selected fin field effect transistor memory cell by means of tunneling hot charge carriers.
• tunneling hot electrons or tunneling hot holes electrical charge carriers can be permanently introduced into the charge-evacuating layer with short writing times electrical charge carriers the storage information is encoded.
• the described bridge field effect transistor memory cell arrangement can be used to store two bits of information in a bridge field effect transistor memory cell by introducing charge carriers into the charge storage layer into a boundary region between the first source / drain region and the channel region and into one Border region between the second source / drain region and the channel region of the respective land field effect transistor memory cell can be set up.
• the memory cell arrangement of the invention can thus be operated as a dual-bit memory cell, so that a high-density semiconductor memory is created.
• the first and second bit line areas can be implemented as virtual ground wiring.
• the semiconductor fins of adjacent fin field effect transistors can be combined in one . Distance from 10 nm to 100 nm, preferably at most 30 nm, more preferably at most 20 nm or at most 10 nm from one another. Even with very small distances between adjacent semiconductor fins, it is possible to create a gate region of sufficient conformity and quality from a carbon-containing material.
• an electrically insulating cover layer covering at least partially the word line regions can be provided.
• a silicon nitride cover layer has particularly good material properties in combination with a carbon-containing word line region. In particular, detachment of such a cover layer is reliably avoided.
• the cover layer can extend into cavities between semiconductor webs covered with the word line region.
• the cover layer can thus also be used as a spacer or decoupling element between adjacent fins, as a result of which undesired crosstalk between adjacent memory cells is avoided.
• a mechanical decoupling of adjacent memory cells is realized by means of the regions of the cover layer between adjacent semiconductor fins
• the method according to the invention for producing a fin field effect transistor memory cell is described in more detail below. Refinements of the fin field effect transistor memory cell or the fin field effect transistor memory cell arrangement also apply to the method for producing a fin field effect transistor memory cell and vice versa.
• the carbon material of the gate area can be under
• CVD chemical vapor deposition
• methane (CH 4 ) acetylene (C 2 H 2 ) or ethene (C 2 H 4 ) can be used to form the carbon material.
• methane gas is particularly suitable as a precursor in a CVD process, since this small molecule can penetrate particularly well into the narrow spaces between adjacent semiconductor fins.
• methane gas is particularly suitable as a precursor to form the carbon-containing gate region, air holes are particularly reliably avoided.
• Doping material is set up in such a way that it increases the electrical conductivity of the gate region.
• diborane can be supplied as a boron source for doping the carbon-containing material of the gate region, which results in a very homogeneous boron doping in the
• the carbon material After the carbon material has been formed, it can be subjected to a tempering process step.
• the carbon material formed can be treated for approximately two minutes in an argon atmosphere and at a temperature of typically 1000 to 1100 ° C., preferably 1050 ° C.
• the ohmic resistance of the carbon layer can typically be reduced by a factor of two or more.
• the material property of the gate region can therefore be additionally improved by means of the tempering process step.
• the following parameters can be used for a production process for the carbon-containing layer in the context of a CVD process.
• Hydrogen gas with a pressure between 10 "4 bar and 10 " 2 bar, preferably 10 "3 bar, for example, can be used as the gas for preconditioning.
• methane can be used as a carbon source for forming the carbon-containing layer with a pressure between 0.2bar and 0.7bar
• the operating temperature during the production process is typically between 950 ° C. and 1000 ° C.
• the thickness of the carbon layer can be set by specifying the processing time.
• Energy can be supplied by means of an electromagnetic radiation source in order to produce the fin field effect transistor memory cell according to the invention.
• the process chamber can thus be heated to 800 ° C. with a vivid photonic heater, that is to say an electromagnetic radiation source as an energy source.
• the carbon layer is then produced at a pressure between 10 "3 bar and 10 " 2 bar, preferably 3.3 10 "3 bar, hydrogen and between 10 " 3 bar and 10 _1 bar, preferably 10% methane.
• the carbon material can be deposited and patterned using a plasma etch process to form the gate region.
• a hydrogen plasma or oxygen plasma etching method is preferably used for the plasma etching method.
• FIG. 1 shows a cross-sectional view of a fin field effect transistor memory cell arrangement according to a first exemplary embodiment of the invention
• FIG. 2 shows the fin field effect transistor memory cell arrangement shown in FIG. 1 in an operating state in which electrical charge carriers are introduced into the charge storage layer
• FIGS. 3A to 3D to produce layer sequences at different times during a method the fin field effect transistor memory cell arrangement from FIG. 1,
• FIG. 4 shows a layout top view of a fin field effect transistor memory cell arrangement according to the first exemplary embodiment of the invention
• FIG. 5 shows a layout top view of a fin field effect transistor memory cell arrangement according to a second exemplary embodiment of the invention
• FIG. 6 shows a fin field effect transistor memory cell arrangement according to a third exemplary embodiment of the invention, with sawtooth-shaped bit lines,
• FIG. 7 shows a cross-sectional view of a fin field effect transistor memory cell arrangement according to a fourth exemplary embodiment of the invention.
• FIG. 8 shows a layout top view of a fin field effect transistor memory cell arrangement according to the fourth exemplary embodiment of the invention
• FIG. 9 shows an energy band profile between the channel region, the ONO charge storage layer and the metallically conductive gate region of a fin field effect transistor memory cell according to an exemplary embodiment of the invention.
• the gate region is formed from carbon-containing material
• all of these exemplary embodiments can alternatively be implemented with another metallic conductive material as the gate region, in particular with polysilicon material, preferably with p- doped polysilicon material and further preferably with p + -doped polysilicon material
• a first land field effect transistor memory cell 110 and a second land field effect transistor memory cell 111 are shown.
• the fin field effect transistor memory cell arrangement 10O is formed on a silicon substrate 101.
• a buried silicon oxide layer 102 is formed on the silicon substrate 101.
• the fin field effect transistor memory cell arrangement 100 is formed from an SOI substrate which has the silicon substrate 101, the buried silicon oxide layer 102 and a silicon layer arranged on the buried silicon oxide layer 102 from the in Fig.l due to the
• Each of the fin field effect transistor memory cells 110, 111 has a first and a second source / drain region, which cannot be seen in FIG. 1.
• a channel region 105 is shown in the cross-sectional view of FIG. The first and second source / drain areas are clearly in one the paper plane of Fig.l vertical direction above the
• Each channel region 105 forms, together with the two assigned source / drain regions, a silicon fin or a silicon web, which is arranged perpendicular to the paper plane of FIG.
• An ONO charge storage layer sequence 106 is formed on each silicon ridge.
• the ONO charge storage layer sequence 106 consists of two
• Silicon oxide layers and a silicon nitride layer arranged between them as a trapping layer for introducing electrical charge carriers are provided.
• a carbon word line 107 is applied to the charge barrier layer 106.
• those sections of the carbon word line 107 which cover the region of the charge storage layer 106 arranged on a respective channel region 105 form the gate region of the associated fin field effect transistor memory cell 110 or 111.
• the distance is between adjacent silicon fins in the range of 30nm or less as shown in Fig.2. Despite this very small distance between adjacent semiconductor fins, the carbon layer 107 can be deposited on the charge storage layer 106 in a very conformal manner and avoiding air holes.
• the carbon word line 107 is coated with a silicon nitride cover layer 108 which extends into areas between the fins.
• Silicon nitride has very good adhesive properties on carbon and, due to the post-like spacers in the trenches covered with carbon material, causes one between adjacent fins mechanical decoupling between adjacent fin field effect transistor memory cells 110, 111. If the distances between the fins are very narrow, the silicon nitride material no longer penetrates into the trench, since the carbon material completely fills the trench.
• FIG. 2 shows the fin field-effect transistor memory cell arrangement 100 in an operating state in which electrical charge carriers 200, namely electrons, are inserted into the silicon oxide trapping layer of the ONO-
• Charge storage layer sequence 106 are introduced.
• the information stored in the memory cells 110, 111 is encoded in these introduced electrons.
• the electrical charge carriers 200 are introduced into the ONO charge storage layer sequence 106 by means of Fowler-Nordheim tunnels.
• the bridge field effect transistor memory cell arrangement 100 as
• the electrical charge carriers 200 are introduced into the ONO charge storage layer sequence 106 by means of tunneling hot charge carriers.
• Charge storage layer sequence 106 effectively have the effect of a gate voltage, as can be applied to a carbon word line 107. This is because the electrical charge carriers 200 influence the electrical conductivity of the channel region 105 in a manner similar to an electrical voltage applied to the gate region 107.
• 111 the value of the electrical current flow between the two source / drain regions depending on whether or not charge carriers are introduced in the ONO charge storage layer sequence 106.
• the storage information of the respective land field effect transistor memory cell 110, 111 is thus encoded in the electrical charge carriers 200.
• a method for producing the fin field effect transistor memory cell arrangement 100 shown in FIG. 1 is described below with reference to FIGS. 3A to 3D.
• the field effect transistor memory cell arrangement 100 is formed on the basis of an SOI substrate 302 (“silicon-on-insulator”), which consists of silicon substrate 101, the buried silicon oxide layer 102 arranged thereon and a silicon layer 301 arranged thereon ,
• SOI substrate 302 silicon-on-insulator
• a bulk wafer with a suitable well doping can also be used.
• the silicon layer 301 of the layer sequence 300 is structured using a lithography and an etching method in such a way that first and second silicon fins are spaced apart from one another by less than 30 nm 311, 312 are formed.
• a photoresist layer (not shown) is first applied to the silicon layer 301 and structured using an etching process. After the areas between adjacent fins 311, 312 have been etched, the photoresist layer is removed (“stripped”) from the surface of the layer sequence.
• an ONO charge storage layer sequence 106 is applied to the silicon fins 311, 312.
• a first silicon oxide partial layer is first deposited, a silicon nitride partial layer is deposited on the first silicon oxide partial layer, and a second silicon oxide partial layer is deposited on the silicon nitride partial layer.
• the two silicon oxide partial layers and the silicon nitride partial layer arranged between them form the ONO charge storage layer sequence 106.
• a carbon layer 321 is formed on the ONO charge storage layer sequence 106 using a chemical vapor deposition (CVD) method to form gate layers. or word line areas separated.
• CVD chemical vapor deposition
• the carbon layer 321 is structured using a lithography and a plasma etching method (oxygen plasma etching) such that the carbon word line 107 is thereby formed.
• the carbon word lines 107 are used as an implantation mask when introducing doping material of the n-type into those regions of the silicon fins 311, 312 which form first and second source / drain regions of the fin field effect transistor memory cells.
• a silicon nitride cover layer 108 The layer sequence thus obtained is then covered with a silicon nitride cover layer 108.
• a TEOS layer sequence (“tetraethyl orthosilicate”) can be formed as a cover layer.
• Processed top layer 108 of the back-end area in particular metallization levels formed (not shown).
• Storage cell arrangement as a NAND memory cell arrangement or as a dual bit memory cell arrangement.
• a layout plan view of a fin field effect transistor memory cell arrangement 400 according to a second exemplary embodiment of the invention is described below with reference to FIG.
• the fin field effect transistor memory cell arrangement 400 is implemented in NAND architecture (NAND architecture).
• NAND architecture NAND architecture
• the cross-sectional view shown in Figure 1 is taken along line A-A 'shown in Figure 4.
• the semiconductor fins 311, 312 run perpendicular to the carbon word lines 107.
• a fin field effect transistor memory cell is arranged in each crossing region of a silicon fin 311, 312 with a carbon word line 107.
• the extension of a fin field-effect transistor memory cell in the horizontal or vertical direction according to FIG. 4 is 2F, where F is in a
• the land field effect transistor memory cells of the invention are thus formed as memory cells with an area requirement of 4F 2 .
• Word line 107 are free, are formed as n-doped regions.
• a first source / drain region 401 and a second source / drain region 402 are those shown in FIG shown first ridge field effect transistor memory cell 110.
• the web direction 403 is orthogonal to the word line direction 109.
• select transistors and the level of the global bit lines which typically contact the respective source / drain regions at a distance of eight to sixteen memory cells using vias. External control, programming or read voltages can be applied to such low-resistance bit lines. Information of one bit can be stored in each field effect transistor memory cell of the memory cell arrangement 400.
• FIG. 5 shows a layout top view of the memory cell arrangement 500.
• the cross-sectional view shown in FIG. 1 is taken along the line B-B 'shown in FIG.
• the cross-sectional view from FIG. 1 is identical for the memory cell arrangements shown in FIGS. 4 and 5, whereas the interconnection architecture is different for the memory cell arrangements 400 and 500, as can be seen from FIGS. 4 and 5 ,
• the memory cell arrangement 500 is designed as a dual-bit memory cell arrangement, in which each
• Information of two bits can be stored in the memory cell. Because of the design of the memory cell arrangement 500 as a dual-bit memory cell arrangement, it is required to contact the source / drain regions of the fin field effect transistor memory cells of the memory cell arrangement 500 with bitlines, via which electrical control and readout signals can be applied in accordance with a "virtual ground array" architecture. For this purpose, a plurality of bit lines arranged above the paper level of FIG. 5 are formed, which are coupled to respective source / drain regions of the fin field effect transistor memory cell arrangement 500.
• bit lines starting from FIG. 3D, the silicon nitride cover layer 108 is subjected to a lithography and an etching process, as a result of which bitline contacts are etched as through-holes and filled with titanium nitride and tungsten material.
• the bit lines are formed in a metallization level arranged above them, by first depositing a full-area metallization layer and structuring them using an additional lithography and an additional etching method. The back-end contact can then be made.
• two bits of information can be stored in each of the fin field effect transistor memory cells 110, 111 of the fin field effect transistor memory cell arrangement 500, by placing them in a first charge storage area 501 and in a second charge storage area 502 of a respective memory cell electrical charge carriers can be introduced independently of one another or not.
• the 501 is arranged in a boundary region between a first source / drain region 401 of a memory cell 110 and the channel region 105 of the memory cell.
• the second Charge storage region 502 is arranged in a boundary region between the channel region 105 and the second source / drain region 402.
• a web field effect transistor memory cell arrangement 600 according to a third exemplary embodiment of the invention is described below with reference to FIG. 6.
• the memory cell arrangement 600 like the memory cell arrangement 500, is designed as a dual-bit memory cell arrangement.
• the layout top view of Figure 6 shows how the bit lines for
• the direction of development between word lines 109 and semiconductor webs or fins 403 can run orthogonally to one another.
• the source / drain regions of the memory cell can be controlled by means of bit lines.
• bit lines 601, 602 arranged obliquely to the word lines. This can
• Example are formed at a 45 ° angle to the word lines.
• the bit lines 601, 602 are, however, sawtooth-shaped or zigzag-shaped, with a source / drain region in each crossing region of the bit lines 601, 602
• the sawtooth-like structure of the bit lines has the advantage that all sawtooth bit lines of a memory cell arrangement with a plurality of memory cells in the
• bit lines 601, 602 are of essentially the same length, so that the ohmic resistances of the bit lines 601, 602 are approximately the same for all bit lines.
• Bit lines 601, 602 are formed in a single metal level (bit line level).
• the minimum structure width of the semiconductor memory depends on the extension of the bit lines.
• the dimension of a memory cell in the horizontal direction according to FIG. 6 corresponds to 2F / 2.
• Bit lines 601, 602 are formed at an angle of 45 ° to word lines 107.
• the width of the word line 107 and the width of the semiconductor fins 311, 312 is F 2 in each case.
• the space requirement of an individual memory cell according to the configuration of FIG. 6 is 8F 2 .
• the method for producing the memory cell array shown in FIG. 6 in a "virtual ground array" architecture is not very complex due to the only one bit line level required.
• a fin field effect transistor memory cell arrangement 700 according to a fourth exemplary embodiment of the invention is described below with reference to FIG.
• the fin field effect transistor memory cell arrangement 700 is designed in a dual-bit architecture.
• FIG. 8 shows a layout top view 800 of the fin field effect transistor memory cell arrangement 700.
• the cross-sectional view shown in Figure 7 is taken along the line C-C shown in Figure 8.
• the fin field effect transistor memory cell arrangement 700 differs from the fin field effect transistor memory cell arrangement 500 shown in FIG.
• bit lines 703 which can be seen in the cross-sectional view of FIG. 7, are of word lines 107 by means of a
• TEOS layer 701 ("tetra ethyl orthosilicate") electrically decoupled. Furthermore, an insulation layer 702 is formed between word lines 107. A spacer 801 is also shown in FIG.
• the energy band curve 900 schematically shows the potential curve along a web Field effect transistor memory cell in an operating state in which an erase voltage (for example 10V) is applied.
• an erase voltage for example 10V
• FIG. 9 shows the potential curve shown in which the potential of a channel region 901 is reduced compared to the potential of a metallically conductive p + -doped polysilicon gate region 902.
• An ONO layer sequence 903 is arranged between the channel region 901 and the polysilicon gate region 902 as a charge storage region.
• the ONO layer sequence contains a first silicon oxide layer 904, which adjoins the channel region 901, a second silicon oxide layer 906, which adjoins the p + -doped polysilicon gate region 902, and a silicon nitride layer 905 between the two silicon oxide layers 904 and 906: In the silicon nitride layer 905, electrical charge carriers are earlier in time

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