EP1661175A1 - Scellement metallique multifonction - Google Patents
Scellement metallique multifonctionInfo
- Publication number
- EP1661175A1 EP1661175A1 EP04787275A EP04787275A EP1661175A1 EP 1661175 A1 EP1661175 A1 EP 1661175A1 EP 04787275 A EP04787275 A EP 04787275A EP 04787275 A EP04787275 A EP 04787275A EP 1661175 A1 EP1661175 A1 EP 1661175A1
- Authority
- EP
- European Patent Office
- Prior art keywords
- layer
- substrate
- semiconductor material
- thin layer
- intermediate substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02002—Preparing wafers
- H01L21/02005—Preparing bulk and homogeneous wafers
- H01L21/02032—Preparing bulk and homogeneous wafers by reclaiming or re-processing
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
- H01L21/76254—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
- H01L21/76259—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along a porous layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/005—Processes
- H01L33/0093—Wafer bonding; Removal of the growth substrate
Definitions
- This transfer is broken down into two critical steps: metallic bonding of the final support to the active epitaxial layers on the initial substrate, then removal of the latter.
- the laser separation technique, or "lift-off" laser described for example in US 6,071,795 is a first known means for removing the initial support used for the growth of the active layers after metallic bonding.
- This technique consists in decomposing using a laser the interface separating the initial substrate from the first thin layer resting on the latter, by illumination on the rear face of the starting structure. The interface thus broken down releases the thin layer from its support.
- This technique is limited to the starting structures comprising an initial substrate transparent to the laser beam and a first thin layer absorbing the laser radiation.
- the subject of the invention is firstly a method of producing a thin layer of semiconductor material on a substrate, called the final substrate, comprising: the formation of said layer of semiconductor material, on a support, said initial support, - the assembly of said thin layer and the final substrate, by metallic bonding, mechanical separation of the initial support and the thin layer.
- the initial support comprises at least one surface film on which the thin layer of semiconductor material is formed, preferably by epitaxy, and a mechanical support.
- the initial support is said to be removable because of the presence of a fragile interface between the layer of semiconductor material and the mechanical support.
- Example 2 Realization of an intermediate substrate for the manufacture of LEDs or LDs emitting in red and based on AIGalnP.
- Example 3 Realization of LEDs emitting in the green and based on GaN epitaxy on Si (111).
- the removable substrate used in this example is composed of a support 101 in Si and a surface epitaxy film 102 in Si of crystallographic orientation (111). Between these two parts, there is a buried oxide layer as well as the removable interface 103.
- the active layers 104 based on GaN and AIGaInN alloys are applied by epitaxy directly on the Si film 102 or via a buffer layer based on AIN. Then, metallic deposits are successively carried out over the active layers: Ni / Cr / Au: ohmic contact on the p layer, with diffusion barrier integrated in Cr Au: mirror and bonding layer.
Abstract
Description
Claims
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
FR0310369A FR2859312B1 (fr) | 2003-09-02 | 2003-09-02 | Scellement metallique multifonction |
PCT/FR2004/002219 WO2005024934A1 (fr) | 2003-09-02 | 2004-09-01 | Scellement metallique multifonction |
Publications (1)
Publication Number | Publication Date |
---|---|
EP1661175A1 true EP1661175A1 (fr) | 2006-05-31 |
Family
ID=34130702
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
EP04787275A Withdrawn EP1661175A1 (fr) | 2003-09-02 | 2004-09-01 | Scellement metallique multifonction |
Country Status (8)
Country | Link |
---|---|
US (2) | US7189632B2 (fr) |
EP (1) | EP1661175A1 (fr) |
JP (1) | JP4490424B2 (fr) |
KR (2) | KR100896095B1 (fr) |
CN (1) | CN1856874A (fr) |
FR (1) | FR2859312B1 (fr) |
TW (1) | TWI267167B (fr) |
WO (1) | WO2005024934A1 (fr) |
Families Citing this family (45)
Publication number | Priority date | Publication date | Assignee | Title |
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US20040124538A1 (en) * | 2002-12-31 | 2004-07-01 | Rafael Reif | Multi-layer integrated semiconductor structure |
WO2004061961A1 (fr) * | 2002-12-31 | 2004-07-22 | Massachusetts Institute Of Technology | Structure integree multicouche de semi-conducteur avec partie d'ecran electrique |
US7161169B2 (en) * | 2004-01-07 | 2007-01-09 | International Business Machines Corporation | Enhancement of electron and hole mobilities in <110> Si under biaxial compressive strain |
JP2005317676A (ja) * | 2004-04-27 | 2005-11-10 | Sony Corp | 半導体発光素子、半導体発光装置及び半導体発光素子の製造方法 |
US8174037B2 (en) * | 2004-09-22 | 2012-05-08 | Cree, Inc. | High efficiency group III nitride LED with lenticular surface |
TWI246784B (en) * | 2004-12-29 | 2006-01-01 | Univ Nat Central | Light emitting diode and manufacturing method thereof |
US7932111B2 (en) * | 2005-02-23 | 2011-04-26 | Cree, Inc. | Substrate removal process for high light extraction LEDs |
CN100372137C (zh) * | 2005-05-27 | 2008-02-27 | 晶能光电(江西)有限公司 | 具有上下电极结构的铟镓铝氮发光器件及其制造方法 |
TWI285969B (en) * | 2005-06-22 | 2007-08-21 | Epistar Corp | Light emitting diode and method of the same |
KR100655437B1 (ko) * | 2005-08-09 | 2006-12-08 | 삼성전자주식회사 | 반도체 웨이퍼 및 그 제조방법 |
DE102005052358A1 (de) * | 2005-09-01 | 2007-03-15 | Osram Opto Semiconductors Gmbh | Verfahren zum lateralen Zertrennen eines Halbleiterwafers und optoelektronisches Bauelement |
DE102005052357A1 (de) * | 2005-09-01 | 2007-03-15 | Osram Opto Semiconductors Gmbh | Verfahren zum lateralen Zertrennen eines Halbleiterwafers und optoelektronisches Bauelement |
WO2007040295A1 (fr) * | 2005-10-04 | 2007-04-12 | Seoul Opto Device Co., Ltd. | Semi-conducteur à composé à base de (al, ga, in)n et son procédé de fabrication |
TWI298555B (en) * | 2006-06-05 | 2008-07-01 | Epistar Corp | Light emitting device |
TWI370555B (en) * | 2006-12-29 | 2012-08-11 | Epistar Corp | Light-emitting diode and method for manufacturing the same |
JP5228381B2 (ja) * | 2007-06-25 | 2013-07-03 | 三菱電機株式会社 | 半導体装置の製造方法 |
US20090181492A1 (en) * | 2008-01-11 | 2009-07-16 | Peter Nunan | Nano-cleave a thin-film of silicon for solar cell fabrication |
TWI495141B (zh) * | 2008-08-01 | 2015-08-01 | Epistar Corp | 晶圓發光結構之形成方法及光源產生裝置 |
TWI455252B (zh) * | 2008-08-28 | 2014-10-01 | 玉晶光電股份有限公司 | A mold release mechanism for a light emitting diode package process |
US8058143B2 (en) * | 2009-01-21 | 2011-11-15 | Freescale Semiconductor, Inc. | Substrate bonding with metal germanium silicon material |
US9847243B2 (en) | 2009-08-27 | 2017-12-19 | Corning Incorporated | Debonding a glass substrate from carrier using ultrasonic wave |
CN103262210B (zh) * | 2010-09-10 | 2017-09-08 | 维尔雷思科技有限公司 | 使用与半导体施主分离的层来制造光电装置的方法和由该方法制成的装置 |
KR20120052160A (ko) * | 2010-11-15 | 2012-05-23 | 엔지케이 인슐레이터 엘티디 | 복합 기판 및 복합 기판의 제조 방법 |
FR2977069B1 (fr) | 2011-06-23 | 2014-02-07 | Soitec Silicon On Insulator | Procede de fabrication d'une structure semi-conductrice mettant en oeuvre un collage temporaire |
CN102255027B (zh) * | 2011-07-15 | 2013-05-29 | 上海蓝光科技有限公司 | 一种GaN基垂直结构LED芯片结构及其制备方法 |
US9343641B2 (en) * | 2011-08-02 | 2016-05-17 | Manutius Ip, Inc. | Non-reactive barrier metal for eutectic bonding process |
US9064980B2 (en) * | 2011-08-25 | 2015-06-23 | Palo Alto Research Center Incorporated | Devices having removed aluminum nitride sections |
KR20130060065A (ko) * | 2011-11-29 | 2013-06-07 | 에스케이하이닉스 주식회사 | 비휘발성 메모리 장치 및 이의 제조 방법 |
EP2600389B1 (fr) * | 2011-11-29 | 2020-01-15 | IMEC vzw | Procédé pour la liaison de substrats semi-conducteurs |
WO2015157202A1 (fr) | 2014-04-09 | 2015-10-15 | Corning Incorporated | Article de substrat modifié de dispositif et procédés de fabrication |
US10543662B2 (en) | 2012-02-08 | 2020-01-28 | Corning Incorporated | Device modified substrate article and methods for making |
US10014177B2 (en) | 2012-12-13 | 2018-07-03 | Corning Incorporated | Methods for processing electronic devices |
US9340443B2 (en) | 2012-12-13 | 2016-05-17 | Corning Incorporated | Bulk annealing of glass sheets |
TWI617437B (zh) | 2012-12-13 | 2018-03-11 | 康寧公司 | 促進控制薄片與載體間接合之處理 |
US10086584B2 (en) | 2012-12-13 | 2018-10-02 | Corning Incorporated | Glass articles and methods for controlled bonding of glass sheets with carriers |
US10510576B2 (en) | 2013-10-14 | 2019-12-17 | Corning Incorporated | Carrier-bonding methods and articles for semiconductor and interposer processing |
WO2015112958A1 (fr) | 2014-01-27 | 2015-07-30 | Corning Incorporated | Articles et procédés pour la liaison contrôlée de feuilles minces avec des supports |
CN103996755B (zh) * | 2014-05-21 | 2016-08-17 | 天津三安光电有限公司 | 一种氮化物发光二极管组件的制备方法 |
CN107635769B (zh) | 2015-05-19 | 2020-09-15 | 康宁股份有限公司 | 使片材与载体粘结的制品和方法 |
JP7106276B2 (ja) | 2015-06-26 | 2022-07-26 | コーニング インコーポレイテッド | シート及び担体を有する物品及び方法 |
US9865565B2 (en) * | 2015-12-08 | 2018-01-09 | Amkor Technology, Inc. | Transient interface gradient bonding for metal bonds |
TW202216444A (zh) | 2016-08-30 | 2022-05-01 | 美商康寧公司 | 用於片材接合的矽氧烷電漿聚合物 |
TWI821867B (zh) | 2016-08-31 | 2023-11-11 | 美商康寧公司 | 具以可控制式黏結的薄片之製品及製作其之方法 |
WO2019118660A1 (fr) | 2017-12-15 | 2019-06-20 | Corning Incorporated | Procédés de traitement d'un substrat et procédé de fabrication d'articles à base de feuilles liées |
US20220238747A1 (en) * | 2021-01-28 | 2022-07-28 | Solaero Technologies Corp. | Inverted metamorphic multijunction solar cell |
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FR2681472B1 (fr) | 1991-09-18 | 1993-10-29 | Commissariat Energie Atomique | Procede de fabrication de films minces de materiau semiconducteur. |
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KR100481994B1 (ko) * | 1996-08-27 | 2005-12-01 | 세이코 엡슨 가부시키가이샤 | 박리방법,박막디바이스의전사방법,및그것을이용하여제조되는박막디바이스,박막집적회로장치및액정표시장치 |
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US6335263B1 (en) * | 2000-03-22 | 2002-01-01 | The Regents Of The University Of California | Method of forming a low temperature metal bond for use in the transfer of bulk and thin film materials |
JP2001284622A (ja) * | 2000-03-31 | 2001-10-12 | Canon Inc | 半導体部材の製造方法及び太陽電池の製造方法 |
DE10051465A1 (de) | 2000-10-17 | 2002-05-02 | Osram Opto Semiconductors Gmbh | Verfahren zur Herstellung eines Halbleiterbauelements auf GaN-Basis |
TWI292227B (en) * | 2000-05-26 | 2008-01-01 | Osram Opto Semiconductors Gmbh | Light-emitting-dioed-chip with a light-emitting-epitaxy-layer-series based on gan |
FR2809867B1 (fr) | 2000-05-30 | 2003-10-24 | Commissariat Energie Atomique | Substrat fragilise et procede de fabrication d'un tel substrat |
JP4024994B2 (ja) * | 2000-06-30 | 2007-12-19 | 株式会社東芝 | 半導体発光素子 |
JP2002075917A (ja) * | 2000-08-25 | 2002-03-15 | Canon Inc | 試料の分離装置及び分離方法 |
US6480320B2 (en) * | 2001-02-07 | 2002-11-12 | Transparent Optical, Inc. | Microelectromechanical mirror and mirror array |
FR2823599B1 (fr) | 2001-04-13 | 2004-12-17 | Commissariat Energie Atomique | Substrat demomtable a tenue mecanique controlee et procede de realisation |
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JP4748986B2 (ja) * | 2002-11-01 | 2011-08-17 | 株式会社半導体エネルギー研究所 | 半導体装置の作製方法 |
-
2003
- 2003-09-02 FR FR0310369A patent/FR2859312B1/fr not_active Expired - Lifetime
- 2003-12-22 US US10/744,867 patent/US7189632B2/en not_active Expired - Lifetime
-
2004
- 2004-09-01 WO PCT/FR2004/002219 patent/WO2005024934A1/fr active Application Filing
- 2004-09-01 JP JP2006525161A patent/JP4490424B2/ja active Active
- 2004-09-01 EP EP04787275A patent/EP1661175A1/fr not_active Withdrawn
- 2004-09-01 KR KR1020087007939A patent/KR100896095B1/ko active IP Right Grant
- 2004-09-01 KR KR1020067004346A patent/KR100878915B1/ko active IP Right Grant
- 2004-09-01 CN CNA200480027890XA patent/CN1856874A/zh active Pending
- 2004-09-02 TW TW093126531A patent/TWI267167B/zh active
-
2006
- 2006-06-07 US US11/447,863 patent/US7232739B2/en not_active Expired - Lifetime
Non-Patent Citations (2)
Title |
---|
See also references of WO2005024934A1 * |
WOLFFENBUTTEL ET AL: "Low-temperature intermediate Au-Si wafer bonding; eutectic or silicide bond", SENSORS AND ACTUATORS A, ELSEVIER SEQUOIA S.A., LAUSANNE, CH, vol. 62, no. 1-3, 1 July 1997 (1997-07-01), pages 680 - 686, XP022542091, ISSN: 0924-4247, DOI: DOI:10.1016/S0924-4247(97)01550-1 * |
Also Published As
Publication number | Publication date |
---|---|
KR20080055877A (ko) | 2008-06-19 |
TWI267167B (en) | 2006-11-21 |
KR20060082855A (ko) | 2006-07-19 |
FR2859312A1 (fr) | 2005-03-04 |
KR100878915B1 (ko) | 2009-01-15 |
TW200531205A (en) | 2005-09-16 |
JP4490424B2 (ja) | 2010-06-23 |
US7232739B2 (en) | 2007-06-19 |
FR2859312B1 (fr) | 2006-02-17 |
JP2007504658A (ja) | 2007-03-01 |
CN1856874A (zh) | 2006-11-01 |
US7189632B2 (en) | 2007-03-13 |
US20050048739A1 (en) | 2005-03-03 |
US20060228820A1 (en) | 2006-10-12 |
KR100896095B1 (ko) | 2009-05-06 |
WO2005024934A1 (fr) | 2005-03-17 |
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Inventor name: MORALES, CHRISTOPHE Inventor name: MORICEAU, HUBERT Inventor name: LETERTRE, FABRICE Inventor name: KERDILES, SEBASTIEN |
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Owner name: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES Owner name: S.O.I. TEC SILICON ON INSULATOR TECHNOLOGIES |
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