EP1537486A1 - Reconfigurable sequencer structure - Google Patents

Reconfigurable sequencer structure


Publication number
EP1537486A1 EP03782172A EP03782172A EP1537486A1 EP 1537486 A1 EP1537486 A1 EP 1537486A1 EP 03782172 A EP03782172 A EP 03782172A EP 03782172 A EP03782172 A EP 03782172A EP 1537486 A1 EP1537486 A1 EP 1537486A1
European Patent Office
Prior art keywords
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Application number
Other languages
German (de)
French (fr)
Martin Vorbach
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Original Assignee
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Family has litigation
Priority to DE10241812 priority Critical
Priority to DE2002141812 priority patent/DE10241812A1/en
Priority to DE10315295 priority
Priority to DE10315295 priority
Priority to DE10321834 priority
Priority to DE10321834 priority
Priority to EP03019428 priority
Priority to EP03019428 priority
Application filed by PACT XPP Tech AG filed Critical PACT XPP Tech AG
Priority to EP03782172A priority patent/EP1537486A1/en
Priority to PCT/EP2003/009957 priority patent/WO2004038599A1/en
Publication of EP1537486A1 publication Critical patent/EP1537486A1/en
First worldwide family litigation filed litigation Critical https://patents.darts-ip.com/?family=32180554&utm_source=google_patent&utm_medium=platform_link&utm_campaign=public_patent_search&patent=EP1537486(A1) "Global patent litigation dataset” by Darts-ip is licensed under a Creative Commons Attribution 4.0 International License.
Application status is Withdrawn legal-status Critical



    • G06F15/00Digital computers in general; Data processing equipment in general
    • G06F15/76Architectures of general purpose stored program computers
    • G06F15/78Architectures of general purpose stored program computers comprising a single central processing unit
    • G06F15/7867Architectures of general purpose stored program computers comprising a single central processing unit with reconfigurable architecture
    • G06F13/00Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14Handling requests for interconnection or transfer
    • G06F13/16Handling requests for interconnection or transfer for access to memory bus
    • G06F13/00Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14Handling requests for interconnection or transfer
    • G06F13/36Handling requests for interconnection or transfer for access to common bus or bus system
    • G06F13/00Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38Information transfer, e.g. on bus
    • G06F13/40Bus structure
    • G06F13/4063Device-to-bus coupling
    • G06F13/4068Electrical coupling
    • G06F9/00Arrangements for program control, e.g. control units
    • G06F9/06Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30145Instruction analysis, e.g. decoding, instruction word fields
    • H03K19/00Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components


The invention relates to a cellular element field for data processing, with functional cell means for carrying out algebraic and/or logical functions and memory cell means for receipt, storage and/or output of information. Functional cell/memory cell combinations are thus formed whereby a control connection is run from the functional cell means to the memory cell means.


Title: Reconfigurable Sequenzerstruktur


The present invention relates to a Zeilelementefeld and a method of operating the same. Thus, the present invention is concerned in particular with tenverarbeitungsarchitekturen reconfigurable DA.

Under a reconfigurable architecture (VPU) are meant, inter alia, blocks that sen a plurality of function and / or crosslinking in the operating variable elements aufwei-. To the elements of arithmetic logic units, FPGA areas, input-output cells, memory cells, analog components, etc. may belong. Building blocks of this type are known, for example, under the name VPU. This typically comprises as PAEs designated mono- or multi-dimensionally arranged arithmetic and / or logical and / or analog and / or storing and / or crosslinking components and / or communication peripheral modules (IO), which are connected directly or through one or more bus systems , The PAEs are Toggle arranged in any configuration, mixing and hierarchy, the arrangement is referred to as PAE-Ärray or shortly PA. It may be associated with the PAE array configure a unit. In principle, next to VPU building blocks also systolic arrays, neural networks, multiprocessor systems, processors with multiple arithmetic units and / or logic cells, cross-linking and network devices such as crossbar switch, etc. known, as FPGAs, DPGAs, transputer etc. It is noted that key aspects of the VPU technology z. B. in the following property rights of the same applicant and the associated subsequent applications are described with the following property rights:

P 44 16 881.0-53, DE 197 81 412.3, DE 197 81 483.2, DE 196 54 846.2-53, DE 196 54 593.5-53, DE 197 04 044.6-53, DE 198 80 129.7, DE 198 61 088.2-53, DE 199 80 312.9, PCT / DE 00/01869, DE 100 36 627.9-33, DE 100 28 397.7, DE 101 10 530.4, DE 101 11 014.6, PCT / EP 00/10516, EP 01 102 674.7, DE 102 06 856.9 , 60 / 317.876, DE 102 02 044.2, DE 101 29 237.6-53, DE 101 39 170.6.

It should be noted that the aforementioned documents for disclosure purposes in particular with regard to specifics and details of networking, configuration, design of architectural elements, triggers, procedures, etc., are incorporated.

The architecture has significant advantages over conventional processor architectures, so far as data processing is done in a way that has high levels of parallel and / or vector data processing steps. The advantages of the architecture over other processes sorting, but coprocessor or general data processing units are less if not let the benefits of networking and the given processor architectural features realize the full extent.

This is especially the case when data processing steps must be carried that can be conventionally best mapped to sequencer structures. It is worth wishes to design the reconfigurable architecture such and to use that even with sequencers particularly well be executed data processing steps can be processed typically very fast and efficient.

The object of the present invention is to provide something new for industrial application.

The solution of this object is claimed independently. Forthcoming ferred embodiments can be found in the dependent claims.

According to a first essential aspect of the invention is thus in an in function and / or networking in particular not reconfigured at runtime without interference elements re- configurable cell elements field for data processing with particular coarse-grained function cell means for performing algebraic and / or logic functions and memory cell means to receive information to store and / or output, suggested that Funktionszellen- memory cell combinations are formed, in which a control connection is performed to the memory cell means from the function cell means. This control connection serves to make the address and / or data input / output from the memory by the associated function cell, typically an ALU PAE, tax Erbar. Thus it can be stated about whether the next transmitted information to be treated as an address or data and whether a read and / or write access is required. This transfer of data from the memory cell or the memory cell means, which may be about a RAM-PAE, the function cell center, which may be about an ALU-PAE, then allow that new, from the ALU to be executed instructions may be loaded into them. It should be noted that functional cell means and memory cell means may be close sums together by integration into a structural unit. In such a case, it is possible to use a single Zigen bus to introduce data into the memory cell and / or the ALU. It can then be provided and, if desired, different therefrom additional data and / or configuration registers as Speicherzellmit- tel suitable input registers and / or output registers.

It should also be mentioned that it is possible to construct a Zellelemente- field containing a plurality of different cells or cell groups, regular patterns are preferred with the different cells strips or the like are provided, since these very regular arrangement allows the hardware technical structure and to facilitate the operation alike. With such a strip-like or other regular structure of a small plurality of different cell elements, for example elements having integrated functional cell center memory cell means combinations, that is, cells in which Funktionszeil- and memory cell means are integrated according to the invention are provided centrally in the field, where typically only a few must be processed different program steps within a Sequenzerstruk- tur, because this, as has been recognized, gives very good results for conventional data stream applications while can be built on field boundaries complex sequencer structures in which about an ALU-PAE, a separate unit represents, in addition to a separate RAM PAE and optionally a number of I / O-PAEs using and arrangement of corresponding control lines, or combinations thereof can be arranged, because there is often more memory is needed, for example to the field central region buffering the Zellele duck field generated results and / or for the data streams by this unnecessary data set in advance and / or prepare accordingly.

If, are provided approximately in the center of the field, cells that integrate the memory cell center and cell function means, so that in a small memory for different, to be executed by the function cell such as the ALU instructions can be provided. It is in particular possible to separate the command or configuration memory of a data memory, and it is possible to make the memory function such that alternatively one of several examples, two game, different sequences can be processed. Each sequence to be processed can be performed in response to results generated in the cell and / or into the cell from the outside incoming control signals such as Carry, etc. Overflow trigger signals. In this way, this arrangement is also suitable for the method Wave reconfiguration.

It is possible in this manner merely by providing a dedicated and dedicated function cells controlled control connection between the functional cell or function cell means and memory cell or memory cell means already with only two elements, which are connected via the appropriate buses to establish a Sequenzerstruktur in a Zeilelementefeld without otherwise more measures and / or structural way any changes required. In the memory cell data, addresses, program steps can be taken in per se from conventional processors known manner so. Because both elements can be used if configured in other ways, there is a particularly efficient design that is particularly well adapted both sequencer structures as well as vectorial len and / or parallelizable structures. So can be supported solely by means of suitable PAE parallelizations embodiments, such as by the provision of operating in two different spatial directions PAEs and / or provided with Datendurchschleuseregi- stern cell units.

It will be appreciated that a variety of structures sequenzerartigen in the reconfigurable cell array elements can be constructed by the use of only two cells in a Zeilelementefeld, namely the function cell and the information providing cell. This is advantageous, as often varied and must be processed per se different from each other tasks during data processing, such as in a multitasking operating system, a set. It can then be processed efficiently at the same time a variety derar- term tasks in a single Zeilelementefeld. The advantages for real-time applications are obvious. Further, it is also possible for the individual sequencer structures that are built bond in a cell element field under providence of Steuerver- invention to operate at different clock rates, to reduce as the power consumption by the fact that tasks of lower priority are processed slower. Moreover, it is possible to process in the embodiment per se largely parallel algorithms sequencer-program parts in the field parallel or vector and vice versa. Typically, however, be preferred that sequencer-structures in the cell element field, whether sequencer-structures in a by combining with neighboring cells or buses connected region or be it combinations of spatially distinct, separate and separately usable function cellular elements, such as ALU-PAEs and memory cell elements such as RAM -PAEs be clocked higher. This has the advantage that sequential program parts that can be parallelized only very bad, can be used in a general data flow processing, without increasing the overall data processing is impaired. Examples of these are represented by a Huffman coding, which is substantially better than parallel sequentially processable and at the same time plays an important role in applications such as the MPEG4 coding, but the essential parts of the other MPEG-4 coding are well parallelized. It is then used a parallel data processing for the most parts of an algorithm and a sequenziel- ler processing block provided therein. Typically, a ER is heightening the clock frequency in the sequencer Empire already be enough a factor of 2 to fourth

It should be noted that, instead of a strip-like arrangement of different cell elements, a different, and in particular multi-dimensional array can be selected.

The cell element field with the configurable in function and / or cross-linking cells can einsichtigerweise form a processor, a coprocessor and / or a microcontroller, or a plurality of parallel, or combinations thereof. The functional cells are typically formed as arithmetic logic units, wherein they are in particular coarse-grained elements, but z. B. can be provided with a fine granular state machine. In a particularly preferred embodiment is in the so-called advanced ALUs ALUs (EALU) as they were described in the earlier applications of the present applicant. An extension may include in particular the control line control, instruction decode, etc., if necessary.

The memory cell can store data and / or information volatile and / or non-volatile. If in the memory cells stored information, whether program steps, addresses for accessing data or in register or heap-like data stored are stored as nonvolatile data, a complete reconfiguration during operation can take place. Alternatively, it is possible to provide non-volatile memory cells. The non-volatile memory cells can be provided for example as EE-PROM area and the like, in which a rudimentary BIOS program is stored, to be executed at start-up of the assembly. In this way, a commissioning of a data processing device can be carried out without further components. A non-volatile memory can also be provided, if it is decided for reasons of cost and / space reasons, that the same parts of the program are to be performed repeatedly, wherein, may be changed during operation even under such fixed parts of the program, such as the type of WAVE reconfiguration. The possibilities to provide such non-volatile storage and use, are the subject of other rights of the applicant. It is possible to save both volatile and non-volatile data in the memory cells, f.est about a BIOS program to store and the memory cell to be able to still use for other purposes.

The memory cell is preferably configured so that it can store a sufficient number of data to be processed and / or to be executed program parts. There it will be noted that these program parts can be designed both as program steps that purport each what an individual, in particular the associated PAE, ie in particular the memory cell controlling function cell has to do in the next step, and all configurations for field areas or may include other fields. In such a case, it is readily possible that the established Sequenzerstruktur issues a command on the basis of which a reconfiguration is performed by Zeilelementefeldbereichen. So that the triggering this configuration function cell then also works as a charging logic. It should be noted that the configuration of other cells, in turn, can be performed such that there is a sequenzerarti- ge data processing takes place and it is in these fields again possible to configure other cells during the Programmarbei- for, or reconfigure. This results in an iterative Configuring Zeilelementebereichen and it is a nesting of programs with sequencer and In parallel structures possible, which are similar to nested like a babushka. It should be noted that this can be done by input-output cells to further web Zeilelementefelder outside a single integrated block particular what the Gesamtrechenlei- stung can increase massively. It is in particular possible in the event of configurations in a code part of a hineinkonfigurierten in a cell element field Sequenzerstruktur appropriate, either the configuration requirements gege- on an assigned cell element field, which is managed by the respective Sequenzerstruktur alone to perform and / or there may be such requirements for a configuration Master unit are given to ensure that a uniform coating of all Zellelementefeider done to ensure. The result is thus virtually a subroutine call by delivery of required configurations of cells or load logic. This is considered to be worthy of protection. It should also be noted that the cells unless they themselves have to configure other cell element field areas of responsibility, can be provided with hardware or software implemented like FILMO structures and the like to ensure proper reconfiguration. On the way to describe the memory cells during the execution of commands such that the code to be processed or the program to be processed is changed, it should be noted. In a particularly preferred variant of this type of self-modification (SM) but suppressed by appropriate control of the function cell.

It is possible that the memory cell information stored on the control of the function cell controlling them out are directly or indirectly to a leading to the function cell bus. Indirect output can then take place in particular when the two cells are adjacent, and the requested through control information to the ALU-PAE must occur over a bus segment which can not be directly connected to the output of the memory cell. In a sol-chen case, the memory cell can output data on this bus system in particular backward register (backward register). It is therefore preferable, if at least one of storage

ιo - cherzelle and / or function cell such Backward having registers which can be arranged in the information path between the memory cell and function cell. These registers need not necessarily be provided with additional functionalities in such a case, although this example when requesting data from the memory cell for further processing, according to a conventional LOAD command of a typical microprocessor, to change the data before the Into loading into the PAE is readily conceivable to z. to realize as a LOAD ++ command. The data transmission through working in the reverse direction ALUs and the like having PAEs be mentioned.

The memory cell is preferably be arranged to infor- mation from the controlling them to receive function cell, whereby further a Informationseinspeichern via an input output cell and / or the memory cell can not be controlled cell. In particular, when data is written from an input-output cell in the memory cell len sol, it is preferred if these input-output cell (I / O- PAE) controlled by the function cell. In this case, as the address is in which a in the memory cell to be written or optionally directly to the function cell (PAE) transmitted information to be read, are transmitted to the I / O-PAE from ALU-PAE. It should be noted in this connection that this address can be set via an address translation table (Address Translation Table), an address translation buffer or an MMU-like structure in the I / O-PAE. This results in a sol-chen case, the full functionalities of typical microprocessors. can be that an I / O functionality with a functional cell center, a memory cell means and / or function cell center memory cell agent combination integrate, be mentioned.

The combination of function cells and memory cells, either as integrated Funktionszellen- and memory cell combination, or as composed of separate units Funktionszellen- and memory cell combination, therefore, in a preferred variant, at least one input-output means is associated with which then to an external can be sent unit, another function cell function cell memory cell combination and / or the memory cell information and / or received from.

The input-output unit is preferably also arranged to receive control commands from the function cell or from the cell center function.

In a preferred variant, the control connection is adapted to at least some and preferably all of the successor to transmit constricting commands:


















This can be done by a corresponding bit-width of the control line and an associated decoding among the recipients. Each required control and decoding means can be problem-free and cost provided. As can be seen, it follows the commands virtually complete Sequenzerfähigkeit the arrangement. a general purpose processor data processing unit is obtained that in this way should be mentioned.

The arrangement will typically be chosen such that the function cell can be accessed as a single master to the control connection and / or serving as a control link bus segment or bus system. This results in an arrangement in which the control line acts as a command line, as provided in conventional processors.

The function cell and the memory cell and I / O cell are arranged preferably adjacent. Under adjacent as can be preferably understood to mean that the cells are arranged directly adjacent one another. Immediately means in particular a combination of such cells to form integrated units, which are provided repeatedly thereof on the cell element field or as a part to form the pitch. It can thus be meant an integral unit of memory and logic cells. Alternatively, they are at least close together. The arrangement of the function and memory cells in an integrated or close proximity ensures each other that no, at least no significant latency between control and data input of the requested information occur in the function cell just because the connections between the cells are too long. This is understood as "di- rectly". Must latencies are taken into account, including pipelining can be provided in the sequencer structures. This is particularly important at very high clock arrangements. It should be noted that it is readily possible, according to high-frequency provide clocked cell units known in the art per se, and quick access to appropriate memory cells accordingly. in such a case, such as when used per se known architectural elements for the function of cells at the same time reconfigurability of the functional cell element and the associated be provided crosslinks. In a particularly preferred variant, the functional cells, the information providing cells such as memory cells, I / O cells and the like arranged multidi ensio- nal, particularly in the manner of a matrix or on grid points of a one-dimensional lattice, etc. When a regular äßige structure is present, as there is the case, a cell is supplied typically from a first series of information, that is operands, configurations, trigger signals, etc., while data, trigger signals and other information are delivered in a underlying series. In such a case it will be preferred if the cells are in the same row, and it can then be made of the transfer of information from the information providing cell in the required input of the function cell over a Backward register. The ability to use the registers for Pipeli- ning should be mentioned.

It is further protection is claimed for a method for operating a cell element array, and in particular multidimensional cell elements len field with functional cells for performing algebraic and / or logic functions and information provision cells, in particular memory cells, and / or

An output cell for receiving and / or outputting information and / or storing the same, wherein at least one of the functional cell control commands outputting at least a of information provision cell, is provided therein in response to the control commands information for the function of cell and the function cell is adapted to perform further data processing in response to the information provided to a sequencer so at least temporarily to process data.

It is thus to the memory cell allows a Sequenzerstruktur in a reconfigurable field by the output of a sequencer-control commands data processing. which can be output as control commands from the function cell commands, thereby enabling a sequencer-like operation as is known from conventional processors. It should be noted that it is readily possible to implement only parts of the above commands, yet to ensure a fully sequencer-data processing. The invention will be described below and, for example, with reference to the drawings. This is shown by:

FIG. 1 shows an inventive cell element field,

FIG. 2a shows a detail thereof,

FIG. 2b, c the detail of FIG. 2 during various

Data processing times

FIG. 3 shows an alternative embodiment of the detail of Fig. 2,

FFiigg .. 44, a particularly preferred variant of the


FIG. 5 shows an example for the function of convolution on a function-cell memory cell combination of the invention, Fig. 6a an example of a sequential-parallel

Data processing, Fig. 6b, a particularly preferred embodiment of the invention, Fig. 7 shows an alternative to a Funktionsfaltungs- unit.

According to Fig. 1, generally designated with 1 cell element field includes data processing 1 Function cell means 2 for performing arithmetic and / or logic functions and memory cell means 3, to receive information, store and / or output, wherein a control link 4 of function cells 2 to the memory cells is performed. 3

The cell element field 1 can be freely configured in the networking of the elements 2, 3, 4, and not to bother re-configure Zeilelementeteile without the operation. The compounds can be configured by bus systems 5 are switched as required. Next the function of cells 2 are configurable in their function. The functional cells is arithmetic logic units that are added to certain reconfiguration enabling circuits such as state machines, interface wiring for communication with the external load logic 6, etc. In the corresponding Reservations applicant is pointed.

The cell elements 2, 3 of the cell element array 1 are arranged two-dimensionally in rows and columns, each memory cell 3 is located immediately adjacent to a functional cell 2 and here per row three memory cell Funktionszellen- present couples in which the function and the memory cells each have control links 4 are connected to each other. The function and memory cell 2, 3, or the combination of these, have inputs which are connected to the bus system above the row in which the respective cell elements are to receive data therefrom. Next 2, 3, the cells on outputs below the row output to the bus system 5 data. As will be explained, in addition, each memory cell 3 with a backward register (BW) is provided, through which data can be pushed through from the bus below a row on the bus above the respective row.

The storage cell means 3 comprises also preferably at least 3 memory areas, namely reaching a so-called data stock, a program memory area and a stack area, etc. It, however, may be sufficient in other variants of the invention to provide only two regions, namely a data memory and a program memory area, each may form part of a memory cell agent. It is in particular possible to carry out not easy separation of a per se homogeneous and identical in hardware memory in Differing areas, but actually provide physically or in terms of hardware separate memory areas. In this case, an adaptation of the memory width and / or depth to respective requirements can be provided in particular. In such a way at the design of a memory that it has a program area and a data area in operation, it will be preferable to form this memory or memory area for the concurrent access to data and program memory spaces, such as a dual-port memory. It may also be possible to tightly coupled memory areas, in particular within a Speicherzellmittel- function cell agent combination, which is formed into an integrated area to provide as clean cache memory, in particular data from remote locations for quick access during data processing be loaded upstream.

With the exception of the control compounds 4 and the associated circuitry inside the function cells (ALU in Fig. 2) or memory cells (RAM in Fig. 2) is in the cell element field for data processing of Fig. 1 is a conventional cell element field, as is the case reconfigurable Datenverarbeitunsanordnungen is, for example, a VPU corresponding to the XPP technology of the applicant's conventional and known. In particular, the cell element array of Fig can be operated as known. 1, that has corresponding loading circuits for wave reconfiguration, for debugging, transmitting trigger signals etc. on. Special features of the first cell element array of the present invention result from the control link 4 and the associated wiring, which will be described in more detail below with reference to FIGS. 2a-c. It should be mentioned here is that while is always performed in FIG. 1, a control connection 4 from a more left-function cell element to a right lying further memory cell, and indeed, it is only and precisely to such a memory cell plausible legally possible for the control lines a provide con- urable crosslinking to address either lying elsewhere memory cells and / or to optionally be able to address more than one memory cell when there is approximately a large scale memory requirement for information to be received from the memory cells to store and / or output is. For the sake of clarity, but merely took in Fig. 1 and 2 on fixed-provided individual control compounds respectively which substantially facilitates the understanding of the invention. The control connection is gen moreover necessary, by conventional cables or providing appropriate protocols substitutable.

In FIG. 2, the function cell 2 is referred to as ALU and the function cell 3 as a RAM. Above the row in which the cells are located, the bus 5a, which connects the above-mentioned backward register 3a to the inputs of the memory cell 3b and 2b of the ALU passes. The below series of runs bus system is designated by 5b, and it is from the bus system 5a, 5b drawn only the relevant segments. It will be appreciated that the bus system 5b alternatively receives data from an output 2c of the ALU 2, an output 3c of the RAM 3, and that it performs data in the input 3al of the backward register. The ALU 2 also comprises further inputs and outputs 2al, 2a2, which can be connected to other bus segments and which receives the ALU data such as operands and outputs results.

The control link 4 is located permanently under the control of the extended circuits of the ALU and provides here a connection is, by means of which a plurality of bits can be transmitted. The width of the control link 4 is DA, selected in such that at least the following control commands can be transmitted to the memory cell: DATA WRITE, DATA READ address pointer WRITE ADDRESS POINTER READ, PROGRAM POINTER WRITE PROGRAM POINTER READ, PROGRAM POINTER INCREMENT, STACK POINTER WRITE, STACK POINTER READ , PUSH, POP. The storage cherzelle 3 also has at least three memory areas, namely, a so-called. stack area, a heap area and a program area. Each region has its own pointer is assigned to the process is determined by the, is what part of the stacks of the heap and the program area accessed each le- transmitting or writing.

The bus 5a is used in time multiplex together by the units 2 and 3. FIG. This is indicated in Fig 2c. 2b. Such a situation is shown in Fig. 2b, in which from the output 2a2 of the ALU PAE data over the backward register may be sent to the input of RAM cell, whereas the same time as existing, even though unused connection between the output 3c of RAM to the bus 5b, and the connection between the output of the backward register BW to the input 2b of the ALU-PAE at the time of Fig. 2b no significance, so these are indicated by dashed lines. In Fig. 2c, however, a time is shown, feeds to which the memory cell 3 via its output 3c of the particular via control line 4 memory area stack, heap or Program 2b, the information about the backward register at the input of the ALU PAE 2, while the output of the ALU-PAE 2c is in- active, and the input of the RAM-PAE 3b no signal is received. For this reason, the corresponding compounds are dot-dash lines, and thus represented as inactive.

Within the RAM cell 3 is a circuit 3d is provided, in which via the control line 4 or the bus segment control line 4 received information is decoded.

The invention is used as follows:

First, the ALU 2 receives configuration information from a central load logic as in the prior art already known. The information transfer can be done in a known per se manner using the RDY / ACK protocol and the like. On the possibility of providing a FIL MO memory, etc. at the PLU to "ration proper configurations to allow the arrangement is pointed.

With the data for the configuration of the ALU 2, a series of data from the charging logic is at the same time transfer, which is a sequencer-program to be executed or program part. Reference is made in this example only to FIG. 6, in which the Huffman coding is shown as a central sequential essential part of a data flow like taking place per se MPEG4 encoding. The ALU is, therefore, during their configuration on the line 4 a corresponding command that sets the program pointer for writing to a predetermined value within the RAM. Thereafter, 2c by the PLU in the ALU data received via the output of the bus 5BL and fed the backward register 3a and from there to the input 3b of the RAM-PAE 3. From the unit 3d of the control command are accordingly to control 4 line then data is written to the instructed program memory space. This is repeated until all, received by the PLU in the configuration of parts of the program are stored in the memory cell. 3 Then, when the configuration of the ALU is completed, this speaking by outputting the decision commands will request the next, a sequencer to be processed by its program steps to the control line 4, and 3c via the output, the bus 5b, the backward register, the RAM-PAE 3 and the bus 5a received at its input. During program execution can thereby th situations occurring in which jumps within the program memory area required data is loaded into the ALU-PAE from the RAM-PAE, data, etc., must be stored in the stack The relevant communication between ALU-PAE and RAM -PAE via the control line 4, so that the ALU can JE PAE to the time to perform the decoding. Moreover, can also, as with a conventional microprocessor, data is received from a stack or other RAM memory area, and it can be received from outside as operands in the ALU PAE moreover data.

It takes place here, the processing of the program sequence which has been pre-configured in the RAM-PAE by the PLU. In the ALU-PAE about to instruction decode at the same time, as required per se made. This is done with the same per se circuits that are already used for decoding the information obtained from the PLU commands. It is controlled via the ALU at each time the control line 4 that the RAM cell is always followed exactly the type of memory access, which is specified by the ALU. In this way it is ensured that regardless of the time multiplex use of bus elements 5a, b is always given the present in the Sequenzerstruktur elements, whether lying on the buses addresses to be fetched and / or write data or code or whether, and if where to write data, etc.

The arrangement shown with respect to Fig. 2 can be extended in different ways or modified. Particularly relevant are the variants shown in Fig. 3, 4 and 6.

According to FIG. 3, not only a backward register at the RAM-PAE is provided for connection of the upper and lower buses, but there are also a forward register to the RAM PAE and forward and backward register to the ALU PAE available. These can, as indicated by the multiple arrows are used by other units, such as external hosts, external peripheral devices such as hard disks, memory, and the like, and / or other sequencer structures, PAEs, RAM PAEs etc. to receive data to send to them. If a corresponding request command for new program parts from the Sequenzerstruktur, which is formed by the ALU PAE and the RAM-PAE, is dispatched, it is possible to process program blocks in the Sequenzerstruktur that are far larger than those in the RAM PAE can be stored. This is especially for complex data processing tasks, jumps over large areas, particularly in sub-programs, etc. of massive advantage. A further preferred variant is shown in Fig. 4. Here the ALU PAE communicates not only with a RAM-PAE, but also with an input / output PAE, which is adapted to an interface wiring for the communications provided with external devices, such as hard disks, other XPP VPUs, foreign processors and coprocessors again, so the ALU-PAE, the unit operates as a master for the designated as "CMD" control connection and turn the buses in multiplex mode are used. again, a transfer of data from the bus below the row in the bus of the row above carried out by the backward register.

The arrangement shown in Fig. 4 allows external supply handles on not in the memory cell RAM-PAE storable information especially easy to make, thus enabling an adjustment of Sequenzerstruktur to existing, conventional CPU technologies and their operating procedures even more so to the extent as now output cell in the input address translation means, memory management units (MMU functions) and the like may be implemented. The RAM-PAE can serve here as a cache, but especially as a preloaded cache.

It should be noted that several sequencer structures another in one and the same box can be configured into that function cells, memory cells and, if necessary, input-output cells can be selectively configured for sequencer structures and / or conventional for the XPP technology way and that without simultaneously is possible that an ALU outputs data to another ALU that configure them in a sequencer-way and / or to make part of a Zellel- mente field with which a particular configuration is processed. In this way, the PLU is then optionally be dispensed with.

According to FIG. 6, two embodiments of the invention in one and the same cell element field are combined, sequencer namely formed at the edges of two respective PAEs, namely each with a RAM and an ALU PAE, and when integrated inside with integrated RAM ALU-PAEs function cell memory cell units sequencer formed, whereby it is possible to form only part of the inner frame cells as a combination of cells.

Fig. 5 shows the right (Fig. 5c) a function of cell-cell storage medium combination.

According to Fig. 5c includes a generally designated 50 functional cell memory cell agent combination buses or inputs 51 for the input of operand and configuration data as well as more preferably also possible trigger signals (not shown) here, and the like, and a bus output 52 for the corresponding output data or signals. Within the function cell agent Speicherzellmittel- combination an ALU 53 is provided, as well as the input register Rio to Ri3 for operand data and trigger signal-input register (not shown). The configuration data register RCO to Rc7 for configuration data or ALU opcode data, result data register RDO ^ RS and output registers Roo to Ro3 for results or be output trigger signals. The registers Rc and Rd for the configuration data or option code data is controlled by the ALU 53 via command lines 4 and feed through appropriate data lines data to the ALU and received from this result data. It is also possible, from the bus 51 and the input registers Ri to supply information directly to the output register and the bus 52, just as from the data registers RDO information not only to the ALU, but also to the output register can be fed. If necessary connections between the storage areas Rd and Rc are provided, such as to realize the possibility of self-modifying code.

The configuration data area RCO to Rc7 has a controller that allows to work on parts of the area, in particular cyclically repeated and / or by jumps. This allows, for example, in a first part of configuration commands which are in RCO to Rc3, repeated work off and, alternatively, to process about to input of a respective other trigger signal via the bus line 51, configuration commands which are in Rc4 to Rc7. In order for a feasibility of a wave configura- tion is guaranteed. It should be noted that the stored configuration commands are merely typical instructions to the ALU, but not define full bus services, etc..

The illustrated in Fig. 5, above-described unit is adapted here to operate at four times the clock, like a normal PAE without memory cell means and / or control signal lines 4.

To be on the thus formed function convolution unit (function- folding-unit) work through a sequencer data in a data flow, data are supplied to predetermined algorithms first flow graph or regions shown in FIG. 5a created. Then, each assigned to be processed in the graph operation storage areas RCO, assigned to the flowing into the graph portion data internal input registers RiO, the intermediate results assigned to the memories RDO to Rd3 and the output results Ro registers. With this allocation, the graph area is on the FUNCTION Folding Unit processable. There is almost a data flow sequencer transformation tion by this hardware.

It should be noted in this context that it will be generally preferable to employ the arrangement of the present invention such that initially creates trollflußgraph for a data processing program with a compiler, a data flow and a con-, then a corresponding Par titionierung perform, with the pieces obtained by the partitioning then can be processed in whole or in part for execution on sequencer units, as they can be formed, for example according to the present invention. In this way a datenflußartige data processing in progress from one cell to the next is virtually achieved, but within the cell (s) causes a sequential processing. This is advantageous if the clock frequency is to be increased due to the very high computing power of an arrangement to reduce the area or number of cells in turn. It should here also be mentioned that it is possible, this transformation-like transition from a purely datenflußartigen data processing to a DA tenflußverarbeiturtg with locally sequential parts in such a way to make that an iterative process is executed, for example in such a way that initially a first partitioning is made and then, should be at the subsequent the "rolling up" the partitioned parts zereinheiten on sequencing be noted that as the cern or the sequencing agencies available not resources are sufficient another, it considered partitioning and a renewed "rolling up" make. When desired intensive use of the function folding units, the register number can be increased as necessary.

It should also be noted that in this case the register as a memory cell means or parts thereof be construed. It will be appreciated that by increasing the memory cell regions more complex tasks can be arranged in particular sequencer like that but already significant parts of important algorithms can be executed with the specified small sizes specifically with high efficiency.

In the present example, the Funktionsfaltungseinhei- th are preferably formed so that data can be switched therethrough without being processed in the ALU. This can be exploited to achieve a path balancing process in which about data packets through different branches and then have to be merged (again) without forward-register as they are known in the architecture of the applicant must be employed. Supply the same and / or alternatively it is possible, the data flow direction in the cell element field tion convolution units not to run strictly in one direction by corresponding alignment of some function cell means, memory cell means, radio, but in two opposite directions. For example preserved. As in every even number the ALUs their input operands from the left side and in every odd row ALUs receive their input operands from the right. If data needs to be sent through the field several times, such an arrangement is advantageous, for example when the rolled-loop bodies, etc. The alternating arrangement has to not be strict. For certain applications Toggle particular geometries can be selected. Thus, in the center of the field to another direction may be selected as at the edges, etc. The arrangement of functional units of the same cells the running direction next to one another, with respect to the bus may be advantageous. It should be noted that the counter provisional assembly of a plurality of function cells directed in one field and the resulting thus improved data processing is considered independently from the provision of a control line or the like as inventive.

An alternative to the embodiment shown in Fig. 5 Funktionsfal- processing unit shown in Fig. 7.


1. Cell Mente field for data processing with Funktionszell- mittein to perform algebraic and / or logical
Functions and memory cell means to receive information store, and / or output, characterized in that function-cell memory cell combinations are formed, in which the Funktionszell- mittein a Ξteuerverbindung to the memory cell means is guided.
2. Cell members box according to the preceding claim, characterized in that a processor, co-processor and / or microcontroller forms with a variety of function and / or crosslinking of reconfigurable and / or predeterminable function units such as cells and / or memory cells.
3. field cell elements according to any one of the preceding claims, characterized in that the functional cells are formed as arithmetic logic units.
4. cell members box according to the preceding claim, characterized in that the arithmetic logic units are formed as extended ALUs.
5. cell members box according to any one of the preceding claims, characterized in that the memory cells are formed to the volatile and / or nonvolatile data storage.
6. cell members box according to any one of the preceding claims, characterized in that the memory cells for storing data to be processed and / or are formed to be processed program steps.
7. cell elements field of data processing, characterized in that the memory cells are designed to memorized information on control of the controlling them to give a leading to the function cell bus function cell directly and / or indirectly.
8. cell members box according to any one of the preceding claims, wherein at least one memory cell and / or cell function registers are allocated, in particular a back-ward-register which is arranged in the information path between the memory cell and function cell.
9. cell members box according to any one of the preceding claims, characterized in that the memory cell is arranged to reasonable, information from the controlling them function cell, one of input-output cell, and / or they do not controlled cell to receive with arithmetic logic unit.
10. cell members box according to any one of the preceding claims, characterized in that the Funktionszellen- memory cell combination a one output is associated with at least means for information to an external unit and / or a different function cell function cell memory cell combination and / or transmit memory cell and / or to receive from the latter.
11 cell members box according to the preceding claim, characterized in that the input-output means is also arranged to receive control commands from the function cell.
12 cell elements field according to one of the preceding claims, characterized in that the controller is adapted to at least some, preferably to transfer all of the following commands and / or the memory cell and input / output cell is adapted to decode the following commands : DATA WRITE / READ, address pointer WRITE / READ, PROGRAM POINTER WRITE / READ, PROGRAM POINTER INCREMENT, STACK POINTER WRITE / READ, the aforesaid commands in each case in particular for internal and / or external supply handle, PUSH, POP, OPCODE, FETCH.
13 cell elements field according to one of the preceding claims, characterized in that the function cell can be accessed as a single master to the control connection and / or serving as a control link bus segment.
14 cell elements field for data processing according to any one of the preceding claims, characterized in that the functional cell is arranged at least one of the memory cell and input output cell adjacent.
15 cell elements field according to one of the preceding claims, characterized in that the cell elements are arranged multidimen--dimensionally, in particular matrix-like manner, wherein the function of cell and / or the adjacent Speicherbzw. An output cell from an upper row to receive data and can output data in a lower row, in WO in a row buses are provided and the function cell and at least one memory and / or input output cell lie in one and the same row.
16. A method for operating a cell element array, and in particular multidimensional cell element array with functional cells for performing algebraic and / or logic functions and information providing cells, in particular memory cells, and / or input-output cells for receiving and / or outputting information, and / or
Storing the same, characterized in that at least one of the functional cell control commands at least to output of an information providing cell, where it is processed in response to the control command information for the function of cell and the function cell is adapted to perform a further data processing in response to from the information providing cell information provided to process data so sequencer-like.
17. The method according to any one of the preceding claims, characterized in that the function cell is adapted to at least some of the control commands OPCODE FETCH, DATA WRITE INTERNAL, DATA WRITE EXTERNAL DATA READ INTERNAL, DATA READ EXTERNAL address pointer WRITE INTERNAL, address pointer WRITE EXTERNAL ADDRESS POINTER READ INTERNAL, EXTERNAL ADDRESS POINTER READ, WRITE PROGRAM POINTER INTERN,
PROGRAM POINTER INCREMENT and outputs throughout the cell element operation at least some, in particular all of the above commands as outputs required.
EP03782172A 2002-09-06 2003-09-08 Reconfigurable sequencer structure Withdrawn EP1537486A1 (en)

Priority Applications (10)

Application Number Priority Date Filing Date Title
DE10241812 2002-09-06
DE2002141812 DE10241812A1 (en) 2002-09-06 2002-09-06 Cell element field for processing data has function cells for carrying out algebraic/logical functions and memory cells for receiving, storing and distributing data.
DE10315295 2003-04-04
DE10315295 2003-04-04
DE10321834 2003-05-15
DE10321834 2003-05-15
EP03019428 2003-08-28
EP03019428 2003-08-28
EP03782172A EP1537486A1 (en) 2002-09-06 2003-09-08 Reconfigurable sequencer structure
PCT/EP2003/009957 WO2004038599A1 (en) 2002-09-06 2003-09-08 Reconfigurable sequencer structure

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
EP03782172A EP1537486A1 (en) 2002-09-06 2003-09-08 Reconfigurable sequencer structure

Publications (1)

Publication Number Publication Date
EP1537486A1 true EP1537486A1 (en) 2005-06-08



Family Applications (1)

Application Number Title Priority Date Filing Date
EP03782172A Withdrawn EP1537486A1 (en) 2002-09-06 2003-09-08 Reconfigurable sequencer structure

Country Status (5)

Country Link
US (9) US7394284B2 (en)
EP (1) EP1537486A1 (en)
JP (1) JP4388895B2 (en)
AU (1) AU2003289844A1 (en)
WO (1) WO2004038599A1 (en)

Families Citing this family (53)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1378665A (en) 1999-06-10 2002-11-06 Pact信息技术有限公司 Programming concept
US9552047B2 (en) 2001-03-05 2017-01-24 Pact Xpp Technologies Ag Multiprocessor having runtime adjustable clock and clock dependent power supply
US9037807B2 (en) * 2001-03-05 2015-05-19 Pact Xpp Technologies Ag Processor arrangement on a chip including data processing, memory, and interface elements
US9250908B2 (en) 2001-03-05 2016-02-02 Pact Xpp Technologies Ag Multi-processor bus and cache interconnection system
US9436631B2 (en) 2001-03-05 2016-09-06 Pact Xpp Technologies Ag Chip including memory element storing higher level memory data on a page by page basis
DE50115584D1 (en) * 2000-06-13 2010-09-16 Krass Maren Pipeline ct protocols and communication
US9141390B2 (en) 2001-03-05 2015-09-22 Pact Xpp Technologies Ag Method of processing data with an array of data processors according to application ID
US8058899B2 (en) 2000-10-06 2011-11-15 Martin Vorbach Logic cell array and bus system
US10031733B2 (en) 2001-06-20 2018-07-24 Scientia Sol Mentis Ag Method for processing data
US9411532B2 (en) 2001-09-07 2016-08-09 Pact Xpp Technologies Ag Methods and systems for transferring data between a processing device and external devices
US7624204B2 (en) * 2001-03-22 2009-11-24 Nvidia Corporation Input/output controller node in an adaptable computing environment
US7594229B2 (en) * 2001-10-09 2009-09-22 Nvidia Corp. Predictive resource allocation in computing systems
US7802108B1 (en) 2002-07-18 2010-09-21 Nvidia Corporation Secure storage of program code for an embedded system
US7644279B2 (en) * 2001-12-05 2010-01-05 Nvidia Corporation Consumer product distribution in the embedded system market
US9170812B2 (en) 2002-03-21 2015-10-27 Pact Xpp Technologies Ag Data processing system having integrated pipelined array data processor
US7093255B1 (en) * 2002-05-31 2006-08-15 Quicksilver Technology, Inc. Method for estimating cost when placing operations within a modulo scheduler when scheduling for processors with a large number of function units or reconfigurable data paths
US7620678B1 (en) 2002-06-12 2009-11-17 Nvidia Corporation Method and system for reducing the time-to-market concerns for embedded system design
EP1537486A1 (en) 2002-09-06 2005-06-08 PACT XPP Technologies AG Reconfigurable sequencer structure
US7502915B2 (en) * 2002-09-30 2009-03-10 Nvidia Corporation System and method using embedded microprocessor as a node in an adaptable computing machine
US8949576B2 (en) * 2002-11-01 2015-02-03 Nvidia Corporation Arithmetic node including general digital signal processing functions for an adaptive computing machine
US7617100B1 (en) 2003-01-10 2009-11-10 Nvidia Corporation Method and system for providing an excitation-pattern based audio coding scheme
US9330060B1 (en) * 2003-04-15 2016-05-03 Nvidia Corporation Method and device for encoding and decoding video image data
US8296764B2 (en) * 2003-08-14 2012-10-23 Nvidia Corporation Internal synchronization control for adaptive integrated circuitry
US8130825B2 (en) * 2004-05-10 2012-03-06 Nvidia Corporation Processor for video data encoding/decoding
US8018463B2 (en) * 2004-05-10 2011-09-13 Nvidia Corporation Processor for video data
TWI256013B (en) * 2004-10-12 2006-06-01 Uli Electronics Inc Sound-effect processing circuit
US8731071B1 (en) 2005-12-15 2014-05-20 Nvidia Corporation System for performing finite input response (FIR) filtering in motion estimation
US7999820B1 (en) 2006-10-23 2011-08-16 Nvidia Corporation Methods and systems for reusing memory addresses in a graphics system
US20080111923A1 (en) * 2006-11-09 2008-05-15 Scheuermann W James Processor for video data
US7761728B2 (en) * 2007-01-23 2010-07-20 International Business Machines Corporation Apparatus, system, and method for resetting an inter-integrated circuit data line with a clock line
US8169789B1 (en) 2007-04-10 2012-05-01 Nvidia Corporation Graphics processing unit stiffening frame
US7987065B1 (en) 2007-04-17 2011-07-26 Nvidia Corporation Automatic quality testing of multimedia rendering by software drivers
US8572598B1 (en) 2007-04-18 2013-10-29 Nvidia Corporation Method and system for upgrading software in a computing device
US8756482B2 (en) 2007-05-25 2014-06-17 Nvidia Corporation Efficient encoding/decoding of a sequence of data frames
US8726283B1 (en) 2007-06-04 2014-05-13 Nvidia Corporation Deadlock avoidance skid buffer
US7944453B1 (en) 2007-06-07 2011-05-17 Nvidia Corporation Extrapolation texture filtering for nonresident mipmaps
US7948500B2 (en) * 2007-06-07 2011-05-24 Nvidia Corporation Extrapolation of nonresident mipmap data using resident mipmap data
US9118927B2 (en) 2007-06-13 2015-08-25 Nvidia Corporation Sub-pixel interpolation and its application in motion compensated encoding of a video signal
US8873625B2 (en) 2007-07-18 2014-10-28 Nvidia Corporation Enhanced compression in representing non-frame-edge blocks of image frames
US9081901B2 (en) * 2007-10-31 2015-07-14 Raytheon Company Means of control for reconfigurable computers
WO2009126971A1 (en) * 2008-04-11 2009-10-15 Massachusetts Institute Of Technology Asynchronous logic automata
US8359479B2 (en) * 2008-07-17 2013-01-22 Lsi Corporation High performance arithmetic logic unit (ALU) for cryptographic applications with built-in countermeasures against side channel attacks
GB2474250B (en) * 2009-10-07 2015-05-06 Advanced Risc Mach Ltd Video reference frame retrieval
US9480077B2 (en) 2011-06-06 2016-10-25 Telefonaktiebolaget Lm Ericsson (Publ) Methods and systems for a generic multi-radio access technology
US8782161B2 (en) * 2011-06-30 2014-07-15 Oracle International Corporation Method and system for offloading computation flexibly to a communication adapter
US20130046955A1 (en) * 2011-08-17 2013-02-21 International Business Machines Corporation Local Computation Logic Embedded in a Register File to Accelerate Programs
US8476926B1 (en) 2012-02-08 2013-07-02 Altera Corporation Method and apparatus for implementing periphery devices on a programmable circuit using partial reconfiguration
US9160617B2 (en) 2012-09-28 2015-10-13 International Business Machines Corporation Faulty core recovery mechanisms for a three-dimensional network on a processor array
US8990616B2 (en) * 2012-09-28 2015-03-24 International Business Machines Corporation Final faulty core recovery mechanisms for a two-dimensional network on a processor array
US9553590B1 (en) * 2012-10-29 2017-01-24 Altera Corporation Configuring programmable integrated circuit device resources as processing elements
CN103853620B (en) 2012-11-30 2017-06-09 华为技术有限公司 An inter-process many-core processor communicate with each other method, apparatus and system
JP2016178229A (en) 2015-03-20 2016-10-06 株式会社東芝 Reconfigurable circuit
US10242728B2 (en) * 2016-10-27 2019-03-26 Samsung Electronics Co., Ltd. DPU architecture

Family Cites Families (748)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US2067477A (en) * 1931-03-20 1937-01-12 Allis Chalmers Mfg Co Gearing
US2748872A (en) 1954-10-04 1956-06-05 Madge Johnston Well tool anchoring device
GB971191A (en) * 1962-05-28 1964-09-30 Wolf Electric Tools Ltd Improvements relating to electrically driven equipment
US3473160A (en) 1966-10-10 1969-10-14 Stanford Research Inst Electronically controlled microelectronic cellular logic array
US3531662A (en) 1967-04-10 1970-09-29 Sperry Rand Corp Batch fabrication arrangement for integrated circuits
US3564506A (en) * 1968-01-17 1971-02-16 Ibm Instruction retry byte counter
GB1253309A (en) 1969-11-21 1971-11-10 Marconi Co Ltd Improvements in or relating to data processing arrangements
US3753008A (en) 1970-06-20 1973-08-14 Honeywell Inf Systems Memory pre-driver circuit
DE2057312A1 (en) 1970-11-21 1972-05-25 Bhs Bayerische Berg Planetary gear with load pressure compensation
US3754211A (en) 1971-12-30 1973-08-21 Ibm Fast error recovery communication controller
US3855577A (en) 1973-06-11 1974-12-17 Texas Instruments Inc Power saving circuit for calculator system
US3956589A (en) 1973-11-26 1976-05-11 Paradyne Corporation Data telecommunication system
US4020469A (en) 1975-04-09 1977-04-26 Frank Manning Programmable arrays
DE2713648C3 (en) 1976-03-26 1980-02-21 Tokyo Shibaura Electric Co., Ltd., Kawasaki, Kanagawa (Japan)
US4233667A (en) 1978-10-23 1980-11-11 International Business Machines Corporation Demand powered programmable logic array
US4412303A (en) 1979-11-26 1983-10-25 Burroughs Corporation Array processor architecture
CA1174370A (en) 1980-05-19 1984-09-11 Hidekazu Matsumoto Data processing unit with pipelined operands
US4442508A (en) 1981-08-05 1984-04-10 General Instrument Corporation Storage cells for use in two conductor data column storage logic arrays
US4498134A (en) * 1982-01-26 1985-02-05 Hughes Aircraft Company Segregator functional plane for use in a modular array processor
US4489857A (en) 1982-03-22 1984-12-25 Bobrick Washroom Equipment, Inc. Liquid dispenser
US4590583A (en) 1982-07-16 1986-05-20 At&T Bell Laboratories Coin telephone measurement circuitry
US4498172A (en) * 1982-07-26 1985-02-05 General Electric Company System for polynomial division self-testing of digital networks
US4667190A (en) 1982-07-30 1987-05-19 Honeywell Inc. Two axis fast access memory
JPH0222423B2 (en) 1982-08-25 1990-05-18 Nippon Electric Co
US4539637A (en) 1982-08-26 1985-09-03 At&T Bell Laboratories Method and apparatus for handling interprocessor calls in a multiprocessor system
US4663706A (en) 1982-10-28 1987-05-05 Tandem Computers Incorporated Multiprocessor multisystem communications network
US4594682A (en) 1982-12-22 1986-06-10 Ibm Corporation Vector processing
US4739474A (en) * 1983-03-10 1988-04-19 Martin Marietta Corporation Geometric-arithmetic parallel processor
US4566102A (en) * 1983-04-18 1986-01-21 International Business Machines Corporation Parallel-shift error reconfiguration
US5123109A (en) 1983-05-31 1992-06-16 Thinking Machines Corporation Parallel processor including a processor array with plural data transfer arrangements including (1) a global router and (2) a proximate-neighbor transfer system
US4571736A (en) 1983-10-31 1986-02-18 University Of Southwestern Louisiana Digital communication system employing differential coding and sample robbing
US4646300A (en) * 1983-11-14 1987-02-24 Tandem Computers Incorporated Communications method
USRE34363E (en) 1984-03-12 1993-08-31 Xilinx, Inc. Configurable electrical circuit having configurable logic elements and configurable interconnects
US4870302A (en) 1984-03-12 1989-09-26 Xilinx, Inc. Configurable electrical circuit having configurable logic elements and configurable interconnects
JPS60198618A (en) 1984-03-21 1985-10-08 Oki Electric Ind Co Ltd Dynamic logical circuit
US4577293A (en) 1984-06-01 1986-03-18 International Business Machines Corporation Distributed, on-chip cache
US4761755A (en) 1984-07-11 1988-08-02 Prime Computer, Inc. Data processing system and method having an improved arithmetic unit
US4642487A (en) 1984-09-26 1987-02-10 Xilinx, Inc. Special interconnect for configurable logic array
US4682284A (en) 1984-12-06 1987-07-21 American Telephone & Telegraph Co., At&T Bell Lab. Queue administration method and apparatus
US4623997A (en) 1984-12-13 1986-11-18 United Technologies Corporation Coherent interface with wraparound receive and transmit memories
EP0190813B1 (en) 1985-01-29 1991-09-18 Secretary of State for Defence in Her Britannic Majesty's Gov. of the United Kingdom of Great Britain and Northern Ireland Processing cell for fault tolerant arrays
US4720778A (en) * 1985-01-31 1988-01-19 Hewlett Packard Company Software debugging analyzer
US5023775A (en) 1985-02-14 1991-06-11 Intel Corporation Software programmable logic array utilizing "and" and "or" gates
US5247689A (en) 1985-02-25 1993-09-21 Ewert Alfred P Parallel digital processor including lateral transfer buses with interrupt switches to form bus interconnection segments
US4706216A (en) 1985-02-27 1987-11-10 Xilinx, Inc. Configurable logic element
US5225719A (en) * 1985-03-29 1993-07-06 Advanced Micro Devices, Inc. Family of multiple segmented programmable logic blocks interconnected by a high speed centralized switch matrix
US5015884A (en) 1985-03-29 1991-05-14 Advanced Micro Devices, Inc. Multiple array high performance programmable logic device family
US4972314A (en) 1985-05-20 1990-11-20 Hughes Aircraft Company Data flow signal processor method and apparatus
US4967340A (en) 1985-06-12 1990-10-30 E-Systems, Inc. Adaptive processing system having an array of individually configurable processing components
GB8517376D0 (en) 1985-07-09 1985-08-14 Jesshope C R Processor array
US4748580A (en) 1985-08-30 1988-05-31 Advanced Micro Devices, Inc. Multi-precision fixed/floating-point processor
US4720780A (en) * 1985-09-17 1988-01-19 The Johns Hopkins University Memory-linked wavefront array processor
US4722084A (en) 1985-10-02 1988-01-26 Itt Corporation Array reconfiguration apparatus and methods particularly adapted for use with very large scale integrated circuits
DE3687400T2 (en) 1985-11-04 1993-07-15 Ibm nachrichtenuebertragungsnetzwerke digital and construction of uebertragungswegen in these networks.
US5070475A (en) 1985-11-14 1991-12-03 Data General Corporation Floating point unit interface
US4700187A (en) 1985-12-02 1987-10-13 Concurrent Logic, Inc. Programmable, asynchronous logic cell and array
US4852048A (en) 1985-12-12 1989-07-25 Itt Corporation Single instruction multiple data (SIMD) cellular array processing apparatus employing a common bus where a first number of bits manifest a first bus portion and a second number of bits manifest a second bus portion
US4720822A (en) 1986-03-07 1988-01-19 International Business Machines Corporation High frequency signal measurement method and apparatus
US4882687A (en) * 1986-03-31 1989-11-21 Schlumberger Technology Corporation Pixel processor
US5021947A (en) 1986-03-31 1991-06-04 Hughes Aircraft Company Data-flow multiprocessor architecture with three dimensional multistage interconnection network for efficient signal and data processing
US4724307A (en) 1986-04-29 1988-02-09 Gtech Corporation Marked card reader
US5034914A (en) 1986-05-15 1991-07-23 Aquidneck Systems International, Inc. Optical disk data storage method and apparatus with buffered interface
GB8612396D0 (en) 1986-05-21 1986-06-25 Hewlett Packard Ltd Chain-configured interface bus system
US4760525A (en) 1986-06-10 1988-07-26 The United States Of America As Represented By The Secretary Of The Air Force Complex arithmetic vector processor for performing control function, scalar operation, and set-up of vector signal processing instruction
US4791603A (en) * 1986-07-18 1988-12-13 Honeywell Inc. Dynamically reconfigurable array logic
US4860201A (en) 1986-09-02 1989-08-22 The Trustees Of Columbia University In The City Of New York Binary tree parallel processor
US4910665A (en) * 1986-09-02 1990-03-20 General Electric Company Distributed processing system including reconfigurable elements
US5367208A (en) * 1986-09-19 1994-11-22 Actel Corporation Reconfigurable programmable interconnect architecture
US4884231A (en) * 1986-09-26 1989-11-28 Performance Semiconductor Corporation Microprocessor system with extended arithmetic logic unit
US4768196A (en) 1986-10-28 1988-08-30 Silc Technologies, Inc. Programmable logic array
JP2900359B2 (en) 1986-10-30 1999-06-02 日立マクセル株式会社 Multi-processor system
FR2606184B1 (en) * 1986-10-31 1991-11-29 Thomson Csf Computing device reconfigurable
US4918440A (en) * 1986-11-07 1990-04-17 Furtek Frederick C Programmable logic cell and array
US4811214A (en) * 1986-11-14 1989-03-07 Princeton University Multinode reconfigurable pipeline computer
US4786904A (en) 1986-12-15 1988-11-22 Zoran Corporation Electronically programmable gate array having programmable interconnect lines
US4837735A (en) 1987-06-09 1989-06-06 Martin Marietta Energy Systems, Inc. Parallel machine architecture for production rule systems
US5226122A (en) 1987-08-21 1993-07-06 Compaq Computer Corp. Programmable logic system for filtering commands to a microprocessor
CA1299757C (en) 1987-08-28 1992-04-28 Brent Cameron Beardsley Device initiated partial system quiescing
US5119290A (en) 1987-10-02 1992-06-02 Sun Microsystems, Inc. Alias address support
US4862407A (en) 1987-10-05 1989-08-29 Motorola, Inc. Digital signal processing apparatus
CA1286421C (en) 1987-10-14 1991-07-16 Martin Claude Lefebvre Message fifo buffer controller
US5115510A (en) 1987-10-20 1992-05-19 Sharp Kabushiki Kaisha Multistage data flow processor with instruction packet, fetch, storage transmission and address generation controlled by destination information
GB2211638A (en) * 1987-10-27 1989-07-05 Ibm Simd array processor
US5081575A (en) 1987-11-06 1992-01-14 Oryx Corporation Highly parallel computer architecture employing crossbar switch with selectable pipeline delay
US5031179A (en) 1987-11-10 1991-07-09 Canon Kabushiki Kaisha Data communication apparatus
US4918690A (en) 1987-11-10 1990-04-17 Echelon Systems Corp. Network and intelligent cell for providing sensing, bidirectional communications and control
US5113498A (en) 1987-11-10 1992-05-12 Echelon Corporation Input/output section for an intelligent cell which provides sensing, bidirectional communications and control
NL8800053A (en) * 1988-01-11 1989-08-01 Philips Nv Video processor system, as well as imaging system, and image storage system provided with such a video processor system.
USRE34444E (en) * 1988-01-13 1993-11-16 Xilinx, Inc. Programmable logic device
NL8800071A (en) * 1988-01-13 1989-08-01 Philips Nv Data processor system and video processor system, provided with such a data processor system.
US5197016A (en) 1988-01-13 1993-03-23 International Chip Corporation Integrated silicon-software compiler
DE68917326D1 (en) 1988-01-20 1994-09-15 Advanced Micro Devices Inc Organizing an integrated cache for flexible application to support multi-processor operations.
US5261113A (en) 1988-01-25 1993-11-09 Digital Equipment Corporation Apparatus and method for single operand register array for vector and scalar data processing operations
US5303172A (en) * 1988-02-16 1994-04-12 Array Microsystems Pipelined combination and vector signal processor
US4959781A (en) 1988-05-16 1990-09-25 Stardent Computer, Inc. System for assigning interrupts to least busy processor that already loaded same class of interrupt routines
JP2741867B2 (en) 1988-05-27 1998-04-22 株式会社日立マイコンシステム An information processing system and processor
US4939641A (en) 1988-06-30 1990-07-03 Wang Laboratories, Inc. Multi-processor system with cache memories
JPH06101043B2 (en) 1988-06-30 1994-12-12 三菱電機株式会社 Micro computer
US5287511A (en) * 1988-07-11 1994-02-15 Star Semiconductor Corporation Architectures and methods for dividing processing tasks into tasks for a programmable real time signal processor and tasks for a decision making microprocessor interfacing therewith
WO1990001192A1 (en) 1988-07-22 1990-02-08 United States Department Of Energy Data flow machine for data driven computing
US5010401A (en) 1988-08-11 1991-04-23 Mitsubishi Denki Kabushiki Kaisha Picture coding and decoding apparatus using vector quantization
US4901268A (en) * 1988-08-19 1990-02-13 General Electric Company Multiple function data processor
US5204935A (en) * 1988-08-19 1993-04-20 Fuji Xerox Co., Ltd. Programmable fuzzy logic circuits
US5353432A (en) 1988-09-09 1994-10-04 Compaq Computer Corporation Interactive method for configuration of computer system and circuit boards with user specification of system resources and computer resolution of resource conflicts
ES2047629T3 (en) 1988-09-22 1994-03-01 Siemens Ag Circuit arrangement for telecommunications switching installations, especially telephone switching facilities temporary-pcm multiplexing with central field coupling and coupling fields partially connected.
US5452231A (en) 1988-10-05 1995-09-19 Quickturn Design Systems, Inc. Hierarchically connected reconfigurable logic assembly
AT131643T (en) * 1988-10-05 1995-12-15 Quickturn Systems Inc A method of using an electronically reconfigurable gate array logic and device manufactured thereby
DE68926783D1 (en) 1988-10-07 1996-08-08 Martin Marietta Corp Parallel data processor
US5014193A (en) 1988-10-14 1991-05-07 Compaq Computer Corporation Dynamically configurable portable computer system
US5136717A (en) 1988-11-23 1992-08-04 Flavors Technology Inc. Realtime systolic, multiple-instruction, single-data parallel computer system
US5041924A (en) 1988-11-30 1991-08-20 Quantum Corporation Removable and transportable hard disk subsystem
US5459846A (en) * 1988-12-02 1995-10-17 Hyatt; Gilbert P. Computer architecture system having an imporved memory
US5081375A (en) * 1989-01-19 1992-01-14 National Semiconductor Corp. Method for operating a multiple page programmable logic device
US5245616A (en) 1989-02-24 1993-09-14 Rosemount Inc. Technique for acknowledging packets
GB8906145D0 (en) * 1989-03-17 1989-05-04 Algotronix Ltd Configurable cellular array
US5203005A (en) * 1989-05-02 1993-04-13 Horst Robert W Cell structure for linear array wafer scale integration architecture with capability to open boundary i/o bus without neighbor acknowledgement
US5237686A (en) 1989-05-10 1993-08-17 Mitsubishi Denki Kabushiki Kaisha Multiprocessor type time varying image encoding system and image processor with memory bus control table for arbitration priority
US5109503A (en) * 1989-05-22 1992-04-28 Ge Fanuc Automation North America, Inc. Apparatus with reconfigurable counter includes memory for storing plurality of counter configuration files which respectively define plurality of predetermined counters
JP2584673B2 (en) 1989-06-09 1997-02-26 株式会社日立製作所 Logic tester having a test data changing circuit
US5343406A (en) 1989-07-28 1994-08-30 Xilinx, Inc. Distributed memory architecture for a configurable logic array and method for using distributed memory
CA2021192A1 (en) * 1989-07-28 1991-01-29 Malcolm A. Mumme Simplified synchronous mesh processor
US5212652A (en) 1989-08-15 1993-05-18 Advanced Micro Devices, Inc. Programmable gate array with improved interconnect structure
US5233539A (en) 1989-08-15 1993-08-03 Advanced Micro Devices, Inc. Programmable gate array with improved interconnect structure, input/output structure and configurable logic block
US5128559A (en) 1989-09-29 1992-07-07 Sgs-Thomson Microelectronics, Inc. Logic block for programmable logic devices
JP2968289B2 (en) * 1989-11-08 1999-10-25 株式会社リコー Central processing unit
GB8925721D0 (en) 1989-11-14 1990-01-04 Amt Holdings Processor array system
GB8925723D0 (en) * 1989-11-14 1990-01-04 Amt Holdings Processor array system
US5522083A (en) 1989-11-17 1996-05-28 Texas Instruments Incorporated Reconfigurable multi-processor operating in SIMD mode with one processor fetching instructions for use by remaining processors
US5212777A (en) * 1989-11-17 1993-05-18 Texas Instruments Incorporated Multi-processor reconfigurable in single instruction multiple data (SIMD) and multiple instruction multiple data (MIMD) modes and method of operation
DE58908974D1 (en) * 1989-11-21 1995-03-16 Itt Ind Gmbh Deutsche Data-controlled array processor.
US5099447A (en) * 1990-01-22 1992-03-24 Alliant Computer Systems Corporation Blocked matrix multiplication for computers with hierarchical memory
AU7305491A (en) 1990-01-29 1991-08-21 Teraplex, Inc. Architecture for minimal instruction set computing system
US5125801A (en) 1990-02-02 1992-06-30 Isco, Inc. Pumping system
JPH03254497A (en) 1990-03-05 1991-11-13 Mitsubishi Electric Corp Microcomputer
JP3118266B2 (en) 1990-03-06 2000-12-18 ゼロックス コーポレイション Synchronization segment bus and the bus communication method
US5036493A (en) 1990-03-15 1991-07-30 Digital Equipment Corporation System and method for reducing power usage by multiple memory modules
US5142469A (en) 1990-03-29 1992-08-25 Ge Fanuc Automation North America, Inc. Method for converting a programmable logic controller hardware configuration and corresponding control program for use on a first programmable logic controller to use on a second programmable logic controller
US5555201A (en) 1990-04-06 1996-09-10 Lsi Logic Corporation Method and system for creating and validating low level description of electronic design from higher level, behavior-oriented description, including interactive system for hierarchical display of control and dataflow information
IL96808A (en) 1990-04-18 1996-03-31 Rambus Inc Integrated circuit i/o using a high performance bus interface
EP0463721A3 (en) 1990-04-30 1993-06-16 Gennum Corporation Digital signal processing device
WO1991017507A1 (en) * 1990-05-07 1991-11-14 Mitsubishi Denki Kabushiki Kaisha Parallel data processing system
US5198705A (en) 1990-05-11 1993-03-30 Actel Corporation Logic module with configurable combinational and sequential blocks
US5483620A (en) * 1990-05-22 1996-01-09 International Business Machines Corp. Learning machine synapse processor system apparatus
US5193202A (en) * 1990-05-29 1993-03-09 Wavetracer, Inc. Processor array with relocated operand physical address generator capable of data transfer to distant physical processor for each virtual processor while simulating dimensionally larger array processor
CA2045773A1 (en) 1990-06-29 1991-12-30 Compaq Computer Corporation Byte-compare operation for high-performance processor
US5111079A (en) 1990-06-29 1992-05-05 Sgs-Thomson Microelectronics, Inc. Power reduction circuit for programmable logic device
SE9002558D0 (en) 1990-08-02 1990-08-02 Carlstedt Elektronik Ab processor
DE4129614C2 (en) 1990-09-07 2002-03-21 Hitachi Ltd System and method for data processing
US5274593A (en) 1990-09-28 1993-12-28 Intergraph Corporation High speed redundant rows and columns for semiconductor memories
US5305446A (en) * 1990-09-28 1994-04-19 Texas Instruments Incorporated Processing devices with improved addressing capabilities, systems and methods
US5076482A (en) 1990-10-05 1991-12-31 The Fletcher Terry Company Pneumatic point driver
US5245227A (en) 1990-11-02 1993-09-14 Atmel Corporation Versatile programmable logic cell for use in configurable logic arrays
US5144166A (en) 1990-11-02 1992-09-01 Concurrent Logic, Inc. Programmable logic cell and array
US5617577A (en) * 1990-11-13 1997-04-01 International Business Machines Corporation Advanced parallel array processor I/O connection
US5794059A (en) 1990-11-13 1998-08-11 International Business Machines Corporation N-dimensional modified hypercube
US5590345A (en) * 1990-11-13 1996-12-31 International Business Machines Corporation Advanced parallel array processor(APAP)
US5734921A (en) * 1990-11-13 1998-03-31 International Business Machines Corporation Advanced parallel array processor computer package
US5588152A (en) 1990-11-13 1996-12-24 International Business Machines Corporation Advanced parallel processor including advanced support hardware
US5765011A (en) 1990-11-13 1998-06-09 International Business Machines Corporation Parallel processing system having a synchronous SIMD processing with processing elements emulating SIMD operation using individual instruction streams
EP0485690B1 (en) 1990-11-13 1999-05-26 International Business Machines Corporation Parallel associative processor system
US5625836A (en) 1990-11-13 1997-04-29 International Business Machines Corporation SIMD/MIMD processing memory element (PME)
US5708836A (en) * 1990-11-13 1998-01-13 International Business Machines Corporation SIMD/MIMD inter-processor communication
CA2051222C (en) 1990-11-30 1998-05-05 Pradeep S. Sindhu Consistent packet switched memory bus for shared memory multiprocessors
US5613128A (en) * 1990-12-21 1997-03-18 Intel Corporation Programmable multi-processor interrupt controller system with a processor integrated local interrupt controller
US5276836A (en) * 1991-01-10 1994-01-04 Hitachi, Ltd. Data processing device with common memory connecting mechanism
US5301284A (en) * 1991-01-16 1994-04-05 Walker-Estes Corporation Mixed-resolution, N-dimensional object space method and apparatus
US5301344A (en) 1991-01-29 1994-04-05 Analogic Corporation Multibus sequential processor to perform in parallel a plurality of reconfigurable logic operations on a plurality of data sets
JP2867717B2 (en) 1991-02-01 1999-03-10 日本電気株式会社 Micro computer
US5212716A (en) 1991-02-05 1993-05-18 International Business Machines Corporation Data edge phase sorting circuits
US5218302A (en) 1991-02-06 1993-06-08 Sun Electric Corporation Interface for coupling an analyzer to a distributorless ignition system
JPH07168610A (en) 1991-02-22 1995-07-04 Siemens Ag Memory programmable controller and operation method therefor
JPH04290155A (en) 1991-03-19 1992-10-14 Fujitsu Ltd Parallel data processing system
JPH04293151A (en) * 1991-03-20 1992-10-16 Fujitsu Ltd Parallel data processing system
US5617547A (en) * 1991-03-29 1997-04-01 International Business Machines Corporation Switch network extension of bus architecture
WO1992018935A1 (en) 1991-04-09 1992-10-29 Fujitsu Limited Data processor and data processing method
JPH04328657A (en) * 1991-04-30 1992-11-17 Toshiba Corp Cache memory
US5551033A (en) 1991-05-17 1996-08-27 Zenith Data Systems Corporation Apparatus for maintaining one interrupt mask register in conformity with another in a manner invisible to an executing program
AU2158692A (en) 1991-05-24 1993-01-08 British Technology Group Usa, Inc. Optimizing compiler for computers
US5659797A (en) 1991-06-24 1997-08-19 U.S. Philips Corporation Sparc RISC based computer system including a single chip processor with memory management and DMA units coupled to a DRAM interface
JP3259969B2 (en) 1991-07-09 2002-02-25 株式会社東芝 Cache memory controller
US5347639A (en) 1991-07-15 1994-09-13 International Business Machines Corporation Self-parallelizing computer system and method
US5317209A (en) 1991-08-29 1994-05-31 National Semiconductor Corporation Dynamic three-state bussing capability in a configurable logic array
US5298805A (en) 1991-08-29 1994-03-29 National Semiconductor Corporation Versatile and efficient cell-to-local bus interface in a configurable logic array
US5581731A (en) 1991-08-30 1996-12-03 King; Edward C. Method and apparatus for managing video data for faster access by selectively caching video data
US5550782A (en) 1991-09-03 1996-08-27 Altera Corporation Programmable logic array integrated circuits
US5260610A (en) * 1991-09-03 1993-11-09 Altera Corporation Programmable logic element interconnections for programmable logic array integrated circuits
FR2681791B1 (en) * 1991-09-27 1994-05-06 Salomon Sa Device vibration damping golf club.
CA2073516A1 (en) 1991-11-27 1993-05-28 Peter Michael Kogge Dynamic multi-mode parallel processor array architecture computer system
WO1993011503A1 (en) 1991-12-06 1993-06-10 Norman Richard S Massively-parallel direct output processor array
US5208491A (en) 1992-01-07 1993-05-04 Washington Research Foundation Field programmable gate array
FR2686175B1 (en) 1992-01-14 1996-12-20 Andre Thepaut multiprocessor data processing system.
US5412795A (en) 1992-02-25 1995-05-02 Micral, Inc. State machine having a variable timing mechanism for varying the duration of logical output states of the state machine based on variation in the clock frequency
JP2791243B2 (en) * 1992-03-13 1998-08-27 株式会社東芝 Large-scale integrated circuit using inter-hierarchy synchronizing system and this
US5452401A (en) 1992-03-31 1995-09-19 Seiko Epson Corporation Selective power-down for high performance CPU/system
JP2647327B2 (en) * 1992-04-06 1997-08-27 インターナショナル・ビジネス・マシーンズ・コーポレイション Massively parallel computing system device
US5493663A (en) * 1992-04-22 1996-02-20 International Business Machines Corporation Method and apparatus for predetermining pages for swapping from physical memory in accordance with the number of accesses
JP2572522B2 (en) 1992-05-12 1997-01-16 インターナショナル・ビジネス・マシーンズ・コーポレイション Computing device
US5611049A (en) * 1992-06-03 1997-03-11 Pitts; William M. System for accessing distributed data cache channel at each network node to pass requests and data
WO1993024895A2 (en) 1992-06-04 1993-12-09 Xilinx, Inc. Timing driven method for laying out a user's circuit onto a programmable integrated circuit device
DE4221278C2 (en) 1992-06-29 1996-02-29 Martin Vorbach Busgekoppeltes multicomputer system
AT207234T (en) 1992-07-02 2001-11-15 Atmel Corp Uninterrupted optional free access memory system
US5475803A (en) 1992-07-10 1995-12-12 Lsi Logic Corporation Method for 2-D affine transformation of images
JP3032382B2 (en) 1992-07-13 2000-04-17 シャープ株式会社 Sampling frequency converting apparatus of the digital signal
US5365125A (en) * 1992-07-23 1994-11-15 Xilinx, Inc. Logic cell for field programmable gate array having optional internal feedback and optional cascade
US5386154A (en) * 1992-07-23 1995-01-31 Xilinx, Inc. Compact logic cell for field programmable gate array chip
US5590348A (en) 1992-07-28 1996-12-31 International Business Machines Corporation Status predictor for combined shifter-rotate/merge unit
US5802290A (en) 1992-07-29 1998-09-01 Virtual Computer Corporation Computer network of distributed virtual computers which are EAC reconfigurable in response to instruction to be executed
US5489857A (en) * 1992-08-03 1996-02-06 Advanced Micro Devices, Inc. Flexible synchronous/asynchronous cell structure for a high density programmable logic device
US5581778A (en) 1992-08-05 1996-12-03 David Sarnoff Researach Center Advanced massively parallel computer using a field of the instruction to selectively enable the profiling counter to increase its value in response to the system clock
AT237861T (en) * 1992-09-03 2003-05-15 Sony Corp Data recording apparatus and method
US5572710A (en) 1992-09-11 1996-11-05 Kabushiki Kaisha Toshiba High speed logic simulation system using time division emulation suitable for large scale logic circuits
US5425036A (en) 1992-09-18 1995-06-13 Quickturn Design Systems, Inc. Method and apparatus for debugging reconfigurable emulation systems
JPH06180653A (en) 1992-10-02 1994-06-28 Hudson Soft Co Ltd Interruption processing method and device therefor
GB9223226D0 (en) 1992-11-05 1992-12-16 Algotronix Ltd Improved configurable cellular array (cal ii)
US5497498A (en) * 1992-11-05 1996-03-05 Giga Operations Corporation Video processing module using a second programmable logic device which reconfigures a first programmable logic device for data transformation
US5857109A (en) * 1992-11-05 1999-01-05 Giga Operations Corporation Programmable logic device for real time video processing
US5392437A (en) * 1992-11-06 1995-02-21 Intel Corporation Method and apparatus for independently stopping and restarting functional units
US5394030A (en) 1992-11-10 1995-02-28 Infinite Technology Corporation Programmable logic device
US5357152A (en) 1992-11-10 1994-10-18 Infinite Technology Corporation Logic system of logic networks with programmable selected functions and programmable operational controls
US5361373A (en) 1992-12-11 1994-11-01 Gilson Kent L Integrated circuit computing device comprising a dynamically configurable gate array having a microprocessor and reconfigurable instruction execution means and method therefor
EP0601715A1 (en) * 1992-12-11 1994-06-15 National Semiconductor Corporation Bus of CPU core optimized for accessing on-chip memory devices
US5311079A (en) 1992-12-17 1994-05-10 Ditlow Gary S Low power, high performance PLA
JP2977688B2 (en) 1992-12-18 1999-11-15 富士通株式会社 Multiprocessing system, method, and processor used in these
US5428526A (en) 1993-02-03 1995-06-27 Flood; Mark A. Programmable controller with time periodic communication
US5386518A (en) * 1993-02-12 1995-01-31 Hughes Aircraft Company Reconfigurable computer interface and method
GB9303084D0 (en) 1993-02-16 1993-03-31 Inmos Ltd Programmable logic circuit
JPH06276086A (en) 1993-03-18 1994-09-30 Fuji Xerox Co Ltd Field programmable gate array
US5548773A (en) 1993-03-30 1996-08-20 The United States Of America As Represented By The Administrator Of The National Aeronautics And Space Administration Digital parallel processor array for optimum path planning
US5386155A (en) 1993-03-30 1995-01-31 Intel Corporation Apparatus and method for selecting polarity and output type in a programmable logic device
US5596742A (en) * 1993-04-02 1997-01-21 Massachusetts Institute Of Technology Virtual interconnections for reconfigurable logic systems
US5761484A (en) 1994-04-01 1998-06-02 Massachusetts Institute Of Technology Virtual interconnections for reconfigurable logic systems
US5418953A (en) 1993-04-12 1995-05-23 Loral/Rohm Mil-Spec Corp. Method for automated deployment of a software program onto a multi-processor architecture
US5473266A (en) 1993-04-19 1995-12-05 Altera Corporation Programmable logic device having fast programmable logic array blocks and a central global interconnect array
WO1994025917A1 (en) 1993-04-26 1994-11-10 Comdisco Systems, Inc. Method for scheduling synchronous data flow graphs
DE4416881C2 (en) 1993-05-13 1998-03-19 Pact Inf Tech Gmbh A method of operating a data processing device
US5435000A (en) 1993-05-19 1995-07-18 Bull Hn Information Systems Inc. Central processing unit using dual basic processing units and combined result bus
US5349193A (en) 1993-05-20 1994-09-20 Princeton Gamma Tech, Inc. Highly sensitive nuclear spectrometer apparatus and method
SG46393A1 (en) 1993-05-28 1998-02-20 Univ California Field programmable logic device with dynamic interconnections to a dynamic logic core
IT1260848B (en) 1993-06-11 1996-04-23 Finmeccanica Spa Multiprocessor System
US5444394A (en) 1993-07-08 1995-08-22 Altera Corporation PLD with selective inputs from local and global conductors
JPH0736858A (en) 1993-07-21 1995-02-07 Hitachi Ltd Signal processor
US5581734A (en) 1993-08-02 1996-12-03 International Business Machines Corporation Multiprocessor system with shared cache and data input/output circuitry for transferring data amount greater than system bus capacity
CA2129882A1 (en) 1993-08-12 1995-02-13 Soheil Shams Dynamically reconfigurable interprocessor communication network for simd multiprocessors and apparatus implementing same
US5457644A (en) 1993-08-20 1995-10-10 Actel Corporation Field programmable digital signal processing array integrated circuit
US5440538A (en) 1993-09-23 1995-08-08 Massachusetts Institute Of Technology Communication system with redundant links and data bit time multiplexing
GB2282244B (en) 1993-09-23 1998-01-14 Advanced Risc Mach Ltd Integrated circuit
US6219688B1 (en) 1993-11-30 2001-04-17 Texas Instruments Incorporated Method, apparatus and system for sum of plural absolute differences
US5455525A (en) 1993-12-06 1995-10-03 Intelligent Logic Systems, Inc. Hierarchically-structured programmable logic array and system for interconnecting logic elements in the logic array
US6064819A (en) 1993-12-08 2000-05-16 Imec Control flow and memory management optimization
US5574753A (en) * 1993-12-23 1996-11-12 Unisys Corporation Glitch free clock start/stop control circuit for outputting a single clock signal and a single sync signal from a plurality of sync signal inputs and a plurality of clock signal inputs
US5535406A (en) 1993-12-29 1996-07-09 Kolchinsky; Alexander Virtual processor module including a reconfigurable programmable matrix
US5680583A (en) 1994-02-16 1997-10-21 Arkos Design, Inc. Method and apparatus for a trace buffer in an emulation system
JPH07234842A (en) 1994-02-22 1995-09-05 Fujitsu Ltd Parallel data processing system
US5778237A (en) 1995-01-10 1998-07-07 Hitachi, Ltd. Data processor and single-chip microcomputer with changing clock frequency and operating voltage
WO1995025306A2 (en) 1994-03-14 1995-09-21 Stanford University Distributed shared-cache for multi-processors
DE69519426D1 (en) 1994-03-22 2000-12-21 Hyperchip Inc Cell-based fault-tolerant architecture with advantageous use of the non-allocated redundant cells
US5561738A (en) 1994-03-25 1996-10-01 Motorola, Inc. Data processor for executing a fuzzy logic operation and method therefor
US5574927A (en) 1994-03-25 1996-11-12 International Meta Systems, Inc. RISC architecture computer configured for emulation of the instruction set of a target computer
US5781756A (en) 1994-04-01 1998-07-14 Xilinx, Inc. Programmable logic device with partially configurable memory cells and a method for configuration
US5504439A (en) * 1994-04-01 1996-04-02 Xilinx, Inc. I/O interface cell for use with optional pad
US5430687A (en) 1994-04-01 1995-07-04 Xilinx, Inc. Programmable logic device including a parallel input device for loading memory cells
US5896551A (en) * 1994-04-15 1999-04-20 Micron Technology, Inc. Initializing and reprogramming circuitry for state independent memory array burst operations control
WO1995028671A1 (en) 1994-04-18 1995-10-26 Green Logic Inc. An improved system logic controller for digital computers
US5426378A (en) 1994-04-20 1995-06-20 Xilinx, Inc. Programmable logic device which stores more than one configuration and means for switching configurations
US5502838A (en) 1994-04-28 1996-03-26 Consilium Overseas Limited Temperature management for integrated circuits
US5677909A (en) 1994-05-11 1997-10-14 Spectrix Corporation Apparatus for exchanging data between a central station and a plurality of wireless remote stations on a time divided commnication channel
JP2671804B2 (en) 1994-05-27 1997-11-05 日本電気株式会社 Hierarchical resource management method
US5532693A (en) 1994-06-13 1996-07-02 Advanced Hardware Architectures Adaptive data compression system with systolic string matching logic
EP0690378A1 (en) 1994-06-30 1996-01-03 Tandem Computers Incorporated Tool and method for diagnosing and correcting errors in a computer programm
JP3308770B2 (en) 1994-07-22 2002-07-29 三菱電機株式会社 The calculation method in an information processing apparatus and an information processing apparatus
US5600845A (en) * 1994-07-27 1997-02-04 Metalithic Systems Incorporated Integrated circuit computing device comprising a dynamically configurable gate array having a microprocessor and reconfigurable instruction execution means and method therefor
JP3365581B2 (en) 1994-07-29 2003-01-14 富士通株式会社 Self-repair function with an information processing apparatus
US5703793A (en) 1994-07-29 1997-12-30 Discovision Associates Video decompression
US5574930A (en) 1994-08-12 1996-11-12 University Of Hawaii Computer system and method using functional memory
US5513366A (en) * 1994-09-28 1996-04-30 International Business Machines Corporation Method and system for dynamically reconfiguring a register file in a vector processor
US5619720A (en) * 1994-10-04 1997-04-08 Analog Devices, Inc. Digital signal processor having link ports for point-to-point communication
US5450022A (en) * 1994-10-07 1995-09-12 Xilinx Inc. Structure and method for configuration of a field programmable gate array
EP0707269A1 (en) 1994-10-11 1996-04-17 International Business Machines Corporation Cache coherence network for a multiprocessor data processing system
US5530946A (en) 1994-10-28 1996-06-25 Dell Usa, L.P. Processor failure detection and recovery circuit in a dual processor computer system and method of operation thereof
US5815726A (en) 1994-11-04 1998-09-29 Altera Corporation Coarse-grained look-up table architecture
JPH08137824A (en) 1994-11-15 1996-05-31 Mitsubishi Electric Corp Single-chip microcomputer with built-in self-test function
US6154826A (en) 1994-11-16 2000-11-28 University Of Virginia Patent Foundation Method and device for maximizing memory system bandwidth by accessing data in a dynamically determined order
US5808487A (en) 1994-11-30 1998-09-15 Hitachi Micro Systems, Inc. Multi-directional small signal transceiver/repeater
US5584013A (en) 1994-12-09 1996-12-10 International Business Machines Corporation Hierarchical cache arrangement wherein the replacement of an LRU entry in a second level cache is prevented when the cache entry is the only inclusive entry in the first level cache
EP0721157A1 (en) * 1994-12-12 1996-07-10 Advanced Micro Devices Inc. Microprocessor with selectable clock frequency
US5537580A (en) 1994-12-21 1996-07-16 Vlsi Technology, Inc. Integrated circuit fabrication using state machine extraction from behavioral hardware description language
US5603005A (en) * 1994-12-27 1997-02-11 Unisys Corporation Cache coherency scheme for XBAR storage structure with delayed invalidates until associated write request is executed
JP3598139B2 (en) 1994-12-28 2004-12-08 株式会社日立製作所 Data processing equipment
US5682491A (en) * 1994-12-29 1997-10-28 International Business Machines Corporation Selective processing and routing of results among processors controlled by decoding instructions using mask value derived from instruction tag and processor identifier
US6128720A (en) * 1994-12-29 2000-10-03 International Business Machines Corporation Distributed processing array with component processors performing customized interpretation of instructions
US5696791A (en) 1995-01-17 1997-12-09 Vtech Industries, Inc. Apparatus and method for decoding a sequence of digitally encoded data
US5493239A (en) * 1995-01-31 1996-02-20 Motorola, Inc. Circuit and method of configuring a field programmable gate array
US5532957A (en) 1995-01-31 1996-07-02 Texas Instruments Incorporated Field reconfigurable logic/memory array
US5659785A (en) 1995-02-10 1997-08-19 International Business Machines Corporation Array processor communication architecture with broadcast processor instructions
US5742180A (en) * 1995-02-10 1998-04-21 Massachusetts Institute Of Technology Dynamically programmable gate array with multiple contexts
US6052773A (en) 1995-02-10 2000-04-18 Massachusetts Institute Of Technology DPGA-coupled microprocessors
US5537057A (en) 1995-02-14 1996-07-16 Altera Corporation Programmable logic array device with grouped logic regions and three types of conductors
EP0809825A1 (en) 1995-02-14 1997-12-03 Vlsi Technology, Inc. Method and apparatus for reducing power consumption in digital electronic circuits
US5862403A (en) * 1995-02-17 1999-01-19 Kabushiki Kaisha Toshiba Continuous data server apparatus and data transfer scheme enabling multiple simultaneous data accesses
US5892961A (en) * 1995-02-17 1999-04-06 Xilinx, Inc. Field programmable gate array having programming instructions in the configuration bitstream
US5675743A (en) 1995-02-22 1997-10-07 Callisto Media Systems Inc. Multi-media server
US5570040A (en) 1995-03-22 1996-10-29 Altera Corporation Programmable logic array integrated circuit incorporating a first-in first-out memory
US5757207A (en) 1995-03-22 1998-05-26 Altera Corporation Programmable logic array integrated circuit incorporating a first-in first-out memory
US5600342A (en) * 1995-04-04 1997-02-04 Hughes Aircraft Company Diamond lattice void structure for wideband antenna systems
US5748979A (en) 1995-04-05 1998-05-05 Xilinx Inc Reprogrammable instruction set accelerator using a plurality of programmable execution units and an instruction page table
US5752035A (en) 1995-04-05 1998-05-12 Xilinx, Inc. Method for compiling and executing programs for reprogrammable instruction set accelerator
US5651137A (en) 1995-04-12 1997-07-22 Intel Corporation Scalable cache attributes for an input/output bus
JP3313007B2 (en) * 1995-04-14 2002-08-12 三菱電機システムエル・エス・アイ・デザイン株式会社 Micro computer
US5933642A (en) 1995-04-17 1999-08-03 Ricoh Corporation Compiling system and method for reconfigurable computing
US5794062A (en) 1995-04-17 1998-08-11 Ricoh Company Ltd. System and method for dynamically reconfigurable computing using a processing unit having changeable internal hardware organization
US6077315A (en) 1995-04-17 2000-06-20 Ricoh Company Ltd. Compiling system and method for partially reconfigurable computing
EP0823091A1 (en) * 1995-04-28 1998-02-11 Xilinx, Inc. Microprocessor with distributed registers accessible by programmable logic device
JP3329986B2 (en) 1995-04-28 2002-09-30 富士通株式会社 Multi-processor system
US5600597A (en) * 1995-05-02 1997-02-04 Xilinx, Inc. Register protection structure for FPGA
GB9508931D0 (en) 1995-05-02 1995-06-21 Xilinx Inc Programmable switch for FPGA input/output signals
US5701091A (en) * 1995-05-02 1997-12-23 Xilinx, Inc. Routing resources for hierarchical FPGA
US5541530A (en) 1995-05-17 1996-07-30 Altera Corporation Programmable logic array integrated circuits with blocks of logic regions grouped into super-blocks
US5649179A (en) 1995-05-19 1997-07-15 Motorola, Inc. Dynamic instruction allocation for a SIMD processor
US5721921A (en) 1995-05-25 1998-02-24 Cray Research, Inc. Barrier and eureka synchronization architecture for multiprocessors
US5821774A (en) * 1995-05-26 1998-10-13 Xilinx, Inc. Structure and method for arithmetic function implementation in an EPLD having high speed product term allocation structure
JPH08328941A (en) 1995-05-31 1996-12-13 Nec Corp Memory access control circuit
JP3677315B2 (en) * 1995-06-01 2005-07-27 シャープ株式会社 Data driven information processor
US5646546A (en) 1995-06-02 1997-07-08 International Business Machines Corporation Programmable logic cell having configurable gates and multiplexers
US5631578A (en) 1995-06-02 1997-05-20 International Business Machines Corporation Programmable array interconnect network
US5671432A (en) 1995-06-02 1997-09-23 International Business Machines Corporation Programmable array I/O-routing resource
US5652529A (en) 1995-06-02 1997-07-29 International Business Machines Corporation Programmable array clock/reset resource
US5646544A (en) 1995-06-05 1997-07-08 International Business Machines Corporation System and method for dynamically reconfiguring a programmable gate array
US5815715A (en) 1995-06-05 1998-09-29 Motorola, Inc. Method for designing a product having hardware and software components and product therefor
ZA9605340B (en) 1995-06-30 1997-01-27 Interdigital Tech Corp Code division multiple access (cdma) communication system
US5889982A (en) * 1995-07-01 1999-03-30 Intel Corporation Method and apparatus for generating event handler vectors based on both operating mode and event type
US5559450A (en) 1995-07-27 1996-09-24 Lucent Technologies Inc. Field programmable gate array with multi-port RAM
US5978583A (en) 1995-08-07 1999-11-02 International Business Machines Corp. Method for resource control in parallel environments using program organization and run-time support
US5649176A (en) 1995-08-10 1997-07-15 Virtual Machine Works, Inc. Transition analysis and circuit resynthesis method and device for digital circuit modeling
US5996083A (en) 1995-08-11 1999-11-30 Hewlett-Packard Company Microprocessor having software controllable power consumption
GB2304438A (en) 1995-08-17 1997-03-19 Kenneth Austin Re-configurable application specific device
US5778439A (en) 1995-08-18 1998-07-07 Xilinx, Inc. Programmable logic device with hierarchical confiquration and state storage
US5784313A (en) 1995-08-18 1998-07-21 Xilinx, Inc. Programmable logic device including configuration data or user data memory slices
US5646545A (en) 1995-08-18 1997-07-08 Xilinx, Inc. Time multiplexed programmable logic device
US5583450A (en) 1995-08-18 1996-12-10 Xilinx, Inc. Sequencer for a time multiplexed programmable logic device
US5737565A (en) 1995-08-24 1998-04-07 International Business Machines Corporation System and method for diallocating stream from a stream buffer
US5737516A (en) * 1995-08-30 1998-04-07 Motorola, Inc. Data processing system for performing a debug function and method therefor
US5734869A (en) * 1995-09-06 1998-03-31 Chen; Duan-Ping High speed logic circuit simulator
US6430309B1 (en) 1995-09-15 2002-08-06 Monogen, Inc. Specimen preview and inspection system
US5745734A (en) 1995-09-29 1998-04-28 International Business Machines Corporation Method and system for programming a gate array using a compressed configuration bit stream
US5652894A (en) 1995-09-29 1997-07-29 Intel Corporation Method and apparatus for providing power saving modes to a pipelined processor
JP3223769B2 (en) 1995-10-11 2001-10-29 三菱電機株式会社 Rotation sensor and its manufacturing method
US5754827A (en) 1995-10-13 1998-05-19 Mentor Graphics Corporation Method and apparatus for performing fully visible tracing of an emulation
US5642058A (en) * 1995-10-16 1997-06-24 Xilinx , Inc. Periphery input/output interconnect structure
US5815004A (en) * 1995-10-16 1998-09-29 Xilinx, Inc. Multi-buffered configurable logic block output lines in a field programmable gate array
US5608342A (en) * 1995-10-23 1997-03-04 Xilinx, Inc. Hierarchical programming of electrically configurable integrated circuits
US5656950A (en) * 1995-10-26 1997-08-12 Xilinx, Inc. Interconnect lines including tri-directional buffer circuits
US5675262A (en) * 1995-10-26 1997-10-07 Xilinx, Inc. Fast carry-out scheme in a field programmable gate array
US5633830A (en) 1995-11-08 1997-05-27 Altera Corporation Random access memory block circuitry for programmable logic array integrated circuit devices
US5943242A (en) 1995-11-17 1999-08-24 Pact Gmbh Dynamically reconfigurable data processing system
US5732209A (en) * 1995-11-29 1998-03-24 Exponential Technology, Inc. Self-testing multi-processor die with internal compare points
US5812844A (en) 1995-12-07 1998-09-22 Microsoft Corporation Method and system for scheduling the execution of threads using optional time-specific scheduling constraints
US5773994A (en) 1995-12-15 1998-06-30 Cypress Semiconductor Corp. Method and apparatus for implementing an internal tri-state bus within a programmable logic circuit
JPH09231788A (en) 1995-12-19 1997-09-05 Fujitsu Ltd Shift register and programmable logic circuit and programmable logic circuit system
CA2166369C (en) 1995-12-29 2004-10-19 Robert J. Blainey Method and system for determining inter-compilation unit alias information
US5715476A (en) 1995-12-29 1998-02-03 Intel Corporation Method and apparatus for controlling linear and toggle mode burst access sequences using toggle mode increment logic
US5804986A (en) 1995-12-29 1998-09-08 Cypress Semiconductor Corp. Memory in a programmable logic device
JP3247043B2 (en) 1996-01-12 2002-01-15 株式会社日立製作所 The information processing system and logic lsi performing fault detection in internal signal
JP3573755B2 (en) 1996-01-15 2004-10-06 シーメンス アクチエンゲゼルシヤフト Image processing processor
US5760602A (en) 1996-01-17 1998-06-02 Hewlett-Packard Company Time multiplexing a plurality of configuration settings of a programmable switch element in a FPGA
JP2795244B2 (en) 1996-01-17 1998-09-10 日本電気株式会社 Program debugging system
US6247036B1 (en) 1996-01-22 2001-06-12 Infinite Technology Corp. Processor with reconfigurable arithmetic data path
US5854918A (en) 1996-01-24 1998-12-29 Ricoh Company Ltd. Apparatus and method for self-timed algorithmic execution
US5898602A (en) 1996-01-25 1999-04-27 Xilinx, Inc. Carry chain circuit with flexible carry function for implementing arithmetic and logical functions
US5635851A (en) * 1996-02-02 1997-06-03 Xilinx, Inc. Read and writable data bus particularly for programmable logic devices
US5936424A (en) 1996-02-02 1999-08-10 Xilinx, Inc. High speed bus with tree structure for selecting bus driver
US5727229A (en) 1996-02-05 1998-03-10 Motorola, Inc. Method and apparatus for moving data in a parallel processor
US5754459A (en) 1996-02-08 1998-05-19 Xilinx, Inc. Multiplier circuit design for a programmable logic device
KR0165515B1 (en) * 1996-02-17 1999-01-15 김광호 Fifo method and apparatus of graphic data
GB9604496D0 (en) 1996-03-01 1996-05-01 Xilinx Inc Embedded memory for field programmable gate array
US6020758A (en) * 1996-03-11 2000-02-01 Altera Corporation Partially reconfigurable programmable logic device
US5841973A (en) 1996-03-13 1998-11-24 Cray Research, Inc. Messaging in distributed memory multiprocessing system having shell circuitry for atomic control of message storage queue's tail pointer structure in local memory
US6279077B1 (en) 1996-03-22 2001-08-21 Texas Instruments Incorporated Bus interface buffer control in a microprocessor
US6311265B1 (en) 1996-03-25 2001-10-30 Torrent Systems, Inc. Apparatuses and methods for programming parallel computers
US5956518A (en) 1996-04-11 1999-09-21 Massachusetts Institute Of Technology Intermediate-grain reconfigurable processing device
US5687325A (en) * 1996-04-19 1997-11-11 Chang; Web Application specific field programmable gate array
US6173434B1 (en) * 1996-04-22 2001-01-09 Brigham Young University Dynamically-configurable digital processor using method for relocating logic array modules
US5960200A (en) 1996-05-03 1999-09-28 I-Cube System to transition an enterprise to a distributed infrastructure
US5894565A (en) * 1996-05-20 1999-04-13 Atmel Corporation Field programmable gate array with distributed RAM and increased cell utilization
US5784636A (en) 1996-05-28 1998-07-21 National Semiconductor Corporation Reconfigurable computer architecture for use in signal processing applications
US5892370A (en) * 1996-06-21 1999-04-06 Quicklogic Corporation Clock network for field programmable gate array
EP0978051A1 (en) * 1996-06-21 2000-02-09 Mirage Technologies, Inc. Dynamically reconfigurable hardware system for real-time control of processes
US5893165A (en) 1996-07-01 1999-04-06 Sun Microsystems, Inc. System and method for parallel execution of memory transactions using multiple memory models, including SSO, TSO, PSO and RMO
US6785826B1 (en) 1996-07-17 2004-08-31 International Business Machines Corporation Self power audit and control circuitry for microprocessor functional units
US6526461B1 (en) 1996-07-18 2003-02-25 Altera Corporation Interconnect chip for programmable logic devices
US6023742A (en) * 1996-07-18 2000-02-08 University Of Washington Reconfigurable computing architecture for providing pipelined data paths
US6023564A (en) 1996-07-19 2000-02-08 Xilinx, Inc. Data processing system using a flash reconfigurable logic device as a dynamic execution unit for a sequence of instructions
US5774704A (en) 1996-07-29 1998-06-30 Silicon Graphics, Inc. Apparatus and method for dynamic central processing unit clock adjustment
US6058465A (en) 1996-08-19 2000-05-02 Nguyen; Le Trong Single-instruction-multiple-data processing in a multimedia signal processor
CN1129078C (en) 1996-08-19 2003-11-26 三星电子株式会社 Integrated digital signal processor
US5838165A (en) 1996-08-21 1998-11-17 Chatter; Mukesh High performance self modifying on-the-fly alterable logic FPGA, architecture and method
US5933023A (en) 1996-09-03 1999-08-03 Xilinx, Inc. FPGA architecture having RAM blocks with programmable word length and width and dedicated address and data lines
US6624658B2 (en) * 1999-02-04 2003-09-23 Advantage Logic, Inc. Method and apparatus for universal program controlled bus architecture
US5859544A (en) * 1996-09-05 1999-01-12 Altera Corporation Dynamic configurable elements for programmable logic devices
US6049866A (en) 1996-09-06 2000-04-11 Silicon Graphics, Inc. Method and system for an efficient user mode cache manipulation using a simulated instruction
JP3934710B2 (en) 1996-09-13 2007-06-20 株式会社ルネサステクノロジ Microprocessor
US5828858A (en) 1996-09-16 1998-10-27 Virginia Tech Intellectual Properties, Inc. Worm-hole run-time reconfigurable processor field programmable gate array (FPGA)
US6209020B1 (en) 1996-09-20 2001-03-27 Nortel Networks Limited Distributed pipeline memory architecture for a computer system with even and odd pids
US6178494B1 (en) * 1996-09-23 2001-01-23 Virtual Computer Corporation Modular, hybrid processor and method for producing a modular, hybrid processor
US5805477A (en) 1996-09-26 1998-09-08 Hewlett-Packard Company Arithmetic cell for field programmable devices
US5694602A (en) 1996-10-01 1997-12-02 The United States Of America As Represented By The Secretary Of The Air Force Weighted system and method for spatial allocation of a parallel load
SG125044A1 (en) 1996-10-14 2006-09-29 Mitsubishi Gas Chemical Co Oxygen absorption composition
US5832288A (en) 1996-10-18 1998-11-03 Samsung Electronics Co., Ltd. Element-select mechanism for a vector processor
US5901279A (en) 1996-10-18 1999-05-04 Hughes Electronics Corporation Connection of spares between multiple programmable devices
US6247147B1 (en) 1997-10-27 2001-06-12 Altera Corporation Enhanced embedded logic analyzer
US5892962A (en) * 1996-11-12 1999-04-06 Lucent Technologies Inc. FPGA-based processor
US5895487A (en) 1996-11-13 1999-04-20 International Business Machines Corporation Integrated processing and L2 DRAM cache
US5844422A (en) 1996-11-13 1998-12-01 Xilinx, Inc. State saving and restoration in reprogrammable FPGAs
US5860119A (en) 1996-11-25 1999-01-12 Vlsi Technology, Inc. Data-packet fifo buffer system with end-of-packet flags
US6005410A (en) 1996-12-05 1999-12-21 International Business Machines Corporation Interconnect structure between heterogeneous core regions in a programmable array
DE19651075A1 (en) 1996-12-09 1998-06-10 Pact Inf Tech Gmbh Unit for processing numerical and logical operations used in processors (CPU's), multiprocessor systems, Datenflußprozessoren (DFP's), digital signal processors (DSP's) or the like
US5913925A (en) 1996-12-16 1999-06-22 International Business Machines Corporation Method and system for constructing a program including out-of-order threads and processor and method for executing threads out-of-order
US6338106B1 (en) 1996-12-20 2002-01-08 Pact Gmbh I/O and memory bus system for DFPS and units with two or multi-dimensional programmable cell architectures
DE19654593A1 (en) 1996-12-20 1998-07-02 Pact Inf Tech Gmbh Reconfiguration method for programmable devices at runtime
DE19654595A1 (en) 1996-12-20 1998-07-02 Pact Inf Tech Gmbh I0- and memory bus system for DFPs and modules having a two- or multidimensional programmable cell structures
DE19654846A1 (en) 1996-12-27 1998-07-09 Pact Inf Tech Gmbh A method for automatic dynamic reloading of Datenflußprozessoren (DFP) and modules having a two- or multi-dimensional programmable cell structure (FPGAs, DPGAs, o. The like).
US6427156B1 (en) 1997-01-21 2002-07-30 Xilinx, Inc. Configurable logic block with AND gate for efficient multiplication in FPGAS
EP0858168A1 (en) 1997-01-29 1998-08-12 Hewlett-Packard Company Field programmable processor array
EP0858167A1 (en) 1997-01-29 1998-08-12 Hewlett-Packard Company Field programmable processor device
DE19704044A1 (en) * 1997-02-04 1998-08-13 Pact Inf Tech Gmbh Address generation with systems having programmable modules
US5865239A (en) * 1997-02-05 1999-02-02 Micropump, Inc. Method for making herringbone gears
US6055619A (en) 1997-02-07 2000-04-25 Cirrus Logic, Inc. Circuits, system, and methods for processing multiple data streams
US6542998B1 (en) 1997-02-08 2003-04-01 Pact Gmbh Method of self-synchronization of configurable elements of a programmable module
DE19704728A1 (en) 1997-02-08 1998-08-13 Pact Inf Tech Gmbh A method for self-synchronization of configurable elements of a programmable block
DE19704742A1 (en) 1997-02-11 1998-09-24 Pact Inf Tech Gmbh Internal bus system for DFPs, and modules having a two- or multi-dimensional programmable cell structure, to cope with large amounts of data with high connectivity expenses
JP3730740B2 (en) 1997-02-24 2006-01-05 株式会社日立製作所 Parallel job multiple scheduling method
US6150837A (en) 1997-02-28 2000-11-21 Actel Corporation Enhanced field programmable gate array
US5927423A (en) 1997-03-05 1999-07-27 Massachusetts Institute Of Technology Reconfigurable footprint mechanism for omnidirectional vehicles
US5884075A (en) * 1997-03-10 1999-03-16 Compaq Computer Corporation Conflict resolution using self-contained virtual devices
US5857097A (en) * 1997-03-10 1999-01-05 Digital Equipment Corporation Method for identifying reasons for dynamic stall cycles during the execution of a program
US6125408A (en) 1997-03-10 2000-09-26 Compaq Computer Corporation Resource type prioritization in generating a device configuration
GB2323188B (en) 1997-03-14 2002-02-06 Nokia Mobile Phones Ltd Enabling and disabling clocking signals to elements
US6246396B1 (en) 1997-04-30 2001-06-12 Canon Kabushiki Kaisha Cached color conversion method and apparatus
AUPO647997A0 (en) 1997-04-30 1997-05-22 Canon Information Systems Research Australia Pty Ltd Memory controller architecture
US20020152060A1 (en) 1998-08-31 2002-10-17 Tseng Ping-Sheng Inter-chip communication system
US6389379B1 (en) 1997-05-02 2002-05-14 Axis Systems, Inc. Converification system and method
US6321366B1 (en) 1997-05-02 2001-11-20 Axis Systems, Inc. Timing-insensitive glitch-free logic system and method
US6035371A (en) * 1997-05-28 2000-03-07 3Com Corporation Method and apparatus for addressing a static random access memory device based on signals for addressing a dynamic memory access device
US6421817B1 (en) 1997-05-29 2002-07-16 Xilinx, Inc. System and method of computation in a programmable logic device using virtual instructions
US6047115A (en) 1997-05-29 2000-04-04 Xilinx, Inc. Method for configuring FPGA memory planes for virtual hardware computation
US6385672B1 (en) 1997-05-30 2002-05-07 3Com Corporation System to optimize packet buffer utilization via selectively partitioned transmit and receive buffer portions
US6339840B1 (en) 1997-06-02 2002-01-15 Iowa State University Research Foundation, Inc. Apparatus and method for parallelizing legacy computer code
US6011407A (en) * 1997-06-13 2000-01-04 Xilinx, Inc. Field programmable gate array with dedicated computer bus interface and method for configuring both
US5996048A (en) 1997-06-20 1999-11-30 Sun Microsystems, Inc. Inclusion vector architecture for a level two cache
US6058266A (en) 1997-06-24 2000-05-02 International Business Machines Corporation Method of, system for, and computer program product for performing weighted loop fusion by an optimizing compiler
US5838988A (en) 1997-06-25 1998-11-17 Sun Microsystems, Inc. Computer product for precise architectural update in an out-of-order processor
US6240502B1 (en) 1997-06-25 2001-05-29 Sun Microsystems, Inc. Apparatus for dynamically reconfiguring a processor
US5970254A (en) 1997-06-27 1999-10-19 Cooke; Laurence H. Integrated processor and programmable data path chip for reconfigurable computing
US6282627B1 (en) 1998-06-29 2001-08-28 Chameleon Systems, Inc. Integrated processor and programmable data path chip for reconfigurable computing
US5966534A (en) 1997-06-27 1999-10-12 Cooke; Laurence H. Method for compiling high level programming languages into an integrated processor with reconfigurable logic
US6072348A (en) 1997-07-09 2000-06-06 Xilinx, Inc. Programmable power reduction in a clock-distribution circuit
US6437441B1 (en) 1997-07-10 2002-08-20 Kawasaki Microelectronics, Inc. Wiring structure of a semiconductor integrated circuit and a method of forming the wiring structure
US6038656A (en) * 1997-09-12 2000-03-14 California Institute Of Technology Pipelined completion for asynchronous communication
US6020760A (en) * 1997-07-16 2000-02-01 Altera Corporation I/O buffer circuit with pin multiplexing
EP0892352B1 (en) 1997-07-18 2005-04-13 Bull S.A. Computer system with a bus having a segmented structure
US6282701B1 (en) 1997-07-31 2001-08-28 Mutek Solutions, Ltd. System and method for monitoring and analyzing the execution of computer programs
US6026478A (en) * 1997-08-01 2000-02-15 Micron Technology, Inc. Split embedded DRAM processor
US6170051B1 (en) * 1997-08-01 2001-01-02 Micron Technology, Inc. Apparatus and method for program level parallelism in a VLIW processor
US6085317A (en) 1997-08-15 2000-07-04 Altera Corporation Reconfigurable computer architecture using programmable logic devices
US7152027B2 (en) 1998-02-17 2006-12-19 National Instruments Corporation Reconfigurable test system
US6078736A (en) 1997-08-28 2000-06-20 Xilinx, Inc. Method of designing FPGAs for dynamically reconfigurable computing
JP3636871B2 (en) 1997-09-16 2005-04-06 株式会社日立製作所 Parallel processor system
JP3612186B2 (en) 1997-09-19 2005-01-19 株式会社ルネサステクノロジ Data processing equipment
US6539415B1 (en) 1997-09-24 2003-03-25 Sony Corporation Method and apparatus for the allocation of audio/video tasks in a network system
US6148407A (en) 1997-09-30 2000-11-14 Intel Corporation Method and apparatus for producing computer platform fingerprints
US6034542A (en) 1997-10-14 2000-03-07 Xilinx, Inc. Bus structure for modularized chip with FPGA modules
US5966143A (en) 1997-10-14 1999-10-12 Motorola, Inc. Data allocation into multiple memories for concurrent access
US5870544A (en) * 1997-10-20 1999-02-09 International Business Machines Corporation Method and apparatus for creating a secure connection between a java applet and a web server
SG82587A1 (en) 1997-10-21 2001-08-21 Sony Corp Recording apparatus, recording method, playback apparatus, playback method, recording/playback apparatus, recording/playback method, presentation medium and recording medium
US6212544B1 (en) 1997-10-23 2001-04-03 International Business Machines Corporation Altering thread priorities in a multithreaded processor
US6076157A (en) 1997-10-23 2000-06-13 International Business Machines Corporation Method and apparatus to force a thread switch in a multithreaded processor
JP4128251B2 (en) 1997-10-23 2008-07-30 富士通株式会社 Wiring density predicting method and cell placement device
US6108737A (en) 1997-10-24 2000-08-22 Compaq Computer Corporation Method and apparatus for reducing latency of inter-reference ordering in a multiprocessor system
US6209065B1 (en) 1997-10-24 2001-03-27 Compaq Computer Corporation Mechanism for optimizing generation of commit-signals in a distributed shared-memory system
US5915123A (en) 1997-10-31 1999-06-22 Silicon Spice Method and apparatus for controlling configuration memory contexts of processing elements in a network of multiple context processing elements
US6108760A (en) 1997-10-31 2000-08-22 Silicon Spice Method and apparatus for position independent reconfiguration in a network of multiple context processing elements
US6122719A (en) 1997-10-31 2000-09-19 Silicon Spice Method and apparatus for retiming in a network of multiple context processing elements
US6127908A (en) 1997-11-17 2000-10-03 Massachusetts Institute Of Technology Microelectro-mechanical system actuator device and reconfigurable circuits utilizing same
JPH11147335A (en) * 1997-11-18 1999-06-02 Fuji Xerox Co Ltd Plot process apparatus
JP4197755B2 (en) * 1997-11-19 2008-12-17 富士通株式会社 Signal transmission system, the receiver circuit of the signal transmission system, and a semiconductor memory device the signal transmission system is applied
US6212650B1 (en) 1997-11-24 2001-04-03 Xilinx, Inc. Interactive dubug tool for programmable circuits
US6237059B1 (en) 1997-11-26 2001-05-22 Compaq Computer Corporation Method for estimating statistics of properties of memory system interactions among contexts in a computer system
US6075935A (en) 1997-12-01 2000-06-13 Improv Systems, Inc. Method of generating application specific integrated circuits using a programmable hardware architecture
US6091263A (en) 1997-12-12 2000-07-18 Xilinx, Inc. Rapidly reconfigurable FPGA having a multiple region architecture with reconfiguration caches useable as data RAM
DE69834942T2 (en) 1997-12-17 2007-06-06 Panasonic Europe Ltd., Uxbridge Means for multiplying
DE69827589T2 (en) * 1997-12-17 2005-11-03 Elixent Ltd. Configurable processing arrangement and method for use of this arrangement is to establish a central unit
DE69737750T2 (en) 1997-12-17 2008-03-06 Hewlett-Packard Development Co., L.P., Houston First and second processors used method
DE69841256D1 (en) 1997-12-17 2009-12-10 Panasonic Corp Masking command to command streams forwarded to a processor
DE19861088A1 (en) * 1997-12-22 2000-02-10 Pact Inf Tech Gmbh Repairing integrated circuits by replacing subassemblies with substitutes
US6260114B1 (en) 1997-12-30 2001-07-10 Mcmz Technology Innovations, Llc Computer cache memory windowing
US6172520B1 (en) * 1997-12-30 2001-01-09 Xilinx, Inc. FPGA system with user-programmable configuration ports and method for reconfiguring the FPGA
US6049222A (en) 1997-12-30 2000-04-11 Xilinx, Inc Configuring an FPGA using embedded memory
US6301706B1 (en) 1997-12-31 2001-10-09 Elbrus International Limited Compiler method and apparatus for elimination of redundant speculative computations from innermost loops
US6105106A (en) * 1997-12-31 2000-08-15 Micron Technology, Inc. Computer system, memory device and shift register including a balanced switching circuit with series connected transfer gates which are selectively clocked for fast switching times
US6216223B1 (en) 1998-01-12 2001-04-10 Billions Of Operations Per Second, Inc. Methods and apparatus to dynamically reconfigure the instruction pipeline of an indirect very long instruction word scalable processor
US6034538A (en) * 1998-01-21 2000-03-07 Lucent Technologies Inc. Virtual logic system for reconfigurable hardware
US6038646A (en) 1998-01-23 2000-03-14 Sun Microsystems, Inc. Method and apparatus for enforcing ordered execution of reads and writes across a memory interface
US6230307B1 (en) 1998-01-26 2001-05-08 Xilinx, Inc. System and method for programming the hardware of field programmable gate arrays (FPGAs) and related reconfiguration resources as if they were software by creating hardware objects
AU2562899A (en) 1998-01-26 1999-08-09 Chameleon Systems, Inc. Reconfigurable logic for table lookup
DE19803593A1 (en) 1998-01-30 1999-08-12 Daimler Chrysler Ag Switching device for a change-speed gearbox
US6034545A (en) * 1998-01-30 2000-03-07 Arm Limited Macrocell for data processing circuit
US6141734A (en) 1998-02-03 2000-10-31 Compaq Computer Corporation Method and apparatus for optimizing the performance of LDxL and STxC interlock instructions in the context of a write invalidate protocol
KR100572945B1 (en) 1998-02-04 2006-04-24 텍사스 인스트루먼츠 인코포레이티드 Digital signal processor with efficiently connectable hardware co-processor
US6086628A (en) 1998-02-17 2000-07-11 Lucent Technologies Inc. Power-related hardware-software co-synthesis of heterogeneous distributed embedded systems
US6198304B1 (en) * 1998-02-23 2001-03-06 Xilinx, Inc. Programmable logic device
US6096091A (en) 1998-02-24 2000-08-01 Advanced Micro Devices, Inc. Dynamically reconfigurable logic networks interconnected by fall-through FIFOs for flexible pipeline processing in a system-on-a-chip
DE19807872A1 (en) * 1998-02-25 1999-08-26 Pact Inf Tech Gmbh Method of managing configuration data in data flow processors
US6088800A (en) 1998-02-27 2000-07-11 Mosaid Technologies, Incorporated Encryption processor with shared memory interconnect
FR2776093A1 (en) 1998-03-10 1999-09-17 Philips Electronics Nv Circuit programmable processor with a reconfigurable memory, to realize a digital filter
US5990910A (en) 1998-03-24 1999-11-23 Ati Technologies, Inc. Method and apparatus for co-processing multi-formatted data
US6124868A (en) 1998-03-24 2000-09-26 Ati Technologies, Inc. Method and apparatus for multiple co-processor utilization of a ring buffer
US6154049A (en) 1998-03-27 2000-11-28 Xilinx, Inc. Multiplier fabric for use in field programmable gate arrays
US6298043B1 (en) 1998-03-28 2001-10-02 Nortel Networks Limited Communication system architecture and a connection verification mechanism therefor
US6374286B1 (en) 1998-04-06 2002-04-16 Rockwell Collins, Inc. Real time processor capable of concurrently running multiple independent JAVA machines
US6456628B1 (en) 1998-04-17 2002-09-24 Intelect Communications, Inc. DSP intercommunication network
US6084429A (en) 1998-04-24 2000-07-04 Xilinx, Inc. PLD having a window pane architecture with segmented and staggered interconnect wiring between logic block arrays
US6421808B1 (en) 1998-04-24 2002-07-16 Cadance Design Systems, Inc. Hardware design language for the design of integrated circuits
US6119219A (en) 1998-04-30 2000-09-12 International Business Machines Corporation System serialization with early release of individual processor
US6052524A (en) 1998-05-14 2000-04-18 Software Development Systems, Inc. System and method for simulation of integrated hardware and software components
US6173419B1 (en) 1998-05-14 2001-01-09 Advanced Technology Materials, Inc. Field programmable gate array (FPGA) emulator for debugging software
US6449283B1 (en) 1998-05-15 2002-09-10 Polytechnic University Methods and apparatus for providing a fast ring reservation arbitration
US5999990A (en) 1998-05-18 1999-12-07 Motorola, Inc. Communicator having reconfigurable resources
US6286090B1 (en) 1998-05-26 2001-09-04 Compaq Computer Corporation Mechanism for selectively imposing interference order between page-table fetches and corresponding data fetches
US6092174A (en) * 1998-06-01 2000-07-18 Context, Inc. Dynamically reconfigurable distributed integrated circuit processor and method
US6298396B1 (en) 1998-06-01 2001-10-02 Advanced Micro Devices, Inc. System for loading a current buffer desciptor register with a value different from current value to cause a previously read buffer descriptor to be read again
JP3123977B2 (en) * 1998-06-04 2001-01-15 技術研究組合新情報処理開発機構 Programmable function block
US6202182B1 (en) * 1998-06-30 2001-03-13 Lucent Technologies Inc. Method and apparatus for testing field programmable gate arrays
DE69803373T2 (en) 1998-07-06 2002-08-14 Hewlett Packard Co Wiring of cells in logical fields
WO2000003515A1 (en) 1998-07-08 2000-01-20 Broadcom Corporation Network switching architecture with fast filtering processor
KR100385370B1 (en) 1998-07-21 2003-05-27 시게이트 테크놀로지 엘엘씨 Improved memory system apparatus and method
US6421809B1 (en) 1998-07-24 2002-07-16 Interuniversitaire Micro-Elektronica Centrum (Imec Vzw) Method for determining a storage bandwidth optimized memory organization of an essentially digital device
US6321296B1 (en) 1998-08-04 2001-11-20 International Business Machines Corporation SDRAM L3 cache using speculative loads with command aborts to lower latency
DE19835189C2 (en) 1998-08-04 2001-02-08 Unicor Rohrsysteme Gmbh An apparatus for continuously producing seamless plastic pipes
US6137307A (en) 1998-08-04 2000-10-24 Xilinx, Inc. Structure and method for loading wide frames of data from a narrow input bus
US6289369B1 (en) 1998-08-25 2001-09-11 International Business Machines Corporation Affinity, locality, and load balancing in scheduling user program-level threads for execution by a computer system
US6205458B1 (en) 1998-09-21 2001-03-20 Rn2R, L.L.C. Adder and multiplier circuits employing logic gates having discrete, weighted inputs and methods of performing combinatorial operations therewith
US6216174B1 (en) 1998-09-29 2001-04-10 Silicon Graphics, Inc. System and method for fast barrier synchronization
US6421757B1 (en) 1998-09-30 2002-07-16 Conexant Systems, Inc Method and apparatus for controlling the programming and erasing of flash memory
JP3551353B2 (en) * 1998-10-02 2004-08-04 株式会社日立製作所 Data re-arrangement method
US6467009B1 (en) 1998-10-14 2002-10-15 Triscend Corporation Configurable processor system unit
US6215326B1 (en) 1998-11-18 2001-04-10 Altera Corporation Programmable logic device architecture with super-regions having logic regions and a memory region
DE69910826T2 (en) 1998-11-20 2004-06-17 Altera Corp., San Jose Computer system having a reconfigurable programmable logic device
US6977649B1 (en) 1998-11-23 2005-12-20 3Dlabs, Inc. Ltd 3D graphics rendering with selective read suspend
US6249756B1 (en) 1998-12-07 2001-06-19 Compaq Computer Corp. Hybrid flow control
US6826763B1 (en) 1998-12-11 2004-11-30 Microsoft Corporation Accelerating a distributed component architecture over a network using a direct marshaling
US6044030A (en) * 1998-12-21 2000-03-28 Philips Electronics North America Corporation FIFO unit with single pointer
US6434695B1 (en) 1998-12-23 2002-08-13 Apple Computer, Inc. Computer operating system using compressed ROM image in RAM
US6694434B1 (en) 1998-12-23 2004-02-17 Entrust Technologies Limited Method and apparatus for controlling program execution and program distribution
US6757847B1 (en) 1998-12-29 2004-06-29 International Business Machines Corporation Synchronization for system analysis
US6496902B1 (en) 1998-12-31 2002-12-17 Cray Inc. Vector and scalar data cache for a vector multiprocessor
US6218876B1 (en) * 1999-01-08 2001-04-17 Altera Corporation Phase-locked loop circuitry for programmable logic devices
JP3585800B2 (en) 1999-01-13 2004-11-04 株式会社東芝 The information processing apparatus
US6539438B1 (en) 1999-01-15 2003-03-25 Quickflex Inc. Reconfigurable computing system and method and apparatus employing same
US6490695B1 (en) 1999-01-22 2002-12-03 Sun Microsystems, Inc. Platform independent memory image analysis architecture for debugging a computer program
US6321298B1 (en) 1999-01-25 2001-11-20 International Business Machines Corporation Full cache coherency across multiple raid controllers
US6226717B1 (en) 1999-02-04 2001-05-01 Compaq Computer Corporation System and method for exclusive access to shared storage
US6243808B1 (en) 1999-03-08 2001-06-05 Chameleon Systems, Inc. Digital data bit order conversion using universal switch matrix comprising rows of bit swapping selector groups
US6191614B1 (en) 1999-04-05 2001-02-20 Xilinx, Inc. FPGA configuration circuit including bus-based CRC register
US6512804B1 (en) 1999-04-07 2003-01-28 Applied Micro Circuits Corporation Apparatus and method for multiple serial data synchronization using channel-lock FIFO buffers optimized for jitter
GB9909196D0 (en) 1999-04-21 1999-06-16 Texas Instruments Ltd Transfer controller with hub and ports architecture
US6286134B1 (en) 1999-04-23 2001-09-04 Sun Microsystems, Inc. Instruction selection in a multi-platform environment
US6381624B1 (en) 1999-04-29 2002-04-30 Hewlett-Packard Company Faster multiply/accumulator
US6298472B1 (en) 1999-05-07 2001-10-02 Chameleon Systems, Inc. Behavioral silicon construct architecture and mapping
US6748440B1 (en) 1999-05-12 2004-06-08 Microsoft Corporation Flow of streaming data through multiple processing modules
US7007096B1 (en) * 1999-05-12 2006-02-28 Microsoft Corporation Efficient splitting and mixing of streaming-data frames for processing through multiple processing modules
US6211697B1 (en) * 1999-05-25 2001-04-03 Actel Integrated circuit that includes a field-programmable gate array and a hard gate array having the same underlying structure
CN1378665A (en) * 1999-06-10 2002-11-06 Pact信息技术有限公司 Programming concept
DE19926538A1 (en) 1999-06-10 2000-12-14 Pact Inf Tech Gmbh Hardware with decoupled configuration register partitions data flow or control flow graphs into time-separated sub-graphs and forms and implements them sequentially on a component
EP1061439A1 (en) 1999-06-15 2000-12-20 Hewlett-Packard Company Memory and instructions in computer architecture containing processor and coprocessor
US6757892B1 (en) 1999-06-24 2004-06-29 Sarnoff Corporation Method for determining an optimal partitioning of data among several memories
US6347346B1 (en) * 1999-06-30 2002-02-12 Chameleon Systems, Inc. Local memory unit system with global access for use on reconfigurable chips
JP3420121B2 (en) 1999-06-30 2003-06-23 Necエレクトロニクス株式会社 Nonvolatile semiconductor memory device
GB2352548B (en) * 1999-07-26 2001-06-06 Sun Microsystems Inc Method and apparatus for executing standard functions in a computer system
US6745317B1 (en) 1999-07-30 2004-06-01 Broadcom Corporation Three level direct communication connections between neighboring multiple context processing elements
US6370596B1 (en) 1999-08-03 2002-04-09 Chameleon Systems, Inc. Logic flag registers for monitoring processing system events
US6341318B1 (en) * 1999-08-10 2002-01-22 Chameleon Systems, Inc. DMA data streaming
US6204687B1 (en) * 1999-08-13 2001-03-20 Xilinx, Inc. Method and structure for configuring FPGAS
US6438747B1 (en) 1999-08-20 2002-08-20 Hewlett-Packard Company Programmatic iteration scheduling for parallel processors
US6507947B1 (en) * 1999-08-20 2003-01-14 Hewlett-Packard Company Programmatic synthesis of processor element arrays
US6606704B1 (en) 1999-08-31 2003-08-12 Intel Corporation Parallel multithreaded processor with plural microengines executing multiple threads each microengine having loadable microcode
US6457100B1 (en) 1999-09-15 2002-09-24 International Business Machines Corporation Scaleable shared-memory multi-processor computer system having repetitive chip structure with efficient busing and coherence controls
US6288566B1 (en) 1999-09-23 2001-09-11 Chameleon Systems, Inc. Configuration state memory for functional blocks on a reconfigurable chip
US6349346B1 (en) * 1999-09-23 2002-02-19 Chameleon Systems, Inc. Control fabric unit including associated configuration memory and PSOP state machine adapted to provide configuration address to reconfigurable functional unit
US6311200B1 (en) 1999-09-23 2001-10-30 Chameleon Systems, Inc. Reconfigurable program sum of products generator
US6631487B1 (en) 1999-09-27 2003-10-07 Lattice Semiconductor Corp. On-line testing of field programmable gate array resources
DE19946752A1 (en) 1999-09-29 2001-04-12 Infineon Technologies Ag Reconfigurable gate array
US6412043B1 (en) 1999-10-01 2002-06-25 Hitachi, Ltd. Microprocessor having improved memory management unit and cache memory
US6598128B1 (en) 1999-10-01 2003-07-22 Hitachi, Ltd. Microprocessor having improved memory management unit and cache memory
US6526430B1 (en) 1999-10-04 2003-02-25 Texas Instruments Incorporated Reconfigurable SIMD coprocessor architecture for sum of absolute differences and symmetric filtering (scalable MAC engine for image processing)
US6665758B1 (en) 1999-10-04 2003-12-16 Ncr Corporation Software sanity monitor
US6434642B1 (en) 1999-10-07 2002-08-13 Xilinx, Inc. FIFO memory system and method with improved determination of full and empty conditions and amount of data stored
EP1230591B1 (en) 1999-11-18 2007-01-03 Sun Microsystems, Inc. Decompression bit processing with a general purpose alignment tool
JP2001167066A (en) * 1999-12-08 2001-06-22 Nec Corp Inter-processor communication method and multiprocessor system
US6501999B1 (en) 1999-12-22 2002-12-31 Intel Corporation Multi-processor mobile computer system having one processor integrated with a chipset
US6625654B1 (en) * 1999-12-28 2003-09-23 Intel Corporation Thread signaling in multi-threaded network processor
US6633181B1 (en) * 1999-12-30 2003-10-14 Stretch, Inc. Multi-scale programmable array
EP1115204B1 (en) 2000-01-07 2009-04-22 Nippon Telegraph and Telephone Corporation Function reconfigurable semiconductor device and integrated circuit configuring the semiconductor device
JP2001202236A (en) 2000-01-20 2001-07-27 Fuji Xerox Co Ltd Data processing method for programmable logic circuit device and the same device and information processing system and circuit reconstituting method for the same device
US20020031166A1 (en) 2000-01-28 2002-03-14 Ravi Subramanian Wireless spread spectrum communication platform using dynamically reconfigurable logic
US6925641B1 (en) 2000-02-04 2005-08-02 Xronix Communications, Inc. Real time DSP load management system
US6496971B1 (en) 2000-02-07 2002-12-17 Xilinx, Inc. Supporting multiple FPGA configuration modes using dedicated on-chip processor
US6487709B1 (en) 2000-02-09 2002-11-26 Xilinx, Inc. Run-time routing for programmable logic devices
US7036106B1 (en) 2000-02-17 2006-04-25 Tensilica, Inc. Automated processor generation system for designing a configurable processor and method for the same
US6519674B1 (en) * 2000-02-18 2003-02-11 Chameleon Systems, Inc. Configuration bits layout
WO2001063434A1 (en) 2000-02-24 2001-08-30 Bops, Incorporated Methods and apparatus for dual-use coprocessing/debug interface
JP3674515B2 (en) 2000-02-25 2005-07-20 日本電気株式会社 Array-type processor
US6434672B1 (en) 2000-02-29 2002-08-13 Hewlett-Packard Company Methods and apparatus for improving system performance with a shared cache memory
US6539477B1 (en) * 2000-03-03 2003-03-25 Chameleon Systems, Inc. System and method for control synthesis using a reachable states look-up table
KR100841411B1 (en) 2000-03-14 2008-06-25 소니 가부시끼 가이샤 Transmission apparatus, reception apparatus, transmission method, reception method and recording medium
US6657457B1 (en) 2000-03-15 2003-12-02 Intel Corporation Data transfer on reconfigurable chip
US6871341B1 (en) 2000-03-24 2005-03-22 Intel Corporation Adaptive scheduling of function cells in dynamic reconfigurable logic
US6665865B1 (en) 2000-04-27 2003-12-16 Microsoft Corporation Equivalence class based synchronization optimization
US6624819B1 (en) 2000-05-01 2003-09-23 Broadcom Corporation Method and system for providing a flexible and efficient processor for use in a graphics processing system
US6845445B2 (en) 2000-05-12 2005-01-18 Pts Corporation Methods and apparatus for power control in a scalable array of processor elements
US6362650B1 (en) * 2000-05-18 2002-03-26 Xilinx, Inc. Method and apparatus for incorporating a multiplier into an FPGA
US6373779B1 (en) 2000-05-19 2002-04-16 Xilinx, Inc. Block RAM having multiple configurable write modes for use in a field programmable gate array
US6725334B2 (en) 2000-06-09 2004-04-20 Hewlett-Packard Development Company, L.P. Method and system for exclusive two-level caching in a chip-multiprocessor
US6675265B2 (en) 2000-06-10 2004-01-06 Hewlett-Packard Development Company, L.P. Multiprocessor cache coherence system and method in which processor nodes and input/output nodes are equal participants
US7340596B1 (en) 2000-06-12 2008-03-04 Altera Corporation Embedded processor with watchdog timer for programmable logic
US9436631B2 (en) 2001-03-05 2016-09-06 Pact Xpp Technologies Ag Chip including memory element storing higher level memory data on a page by page basis
US9037807B2 (en) 2001-03-05 2015-05-19 Pact Xpp Technologies Ag Processor arrangement on a chip including data processing, memory, and interface elements
DE10028397A1 (en) 2000-06-13 2001-12-20 Pact Inf Tech Gmbh Registration method in operating a reconfigurable unit, involves evaluating acknowledgement signals of configurable cells with time offset to configuration
DE50115584D1 (en) * 2000-06-13 2010-09-16 Krass Maren Pipeline ct protocols and communication
US7581076B2 (en) 2001-03-05 2009-08-25 Pact Xpp Technologies Ag Methods and devices for treating and/or processing data
US6285624B1 (en) 2000-07-08 2001-09-04 Han-Ping Chen Multilevel memory access method
US6799265B1 (en) 2000-07-11 2004-09-28 Intel Corporation Dependency checking for reconfigurable logic
US20030033450A1 (en) 2000-07-20 2003-02-13 John Appleby-Alis System, method, and article of manufacture for remote updating of hardware
DE10036627A1 (en) 2000-07-24 2002-02-14 Pact Inf Tech Gmbh Integrated cell matrix circuit has at least 2 different types of cells with interconnection terminals positioned to allow mixing of different cell types within matrix circuit
JP2002041489A (en) 2000-07-25 2002-02-08 Mitsubishi Electric Corp Synchronizing signal generation circuit, processor system using the same and synchronizing signal generating method
US7164422B1 (en) * 2000-07-28 2007-01-16 Ab Initio Software Corporation Parameterized graphs with conditional components
US6538468B1 (en) * 2000-07-31 2003-03-25 Cypress Semiconductor Corporation Method and apparatus for multiple boot-up functionalities for a programmable logic device (PLD)
US7924837B1 (en) 2000-07-31 2011-04-12 Avaya Communication Israel Ltd. IP multicast in VLAN environment
US6542844B1 (en) 2000-08-02 2003-04-01 International Business Machines Corporation Method and apparatus for tracing hardware states using dynamically reconfigurable test circuits
US6754805B1 (en) 2000-08-07 2004-06-22 Transwitch Corporation Method and apparatus for configurable multi-cell digital signal processing employing global parallel configuration
AU8116401A (en) 2000-08-07 2002-02-18 Altera Corp Inter-device communication interface
EP1182559B1 (en) 2000-08-21 2009-01-21 Texas Instruments Incorporated Improved microprocessor
US7249351B1 (en) 2000-08-30 2007-07-24 Broadcom Corporation System and method for preparing software for execution in a dynamically configurable hardware environment
US6829697B1 (en) 2000-09-06 2004-12-07 International Business Machines Corporation Multiple logical interfaces to a shared coprocessor resource
US6538470B1 (en) 2000-09-18 2003-03-25 Altera Corporation Devices and methods with programmable logic and digital signal processing regions
US7346644B1 (en) 2000-09-18 2008-03-18 Altera Corporation Devices and methods with programmable logic and digital signal processing regions
US6518787B1 (en) * 2000-09-21 2003-02-11 Triscend Corporation Input/output architecture for efficient configuration of programmable input/output cells
GB2367647B (en) 2000-10-03 2002-11-20 Sun Microsystems Inc Resource access control for a processor
US7595659B2 (en) * 2000-10-09 2009-09-29 Pact Xpp Technologies Ag Logic cell array and bus system
US20040015899A1 (en) * 2000-10-06 2004-01-22 Frank May Method for processing data
US8686475B2 (en) 2001-09-19 2014-04-01 Pact Xpp Technologies Ag Reconfigurable elements
US6525678B1 (en) * 2000-10-06 2003-02-25 Altera Corporation Configuring a programmable logic device
US10031733B2 (en) 2001-06-20 2018-07-24 Scientia Sol Mentis Ag Method for processing data
US7444531B2 (en) 2001-03-05 2008-10-28 Pact Xpp Technologies Ag Methods and devices for treating and processing data
DE10129237A1 (en) 2000-10-09 2002-04-18 Pact Inf Tech Gmbh Integrated cell matrix circuit has at least 2 different types of cells with interconnection terminals positioned to allow mixing of different cell types within matrix circuit
EP1402382B1 (en) 2001-06-20 2010-08-18 Richter, Thomas Data processing method
US20020045952A1 (en) 2000-10-12 2002-04-18 Blemel Kenneth G. High performance hybrid micro-computer
JP2002123563A (en) 2000-10-13 2002-04-26 Nec Corp Compiling method, composing device, and recording medium
US6398383B1 (en) 2000-10-30 2002-06-04 Yu-Hwei Huang Flashlight carriable on one's person
JP3636986B2 (en) 2000-12-06 2005-04-06 松下電器産業株式会社 The semiconductor integrated circuit
GB2370380B (en) 2000-12-19 2003-12-31 Picochip Designs Ltd Processor architecture
EP1346280A1 (en) 2000-12-20 2003-09-24 Philips Electronics N.V. Data processing device with a configurable functional unit
US6571322B2 (en) 2000-12-28 2003-05-27 International Business Machines Corporation Multiprocessor computer system with sectored cache line mechanism for cache intervention
US6483343B1 (en) 2000-12-29 2002-11-19 Quicklogic Corporation Configurable computational unit embedded in a programmable device
US6426649B1 (en) 2000-12-29 2002-07-30 Quicklogic Corporation Architecture for field programmable gate array
US6522167B1 (en) * 2001-01-09 2003-02-18 Xilinx, Inc. User configurable on-chip memory system
US6392912B1 (en) 2001-01-10 2002-05-21 Chameleon Systems, Inc. Loading data plane on reconfigurable chip
US7020673B2 (en) * 2001-01-19 2006-03-28 Sony Corporation Reconfigurable arithmetic device and arithmetic system including that arithmetic device and address generation device and interleave device applicable to arithmetic system
US20020099759A1 (en) 2001-01-24 2002-07-25 Gootherts Paul David Load balancer with starvation avoidance
US6633242B2 (en) 2001-02-08 2003-10-14 Sun Microsystems, Inc. Entropy coding using adaptable prefix codes
US6847370B2 (en) * 2001-02-20 2005-01-25 3D Labs, Inc., Ltd. Planar byte memory organization with linear access
GB2373595B (en) 2001-03-15 2005-09-07 Italtel Spa A system of distributed microprocessor interfaces toward macro-cell based designs implemented as ASIC or FPGA bread boarding and relative common bus protocol
US6836839B2 (en) 2001-03-22 2004-12-28 Quicksilver Technology, Inc. Adaptive integrated circuitry with heterogeneous and reconfigurable matrices of diverse and adaptive computational units having fixed, application specific computational elements
US6792588B2 (en) 2001-04-02 2004-09-14 Intel Corporation Faster scalable floorplan which enables easier data control flow
US20020143505A1 (en) 2001-04-02 2002-10-03 Doron Drusinsky Implementing a finite state machine using concurrent finite state machines with delayed communications and no shared control signals
US6836849B2 (en) 2001-04-05 2004-12-28 International Business Machines Corporation Method and apparatus for controlling power and performance in a multiprocessing system according to customer level operational requirements
US20030086300A1 (en) 2001-04-06 2003-05-08 Gareth Noyes FPGA coprocessing system
US6836842B1 (en) 2001-04-24 2004-12-28 Xilinx, Inc. Method of partial reconfiguration of a PLD in which only updated portions of configuration data are selected for reconfiguring the PLD
US7155602B2 (en) 2001-04-30 2006-12-26 Src Computers, Inc. Interface for integrating reconfigurable processors into a general purpose computing system
US6999984B2 (en) 2001-05-02 2006-02-14 Intel Corporation Modification to reconfigurable functional unit in a reconfigurable chip to perform linear feedback shift register function
US6802026B1 (en) 2001-05-15 2004-10-05 Xilinx, Inc. Parameterizable and reconfigurable debugger core generators
US7100026B2 (en) 2001-05-30 2006-08-29 The Massachusetts Institute Of Technology System and method for performing efficient conditional vector operations for data parallel architectures involving both input and conditional vector values
US6976239B1 (en) * 2001-06-12 2005-12-13 Altera Corporation Methods and apparatus for implementing parameterizable processors and peripherals
JP3580785B2 (en) * 2001-06-29 2004-10-27 株式会社半導体理工学研究センター Lookup tables, programmable logic device comprising a look-up table, and, configuring the look-up table
US7043416B1 (en) 2001-07-27 2006-05-09 Lsi Logic Corporation System and method for state restoration in a diagnostic module for a high-speed microprocessor
US7210129B2 (en) * 2001-08-16 2007-04-24 Pact Xpp Technologies Ag Method for translating programs for reconfigurable architectures
US8914590B2 (en) 2002-08-07 2014-12-16 Pact Xpp Technologies Ag Data processing method and device
AU2003286131A1 (en) 2002-08-07 2004-03-19 Pact Xpp Technologies Ag Method and device for processing data
US7036114B2 (en) 2001-08-17 2006-04-25 Sun Microsystems, Inc. Method and apparatus for cycle-based computation
US6868476B2 (en) 2001-08-27 2005-03-15 Intel Corporation Software controlled content addressable memory in a general purpose execution datapath
US6874108B1 (en) 2001-08-27 2005-03-29 Agere Systems Inc. Fault tolerant operation of reconfigurable devices utilizing an adjustable system clock
US7216204B2 (en) 2001-08-27 2007-05-08 Intel Corporation Mechanism for providing early coherency detection to enable high performance memory updates in a latency sensitive multithreaded environment
US7266725B2 (en) * 2001-09-03 2007-09-04 Pact Xpp Technologies Ag Method for debugging reconfigurable architectures
US7472230B2 (en) 2001-09-14 2008-12-30 Hewlett-Packard Development Company, L.P. Preemptive write back controller
US20030056091A1 (en) * 2001-09-14 2003-03-20 Greenberg Craig B. Method of scheduling in a reconfigurable hardware architecture with multiple hardware configurations
US20030055861A1 (en) * 2001-09-18 2003-03-20 Lai Gary N. Multipler unit in reconfigurable chip
US20030052711A1 (en) * 2001-09-19 2003-03-20 Taylor Bradley L. Despreader/correlator unit for use in reconfigurable chip
US6854073B2 (en) 2001-09-25 2005-02-08 International Business Machines Corporation Debugger program time monitor
US6798239B2 (en) 2001-09-28 2004-09-28 Xilinx, Inc. Programmable gate array having interconnecting logic to support embedded fixed logic circuitry
US6625631B2 (en) 2001-09-28 2003-09-23 Intel Corporation Component reduction in montgomery multiplier processing element
US7000161B1 (en) * 2001-10-15 2006-02-14 Altera Corporation Reconfigurable programmable logic system with configuration recovery mode
US20060264508A1 (en) 2001-10-16 2006-11-23 Stone Richard A Modulation of ocular growth and myopia by gaba drugs
AU2002357739A1 (en) 2001-11-16 2003-06-10 Morpho Technologies Viterbi convolutional coding method and apparatus
US6886092B1 (en) 2001-11-19 2005-04-26 Xilinx, Inc. Custom code processing in PGA by providing instructions from fixed logic processor portion to programmable dedicated processor portion
US8412915B2 (en) * 2001-11-30 2013-04-02 Altera Corporation Apparatus, system and method for configuration of adaptive integrated circuitry having heterogeneous computational elements
US7188234B2 (en) 2001-12-12 2007-03-06 Intel Corporation Run-ahead program execution with value prediction
US6668237B1 (en) 2002-01-17 2003-12-23 Xilinx, Inc. Run-time reconfigurable testing of programmable logic devices
US20030154349A1 (en) 2002-01-24 2003-08-14 Berg Stefan G. Program-directed cache prefetching for media processors
DE20221985U1 (en) 2002-02-01 2010-03-04 Tridonicatco Gmbh & Co. Kg Electronic ballast for gas discharge lamp
US6476634B1 (en) * 2002-02-01 2002-11-05 Xilinx, Inc. ALU implementation in single PLD logic cell
US6961924B2 (en) 2002-05-21 2005-11-01 International Business Machines Corporation Displaying variable usage while debugging
US20030226056A1 (en) 2002-05-28 2003-12-04 Michael Yip Method and system for a process manager
US7415594B2 (en) * 2002-06-26 2008-08-19 Coherent Logix, Incorporated Processing system with interspersed stall propagating processors and communication elements
US20130111188A9 (en) 2003-07-24 2013-05-02 Martin Vorbach Low latency massive parallel data processing device
US6865662B2 (en) 2002-08-08 2005-03-08 Faraday Technology Corp. Controlling VLIW instruction operations supply to functional units using switches based on condition head field
US6908227B2 (en) 2002-08-23 2005-06-21 Intel Corporation Apparatus for thermal management of multiple core microprocessors
US6976131B2 (en) 2002-08-23 2005-12-13 Intel Corporation Method and apparatus for shared cache coherency for a chip multiprocessor or multiprocessor system
EP1537486A1 (en) 2002-09-06 2005-06-08 PACT XPP Technologies AG Reconfigurable sequencer structure
US7167954B2 (en) 2002-09-09 2007-01-23 Broadcom Corporation System and method for caching
US6803787B1 (en) * 2002-09-25 2004-10-12 Lattice Semiconductor Corp. State machine in a programmable logic device
US6802206B2 (en) 2002-10-11 2004-10-12 American Axle & Manufacturing, Inc. Torsional actuation NVH test method
US7571303B2 (en) 2002-10-16 2009-08-04 Akya (Holdings) Limited Reconfigurable integrated circuit
US7299458B2 (en) 2002-10-31 2007-11-20 Src Computers, Inc. System and method for converting control flow graph representations to control-dataflow graph representations
US7155708B2 (en) 2002-10-31 2006-12-26 Src Computers, Inc. Debugging and performance profiling using control-dataflow graph representations with reconfigurable hardware emulation
US6816814B2 (en) 2002-11-12 2004-11-09 Sonics, Inc. Method and apparatus for decomposing and verifying configurable hardware
US7383421B2 (en) 2002-12-05 2008-06-03 Brightscale, Inc. Cellular engine for a data processing system
US7873811B1 (en) * 2003-03-10 2011-01-18 The United States Of America As Represented By The United States Department Of Energy Polymorphous computing fabric
US20070083730A1 (en) 2003-06-17 2007-04-12 Martin Vorbach Data processing device and method
US7127560B2 (en) 2003-10-14 2006-10-24 International Business Machines Corporation Method of dynamically controlling cache size
US7412581B2 (en) * 2003-10-28 2008-08-12 Renesas Technology America, Inc. Processor for virtual machines and method therefor
TW200532454A (en) 2003-11-12 2005-10-01 Gatechange Technologies Inc System and method for message passing fabric in a modular processor architecture
US7840627B2 (en) 2003-12-29 2010-11-23 Xilinx, Inc. Digital signal processing circuit having input register blocks
US7870182B2 (en) 2003-12-29 2011-01-11 Xilinx Inc. Digital signal processing circuit having an adder circuit with carry-outs
US7472155B2 (en) 2003-12-29 2008-12-30 Xilinx, Inc. Programmable logic device with cascading DSP slices
US7567997B2 (en) 2003-12-29 2009-07-28 Xilinx, Inc. Applications of cascading DSP slices
US8495122B2 (en) 2003-12-29 2013-07-23 Xilinx, Inc. Programmable device with dynamic DSP architecture
US7038952B1 (en) 2004-05-04 2006-05-02 Xilinx, Inc. Block RAM with embedded FIFO buffer
US7290238B2 (en) 2004-05-12 2007-10-30 International Business Machines Corporation Method, system and program product for building an automated datapath system generating tool
JP4396446B2 (en) 2004-08-20 2010-01-13 ソニー株式会社 An information processing apparatus and method, and program
US7299339B2 (en) 2004-08-30 2007-11-20 The Boeing Company Super-reconfigurable fabric architecture (SURFA): a multi-FPGA parallel processing architecture for COTS hybrid computing framework
DE102005021749A1 (en) 2005-05-11 2006-11-16 Fachhochschule Dortmund Program-controlled information processing method, involves initiating information processing operations in selected resources, and disconnecting connections that are no longer needed between selected resources
US7933838B2 (en) 2005-05-17 2011-04-26 Zhishen Ye Apparatus for secure digital content distribution and methods therefor
US20070043965A1 (en) 2005-08-22 2007-02-22 Intel Corporation Dynamic memory sizing for power reduction
US7455450B2 (en) 2005-10-07 2008-11-25 Advanced Micro Devices, Inc. Method and apparatus for temperature sensing in integrated circuits
US7759968B1 (en) 2006-09-27 2010-07-20 Xilinx, Inc. Method of and system for verifying configuration data
US7822897B2 (en) * 2007-09-22 2010-10-26 Hirak Mitra System and methods for connecting multiple functional components
US7971051B2 (en) 2007-09-27 2011-06-28 Fujitsu Limited FPGA configuration protection and control using hardware watchdog timer
US20090193384A1 (en) 2008-01-25 2009-07-30 Mihai Sima Shift-enabled reconfigurable device
JP2010277303A (en) 2009-05-28 2010-12-09 Renesas Electronics Corp Semiconductor device and failure detection method
US8650514B2 (en) * 2010-06-23 2014-02-11 Tabula, Inc. Rescaling

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
See references of WO2004038599A1 *

Also Published As

Publication number Publication date
US7928763B2 (en) 2011-04-19
AU2003289844A1 (en) 2004-05-13
US8803552B2 (en) 2014-08-12
US20110006805A1 (en) 2011-01-13
US9817790B2 (en) 2017-11-14
WO2004038599A1 (en) 2004-05-06
US20100039139A1 (en) 2010-02-18
US20180067896A1 (en) 2018-03-08
US20140351482A1 (en) 2014-11-27
US7602214B2 (en) 2009-10-13
US20110148460A1 (en) 2011-06-23
JP4388895B2 (en) 2009-12-24
JP2006501782A (en) 2006-01-12
US7782087B2 (en) 2010-08-24
US10296488B2 (en) 2019-05-21
US20130024657A1 (en) 2013-01-24
US20080191737A1 (en) 2008-08-14
US8310274B2 (en) 2012-11-13
US9274984B2 (en) 2016-03-01
US20160170925A1 (en) 2016-06-16
US20060192586A1 (en) 2006-08-31
US7394284B2 (en) 2008-07-01

Similar Documents

Publication Publication Date Title
US6076152A (en) Multiprocessor computer architecture incorporating a plurality of memory algorithm processors in the memory subsystem
US5903771A (en) Scalable multi-processor architecture for SIMD and MIMD operations
US6167502A (en) Method and apparatus for manifold array processing
US7151925B2 (en) Software defined radio (SDR) architecture for wireless digital communication systems
US20160112048A1 (en) Psoc architecture
US4943909A (en) Computational origami
JP4391935B2 (en) Processing system comprising a communication element with the processor are scattered
US6175247B1 (en) Context switchable field programmable gate array with public-private addressable sharing of intermediate data
US8099618B2 (en) Methods and devices for treating and processing data
US6205533B1 (en) Mechanism for efficient data access and communication in parallel computations on an emulated spatial lattice
US7353516B2 (en) Data flow control for adaptive integrated circuitry
Beetem et al. The GF 11 supercomputer
US6732354B2 (en) Method, system and software for programming reconfigurable hardware
US8510534B2 (en) Scalar/vector processor that includes a functional unit with a vector section and a scalar section
US20050044344A1 (en) System, method and software for static and dynamic programming and configuration of an adaptive computing architecture
EP0463721A2 (en) Digital signal processing device
US20080222339A1 (en) Processor architecture with switch matrices for transferring data along buses
US20090287859A1 (en) DMA Engine
US6434687B1 (en) System and method for accelerating web site access and processing utilizing a computer system incorporating reconfigurable processors operating under a single operating system image
US6622233B1 (en) Hypercomputer
US7895416B2 (en) Reconfigurable integrated circuit
US5828858A (en) Worm-hole run-time reconfigurable processor field programmable gate array (FPGA)
US7595659B2 (en) Logic cell array and bus system
JP4128956B2 (en) For dual in-line memory module format in a series of multi-adaptive processor was adopted cluster computer switch / network adapter port
US7500083B2 (en) Accelerated processing with scheduling to configured coprocessor for molecular data type by service and control coprocessor upon analysis of software code

Legal Events

Date Code Title Description
17P Request for examination filed

Effective date: 20050324

AK Designated contracting states:

Kind code of ref document: A1


AX Request for extension of the european patent to

Extension state: AL LT LV MK

DAX Request for extension of the european patent (to any country) deleted
RIN1 Inventor (correction)

Inventor name: VORBACH, MARTIN

17Q First examination report

Effective date: 20070718

RAP1 Transfer of rights of an ep published application


Owner name: KRASS, MAREN

RAP1 Transfer of rights of an ep published application


111L Licences


Name of requester: XILINX, INC., US

Effective date: 20141010

INTG Announcement of intention to grant

Effective date: 20160330

18D Deemed to be withdrawn

Effective date: 20160810