AU2002338729A1 - Router - Google Patents

Router

Info

Publication number
AU2002338729A1
AU2002338729A1 AU2002338729A AU2002338729A AU2002338729A1 AU 2002338729 A1 AU2002338729 A1 AU 2002338729A1 AU 2002338729 A AU2002338729 A AU 2002338729A AU 2002338729 A AU2002338729 A AU 2002338729A AU 2002338729 A1 AU2002338729 A1 AU 2002338729A1
Authority
AU
Australia
Prior art keywords
router
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
AU2002338729A
Inventor
Daniel Bretz
Martin Vorbach
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
PACT XPP Technologies AG
Original Assignee
PACT XPP Technologies AG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US09/967,497 external-priority patent/US7266725B2/en
Priority claimed from PCT/EP2001/011593 external-priority patent/WO2002029600A2/en
Priority claimed from PCT/EP2002/002403 external-priority patent/WO2002071249A2/en
Priority claimed from PCT/EP2002/002398 external-priority patent/WO2002071248A2/en
Priority claimed from DE10212622A external-priority patent/DE10212622A1/en
Priority claimed from DE10226186A external-priority patent/DE10226186A1/en
Priority claimed from DE10227650A external-priority patent/DE10227650A1/en
Priority claimed from DE10238174A external-priority patent/DE10238174A1/en
Priority claimed from DE10240000A external-priority patent/DE10240000A1/en
Priority claimed from PCT/DE2002/003278 external-priority patent/WO2003023616A2/en
Priority claimed from PCT/EP2002/010084 external-priority patent/WO2003025770A2/en
Application filed by PACT XPP Technologies AG filed Critical PACT XPP Technologies AG
Publication of AU2002338729A1 publication Critical patent/AU2002338729A1/en
Abandoned legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3885—Concurrent instruction execution, e.g. pipeline or look ahead using a plurality of independent parallel functional units
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored program computers
    • G06F15/78—Architectures of general purpose stored program computers comprising a single central processing unit
    • G06F15/7867—Architectures of general purpose stored program computers comprising a single central processing unit with reconfigurable architecture
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/39—Circuit design at the physical level
    • G06F30/394—Routing

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Software Systems (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Evolutionary Computation (AREA)
  • Geometry (AREA)
  • Multi Processors (AREA)
  • Telephonic Communication Services (AREA)
AU2002338729A 2001-09-19 2002-09-18 Router Abandoned AU2002338729A1 (en)

Applications Claiming Priority (59)

Application Number Priority Date Filing Date Title
DE10146132 2001-09-19
DE10146132.1 2001-09-19
US09/967,497 US7266725B2 (en) 2001-09-03 2001-09-28 Method for debugging reconfigurable architectures
US09/967,497 2001-09-28
AU16952/02 2001-09-30
EP0111299 2001-09-30
AU2002220600 2001-10-08
PCT/EP2001/011593 WO2002029600A2 (en) 2000-10-06 2001-10-08 Cell system with segmented intermediate cell structure
DE10154259.3 2001-11-05
DE10154259 2001-11-05
EP01129923.7 2001-12-14
EP01129923 2001-12-14
EP02001331.4 2002-01-18
EP02001331 2002-01-18
DE10206653 2002-02-15
DE10206653.1 2002-02-15
DE10206856 2002-02-18
DE10206857 2002-02-18
DE10206857.7 2002-02-18
DE10206856.9 2002-02-18
DE10207226 2002-02-21
DE10207224 2002-02-21
DE10207224.8 2002-02-21
DE10207226.4 2002-02-21
DE10208434 2002-02-27
DE10208435.1 2002-02-27
DE10208435 2002-02-27
DE10208434.3 2002-02-27
PCT/EP2002/002403 WO2002071249A2 (en) 2001-03-05 2002-03-05 Method and devices for treating and/or processing data
AU2002244738 2002-03-05
PCT/EP2002/002398 WO2002071248A2 (en) 2001-03-05 2002-03-05 Methods and devices for treating and/or processing data
PCT/EP2002/002402 WO2002071196A2 (en) 2001-03-05 2002-03-05 Methods and devices for treating and processing data
AU2002257615 2002-03-05
AU2002254921 2002-03-05
DE10212622.4 2002-03-21
DE10212621 2002-03-21
DE10212621.6 2002-03-21
DE10212622A DE10212622A1 (en) 2002-03-21 2002-03-21 Computer program translation method allows classic language to be converted for system with re-configurable architecture
EP02009868.7 2002-05-02
DE10219681 2002-05-02
DE10219681.8 2002-05-02
EP02009868 2002-05-02
DE10226186A DE10226186A1 (en) 2002-02-15 2002-06-12 Data processing unit has logic cell clock specifying arrangement that is designed to specify a first clock for at least a first cell and a further clock for at least a further cell depending on the state
DE10226186.5 2002-06-12
DE10227650A DE10227650A1 (en) 2001-06-20 2002-06-20 Reconfigurable elements
DE10227650.1 2002-06-20
DE10236271.8 2002-08-07
DE10236271 2002-08-07
DE10238174.7 2002-08-21
DE10238174A DE10238174A1 (en) 2002-08-07 2002-08-21 Router for use in networked data processing has a configuration method for use with reconfigurable multi-dimensional fields that includes specifications for handling back-couplings
DE10240022.9 2002-08-27
DE10240022 2002-08-27
DE10240000.8 2002-08-27
DE10240000A DE10240000A1 (en) 2002-08-27 2002-08-27 Router for use in networked data processing has a configuration method for use with reconfigurable multi-dimensional fields that includes specifications for handling back-couplings
AU2002336896 2002-09-03
PCT/DE2002/003278 WO2003023616A2 (en) 2001-09-03 2002-09-03 Method for debugging reconfigurable architectures
PCT/EP2002/010084 WO2003025770A2 (en) 2001-09-07 2002-09-09 Reconfigurable system
AU2002342668 2002-09-09
PCT/EP2002/010479 WO2003025781A2 (en) 2001-09-19 2002-09-18 Router

Publications (1)

Publication Number Publication Date
AU2002338729A1 true AU2002338729A1 (en) 2003-04-01

Family

ID=32315059

Family Applications (1)

Application Number Title Priority Date Filing Date
AU2002338729A Abandoned AU2002338729A1 (en) 2001-09-19 2002-09-18 Router

Country Status (3)

Country Link
EP (1) EP1466264B1 (en)
AU (1) AU2002338729A1 (en)
WO (1) WO2003025781A2 (en)

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6542998B1 (en) 1997-02-08 2003-04-01 Pact Gmbh Method of self-synchronization of configurable elements of a programmable module
US8058899B2 (en) 2000-10-06 2011-11-15 Martin Vorbach Logic cell array and bus system
US9037807B2 (en) 2001-03-05 2015-05-19 Pact Xpp Technologies Ag Processor arrangement on a chip including data processing, memory, and interface elements
US7444531B2 (en) 2001-03-05 2008-10-28 Pact Xpp Technologies Ag Methods and devices for treating and processing data
US7996827B2 (en) 2001-08-16 2011-08-09 Martin Vorbach Method for the translation of programs for reconfigurable architectures
WO2003071432A2 (en) 2002-02-18 2003-08-28 Pact Xpp Technologies Ag Bus systems and method for reconfiguration
US8914590B2 (en) 2002-08-07 2014-12-16 Pact Xpp Technologies Ag Data processing method and device
US7693257B2 (en) 2006-06-29 2010-04-06 Accuray Incorporated Treatment delivery optimization
US8078834B2 (en) 2008-01-09 2011-12-13 Analog Devices, Inc. Processor architectures for enhanced computational capability
US8108653B2 (en) 2008-01-09 2012-01-31 Analog Devices, Inc. Processor architectures for enhanced computational capability and low latency

Family Cites Families (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0190813B1 (en) * 1985-01-29 1991-09-18 The Secretary of State for Defence in Her Britannic Majesty's Government of the United Kingdom of Great Britain and Processing cell for fault tolerant arrays
DE4416881C2 (en) 1993-05-13 1998-03-19 Pact Inf Tech Gmbh Method for operating a data processing device
WO2002071249A2 (en) 2001-03-05 2002-09-12 Pact Informationstechnologie Gmbh Method and devices for treating and/or processing data
DE19651075A1 (en) 1996-12-09 1998-06-10 Pact Inf Tech Gmbh Unit for processing numerical and logical operations, for use in processors (CPU's), multi-computer systems, data flow processors (DFP's), digital signal processors (DSP's) or the like
DE19654595A1 (en) 1996-12-20 1998-07-02 Pact Inf Tech Gmbh I0 and memory bus system for DFPs as well as building blocks with two- or multi-dimensional programmable cell structures
DE19654593A1 (en) 1996-12-20 1998-07-02 Pact Inf Tech Gmbh Reconfiguration procedure for programmable blocks at runtime
DE19654846A1 (en) 1996-12-27 1998-07-09 Pact Inf Tech Gmbh Process for the independent dynamic reloading of data flow processors (DFPs) as well as modules with two- or multi-dimensional programmable cell structures (FPGAs, DPGAs, etc.)
DE19704044A1 (en) 1997-02-04 1998-08-13 Pact Inf Tech Gmbh Address generation with systems having programmable modules
DE19704728A1 (en) 1997-02-08 1998-08-13 Pact Inf Tech Gmbh Method for self-synchronization of configurable elements of a programmable module
DE19861088A1 (en) 1997-12-22 2000-02-10 Pact Inf Tech Gmbh Repairing integrated circuits by replacing subassemblies with substitutes
DE19807872A1 (en) 1998-02-25 1999-08-26 Pact Inf Tech Gmbh Method of managing configuration data in data flow processors
DE10028397A1 (en) 2000-06-13 2001-12-20 Pact Inf Tech Gmbh Registration method in operating a reconfigurable unit, involves evaluating acknowledgement signals of configurable cells with time offset to configuration
DE19926538A1 (en) 1999-06-10 2000-12-14 Pact Inf Tech Gmbh Hardware with decoupled configuration register partitions data flow or control flow graphs into time-separated sub-graphs and forms and implements them sequentially on a component
CN1378665A (en) 1999-06-10 2002-11-06 Pact信息技术有限公司 Programming concept
DE10103624A1 (en) 2000-02-10 2001-09-20 Traub Otto Basic frame has recliner element with surface, fixed handles and support
DE10036627A1 (en) 2000-07-24 2002-02-14 Pact Inf Tech Gmbh Integrated cell matrix circuit has at least 2 different types of cells with interconnection terminals positioned to allow mixing of different cell types within matrix circuit
ATE437476T1 (en) 2000-10-06 2009-08-15 Pact Xpp Technologies Ag CELL ARRANGEMENT WITH SEGMENTED INTERCELL STRUCTURE
JP2004536373A (en) 2001-03-05 2004-12-02 ペーアーツェーテー　イクスペーペー　テクノロジーズ　アクチエンゲゼルシャフト Data processing method and data processing device

Also Published As

Publication number Publication date
EP1466264B1 (en) 2011-09-14
WO2003025781A3 (en) 2004-05-27
EP1466264A2 (en) 2004-10-13
WO2003025781A2 (en) 2003-03-27

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Legal Events

Date Code Title Description
MK6 Application lapsed section 142(2)(f)/reg. 8.3(3) - pct applic. not entering national phase