JPH08102492A - Programmable wiring circuit and test board device - Google Patents

Abstract

PURPOSE: To remove influence of a wiring delay, raise the degree of freedom of a wiring and contrive to enhance use efficiency by a method wherein a bypass wiring has beforehand been arranged so that a various-purpose wiring is bypassed every predetermined length. CONSTITUTION: Input and output terminals 12 are regularly arranged on a semiconductor chip 11. Input and output lines 13 for transmitting or receiving data between the input and output terminals 12 and a wiring path within a chip are arranged with respect to these input and output terminals 12, respectively. Various-purpose wires 14, 15 are formed in the semiconductor chip 11 to form an optical wiring path. Further, bypass wires 16, 17 for bypassing these various-purpose wires 14, 15 every predetermined length are arranged. A wiring connection point 18 is arranged in an array-like form in each intersecting point location of the input and output lines 13, the various-purpose wires 14, 15 and the bypass wires 16, 17 and is a program element capable of changing a connection state with respect to each other and controlling a wiring path.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a programmable wiring circuit by which a user can realize desired wiring at a design site and a test board device using this wiring circuit.

[0002]

2. Description of the Related Art For a masked ASIC typified by a general gate array, a user designs a field (field).
PLD (Programmable Logic De) that can be used as it is by programming a desired logic circuit
vice) and FPGA (Field Program)
Able Gate Array) and the like are attracting attention. Among them, the FPGA can significantly reduce the development labor, cost, period, etc. because the user can easily program a desired circuit at hand as compared with the general gate array described above. It is often used as a device for logic verification and trial manufacture before mass production.

The basic structure of an FPGA is that logic blocks as basic cells forming a gate circuit are regularly arranged in a matrix on a chip, and general wiring for connecting the logic blocks is provided around the logic blocks. Provide the wiring area. Further, there are a large number of wiring connection points in the wiring region, and a program element by an anti-fuse or a pass transistor is arranged at the connection point according to the FPGA architecture.

The circuit designer uses these elements and I / O blocks to specify the necessary logic block area, wiring area, wiring connection point, and I / O block according to the specified circuit. , Realizes an arbitrary circuit.

However, when a plurality of FPGAs are used to form an arbitrary circuit on a board, wiring connection between FPGAs is performed by a fixed method such as lapping as in the conventional case. Therefore, there is no problem when changing the circuit only within one FPGA, but when changing the circuit on a scale that spans multiple FPGAs, it is necessary to reconnect the wiring between FPGAs. There was a problem that the advantage of could not be utilized.

To solve the above-mentioned problems,
An LSI dedicated to wiring, in which functional blocks are removed from the FPGA and only program elements are integrated in an array
PIC (Field Programmable in
terconnect components) "and a printed circuit board dedicated to this FPIC have been developed and commercialized by Optix Corp. in the United States (for example, product number A1024D.FBCB-AP4).
-S).

By using this FPIC and a dedicated printed circuit board and mounting a plurality of FPGAs, a general-purpose breadboard can be constructed, and the design and development of a normal printed circuit board becomes unnecessary.

Therefore, if the FPIC and the dedicated printed circuit board are used for the trial verification in the large-scale ASIC, the design change can be flexibly dealt with, and the trial verification period can be greatly shortened.

[0009]

In the above-mentioned FPIC, since the wiring delay increases each time a connection point consisting of programmable elements at each intersection of the wiring paths passes, the critical path of the circuit is solved. Becomes difficult and the operating speed of the circuit decreases.

Further, since the number of programmable elements is finite, there is a problem that the use efficiency of the FPIC is extremely reduced for high fan-out wiring connection. The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a program capable of increasing the degree of freedom of wiring and significantly improving the use efficiency without being affected by wiring delay. To provide a simple wiring circuit and a test board device.

[0011]

That is, according to the present invention, an input / output terminal regularly arranged on a semiconductor chip and an input / output terminal and a wiring path in the chip are provided for each of the input / output terminals. An input / output line for transmitting and receiving data between them, a general-purpose wiring formed on the semiconductor chip to form an arbitrary wiring path, a bypass wiring for bypassing the general-purpose wiring every predetermined length, the input / output line, The general-purpose wiring and the bypass wiring are arranged in an array at each intersection, and the wiring connection points are formed of program elements that control the wiring path by varying the connection state between them.

[0012]

With the above-mentioned structure, by providing the bypass wiring which bypasses the general-purpose wiring for every predetermined length in advance, when the wiring is actually connected, the general-purpose wiring and the bypass wiring are Just select the required one from the program and do not be affected by the wiring delay,
It is possible to increase the degree of freedom of wiring and significantly improve the use efficiency.

[0013]

【Example】

[First Embodiment] A first embodiment in which the present invention is applied to an FPIC chip will be described below with reference to the drawings.

FIG. 1 (A) shows the internal structure.
11 is an FPIC chip, 12, 12, ... are this FPIC chip
It is assumed that there are a large number of input / output terminals which are regularly arranged in a matrix on the above 11, and here a total of nine input / output terminals 12 in 3 rows and 3 columns are arranged as a simplified configuration. Also, 1
3, 13, ... Are input / output terminals 12, 12, ... Connected by segmenting the input / output terminals 12, 12, ... In the horizontal and vertical directions.
Input / output lines having interfaces of 12, ..., Horizontal general-purpose wirings 14, 14, ... And vertical general-purpose wirings 15, 15, so that these input / output lines 13, 13 ,.
Are arranged so as to form a matrix.

Further, the bypass wiring 16 is formed so as to cross the input / output line 13 in a region near the outer periphery of the FPIC chip 11.
16, ..., 17, 17 are provided. Here, bypass wiring 16, 1
6, ... are input / output terminals 12, 12, ...
Among them, the ones arranged on a straight line are directly connected, and the bypass wirings 17 and 17 are directly connected on the two adjacent straight lines which are connected by the bypass wiring 16 and are adjacent to each other. To do.

That is, the input / output terminals located on the outer circumference
When the arrangement of 12, 12, ... Is regarded as a rectangle, the bypass wirings 16, 16, ... Connect the input / output terminals 12, 12 ,. L on 2 sides
The bypass wirings 17, 17 collectively connect the input / output terminals 12, 12, ...

Although not shown in FIG. 1 (A),
Input / output lines 13, 13, ..., Horizontal general-purpose wiring 14, 1
4, ..., vertical general-purpose wiring 15, 15, ..., bypass wiring 1
6,16, ..., 17,17 Figure 1 at each intersection
Connection points 18, 18, ... Are arranged as shown in FIG.

The connection points 18, 18, ... Are made up of elements such as pass transistors and antifuses whose conduction state can be controlled by a program. By collectively downloading the programs showing the connection state, , The connection state is switched and selected.

In the above configuration, for example, when the input / output terminal 12 located at the upper left and the input / output terminal 12 located at the lower right in the figure are connected, diagonal input / output When forming a wiring path for connecting the terminals 12, by selecting the bypass wiring 17 in place of the horizontal general-purpose wiring 14 and the vertical general-purpose wiring 15 and making the corresponding connection point 18 conductive by a program, Since it is possible to reduce the number of connection points 18 that are brought into conduction, it is possible to realize a high-speed pass line with little influence of wiring delay.

In addition, for example, when connecting the input / output terminal 12 located at the lower left and the input / output terminal 12 located at the lower right in the figure, connect the input / output terminals 12 that are separated from each other on a straight line. Horizontal general-purpose wiring 14
Alternatively, if the bypass wiring 16 is selected and the corresponding connection point 18 is made conductive by programming, the number of connection points 18 to be made conductive can be reduced in the same manner as above, so that the influence of the wiring delay is also small. A high-speed pass line can be realized.

The effect described above becomes more remarkable as the number of the n × m input / output terminals 12 on the FPIC chip 11 increases, and the bypass wirings 16, 16, ... By selecting, a high-speed pass line with a minimum of connection points 18 can be realized.

Although the bypass wirings 16, 16, ..., 17, 17 are directly provided to the input / output terminals 12, 12, ... Located on the outer periphery of the FPIC chip 11 in FIG. The bypass wiring for the wiring 14 and the vertical general-purpose wiring 15 may be configured as shown in FIGS. Hereinafter, another configuration example of the first embodiment will be described with reference to FIGS. 2 and 3.

FIG. 2 illustrates an FPIC having a two-layer structure as shown in FIG. 2A, and FIG.
The structure of the first layer 21 is shown. As shown in FIG. 2B, the first layer 21 has a basic structure of the FPIC shown in FIG. 1, that is, a total of 16 horizontal 4 × vertical 4
I / O terminals 12, 12, ..., I / O lines 13, 13 ,.
Horizontal general-purpose wiring 14, 14, ... And vertical general-purpose wiring 15,
15… are formed and connection points 18 and 1 are formed at each intersection.
8, ... (not shown) are arranged.

With respect to the first layer 21, as shown in FIG. 2C, the upper second layer 22 is provided at positions corresponding to the input / output lines 13, 13, ... Of the first layer 21. Bypass wiring 23, 23,
..., 24, 24, ... are arranged. The bypass wirings 23, 23, ... Directly connect the input / output lines 13, 13, ... Which are arranged in an L shape on two orthogonal straight lines, while the bypass wirings 24, 24 ,. Are for directly connecting the input / output lines 13, 13, ... Arranged on one straight line.

However, these bypass wirings 23, 23,
..., 24, 24, ... and the connection points 18, 18, ... indicated by small circles in the figure at the intersections of the input and output lines 13, 13 ,.
By collectively downloading the program showing the connection status to this connection point 18,
The connection state is switched and selected.

With the above-mentioned structure, the bypass wirings 23, 23, ..., 24, 24, .. As required, the horizontal general-purpose wirings 14, 14, ..., The vertical general-purpose wirings 15, 15 ,. By selecting instead and making the corresponding connection point 18 conductive by programming to form a wiring path, the number of connection points 18 to be made conductive can be reduced, so that the influence of wiring delay is small and a high-speed path is provided. Line can be realized.

In the case of the structure shown in FIG. 2, the chip structure is slightly complicated because it has two layers as compared with the structure shown in FIG. 1, but the input / output terminals located inside the chip are not limited to the outer periphery. Freely bypass wiring 23, 2 including 12, 12, ...
Since 3, ..., 24, 24, ... can be arranged, the influence of wiring delay is further reduced, a high-speed pass line can be realized, and the degree of freedom of wiring is increased to greatly improve the use efficiency. Can be improved.

In the configuration of FIG. 2 as well, the above effect is obtained as the number of n × m input / output terminals 12, 12, ... On the chip increases, and the bypass wirings 23, 23 ,.
The more the type and number of 4, ..., the more remarkable.

The following FIG. 3 also illustrates an FPIC having a two-layer structure as shown in FIG. 3A, and FIG. 3B shows the structure of the first layer 25 below the FPIC. As shown in FIG. 2B, the basic structure of the FPIC shown in FIG. 1 is also formed in the first layer 25, that is, for example, a total of 1 horizontal 4 × vertical 4
6 input / output terminals 12, 12, ..., Input / output lines 13, 13,
..., horizontal general-purpose wiring 14, 14, ... and vertical general-purpose wiring
15, 15,… are formed, and connection points 1 are provided at each intersection.
8, 18, ... (not shown) are arranged.

As shown in FIG. 3C, the second layer 26 on the upper side of the first layer 25 has a general-purpose wiring 1 of the first layer 25.
Bypass wiring 2 at the position corresponding to 4, 14, ..., 15, 15 ,.
7, 27, ..., 28, 28, ... are arranged. Here, the bypass wirings 27, 27, ... Are directly connected in an L-shape across the horizontal general-purpose wirings 14, 14, ... And the vertical general-purpose wirings 15, 15 ,. The bypass wirings 28, 28, ... Are arranged directly on the horizontal general-purpose wirings 14, 14, ... Or the vertical general-purpose wirings 15, 15 ,.

However, these bypass wirings 27, 27,
, 28, 28, ... and horizontal general-purpose wiring 14, 14, ..., vertical general-purpose wiring 15, 15, ... are arranged at connection points 18, 18 shown by small circles in the figure. To do.

With the above-described structure, the bypass wirings 27, 27, ..., 28, 28, ..., Horizontal general-purpose wirings 14, 14, ..., Vertical general-purpose wirings 15, 15 ,. By selecting instead and making the corresponding connection point 18 conductive by programming to form a wiring path, the number of connection points 18 to be made conductive can be reduced, so that the influence of wiring delay is small and a high-speed path is provided. Line can be realized.

Similar to the structure shown in FIG. 2, the structure shown in FIG. 3 has two layers as compared with the structure shown in FIG. 1 so that the chip structure is slightly complicated, but is limited to the outer periphery of the chip. Since the bypass wirings 27, 27, ..., 28, 28, ... Including the input / output terminals 12, 12, ... It is possible to realize various pass lines.

The bypass wirings 27, 27, ..., 28, 28,
... for horizontal general-purpose wiring 14, 14, ..., vertical general-purpose wiring 1
Since it is directly arranged on the 5, 15, ..., The degree of freedom of wiring can be increased more than the structure shown in FIG.

Although the bypass wirings 17, 23 and 27 shown in FIGS. 1 to 3 have been described as being provided in an L shape, the present invention is not limited to this, and each of the bypass wirings 17, 23 and 27 is formed by three orthogonal straight lines. It may be in the shape of a letter, or may be in the shape of a diagonal line that directly connects diagonal positions on a rectangular chip.

Further, FIGS. 2 and 3 show the structure in which the second layers 22 and 26 having the bypass wiring formed on the first layers 21 and 25 provided with the basic structure of the FPIC are integrated. But
A multilayer structure may be formed by separately providing a layer provided with general-purpose wiring and a layer provided with bypass wiring with respect to a basic layer provided with input / output terminals and input / output lines.

[Second Embodiment] A second embodiment in which the present invention is applied to a test board device having an FPIC chip will be described below with reference to the drawings.

FIG. 4 shows the entire structure, and 31 is a test board (shown as "FPCB" in the figure). A bus line 32 having an n-bit width is provided on the test board 31. For example, four FPIs are provided for the bus line 32.
It is assumed that the C chips 33a to 33d are connected and arranged via sockets (not shown).

These FPIC chips 33a to 33d are arbitrary LSIs 34a and 34b, 34c and 34d, 34e and 34, respectively.
f, 34g and 34g can be connected, connected L
The SIs 34a to 34g can be connected to the bus line 32 via the FPIC chips 33a to 33d, and can be connected to the FPIC chip 33a via general signal lines 35a and 35b which are not buses.
Since 33b, 33c and 33d are connected, LSI 34a, 34b
And LSI 34c and 34d, and LSI 34e and 34f and LSI
34g and 34g can be connected respectively.

However, through the socket, the FPIC
By using not only general-purpose ICs and LSIs but also FPGAs as the LSIs 34a to 34g connected to the chips 33a to 33d, virtually any circuit can be prototyped and verified.

Next, the FPIC chip 33a (~ 33
The internal configuration of d) will be described with reference to FIG. In the figure,
41, 41, ... are a large number of general-purpose input / output terminals which are regularly arranged in a matrix on the FPIC chip 33a (to 33d). Further, 42, 42, ... are input / output lines 42 having interfaces of the general-purpose input / output terminals 41, 41, ... Connected by segmenting the general-purpose input / output terminals 41, 41 ,. , 42, ... And these input / output lines 42, 42 ,.
The horizontal general-purpose wirings 43, 43, ... And the vertical general-purpose wirings 44, 44 ,.

Further, at the one end portion of the FPIC chip 33a (to 33d), for example, at the left end portion as shown in the figure, bus dedicated wiring lines 45, 45, ... In parallel with the vertical general-purpose wiring lines 44, 44 are provided. Bus dedicated input / output terminals 46, 46, ... Are provided at one end of the bus dedicated wiring 45, 45 ,. Here, assuming that the bus line 32 of the test board 31 has a width of, for example, 4 bits, the dedicated bus lines 45, 45, ... And the dedicated bus input / output terminals 46, 46 are provided for each four lines. In addition, bus dedicated wiring 45, 45, ... and I / O lines 48, 48,
The general-purpose input / output terminals 41, 41, ..., and the general-purpose vertical wirings 44, 44, ...
43, 43, ... and Bus connection wirings 47, 47, ... This bus connection wiring 47, 47, ... is also dedicated to the bus
A total of four will be provided in total for 45, 45, ....

Although not particularly shown in FIG. 5,
The input / output lines 42, 42, ..., Horizontal general-purpose wiring 43, 4
3, ..., general-purpose vertical wiring 44, 44, ..., dedicated bus wiring 4
5, 45, ..., I / O lines 48, 48, ... and bus connection wiring 4
7, 47, ... Connection points are placed at each intersection. This connection point is composed of elements such as pass transistors and antifuses whose conduction state can be controlled by a program. By downloading the program showing the connection state to each connection point at once, Will be switched and selected.

In the above configuration, for example, FPI
FIG. 6 shows a state in which an arbitrary terminal of the LSI 34a is connected to the bus line 32 via the C chip 33a. It is assumed that the connection points at the positions indicated by the cross points except the bus dedicated input / output terminals 46, 46, ... Again, if the bus line 32 is 4 bits wide, the LSI 34a
4 arbitrary terminals are general-purpose input / output terminals 4 of FPIC chip 33a.
Connected to any four of 1, 41, ..., and these four general-purpose input / output terminals 41, 41, ... Are connected to the dedicated bus lines 45, 45 ,. Is.

By realizing such a wiring route, the F
Horizontal general-purpose wiring 43 in the PIC chip 33a (to 33d),
The LSI 34a can be bus-connected without using the vertical wirings 43 ,. Therefore, the wiring delay is reduced and the bus dedicated wiring 45,
It is possible to realize a wiring route without causing variations in delay time for each bit in 45, .... Further, the internal wiring efficiency is improved, the FPIC chip 33a is used more effectively, and a circuit having a higher degree of freedom including the LSI 34a can be configured.

[Third Embodiment] A third embodiment in which the present invention is applied to a test board device having an FPGA chip will be described below with reference to the drawings.

FIG. 7 shows the entire structure, and 51 is a test board. On this test board 51, for example, four FPGA chips 52a to 52d are connected and arranged through sockets (not shown), respectively, and two pin post portions 53 provided with wrapping post pins for verification are arranged.
a, 53b, connector parts (shown as "CON1-5" in the figure) 54a to 54e used for connection to an external board (not shown), free holes 55 to which arbitrary ICs and LSIs can be connected are provided. .

Each of the FPGA chips 52a to 52d has a large number of terminals, of which the terminals t1 to t6 of the FPGA chip 52a and the terminal t of the FPGA chip 52b are among them.
7 to t12, terminals t13 to t18 of the FPGA chip 52c and F
It is assumed that the terminals t19 to t24 of the PGA chip 52d are connected by wiring.

That is, in the FPGA chip 52a, the terminal t1 is connected to the terminal t13 of the FPGA chip 52a via the wiring L1.
And a wiring L2 in which the terminal t2 has a switch sw14 in the middle
Via the terminal t14 of the FPGA chip 52a and the wiring L3, the terminal t8 of the FPGA chip 52b, the terminal t3 via the wiring L4, the terminal t7 of the FPGA chip 52b, and the terminal t4 via the wiring L5. Terminal t16
And F through a wire L6 in which a switch sw11 is arranged
The terminal t10 of the PGA chip 52b, the terminal t5 of which is connected to the terminal t23 of the FPGA chip 52d via the wiring L7, and the terminal t
6 is connected to the terminal t18 of the FPGA chip 52c via the wiring L8.

In the FPGA chip 52b, the terminal t7
Is the pin post TP of the pin post portion 53a via the wiring L9.
11 and the wiring L in which the terminal t8 has a switch sw13 in the middle
Via the terminal 10, the terminal t20 and the wiring L11 of the FPGA chip 52d
Via the pin post TP12 of the pin post portion 53a and the terminal t9 via the line L12 to the terminal t21 of the FPGA chip 52d.
And the pin post T of the pin post portion 53a via the wiring L13.
P14 and the terminal t10 are connected to the FPGA chip 52 via the wiring L14.
The pin post TP13 of the pin post portion 53a via the terminal t22 of d and the wiring L15, and the terminal t11 of the pin post TP13 via the wiring L16 and FP.
The terminal t17 of the GA chip 52c and the wiring L17 are connected to the pin post TP15 of the pin post portion 53a, and the terminal t12 is connected to the terminal t24 of the FPGA chip 52d via the wiring L18.

Further, in the FPGA chip 52c, the terminal t
14 is the terminal t20 of the FPGA chip 52d via the wiring L19.
, The terminal t15 is the terminal t19 of the FPGA chip 52d via the wiring L20, the terminal t16 is the terminal t22 of the FPGA chip 52d via the wiring L21, and the terminal t17 is the switch sw12 in the middle.
Terminal t of the FPGA chip 52d via the wiring L22 in which
23 and each connected.

In the FPGA chip 52d, the terminal t19
Is the pin post TP of the pin post portion 53b via the wiring L23.
22 and the terminal t20 are connected to the pin post TP21 of the pin post portion 53b through the wiring L24.

Further, the connector portion 54 is connected by the wiring L25.
1 terminal c5 of e is connected to the wiring L8 and the wiring 18, so that 1 terminal c5 of the connector portion 54e is connected to the FPGA chip 52.
a terminal t6, terminal t18 of FPGA chip 52c, FPG
The terminal t12 of the A chip 52b and the terminal t24 of the FPGA chip 52d are connected together.

In the pin post portion 53a, however, the pin post TP11 is connected to the one terminal Q1 of the IC 56 mounted in the free hole 55 via the wrapping wiring WR1, and the pin post TP12 is connected to the switches sw21 to sw21.
It is connected via 24 to one terminal of the connector parts 54a to 54d.

The switches sw11 to sw14 and sw21 to s
For w24, there is no need to consider the effect of wiring delay
It is for physically and mechanically disconnecting the wiring state, and is constituted by, for example, a DIP switch arranged in advance on the test board 51.

In FIG. 8 which follows, the test board 51 constructed as shown in FIG. 7 is used as a first test board, and other similar second to fourth test boards 62 to 64 are used for the expansion board 65. An example is shown in which the system is connected by the above.

In the figure, in the first test board 51, the connector portion (CON1) 54a is wired to the connector portion (CON31) 67a of the third test board 63 via the wiring L31, and the connector portion (CON2) 54b is wired. The connector section (CONS2) 69b of the expansion board 65 is connected to the connector section (CON
3) 54c is connected to the connector section (CON41) 68a of the fourth test board 64 via the wiring L33, and to the connector section (CO
N4) 54b connects the second test board 6 via the wiring L34.
The two connectors (CON24) 66d are respectively connected.

In the second test board 62, the connector portion (CON21) 66a is connected to the connector portion (CON33) 67c of the third test board 63 via the wiring L35, and the connector portion (CON22) 66b is connected to the wiring L36. To the connector section (CONS1) 69a of the expansion board 65 and the connector section (C
ON23) 54c is connected to the fourth test board 64 via the wiring L37.
Are respectively connected to the connector part (CON43) 68c.

Further, the connector portion (CON32) 66b of the third test board 63 is connected to the connector portion (CONS3) 69c of the expansion board 65 via the wiring L38 and the connector portion (CON).
34) 67d is connected to the connector part (CON44) 68d of the fourth test board 64 via the wiring L39, and the connector part (CON42) 68b of the fourth test board 64 is connected to the wiring L.
Connector part (CONS4) 69 of expansion board 65 via 40
connected to d.

The wiring operation in the test board 51 shown in FIG. 7 having the above-mentioned configuration will be described first. In FIG. 7, for example, when wiring a signal in the evaluation circuit from the FPGA chip 52a to the FPGA chip 52d, first, as layout processing of the FPGA, the output terminal of the FPGA chip 52a is assigned to t5 and the input of the FPGA chip 52d is input. The terminals are assigned to t23. Since the terminals t5 to t23 are already connected by the wiring L7, the FPGA chip 52a to the FPGA chip 52 are thus connected.
A connection to d is realized.

A similar connection layout process is performed for the wiring L in the figure.
This is also done for the FPGA chips 52a to 52d located at both ends of 16, L12, L1, L20, and L4. Therefore, the terminals t3, t8, t of the FPGA chips 52a to 52d are
When connecting four points by t4 and t20 and wirings L3, L10, L19 and L2 between them, the connection is realized by executing the layout process and turning on the switches sw13 and sw14. Note that the unused external terminals of the FPGA are in a high impedance state, so if the FPGA wiring between the three points is physically performed, the FP between the four points is physically
There is no problem even if the GA is connected.

Further, by turning off the switches sw13 and sw14, the line L3 and the line L19 become independent FPGA connection between two points, and the wiring layout process between the two points can be performed.

A similar connection layout process is realized by turning on / off the switches sw11 and sw12 for the wiring L6 and the wiring L21. Also, the pin L
When the pin post TP12 of 53a is connected to the wiring L3, the state of the wiring L3 can be known by observing the pin post TP12 during measurement and evaluation.

Further, the pin post TP12 has a connector portion 54.
a to 54d and switches sw21 to sw24, the switch sw21 corresponding to the connector parts 54a to 54d.
By arbitrarily turning on / off ~ sw24, one terminal of the desired connector portion 54a to 54d and the wiring L3, that is, FP
The terminal t2 of the GA chip 52a and the terminal t8 of the FPGA chip 52b can be connected.

In this way, the pin posts TPn of the pin post portions 53a and 53b are connected and wired for each wiring between the FPGAs, and each pin post TPn is connected to the connector portions 54a to 54e via the switch. , Any F
The PGA terminal can be observed and can be connected to an arbitrary connector section.

The pin post TP11 of the pin post portion 53a connected to the wiring L4 by the wiring L9 has the discrete I on the free hole 55 by the lapping wiring WR1.
It can be connected to one terminal Q1 of IC56 which is C.

When an external signal is input from one terminal c5 of the connector portion 54e, this external signal is sent from the wiring L25 to the wiring L8.
, L18, the terminal t6 of the FPGA chip 52a, FP
Since the terminal t18 of the GA chip 52c, the terminal t12 of the FPGA chip 52b, and the terminal t24 of the FPGA chip 52d are collectively connected, it can be distributed and supplied to each of the FPGA chips 52a to 52d. Therefore, if the layout processing is performed so as to supply a high fan-out signal such as a clock or reset as the external signal, the FPGA chips 52a to 52d can be used more effectively.

The test board 51 configured as shown in FIG. 7 is used as a first test board, and other similar second to fourth test boards 62 to 64 are provided to the expansion board 65 as shown in FIG. It is assumed that the system is connected.

In this case, the wirings L31, L34, L37, L39,
“CONn1” and “CONn” on the first test board 51 and the second to fourth test boards 62 to 64 by L33 and L35.
Each test board 51, 62 to 64 is connected via a connector portion represented by "3""CONn4" (where n is 0, 2 to 4).

Along with this, wirings L32, L36, L38
And L40, the first test board 51 and second to fourth
Connector part represented by "CONn2" (n is the same as the above) on the test boards 62 to 64 of the above, and "C on the expansion board 65".
Each of the test boards 51, 62 to 64 and the expansion board 65 are connected via connector portions 69a to 69d represented by "ONS 1 to 4".

In the first test board 51, one terminal of each of the connector portions (CON1 to 4) 54a to 54e connected to the second to fourth test boards 62 to 64 and the expansion board 65 is connected to the switch sw21 to. By connecting the sw24 on / off, it is connected to the pin post portion 53a, and this pin post portion 53a is connected to each FPGA chip 52 as shown in FIG.
It is connected to arbitrary terminals a to 52d. Therefore, the FPGA chips 52a to 52d in the first test board 51 can be connected to any FPGA, LSI, IC, or the like mounted on the second to fourth test boards 62 to 64 and the expansion board 65. . In this case, the first test board 51
Since the switches sw11 to sw14 and sw21 to sw24 inside the switch physically and mechanically connect and disconnect the wiring connection state respectively, variably set the connection state of each wiring without considering the influence of wiring delay. You can

[Fourth Embodiment] Hereinafter, the present invention will be described with reference to a wiring circuit using a masked gate array and an FP using this wiring circuit.
A fourth embodiment when applied to a GA chip mounted test board device will be described with reference to the drawings.

FIG. 9 shows the structure of a wiring circuit using a masked gate array, where 71 is a gate array chip, 72,
72, ... are a large number of input / output terminals which are regularly arranged in a matrix on the gate array chip 71. Here, it is assumed that a total of four, for example, two rows and two columns are arranged as a simplified configuration.

The input / output terminals 72, 72, ... Are integrally connected by general-purpose wirings 74, 74, ... Through the input / output buffers 73, 73 ,. Each of them is composed of a pair of tri-state buffers 75, 75 whose input terminals and output terminals are connected to each other.

In each of the pair of tri-state buffers 75, 75, ... Constituting the input / output buffers 73, 73, ..., The enable / disable signal from the control circuit 76 is directly applied to one of the inverters 77, 77 ,. Each of the signals is inverted and inputted via .., and one of them becomes a high-impedance state to cut off the signal transmission, thereby defining the signal transmission direction.

However, the control circuit 76 is, for example, an input / output terminal.
A shift register is composed of flip-flops (F / F) 78, 78, ... Connected in multiple stages by the number of 72, 72 ,. The applied control information is held while being shifted, and the contents held at each stage are used as the enable / disable signal corresponding to the corresponding input / output buffer 7
Serve for 3, 73, ...

In the above configuration, by inputting the control information from the control terminal 80 to the F / Fs 78, 78, ... Of the control circuit 76, the held contents correspond to the input / output buffers 73, 7
When sent as an enable / disable signal to 3, ..., One of the pair of tri-state buffers 75, 75 ,. The transmission of the signal is cut off, and the other transmits the signal of "H" / "L" level.

Therefore, as a result, the input / output terminals 72, 72,
Are used as input terminals or output terminals to define the signal transmission direction, and the input / output terminals 72, 72,
Those corresponding to each other are connected within.

In FIG. 9, the enable / disable signal from the control circuit 76 is inverted directly into one of the pair of tristate buffers 75, 75 forming the input / output buffer 73 and into the other via the inverter 77. , The tristate buffer 75 on one side always transmits an “H” / “L” level signal, and the corresponding input / output terminal 72 is defined as either the input / output terminal or the output terminal. However, by adopting the configuration shown in FIG. 10 instead, it is also possible to set both of the pair of tri-state buffers 75, 75 to a high impedance state to interrupt bidirectional signal transmission.

That is, in FIG. 10, the inverter 7 of FIG.
.. are eliminated, and the F / Fs 78, 78, ... Of the control circuit 76 are connected in multiple stages by the number of all the tri-state buffers 75, 75 ,. Are configured.

In the control circuit 76, the control information externally applied to the control terminal 80 according to the operation clock input from the clock terminal 79 is held while being shifted by the F / Fs 78, 78, ... The enable / disable signals are individually provided to the tri-state buffers 75, 75, ... Of the corresponding input / output buffers 73, 73 ,.

Therefore, both of the pair of tri-state buffers 75, 75 forming the input / output buffers 73, 73, ... Are set to a high impedance state to interrupt bidirectional signal transmission and, as a result, to the corresponding input / output terminal 72. It can also be set so as to disconnect the connection with the other input / output terminals 72, 72, ....

Next, a case where the same wiring circuit as that of the gate array chip 71 shown in FIG. 9 or 10 is applied to a test board device having a plurality of FPGAs will be described.

FIG. 11 shows the overall structure of the test board 81. On this test board 81, for example, four FPGA chips 82a to 82d are respectively connected and arranged via sockets not shown, and two pin post portions 83 provided with wrapping post pins for verification are arranged.
a, 83b, connector parts (shown as "CON51-55" in the figure) 84a-84e used for connection with an external board (not shown), free holes 85 for connecting arbitrary ICs, LSIs, etc. are provided. .

Further, the wiring circuit (G) shown in FIG. 9 or 10 is provided at an intermediate position between the FPGA chips 82a and 82b.
A) 86a has a wiring circuit 86b at an intermediate position between the FPGA chips 82a and 82c, a wiring circuit 86c at an intermediate position between the FPGA chips 82c and 82d, and a wiring circuit 86d at an intermediate position between the FPGA chips 82b and 82d. Wiring circuits 86e to 86g are arranged at intermediate positions between the portions 83a and 83b and the connector portions 84a to 84d.

Each of the FPGA chips 82a to 82d has a large number of terminals.
Terminals t31 to t36 of 82a, terminal t37 of FPGA chip 82b
~ T42, terminals t43 to t48 of FPGA chip 82c and FP
It is assumed that the terminals t49 to t54 of the GA chip 82d are connected by wiring.

That is, in the FPGA chip 82a, the terminal t31 is connected to the terminal t43 of the FPGA chip 82c via the wiring L41.
And a terminal t32 is a wiring circuit 86b via a wiring L42 and a terminal t38 of the FPGA chip 82b via a wiring L43 and a terminal t.
33 is the terminal t37 of the FPGA chip 82b via the wiring L44
And the terminal t34 is a wiring circuit 86b via a wiring L45 and a wiring circuit 86a via a wiring L46, the terminal t35 is a wiring circuit 86a via a wiring L47 and a terminal t47 and a wiring L48 of the FPGA chip 82c, and The terminal t36 is connected to the terminal t54 of the FPGA chip 82d via the wiring L49.

In the FPGA chip 82b, the terminal t37
Is the pin post TP of the pin post portion 83a via the wiring L49.
31 and the terminal t38 via the wiring L50, the wiring circuit 86d via the pin post TP32 of the pin post portion 83a and the wiring L51.
Then, the terminal t39 is connected to the FPGA chip 82 via the wiring L52 and the pin post TP34 of the pin post portion 83a and the wiring L80.
The terminal t51 of d and the terminal t40 are wired circuits via the wiring L53.
The wiring circuit 86d and the terminal t41 via the pin post TP33 and the wiring L55 of the pin post portion 83a via the wiring 86a and the wiring L54.
Is a terminal t53 of the FPGA chip 82d via a wiring circuit 86a and a wiring L57 via a wiring L56, and a terminal t42 is a pin post TP35 of the pin post portion 83a via a terminal t48 and a wiring L59 of the FPGA chip 82c via a wiring L58. Are connected respectively.

Further, in the FPGA chip 82c, the terminal t
44 is a wiring circuit 86b via a wiring L60 and terminal t50 of the FPGA chip 82d is a wiring L61 via a wiring L61.
The terminal t49 of the FPGA chip 82d and the terminal t46 via 62
Is a wiring circuit 86b via a wiring L63 and a wiring circuit 86c via a wiring L64, and a terminal t47 is a wiring circuit via a wiring L65.
It is connected to 86c respectively.

In the FPGA chip 82d, the terminal t49
Is the pin post TP of the pin post portion 83b via the wiring L66.
42 and the terminal t50 via the wiring L67, the wiring circuit 86d via the pin post TP41 of the pin post portion 83b and the wiring L68.
The terminal t52 is connected to the wiring circuit 86c via the wiring L69 and the wiring circuit 86d via the wiring L70, and the terminal t53 is connected to the wiring circuit 86c via the wiring L71.

Further, the connector portion 84 is formed by the wiring L72.
1 terminal c15 of e is connected to the wiring L58 and the wiring 49, so that 1 terminal c15 of the connector portion 84e is the FPGA chip.
82a terminal t36, FPGA chip 82b terminal t42, FP
The terminal t48 of the GA chip 82c and the terminal t54 of the FPGA chip 82d are collectively connected.

In the pin post portion 83a, however, the pin post TP31 is connected to the one terminal Q11 of the IC 87 mounted in the free hole 85 via the wrapping wiring WR11, and the pin post TP32 is connected to the wiring circuit via the wiring L73.
The wiring circuit 86f is connected to the wiring circuit 86f via the wiring 86e and the wiring L74, and the wiring circuit 86g is connected to the wiring circuit 86g via the wiring L75.

The wiring circuit 86e is connected to the connector portion 54a via the wiring L76 and the connector portion 54b via the wiring L77, and the wiring circuit 86f is connected to the connector portion 54c via the wiring L78. Circuit 86g is wiring L
Each of them is connected to the connector portion 54d through 79.

Each of the wiring circuits 86a to 86g is for disconnecting the wiring state in which it is not necessary to consider the influence of the wiring delay as shown in FIG. 9 or FIG. Next, in FIG. 12, the test board 81 configured as shown in FIG. 11 is used as a first test board, and system connection is made to the expansion board 95 together with other similar second to fourth test boards 92 to 94. An example is shown.

In the figure, in the first test board 81, the connector portion (CON51) 84a is wired to the connector portion (CON61) 96a of the second test board 92 via the wiring L81, and the connector portion (CON52) 84b is wired. The connector part (CON82) 98b of the fourth test board 94 is connected via L82, the connector part (CON53) 84c is connected to the connector part (CONS12) 99b of the expansion board 95 via the wiring L83, and the connector part (CON54). 84d is respectively connected to the connector part (CON74) 97d of the 2nd test board 93 via the wiring L84.

In the second test board 92, the connector portion (CON62) 96b is connected to the connector portion (CON72) 97b of the third test board 93 via the wiring L85, and the connector portion (CON63) 96c is connected to the wiring L86. Expansion board through
The connector unit (CONS11) 99a of 95 and the connector unit (CON64) 96d are connected to the connector unit (CON84) 98d of the fourth test board 94 via the wiring L87.

Further, in the third test board 93, the connector portion (CON71) 97a is connected via the wiring L88 to the connector portion (CON81) 98a of the fourth test board 94, and the connector portion (CON73) 97c is connected via the wiring L89. Expansion board
The connector part (CONS13) of 95 is connected to the connector part 99c of the fourth test board 94 (CON83).
98c is connected to the connector part (C
ONS14) 99d is connected.

In the above-mentioned structure, the wiring operation in the test board 81 shown in FIG. 11 will be described first.
In FIG. 11, for a signal in the evaluation circuit, for example, FPG
When wiring from the A chip 82a to the FPGA chip 82b, first, as a layout process of the FPGA chip, FP
The output terminal of the GA chip 82a is allocated to t33, and the FP
The input terminals of the GA chip 82b are assigned to t37.
Since the terminals t33 to t37 are already connected by the wiring L44, the FPGA chip 82a to the FPGA chip
A connection to the chip 82b is realized.

A similar connection layout process is performed for the wiring L in the figure.
The FPGA chips 82a to 82d located at both ends of 49, L58, L80, L41, L62, and L43 are also performed. However, the terminals t35 and t4 of the FPGA chips 82a to 82d are
1, t53, t47 and wiring L48, L56, L57, L7 between them
When the 4-point connection by 1, L65, L47 is performed, the layout process is executed, the wiring circuit 86a connects the wiring L48 and the wiring L56, and the wiring circuit 86c connects the wiring L.
The connection is realized by establishing the connection between 71 and the wiring L65. Since the unused external terminals of the FPGA chip are in a high impedance state, there is no problem even if the FPGA chips of four points are physically connected when wiring the FPGA chips of three points.

On the contrary, by setting all the enable / disable signals to the tri-state buffers forming the internal input / output buffers in the wiring circuits 86a and 86c, the wiring L48, the wiring L56, and the wiring L71 are connected. Since the connection between the wiring L65 will be broken, the wiring L57
And the wiring L47 are independent FPGA connections between two points, and the wiring layout process between these two points can be performed.

Similar connection layout processing is performed by the wiring circuit 86b.
And the wiring circuit 86d. Further, by connecting the pin post TP32 of the pin post portion 83a and the line L43 by the line L50, the state of the line L43 can be known by observing the pin post TP32 during measurement and evaluation.

Further, the pin post TP32 has wirings L73 to L73.
75, the wiring circuits 86e to 86g, and the wirings L76 to L79 are connected to the connector portions 84a to 84d.
Wiring circuits 86e-86g corresponding to 84d-connector section 84a-
By arbitrarily setting the enable / disable signal to the tri-state buffer of the input / output buffer corresponding to 84d, one terminal of the desired connector section 84a to 84d and the wiring L43, that is, the terminals t32 and F of the FPGA chip 82a.
The terminal t38 of the PGA chip 82b can be connected.

In this way, the pin posts TPn of the pin post portions 83a and 83b are connected and wired for each wiring between the FPGA chips, and each pin post TPn is connected to the wiring circuit 86e.
If it is connected to the connector parts 84a to 84d via 86g, the terminal of any FPGA chip can be observed and can be connected to any connector part.

The pin post TP31 of the pin post portion 83a connected to the wiring L44 by the wiring L49 has the discrete I on the free hole 85 by the wrapping wiring WR11.
It can be connected to 1 terminal Q11 of IC87 which is C.

When an external signal is input from one terminal c15 of the connector section 84e, this external signal is transmitted from the wiring L72 to the wiring L5.
8 and L49, the terminal t42 of the FPGA chip 82b, FP
Since the terminal t48 of the GA chip 82c, the terminal t36 of the FPGA chip 82a, and the terminal t54 of the FPGA chip 82d are collectively connected, it can be distributed and supplied to each of the FPGA chips 82a to 82d. Therefore, if the layout processing is performed to supply a signal having a high fanout such as a clock or a reset as the external signal, the FPGA chips 82a to 82d can be used more effectively.

The test board 81 configured as shown in FIG. 11 is used as a first test board, and other similar second to fourth test boards 92 to 94 are used for the expansion board 95 as shown in FIG. It is assumed that the system is connected.

In this case, the wirings L81, L87, L88, L84,
"CONn1" and "CONn" on the first test board 81 and the second to fourth test boards 92 to 94 by L82 and L85.
2 ”“ CONn4 ”(where n is 5, 6, 7, 8) through the test board 81, 92-94.
Is connected.

Along with this, wirings L83, L86, L89
And L90, the first test board 81 and the second to fourth
Connector board represented by "CONn2" (n is the same as above) on the test boards 92 to 94 of the above and "C" on the expansion board 95.
ONS11 to 14 "represented by connector portions 99a to 99d
The test boards 81, 92 to 94 and the expansion board 95 are connected via the.

In the first test board 81, one terminal of each of the connector portions (CON51 to 54) 84a to 84d connected to the second to fourth test boards 92 to 94 and the expansion board 95 is connected to the wiring circuit 86e. .About.86 g is connected to the pin post portion 83a, and this pin post portion 83a is connected to arbitrary terminals of the FPGA chips 82a to 82d as shown in FIG.

Therefore, F in the first test board 81
PGA chips 82a to 82d and second to fourth test boards
Arbitrary FPGA mounted on 92-94 and expansion board 95,
It can be connected to an LSI or IC. In this case, the wiring circuits 86a to 86g in the first test board 81 can variably set the connection state of each wiring without considering the influence of wiring delay.

[0111]

As described above in detail, according to the present invention, a programmable wiring circuit and a test board device which are free from the influence of wiring delay, which can increase the degree of freedom of wiring and greatly improve the use efficiency. Can be provided.

[Brief description of drawings]

FIG. 1 is a diagram illustrating an internal configuration of an FPIC chip according to a first embodiment of the present invention.

FIG. 2 is a diagram illustrating another configuration according to the embodiment.

FIG. 3 is a diagram illustrating another configuration according to the embodiment.

FIG. 4 is a diagram showing an overall configuration of a test board device equipped with an FPIC chip according to a second embodiment of the present invention.

FIG. 5 is a diagram illustrating an internal configuration of an FPIC chip according to the same embodiment.

FIG. 6 is an FPI in the test board device according to the embodiment.
The figure which illustrates the connection state of a C chip and LSI.

FIG. 7 is a diagram showing an overall configuration of a test board device according to a third embodiment of the present invention.

FIG. 8 is a diagram illustrating a connection state with another test board device according to the embodiment.

FIG. 9 is a diagram illustrating an internal configuration of a wiring circuit (gate array chip) according to a fourth embodiment of the present invention.

FIG. 10 is a diagram illustrating another configuration of FIG. 9.

FIG. 11 is a diagram showing an overall configuration of a test board device according to the embodiment.

FIG. 12 is a diagram illustrating a connection state with another test board device according to the embodiment.

[Explanation of symbols]

11, 33a to 33d ... FPIC chip, 12, 72 ... I / O terminals, 13, 42, 48 ... I / O lines, 14, 43 ... Horizontal general-purpose wiring, 15, 44 ... Vertical general-purpose wiring, 16, 17, 23 , 24, 2
7, 28 ... Bypass wiring, 18 ... Connection point, 21, 25 ... First layer, 22, 26 ... Second layer, 31 ... Test board, 32 ... Bus line, 34a-34g ... LSI, 35a, 35b ... General signal line, 41 ... General-purpose input / output terminal, 45 ... Bus dedicated wiring, 46 ... Bus dedicated input / output terminal, 51, 81 ... (first) test board,
52a to 52d, 82a to 82d ... FPGA chip, 53a, 53
b, 83a, 83b ... Pin post portion, 54a to 54e, 66a to 66
e, 67a to 67e, 68a to 68e, 69a to 69e, 84a to 84
e, 96a to 96e, 97a to 97e, 98a to 98e, 99a to 99e
… Connector, 55, 85… Free hole, 56, 87… IC,
62 to 64, 92 to 94 ... Second to fourth test boards, 65, 95
... Expansion board, 71, 86a to 86g ... Wiring circuit (gate array chip), 73 ... Input / output buffer, 74 ... General wiring, 75 ...
Tri-state buffer, control circuits 76 ..., 77 ... Inverter, 78 ... Flip-flop (F / F), 79 ... Clock terminal, 80 ... Control terminal.

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Office reference number FI technical display location H01L 21/82 C

Claims (15)

[Claims] 1. An input / output terminal which is regularly arranged on a semiconductor chip, and an input / output which is arranged for each of the input / output terminals and transmits / receives data between the input / output terminal and a wiring path in the chip. A line, a general-purpose wiring arranged on the semiconductor chip to form an arbitrary wiring path, a bypass wiring that bypasses the general-purpose wiring at a predetermined length, and intersections of the input / output line, the general-purpose wiring, and the bypass wiring A programmable wiring circuit, which is arranged in an array at a position and has a wiring connection point made of a program element that controls a wiring path by varying a connection state between the wiring connection points. 2. The programmable wiring circuit according to claim 1, wherein the bypass wiring is provided with plural kinds of predetermined lengths for bypassing the general-purpose wiring. 3. The programmable wiring circuit according to claim 1, wherein the bypass wiring has a multilayer structure provided in a layer different from the layer provided with the input / output terminals and the input / output lines. 4. The bypass wiring connects the input / output terminals directly in the vicinity of the outer periphery of the chip.
The programmable wiring circuit described. 5. The programmable wiring circuit according to claim 1, wherein the bypass wiring is directly connected to the input / output line. 6. The programmable wiring circuit according to claim 1, wherein the bypass wiring is directly connected to the general-purpose wiring. 7. An input / output terminal which is regularly arranged on a semiconductor chip, and an input / output line which is arranged for each of the input / output terminals and which transmits / receives data between the input / output terminal and a wiring path in the chip. , A general-purpose wiring arranged on the semiconductor chip to form an arbitrary wiring path, a bypass wiring for bypassing the general-purpose wiring for each predetermined length, the input / output line,
A programmable wiring circuit having wiring connection points, which are arranged in an array at intersections of general-purpose wiring and bypass wiring, and each of which controls a wiring path by varying a connection state between the wiring and a programmable wiring circuit, Each input / output terminal of a simple wiring circuit and one body
A test board device having a terminal portion connected in correspondence with, and a socket on which an arbitrary LSI can be mounted. 8. A general-purpose input / output terminal regularly arranged on a semiconductor chip, a general-purpose wiring arranged to form an arbitrary wiring path, and a bus dedicated input / output arranged to connect to an external bus line. A terminal, a bus dedicated wiring connected to the bus input / output terminal, a bus connecting wiring connecting the general-purpose wiring and the bus dedicated wiring, a general-purpose input / output terminal, a general-purpose wiring, a bus dedicated wiring, and a bus connection wiring And a wiring connection point formed of a program element that is arranged in an array at each intersection point and that controls a wiring path by varying a connection state between the wiring connection points. 9. A general-purpose input / output terminal regularly arranged on a semiconductor chip, a general-purpose wiring arranged to form an arbitrary wiring path, and a bus-dedicated input / output terminal arranged to connect to an external bus line. , Bus dedicated wiring connected to the bus input / output terminal, bus connecting wiring connecting the general-purpose wiring and the bus dedicated wiring, intersection points of the general-purpose input / output terminal, general-purpose wiring, dedicated bus, and bus connecting wiring A programmable wiring circuit having wiring connection points, which are arranged in an array in a matrix and each of which controls a wiring path by varying a connection state between them, and a general-purpose input / output terminal of the programmable wiring circuit. A socket having a terminal portion corresponding to one body 1 and capable of mounting an arbitrary LSI, and a bus line connected to a bus input / output terminal of the programmable wiring circuit are provided. Test board apparatus according to claim that it has set. 10. An FPGA (Field Programmable Gate)
Array) dedicated sockets, pin post parts that connect the terminals of these sockets to the verification tool, connector parts that connect the external board and the pin post parts, and between the sockets, the socket and pin post parts. Between the pin post portion and the connector portion, and a physical switch means for connecting and disconnecting the connection state. 11. A plurality of input / output terminals regularly arranged on a semiconductor chip, a general-purpose wiring arranged to connect these input / output terminals to form an arbitrary wiring path, and an upper wiring on the general-purpose wiring. A plurality of input / output buffers, each of which is provided for each input / output terminal, and which comprises a pair of tri-state buffers each connecting the input terminal and the output terminal to each other to define the signal transmission direction at the input / output terminal, Masked gate having holding means for holding enable / disable information of each tri-state buffer constituting a plurality of input / output buffers, and an information input terminal for inputting the enable / disable information held by the holding means A wiring circuit characterized by comprising an array. 12. The holding means holds enable / disable information corresponding to the number of the input / output terminals for the input / output buffer, and enables / disable information held by the holding means and information obtained by inverting the enable / disable information. The wiring circuit according to claim 11, wherein the wiring circuit is provided to a pair of tri-state buffers constituting an input / output buffer. 13. The wiring circuit according to claim 11, wherein said holding means holds enable / disable information for each of the tri-state buffers constituting said input / output buffer. 14. A plurality of input / output terminals regularly arranged on a semiconductor chip, a general-purpose wiring arranged to connect these input / output terminals to form an arbitrary wiring path, and the input / output on the general-purpose wiring. A plurality of input / output buffers each consisting of a pair of tri-state buffers arranged for each terminal to connect the input terminal and the output terminal to each other so as to define the signal transmission direction at the input / output terminal. A holding circuit for holding enable / disable information of each tri-state buffer forming the output buffer, and a wiring circuit composed of a masked gate array having an information input terminal for inputting the enable / disable information held by the holding means. And a socket which has terminal portions connected to each input / output terminal of this wiring circuit corresponding to one body 1 and can mount an arbitrary LSI. Test board apparatus characterized by the bets were placed. 15. An FPGA (Field Programmable Gate)
Array) dedicated sockets, a pin post that connects the terminals of these sockets to the verification tool, a connector that connects the external board to the pin post, and a plurality of regularly arranged semiconductor chips. Input / output terminals, general-purpose wiring arranged to connect these input / output terminals to form an arbitrary wiring path, and the above-mentioned general-purpose wiring is arranged for each of the above-mentioned input / output terminals to provide signals at the input / output terminals. A plurality of input / output buffers each consisting of a pair of tri-state buffers each having its input terminal and output terminal connected to each other to define the transmission direction, and enable / disable of each of the tri-state buffers constituting the plurality of input / output buffers A holding means for holding the disable information and an information input terminal for inputting the enable / disable information held by the holding means are provided. A wiring circuit formed of a masked gate array arranged between at least one of the sockets, between the socket and the pin post portion, and between at least one of the pin post portion and the connector portion to interrupt the connection state therebetween. Test board device characterized by.