WO1995028671A1 - An improved system logic controller for digital computers - Google Patents

An improved system logic controller for digital computers

Info

Publication number
WO1995028671A1
WO1995028671A1 PCT/US1994/004241 US9404241W WO9528671A1 WO 1995028671 A1 WO1995028671 A1 WO 1995028671A1 US 9404241 W US9404241 W US 9404241W WO 9528671 A1 WO9528671 A1 WO 9528671A1
Authority
WO
Grant status
Application
Patent type
Prior art keywords
controller
system
logic
cpu
bus
Prior art date
Application number
PCT/US1994/004241
Other languages
French (fr)
Inventor
Shyun Dii Du
Original Assignee
Green Logic Inc.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date

Links

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00Details not covered by groups G06F3/00 – G06F13/00 and G06F21/00
    • G06F1/26Power supply means, e.g. regulation thereof
    • G06F1/32Means for saving power
    • G06F1/3203Power Management, i.e. event-based initiation of power-saving mode
    • G06F1/3234Action, measure or step performed to reduce power consumption
    • G06F1/3293Power saving by switching to a less power consuming processor, e.g. sub-CPU
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00Details not covered by groups G06F3/00 – G06F13/00 and G06F21/00
    • G06F1/26Power supply means, e.g. regulation thereof
    • G06F1/32Means for saving power
    • G06F1/3203Power Management, i.e. event-based initiation of power-saving mode
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02DCLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THIR OWN ENERGY USE
    • Y02D10/00Energy efficient computing
    • Y02D10/10Reducing energy consumption at the single machine level, e.g. processors, personal computers, peripherals or power supply
    • Y02D10/12Reducing energy consumption at the single machine level, e.g. processors, personal computers, peripherals or power supply acting upon the main processing unit
    • Y02D10/122Low-power processors

Abstract

The present invention is a system logic controller ('SLC') (24) specially adapted for reducing and regulating a personal computer's ('PC's') (10) electrical power consumption. The PC (10) includes a CPU (12) and a direct port access buffer (82) between which the SLC (24) exchanges data that regulates the PC's power consumption. The SLC (24) reduces power consumption by low-power timed interval interrupt generators (142a, 142b through 142n). If the PC (10) enters a low-power 'suspend' operating mode in which the CPU (12) is turned off, the SLC (24) permits quickly resuming normal operation. If the PC (10) incorporating the improved SLC (24) includes a super I/O chip (54) and/or PCMCIA sockets (72), the SLC (24) permits higher speed operation both of a hard disk connected to the super I/O chip (54), and/or of high speed PCMCIA cards. Furthermore, the SLC (24) prevents the application of an excessively high voltage to PCMCIA cards if the PC enters its 'suspend' operating mode.

Description

AN IMPROVED SYSTEM LOGIC CONTROLLER FOR DIGITAL COMPUTERS

Technical Field

The present invention relates generally to the technical field of digital computers and, more particularly, to an im¬ proved, low-power system logic controller which provides facili¬ ties that permit easily regulating a computer's electrical power consumption, while concurrently permitting high performance.

Background Art

Present personal computers include an integrated circuit ("IC") central processing unit ("CPU") that is coupled by a high speed CPU bus having both CPU address lines and CPU data lines to various other ICs included in the computer. Such personal computers conventionally also include a slower speed I/O bus for exchanging signals with I/O cards that may be installed in the computer. Between the high-speed CPU bus and the slower-speed I/O bus these computers generally incorporate a system logic controller ("SLC") IC which performs various functions essential to the computer's operation including interfacing between the high-speed CPU bus and .the slower speed I/O bus. More specifi¬ cally, in the instance of IBM Personal Computers and clone personal computers which utilize Intel X86 IC microprocessors, the high-speed bus may be called a VESA Local Bus ("VLB") , and the slower speed I/O bus is generally either an Industry Standard Architecture ("ISA") bus or an Extended Industry Standard Architecture ("EISA") bus.

A system logic controller included in such a personal computer is coupled to the CPU address lines, CPU data lines, and CPU control lines included in the VLB, and to analogous signal lines in the I/O bus. Accordingly, the system logic controller includes a CPU interface controller for exchanging signals with the CPU bus. Usually, the system logic controller also includes a DRAM controller for generating RAS and CAS signals which are required to access dynamic random access memory ("DRAM") included in the computer, and 'for periodically refreshing the data stored in the DRAM. The system logic controller also includes an I/O bus controller which exchanges with I/O cards signals that are required to effect data transfers between an I/O device and the system logic controller and/or the DRAM. A system logic control¬ ler also includes a peripheral controller which performs a variety of functions also required to effect data transfers between the system logic controller and/or DRAM and I/O devices such as hard and floppy disk drives. The functions performed by the peripheral controller include receiving and storing inter¬ rupts, and effecting direct memory access ("DMA") data transfers between I/O devices and the DRAM. The peripheral controller also includes a clock into which the current date and time are stored when the computer is initialized, and by which the computer subsequently keeps time. The peripheral controller included in the system logic controller IC also includes counters which provides timing signals required for the DRAM controller's periodic refreshing of data stored in the DRAM. Frequently, a system logic controller also includes a battery powered, real¬ time clock which the personal computer reads upon initialization, i.e. "booting", in order to obtain the date and the time which is then stored into the clock within the peripheral controller. A book entitled "Intel's SL Architecture, Designing Portable Application" by Desmond Yuen, copyright 1993 by McGraw-Hill, Inc. , which is hereby incorporated by reference, provides a more thorough and detailed description of various facilities provided by and the various operation performed by a system logic control- Ier.

The traditional way of monitoring a number of different timed events in a digital computer is to assign a different timer for timing each different event. For example, one timer is assigned for timing keyboard events, a second timer is assigned for timing parallel port events, a third timer is assigned for timing display events,' etc. In such a computer system, each separate timer begins counting upon being enabled by a computer program's execution. When the count in the timer reaches a preset value, the timer generates an interrupt which notifies the computer program that some type of timed event needs to be serviced. For example, a timed event may turn off a portion of a battery powered computer to conserve electrical power. The disadvantage of this scheme is that as many timers are required as there are different events to be timed. Since, comparatively speaking, a timer consumes a significant amount of electrical power, every additional timer increases the computer's power consumption merely for counting an interval of time. The amount of power consumed by timers becomes substantial as the number of timed events increases.

To facilitate controlling power consumption in portable personal computers, Intel's 386 SL and 486 SL Enhanced IC microprocessors provide a System Management Mode ("SMM") of operation. SMM in these microprocessors provides a separate environment for the execution of power management routines that is completely independent of the environment in which the operating system and application programs execute. For such microprocessors, a special system management interrupt ("SMI") activates the SMM environment. When an SMI interrupt occurs, the microprocessor pauses execution of the current program, saves the internal data and states of the CPU to a preestablished memory location, e.g. 3000:0000h to 3000:FFFFh, enters SMM, and begins executing SMI routines stored in a dedicated system management random access memory ("SMRAM") . For Intel's 386 SL and 486 SL microprocessors, power management routines executed in SMM in response to specific SMIs may cause the personal computer to enter a "Suspend" mode of operation in which the computer consumes a lesser amount of electrical power because certain parts of the personal computer are turned off, e.g. the display and any backlighting for the display, the hard disk, the modem, etc. Subsequently, the microprocessor's execution of a resume operation restores power to, and thereby once again fully activates, the personal computer. In a particular "Suspend" mode of operation in which the CPU receives no electrical power, restoring the application program that was executing prior to commencing the "Suspend" operating mode is delayed until a hard disk drive included in the computer becomes fully operational, and data essential to resuming application program execution has been read from the hard disk.

There presently exist two different classes of IDE hard drives used in personal computers, those which are designed only to operate on the slower ISA Bus, and those which are designed to operate on the faster speed VLB. Present notebook computers frequently employ a single super I/O IC chip which provides elec¬ tronic circuits for a serial port, a parallel port, a floppy disk controller, and an interface for an IDE hard disk drive. How- ever, since such super I/O IC chips connect to the slower ISA bus, an IDE hard disk drive connected to the super I/O IC chip operates only at the slower ISA speeds, and cannot operate at the faster VLB speeds.

In addition to incorporating super I/O chips, present notebook computers frequently offer a Personal Computer Memory Card International Association ("PCMCIA") socket for receiving various different types of peripheral devices, e.g., modems, hard disk drives, "Flash" random access memory ("RAM") cards, etc. PCMCIA cards may operate at either five (5) volts or at three (3) volts. Each such PCMCIA card includes a Card Detect ("CD") pin and a 3V/5V pin. The CD pin permits a computer to detect insertion of a PCMCIA card into a PCMCIA socket. Upon insertion of a PCMCIA card into a computer's PCMCIA socket, a PCMCIA controller immediately interrogates the card's 3V/5V pin to determine whether the PCMCIA card being inserted operates at either 3 volts or 5 volts, and then provides the proper voltage to the PCMCIA card. However, if a notebook computer begins operating in its low power Suspend mode as described above, its PCMCIA controller is disabled. Consequently, if after the computer begins operating in Suspend mode the PCMCIA card is changed from a 5 volt card to a 3 volt card, the computer cannot sense this change. Under such circumstances, when the computer resumes operating in its higher power mode it will apply 5 volts, rather than the proper 3 volts, to the PCMCIA card. If 5 volt electrical power is applied to a 3 volt PCMCIA card, it is almost certain that the PCMCIA card will permanently damaged. Since PCMCIA cards are comparatively expensive, e.g. $250.00 for a modem which plugs into a PCMCIA socket, owners of PCMCIA cards can lose a significant financial investment if an excessively high voltage is applied to their PCMCIA card. Moreover, conventional PCMCIA controllers connect to the slower ISA Bus rather than the faster VLB. Consequently, the operating speed of any PCMCIA card plugged into a PCMCIA socket is limited to that of the ISA bus. However some of the devices, e.g. ROM or Flash memory, that are presently being incorporated into PCMCIA cards are capable of operating at the higher speed of the VLB. Presently, manufacturers of personal computers are experi- encing a continuing need to reduce electrical power consumption both for desk top computers and for notebook computers. Moreover, manufacturers are also experiencing a continuing demand for low-power notebook computers that provide performance equalling that of desktop computers. Since it is essential that any system logic controller capable of providing such improve¬ ments remain compatible with existing computer programs, the facilities which a system logic controller provides for managing the computer's electrical power consumption while concurrently facilitating construction of higher performance computers must remain compatible with facilities already present in contemporary personal computers, while at the same time solving technical problems which personal computer manufacturers encounter.

Disclosure of Invention The present invention provides an improved system logic controller having facilities that permit easily controlling a computer's electrical power consumption, while at the same time permitting assembly of higher performance computers.

An object of the present invention is to provide an easy way to access a direct port access buffer which stores data that regulates a computer's electrical power consumption.

Another object of the present invention is to provide a system logic controller integrated circuit chip having as few pins as practical. Another object of the present invention is to provide a system logic controller which permits assembling both a simpler and a more compact personal computer, while concurrently reducing the computer's manufacturing cost.

Another object of the present invention is to provide a system logic chip having low power consumption in those circuits which are necessary for effectively and efficiently regulating the computer's electrical power consumption. Another object of the present invention is to provide a Suspend mode of operation for the personal computer which consumes a small amount of power while swiftly resuming full operation. Another object of the present invention is to facilitate construction of a notebook computer capable of high performance. Another object of the present invention is to provide an interface to PCMCIA cards which under all circumstances prevents application of an excessively high voltage to the PCMCIA card. Yet another object of the present invention is to provide a system logic controller that facilitates assembly of an energy efficient personal computer offering high performance.

Briefly the preferred embodiment of the present invention is a digital computer which includes an improved system logic controller having an electrical power management unit. The power management unit generates a variety of different power management signals used in regulating electrical power consumed by the personal computer. To regulate electrical power consumption, the personal computer includes a direct port access buffer and the power management unit includes a direct port access controller for supplying direct port access control signals to the direct port access buffer. Signals supplied to the direct port access buffer by the direct port access controller cause power manage¬ ment data to be stored into or read from the direct port access buffer.

To effect a transfer of power management data between the personal computer's microprocessor and the direct port access buffer, upon receiving an I/O command from the microprocessor central processing unit ("CPU") that specifies an I/O operation between the CPU and the direct port access buffer, the system logic controller transmits a hold control signal to the CPU which requests that the CPU halt operation. In response to this halt request, the CPU halts operation and tristates all the CPU address lines. After the CPU has tristated all the CPU address lines, the direct port access controller transmits a direct port access control signal to the direct port access buffex- which causes an exchange of data between the direct port access buffer and the system logic controller over the CPU address lines. After the power management data has been exchanged between the direct port access buffer and the system logic controller, the system logic controller transmits a signal to the CPU which causes the CPU to resume operating. To provide low-power generation of timed interrupts which activate execution of power management routines by the CPU, the system logic controller includes a plurality of power management unit comparators each one of which respectively generates an independent power management timed interrupt. All of these power management unit comparators simultaneously receive the same timing signals generated by a single continuously running master clock which can be read by a computer program executed by the CPU. Furthermore, each of the power management unit comparators also includes a time data storage register into which the CPU may store time data representing a specific moment in time at which the power management unit comparator is to generate a power management timed interrupt. To generate the various power management interrupts at the proper times, each power management unit comparator continuously compares the timing signals which it receives from the master clock with the time data stored in the time data storage register, and generates a power management timed interrupt when the stored time data equals the timing signals.

A system logic controller in accordance with the present invention is also coupled to DRAM address lines, and the personal computer also includes DRAM that is coupled to the CPU data lines and to the DRAM address lines. In response to an initial SMI that specifies a particular Suspend mode of operation, the system logic controller provides a memory address to a first physical memory SMI data storage area in the DRAM for storage of all CPU internal data and states. After the CPU internal data and states have been stored into the first physical memory SMI data storage area, the system logic controller requests that the CPU execute a power management routine which first disables the first physical memory SMI data storage area so data cannot be stored into that area of the DRAM. The power management routine then establish a memory address to a second physical memory SMI data storage area into which CPU internal data and states will be stored in response to a subsequent system management interrupt. Finally, the power management routine preserves within the system logic controller SMI state information indicating that the system logic controller has caused the CPU internal data and states to be stored into the first physical memory SMI data storage area, and that the second physical memory SMI data storage area has been established for storage of CPU internal data and states in response to a subsequent system management interrupt. The system logic controller then places the personal computer in a power Suspend mode of operation in which it removes electrical power from the CPU while continuing to supply electrical power to the DRAM, and continuing to refresh the DRAM while awaiting an occurrence of a resume event. In response to a resume event, the system logic controller restores electrical power to the CPU, and resumes execution of the power management routine which detects the SMI state information preserved in the system logic control¬ ler. When the power management routine detects that SMI state information has been preserved in the system logic controller, it directs the system logic controller to generate a fake SMI to the CPU which causes the then existing CPU internal data and states to be stored into the second physical memory SMI data storage area, and initiates execution of the SMI routine. After the CPU internal data and states have been stored into the second physical memory SMI data storage area and upon the power management routine's detection that SMI state information has been preserved within the system logic controller, the power management routine disables the second physical memory SMI data storage area so data cannot be stored into or retrieved from that area of the DRAM. The power management routine then reestablish- es the memory address to the first physical memory SMI data storage area into which CPU internal data and states were stored in response to the initial system management interrupt. The Suspend mode of operation is then terminated immediately after which continued execution of the power management routine restores the CPU internal data and states to that previously stored into the first physical memory SMI data storage area.

If the personal computer incorporating the improved system logic controller in accordance with the present invention includes a super I/O chip, the I/O bus includes a first section over which the system logic controller and super I/O chip exchange signals, and a second section over which the system logic controller exchanges signals with I/O cards that may be included in the personal computer. A bidirectional I/O bus section isolation buffer, located between the first and second sections of the I/O bus, selectively isolates the second section of the I/O bus from the first section in response to an I/O bus isolation control signal generated by the system logic control- Ier. The system logic controller includes a hard disk access detection circuit for detecting I/O accesses to the super I/O chip's hard disk drive interface, and for transmitting the I/O bus isolation control signal to the I/O bus section isolation buffer. In response to the I/O bus isolation control signal, during access to the hard disk drive interface the I/O bus section isolation buffer isolates the second section of the I/O bus from the first section of the I/O bus. Thus, while the I/O bus section isolation buffer isolates the second section of the I/O bus from the first section, the system logic controller exchanges signals via the I/O bus with the super I/O chip at a faster speed so the personal computer may use a high speed rather than a slow speed IDE hard disk drive.

The improved system logic controller in accordance with the present invention includes a PCMCIA controller for exchanging data with a PCMCIA card inserted into a PCMCIA socket included in the personal computer. During normal operation of the personal computer, the power management unit included in the system logic controller generates power management signals which turn off the PCMCIA controller to reduce electrical power consumption, and subsequently generates power management signals which turn on the PCMCIA controller. These power management signals include a PCMCIA power restoration control signal transmitted from the power management unit to the PCMCIA controller which within the PCMCIA controller simulates an occurrence of the CD signal. Thus, every time the power management unit restores power to the PCMCIA controller, the PCMCIA controller determines if any PCMCIA card then present in the PCMCIA socket operates at the first lower voltage or at the second higher voltage. Furthermore, the improved system logic controller permits the PCMCIA controller to operate either at the speed of the I/O bus, e.g. ISA bus speed, or at a higher speed which can approach that of the CPU bus, e.g. the VLB speed. These and other features, objects and advantages will be understood or apparent to those of ordinary skill in the art from the following detailed description of the preferred embodiment as illustrated in the various drawing figures.

Brief Description of Drawings

FIG. 1 is a functional block diagram depicting a digital computer that incorporates a system logic controller in accor¬ dance with the present invention, and which illustrates PCMCIA sockets preferably included in such a digital computer; FIG. 2 is a functional block diagram depicting various functional units included in the system logic controller illustrated in FIG. 1 including a power management unit;

FIG. 3 is a functional block diagram illustrating several timed interrupt generators included in the power management unit illustrated in FIG. 2; and

FIG. 4 is a functional block diagram depicting PCMCIA sockets illustrated in FIG. 1.

Best Mode for Carrying Out the Invention FIG. 1 is a functional block diagram depicting a digital computer identified by the general reference character 10. The computer 10 includes an IC CPU 12 that is coupled to a high speed CPU bus 14, e.g. a VLB, having both CPU address lines 16 and CPU data lines 18. The CPU bus 14, which also includes CPU control signal lines 22, couples the CPU 12 to a IC system logic controller 24. The CPU address lines 16 of the CPU bus 14 also couple the CPU 12 to a DRAM 26. A DRAM address and control bus 32, which includes both DRAM address lines 34 and DRAM control signal lines 36, couples the system logic controller 24 to the DRAM 26.

I/O bus data lines 42 and I/O bus control signal lines 44 couple the system logic controller 24 to a first section 46 of an I/O bus 48, e.g. an ISA bus. A buffer 52 included in the computer 10 couples signals directly between the CPU address lines 16 and CPU data lines 18 of the CPU bus 14 and the first section 46 of the I/O bus 48. A single IC super I/O chip 54, which provides electronic circuits for a serial port, a parallel port, a floppy disk controller, and an interface for an IDE hard disk drive (none of which are illustrated in FIG. 1) , is also coupled to the first section 46 of the I/O bus 48. A bidirectional I/O bus section isolation buffer 56 couples the first section 46 of the I/O bus 48 to a second section 58 of the I/O bus 48 to which I/O cards (not illustrated in FIG. 1) may be coupled. The I/O bus control signal lines 44 also couple the system logic controller 24 to an IC keyboard controller 62 and to an IC read only memory ("ROM") BIOS 64. The keyboard controller 62 and the ROM BIOS 64 are also coupled to the second section 58 of the I/O bus 48.

To reduce electrical power consumption within the computer 10, those circuits within the system logic controller 24 which do not interface directly with the I/O bus data lines 42 and the I/O bus control signal lines 44 of the I/O bus 48 operate with only three (3) volts of electrical power. Conversely, those circuits within the system logic controller 24 which interface directly with the I/O bus data lines 42 and the I/O bus control signal lines 44 of the I/O bus 48 operate with five (5) volts of electrical power. To permit achieving an even greater reduction in electrical power consumption, the computer 10 preferably includes a 3V/5V buffer 66 that is coupled between the second section 58 of the I/O bus 48 and a 3V extension 68 of the I/O bus 48.

The computer 10 also includes PCMCIA sockets 72 that are coupled to the system logic controller 24 by the first section 46 of the I/O bus 48, and by a PCMCIA control signal bus 74.

To facilitate regulation of electrical power consumption by a computer program executed by the CPU 12, the computer 10 includes a direct port access buffer 82 that is coupled to the system logic controller 24 by the CPU address lines 16 of the CPU bus 14, and by direct port access control signal lines 84. A plurality of electrical power control signal lines 86 couple the direct port access buffer 82 to various other units of the computer 10 such as a display and any backlighting for the display, a hard disk, a floppy disk, a modem, etc. By storing appropriate data into the direct port access buffer 82, a computer program executed by the CPU 12 may turn such units of the computer 10 on or off thereby regulating electrical power consumption by the computer 10.

Referring now to the block diagram of FIG. 2 which illus¬ trates various functional units included in the system logic controller 24, the system logic controller 24 includes a CPU interface controller 102 that is coupled to the CPU address lines 16, to the CPU data lines 18, and to the CPU control signal lines 22 of the CPU bus 14. The system logic controller 24 also includes a DRAM controller 104 that is coupled to the DRAM address lines 34 and to the DRAM control signal lines 36. The I/O bus control signal lines 44 are coupled to an ISA bus controller 106 included in the system logic controller 24, while the I/O bus data lines 42 are coupled to a ISA bus address/data buffer 108. The system logic controller 24 includes a peripheral controller 112, and preferably includes a real-time clock 118 in accordance with the descriptions set forth herein above. A PCMCIA controller 122 included in the system logic controller 24 is coupled to the PCMCIA control signal bus 74, while a direct port access controller•126 included in a power management unit 128 of the system logic controller 24 is coupled to the direct port access control signal lines 84.

Within the system logic controller 24, SLC data lines 132 and SLC address lines 134 couple signals between the CPU interface controller 102 and the ISA bus address/data buffer 108, while SLC control lines 136 couple signals between the CPU interface controller 102 and the ISA bus controller 106. The SLC address lines 134 couple signals from the CPU interface control¬ ler 102 to the DRAM controller 104, while the SLC data lines 132 couple signals between the CPU interface controller 102 and both the real-time clock 118 and the peripheral controller 112. Thus, for example, the CPU 12 may read the date and time from the real-time clock 118 and then store them into memory locations within the DRAM 26. Analogously, via the SLC data lines 132 and the SLC control lines 136, the peripheral controller 112 may periodically increment the contents of the memory location in the DRAM 26 into which the time data has been stored. The SLC control lines 136 also couple signals between the CPU interface controller 102 and the peripheral controller 112 to permit transmission of interrupts from the peripheral controller 112 to the CPU 12, and to permit the computer program executed by the CPU 12 to control the operation of the peripheral controller 112. Periodically, the peripheral controller 112 transmits a timing signal to the DRAM controller 104 over a DRAM refresh timing signal line 138 which causes the DRAM controller 104 to refresh data stored in the DRAM 26. The SLC control lines 136 and the SLC data lines 132 couple signals between the CPU interface controller 102 and the'power management unit 128 including the direct port access controller 126. The SLC control lines 136 couple control signals between the CPU interface controller 102 and the PCMCIA controller 122 as does an extension of the I/O bus control signal lines 44 that is located within the system logic controller 24.

Direct Port Access

The power management unit 128 included in the system logic controller 24 provides a variety of functions which facilitate power reduction within the computer 10. For example, in addition to other features disclosed in greater detail herein, the power management unit 128 supports CPU clock modulation, detects if the CPU bus is idle, includes an analog-to-digital converter for monitoring battery voltage in a battery powered computer 10, and shadows write only registers. Specifically with regard to the direct port access buffer 82, the power management unit 128 provides a cost-effective method by which a computer program executed by the CPU 12 may store non time-critical power regulation data into or read non time-critical power regulation data from the direct port access buffer 82.

To store non time-critical power regulation data into the direct port access buffer 82, I/O Management Software ("IMS") for the direct port access buffer 82 executed by the CPU 12 transmits to the system logic controller 24 via the CPU bus 14 a write command for the address of the direct port access buffer 82. The system logic controller 24 receives the write command from the CPU 12, and latches the data value present on the CPU data lines 18 into a register within the system logic controller 24 (Not illustrated in FIG. 2.). The system logic controller 24 then asserts a HOLD control signal transmitted from the system logic controller 24 to the CPU 12 thereby requesting that the CPU 12 suspend its operation. After the CPU 12 suspends its operation, the CPU 12 transmits a HLDA (Hold Acknowledge) signal back to the system logic controller 24. Furthermore, concurrently with transmitting HLDA to the system logic controller 24, the CPU 12 tristates the CPU address lines 16. Upon receiving the HLDA signal, the system logic controller 24 then takes over the CPU address lines 16 to send the data from the register in the system logic controller 24 over the CPU address lines 16 to the direct port access buffer 82. To store the data from the system logic controller 24 into the direct port access buffer 82, the direct port access controller 126 first transmits a signal via the direct port access control signal lines 84 to the direct port access buffer 82 which cause the direct port access buffer 82 to receive the data from the CPU address lines 16. After the direct port access buffer 82 receives the data, the direct port access controller 126 transmits a pulse via the direct port access control signal lines 84 to the direct port access buffer 82 which causes the data on the CPU address lines 16 to be loaded into a register (Not separately depicted in FIG. 1) in the direct port access buffer 82 from which such data is transmitted via the electrical power control signal lines 86 to other units in the computer 10. After the data has been thus stored into the direct port access control signal lines 84, the system logic controller 24 removes the data from the CPU address lines 16 and negates the HOLD signal to the CPU 12 which then resumes operating.

To retrieve non time-critical power regulation data from the direct port access buffer 82, IMS for the direct port access buffer 82 executed by the CPU 12 transmits to the system logic controller 24 via the CPU bus 14 a read command for the address of the direct port access buffer 82. Upon receiving the read command from the CPU 12, the system logic controller 24 immedi¬ ately asserts an AHOLD control signal transmitted from the system logic controller 24 to the CPU 12. Upon receiving the AHOLD signal, the CPU 12 immediately suspends the current CPU cycle, and tristates the CPU address lines 16. The system logic controller 24 then takes over the CPU address lines 16 so it may read from the direct port access buffer 82. To retrieve data from the direct port access buffer 82 to the system logic controller 24, the direct port access controller 126 transmits control signals to the direct port access buffer 82 via the direct port access control signal lines 84 which cause the direct port access buffer 82 to place the data present in the direct port access buffer 82 onto the CPU address lines 16. The system logic controller 24 then reads the data from the CPU address lines 16 and latches the data into a register within the system logic controller 24 (Not illustrated in FIG. 2.). The system logic controller 24 then transmits control signals to the direct port access buffer 82 via the direct port access control signal lines 84 which cause the direct port access buffer 82 to disconnect from the CPU address lines 16. The system logic controller 24 then negates AHOLD, and at the same time places the data that has been stored in the register onto the CPU data lines 18 from which it will be read by the CPU 12. The system logic controller 24 then transmits a READY control signal to the CPU 12 thereby causing the CPU 12 to read the data from the CPU data lines 18. The CPU 12 then finishes the current cycle for the CPU bus 14, and resumes operating.

The direct port access buffer 82 of the present invention exchanges data with the system logic controller 24 over the CPU address lines 16 rather than the CPU data lines 18 of the CPU bus 14 to avoid placing any additional electrical load on the CPU data lines 18. Because the CPU data lines 18 carry high speed signals particularly between the CPU 12 and the DRAM 26, any additional electrical load resulting from an extension of the CPU data lines 18 to the direct port access buffer 82 could increase the difficulty of designing the computer 10. Conversely, signals present on the CPU address lines 16 are not as sensitive to additional electrical loading as those on the CPU data lines 18. Therefore, by using the. CPU address lines 16 for exchanging data between the system logic controller 24 and the direct port access buffer 82, the system logic controller 24 eases the difficulty of designing the computer 10. By using the CPU address lines 16 for exchanging data with the direct port access buffer 82, the system logic controller 24 also avoids increasing the number of pins on its IC package.

Low Power Timed Interval Interrupt Generators

The power management unit 128 included in the system logic controller 24 is capable of generating a number of independently timed interrupts that may be used in regulating electrical power consumption by the computer 10. FIG. 3 is a block diagram depicting several timed, interval interrupt generators 142a, 142b thru 142n in accordance with the present invention. Each of the timed interval interrupt generators 142a, 142b thru 142n receives timing signals from a continuously running master clock 144 via a timing signal lines 146. The master clock 144 has a compara¬ tively long interval, e.g. one hour or longer, and a computer program executed by the 12 may read the timing signals that are present on the timing signal lines 146 via the SLC data lines 132 included in the system logic controller 24. In addition to receiving timing signals from the master clock 144, each of the timed interval interrupt generators 142a, 142b thru 142n includes a timed interrupt output signal lines 148a, 148b thru 148n over which the timed interrupt generator 142a, 142b • • ■ 142n may transmit an interrupt to the CPU 12.

Within each of the timed interval interrupt generators 142a, 142b thru 142n, the timing signals present on the timing signal lines 146 are supplied to a first input of a timed event comparator 152. An output of each timed event comparator 152 is coupled to the timed interrupt output signal line 148a, 148b • • • 148n of the timed interrupt generator 142a, 142b • • • 142n to which the timed event comparator 152 belongs. Each of the timed interval interrupt generators 142a, 142b thru 142n also includes an interrupt time register 154 into which a computer program executed by the CPU 12 may store a numerical value via the SLC data lines 132 included in the system logic controller 24. In particular, the computer program executed by the CPU 12 stores a numerical value into the interrupt time register 154 which represents an instant in time at which the timed interrupt generator 142a, 142b • • 142n is to generate an interrupt. Each interrupt time register 154 supplies the numerical value which it holds to a second input of the timed event comparator 152 with which the interrupt time register 154 is associated. Each timed event comparator 152 continuously compares the number which it receives from its associated interrupt time register 154 with the timing signals that it receives from the master clock 144 via the timing signal lines 146. If the numerical value which the timed event comparator 152 receives from the interrupt time register 154 equals the timing signals that the timed event comparator 152 receives from the master clock 144, then the timed event comparator 152 transmits an interrupt signal on the timed interrupt output signal line 148a, 148b • • • 148n to which it is coupled.

To set the instant at which one of the timed interval interrupt generators l*42a, 142b thru 142n is to generate an interrupt, a computer program executed by the CPU 12 first reads the timing signals present on the timing signal lines 146 and adds to that time value the duration of a timed interval after which an interrupt is to occur. The computer program executed by the CPU 12 then stores the number thus computed into the appropriate interrupt time register 154 in a particular timed interrupt generator 142a, 142b • • • 142n. When the timing signals from the master clock 144 equal the numerical value stored in the interrupt time register 154, the timed interrupt generator 142a, 142b • • • 142n generates an interrupt which ultimately arrives at the CPU 12.

For example, if it were necessary to concurrently monitor both a hard disk drive and a parallel port in the manner summa¬ rized in the following table, then the sequence of operations set forth below performs that monitoring function.

Sequence Hard Disk Parallel Port Comment

Startl 00:15 00:15

Endl 00:45 00:50 Service

Start2 00:46 Done

End2 00:26 ( Rippled ) Service 1. A timer service routine executed by the CPU 12 receives a request to monitor both the hard disk and the parallel port to determine if any hard disk events occur during the next 30 minutes, or any parallel port events occur during the next 35 minutes.

2. The timer service routine executed by the CPU 12 first reads the master clock 144 which in the preceding example generates timing signals representing the time 00:15.

3. The timer service routine then: a. adds 30 minutes to the numerical value which it read from the master clock 144 to compute the instant at which a hard disk drive interrupt will occur, which in the preceding example is 00:45, and stores this numerical value into the interrupt time register 154 for a particular timed interrupt generator 142a, 142b

• • • 142n; and b. adds 35 minutes to the numerical value which it read from the master clock 144 to compute the instant at which a parallel port interrupt will occur, which in the preceding example is 00:50, and stores this numerical value into the interrupt time register 154 for a different timed interrupt generator 142a, 142b • • 142n.

4. The operating system executed by the CPU 12 then waits for an interrupt from the timed interval interrupt generators, e.g. 142a and 142b.

5. When the numerical value of the timing signals transmitted from the master clock 144 reach 00:45, the timed event comparator 152 receiving that numerical value from its associated interrupt time register 154 generates a hard disk interrupt that is transmitted to the CPU 12.

6. Upon receiving the hard disk interrupt, the operating system calls a hard disk interrupt service routine to service the interrupt. 7. During execution of the hard disk interrupt service rou¬ tine, that routine calls the timer service routine to set a 40 minute interval for the next hard disk interrupt. 8. The timer service routine again reads the master clock 144 which is presently generating a numerical value represent¬ ing the time 00:46.

9. The timer service routine adds 40 minutes to the numerical value read from the master clock 144 to compute the value

01:26, and then stores the value 00:26 into the interrupt time register 154 of the timed interrupt generator 142a, 142b • • • 142n that is generating timed interrupts for the hard disk. The value 00:26 is stored into that interrupt time register 154 rather than the value 01:26 because in this example the period of the master clock 144 is only one hour long.

10. The operating system then resumes waiting for the next interrupt from the timed interrupt generator 142a, 142b • • • 142n.

11. When the numerical value generated by the master clock 144 reaches 00:50, the timed event comparator 152 receiving that numerical value from its associated interrupt time register 154 generates a parallel port interrupt that is transmitted to the CPU 12.

12. Upon receiving the parallel port interrupt, the operating system calls a parallel port interrupt service routine to service the interrupt.

13. When the numerical value generated by the master clock 144 reaches 00:26, the timed event comparator 152 receiving that numerical value from its associated interrupt time register 154 generates a second hard disk interrupt that is transmitted to the CPU 12.

The timed interval interrupt generators 142a, 142b thru 142n as described above that are included in the system logic controller 24 consume a lesser amount of electrical power than an equal number of independent timers because a CMOS IC consumes electrical power in proportion to the number of circuits which change state (i.e. change from a 0 to a 1 or from a 1 to a 0) during some interval of time. Conversely, a modern CMOS IC maintaining a state consumes virtually no power. If separate timers were used for each event, then because each timer must continuously keep incrementing in order to keep time, each timer continuously consumes power. Conversely, in the present invention each of the timed interval interrupt generators 142a, 142b thru 142n consumes electrical power only when the timer service routine stores a numerical value into the interrupt time register 154, and when the timed event comparator 152 generates an interrupt because it detects coincidence between the numerical value that it receives from the master clock 144 and from its associated interrupt time register 154. Accordingly, the timed interval interrupt generators 142a, 142b thru 142n significantly reduce electrical power consumption by a system logic controller 24 which is concurrently timing a number of different events.

To facilitate generating a succession of interrupts each of which are separated by the same duration in time from the immedi- ately preceding and from the immediately succeeding interrupt, each of the timed inter-val interrupt generators 142a, 142b thru 142n preferably includes an interrupt interval register 156. Via the SLC data lines 132, a computer program executed by the CPU 12 may store a numerical value into the interrupt interval register 156 that represents a duration of time between succes¬ sive interrupts. Each of the timed interval interrupt generators 142a, 142b thru 142n also preferably includes an adder 158 having a first input which receives the numerical value present in the interrupt interval register 156. The interrupt time register 154 in each of the timed interval interrupt generators 142a, 142b thru 142n supplies the numerical value which it holds to a second input of the adder 158. The adder 158 in each of the timed interval interrupt generators 142a, 142b thru 142n stores the result of any addition operation back into the interrupt time register 154 from which it receives a numerical value. Each timed event comparator 152 supplies its output signal as a trigger signal to the adder 158 included in the timed interval interrupt generators 142a, 142b thru 142n to which it belongs. Accordingly, when a time a timed event comparator 152 generates an interrupt, the adder 158 with which it is associated adds together the numerical values present both in the interrupt interval register 156 and in the interrupt time register 154, and then stores the result of that addition back into the interrupt time register 154. Thus, if the numerical value stored in the interrupt interval register 156 is greater than zero, the timed interrupt generator 142a, 142b • • • 142n automatically generates a succession of interrupts each one of which follows the immediately preceding interrupt by a duration of time specified by the numerical value present in the interrupt interval register 156.

Two different methods may be employed with the timed interval interrupt generators 142a, 142b thru 142n for determin- ing which of several timed interrupt generator 142a, 142b • • • 142n generated an interrupt. The present invention is compatible with the traditional method employed with conventional multiple timer systems. In such a traditional system, the power manage¬ ment unit 128 includes a timed interrupts register 162 which receives the output signals from all of the timed interval interrupt generators 142a, 142b thru 142n via the timed interrupt output signal lines 148a, 148b thru 148n. With this alternative strategy for identifying the source of an interrupt, when a timed interrupt occurs, an interrupt service routine executed by the CPU 12 reads the state of all the timed interval interrupt generators 142a, 142b* thru 142n from the timed interrupts register 162 via the SLC data lines 132 to determine which one of several timed interval interrupt generators 142a, 142b thru 142n generated an interrupt. Alternatively, a specific device to be serviced in response to a timed interrupt may be identified if the timer service routine also stores the numerical value present in each interrupt time register 154 into a table which correlates the numerical value of an interrupt time with a device to be serviced at the specified time. When an interrupt occurs, the interrupt service routine first reads the value from the master clock 144 and compares it with the time values stored by the timer service routine into the table, and then services the device whose interrupt time value matches the time value read from the master clock 144. /// /// /// Suspend Mode Operation

In addition to a normal full-power operating mode, the system logic controller 24 is capable of placing the computer 10 into any one of three successively lower power operating modes to conserve electrical power. In the first power conservation mode called "sleep mode," the system logic controller 24 blocks the transmission of clock signals to all of the computer 10 except to the peripheral controller 112, the DRAM controller 104, and the real-time clock 118 included in the system logic controller 24, and to the DRAM 26. In the next lower power consumption operating mode called "5V Suspend," the system logic controller 24 also turns off electrical power to all of the computer 10 except to the peripheral controller 112, the DRAM controller 104, and the real-time clock 118 included in the system logic controller 24, and to the DRAM 26. Thus, in the 5V Suspend operating mode, the CPU 12 and the PCMCIA controller 122 receive no electrical power, and therefore loose all information about the state of the computer 10 which existed immediately before power is turned off. In the lowest power consumption operating mode called "0V Suspend," the system logic controller 24 turns off everything in the computer 10 except the real-time clock 118 included in the system logic controller 24. A computer program executed by the CPU 12 causes the system logic controller 24 to place the computer 10 into one of these three power conservation operating modes in response to an appropriate SMI interrupt.

The system logic controller 24in accordance with the present invention permits the operating system controlling the operation of the computer 10 to quickly resume operating after entering the 5V Suspend mode of operation in which electrical power is removed from the CPU 12. To permit quickly resuming operation of the computer 10, if a SMI interrupt occurs that specifies the 5V Suspend mode of operation, then the system logic controller 24 stores all CPU internal data and states to a first preestablished area in the DRAM 26, e.g. A000:XXXXh. After the CPU internal data and states have been stored into this first physical memory area, the system logic controller 24 transmits signals to the CPU 12 which request that a power management routine ("PMR") executed by the CPU 12:

1. disable the first physical memory area so data will no longer be stored into that area of the DRAM 26; and 2. establish an address to a second preestablished area in the DRAM 26, e.g. 3F000:XXXXh, into which the system logic controller 24 will store CPU internal data and states in response to a subsequent SMI that specifies a suspend mode of operation. Then the PMR stores information, e.g. sets a single bit, in the system logic controller 24 which records the occurrence of the preceding change in physical memory areas. After the PMR has stored this SMI state information into the system logic control¬ ler 24, the system logic controller 24 through data stored into the direct port access,buffer 82 turns off electrical power to the CPU 12 and other units included in the computer 10 while continuing to supply electrical power to the peripheral control¬ ler 112, to the DRAM controller 104, to the real-time clock 118, and to the DRAM 26, and while continuing to refresh the DRAM 26 while awaiting the occurrence of a resume event, e.g. opening of a notebook computer case or typing on the keyboard of the computer 10.

Upon the occurrence of a resume event, the system logic controller 24 restores electrical power to the CPU 12 thereby ultimately causing the CPU 12 to resume execution of the PMR. When the PMR which is executed in response to reapplying electrical power to the CPU 12 detects that the SMI state information has been stored in the system logic controller 24, that PMR then requests the system logic controller 24 to generate a "fake" SMI to the CPU 12 that specifies a suspend mode of operation. This "fake" SMI causes the then existing internal data and states of the CPU 12 to be stored into the second preestablished area in the DRAM 26, e.g. 3F000:XXXXh. After the system logic controller 24 has stored the CPU internal data and states into the second preestablished area in the DRAM 26 in response to the "fake" SMI, the PMR executed in response to the "fake" SMI detects that SMI state information has been preserved within the system logic controller 24. Upon detecting the SMI state information has been stored in the system logic controller 24, the PMR being executed by the CPU 12 in response to the "fake" SMI disables the second preestablished area in the DRAM 26, e.g. 3F000:XXXXh so data cannot be stored into or retrieved from that area, and .the PMR then reestablishes the first preestablished area in the DRAM 26, e.g. AOOO:XXXXh, into which CPU internal data and states were stored in response to the initial SMI. Upon reestablishment of the first preestablished area in the DRAM 26, the system logic controller 24 terminates the 5V Suspend mode of operation immediately after which execution of the PMR by the CPU 12 restores the CPU internal data and states to that previously stored in the first preestablished area in the DRAM 26 in response to the initial SMI.

By permitting the establishment of the second area in the DRAM 26 for the storage of the CPU internal data and states in response to the "fake" SMI, the system logic controller 24 permits restoring the operating state of the CPU 12 with only a few computer program instruction in comparison with the many computer program instructions that must be executed to retrieve CPU internal data and states stored on a hard disk. Furthermore, the use of the second preestablished area for the storage of CPU internal data and states when resuming operation avoids any need to save the first CPU internal data and states to a hard disk. By eliminating any need to access a hard disk for saving and restoring the CPU internal data and states, the 5V Suspend mode of operation disclosed above permits operation of the CPU 12 to be restored more quickly, and consumes a lesser amount of electrical energy in saving and restoring the CPU internal data and states. Finally, the present invention avoids any possibili- ty that there might be insufficient space available on the hard disk to store the initial CPU internal data and states.

High Speed IDE Hard Disk I/O

Referring now to FIG. 1, the system logic controller 24 of the present invention operates in conjunction with super I/O chip

54 to provide both an ISA bus speed interface to an IDE hard disk drive (Not depicted in any of the FIGs.) , or a higher speed interface to the IDE hard disk drive which approaches the speed of the VLB. To provide the higher speed interface to an IDE hard disk drive, the system logic controller 24 monitors the I/O device address to which a computer program executed by the CPU 12 attempts to read or write. If the CPU 12 attempts to access the IDE hard disk drive through the super I/O chip 54, then the system logic controller 24 exchanges signals between the CPU bus 14 and the I/O bus 48 at the higher speed rather than at the slower ISA bus speed. Since the super I/O chip 54 is capable of operating at the higher speed, the super I/O chip 54 passes the higher speed operation*of the I/O bus 48 directly onto the IDE hard disk drive. To prevent the higher speed signals present on the first section 46 of the I/O bus 48 from reaching I/O cards attached to the I/O bus 48, before accessing the IDE drive at higher speeds the system logic controller 24 transmits a control signal to the I/O bus section isolation buffer 56 which causes the I/O bus section isolation buffer 56 to isolate the second section 58 of the I/O bus 48 from the first section 46 of the I/O bus 48 while the system logic controller 24 operates the first section 46 of the I/O bus 48 at the speed of the CPU bus 14.

PCMCIA Over-Voltage Protection

Referring now to FIG. 2, because the system logic controller 24 of the present invention includes both the power management unit 128 and the PCMCIA controller 122, it can prevent damage to a PCMCIA card inserted into the PCMCIA sockets 72 when the computer 10 incorporating the system logic controller 24 chip resumes operating after having entered a 5V Suspend mode of operation such as that described herein above. The power management unit 128 included in the system logic controller 24 prevents the PCMCIA controller 122 from applying an excessively high voltage to the PCMCIA card by providing the PCMCIA control¬ ler 122 with a control signal when the computer 10 resumes operating in its higher power mode that is electrically equiva¬ lent to the signal provided to the PCMCIA controller 122 by the PCMCIA card's CD pin. Accordingly, immediately upon resuming operation in the higher power mode the control signal provided by the power management unit 128 to the PCMCIA controller 122 causes the PCMCIA controller 122 to interrogate the PCMCIA cards 3V/5V pin to determine the PCMCIA card's operating voltage, after which the PCMCIA controller 122 applies the proper voltage to the PCMCIA card.

High Speed Operation For PCMCIA Cards

Conventional PCMCIA controllers connect to the I/O bus 48. Consequently, the operating speed of any PCMCIA card plugged into a PCMCIA socket connected to such a PCMCIA controller is limited to the operating speed of the I/O bus 48. However some of the devices, e.g. Flash memory solid state disks, that are being incorporated into PCMCIA cards are capable of operating at much higher speeds than the speed of the I/O bus 48.

Fig. 4 depicts the preferred embodiment of the PCMCIA sockets 72 included in the computer 10. The PCMCIA sockets 72 preferably includes a Type 2 PCMCIA socket 172 and a Type 3 PCMCIA socket 174 either of which may receive an appropriate PCMCIA card (Not illustrated in any of the FIGs.). The PCMCIA control signal bus 74 connects directly in parallel to the PCMCIA sockets 172 and 174 for exchanging control signals therewith. Conversely, the first section 46 of the I/O bus 48 connects through bidirectional PCMCIA buffers 176 and 178 respectively to the PCMCIA sockets 172 and 174 for exchanging data signals therewith. Control signals supplied to the PCMCIA buffers 176 and 178 via the PCMCIA control signal bus 74 enable one or the other of the PCMCIA buffers 176 or 178 for exchanging signals between the I/O bus 48 and a PCMCIA card plugged into the PCMCIA socket 172 or into the PCMCIA socket 174.

To permit effective utilization of PCMCIA cards having a capacity to operate at speeds higher than the ISA bus speed, the ISA bus address/data buffer 108 detects the presence of such a PCMCIA card in either of the PCMCIA sockets 172 and 174. If the PCMCIA controller 122 detects that a PCMCIA card capable of operating only at the slower ISA bus speed is inserted into the PCMCIA sockets 72, then the PCMCIA controller 122 selects signals supplied to it by the system logic controller 24 to operate the PCMCIA card at the ISA bus speed. However, if the PCMCIA controller 122 detects that a PCMCIA card inserted in the PCMCIA sockets 72 is capable of operating at a higher speed, then the PCMCIA controller 122 selects signals supplied to it by the system logic controller 24 to operate the PCMCIA card at a faster bus speed, while the system logic controller 24 concurrently transmits a control signal to the I/O bus section isolation buffer 56 which causes the I/O bus section isolation buffer 56 to isolate the second section 58 of the I/O bus 48 from the first section 46 of the I/O bus 48.

Industrial Applicability By including the 3V/5V buffer 66 and the 3V extension 68 of the I/O bus 48, the computer 10 may further reduce power consumption by using three (3) volt ICs for the keyboard controller 62 and the ROM BIOS 64 which connect to the 3V extension 68 of the I/O bus 48 (Not illustrated in FIG. 1) instead of the five (5) volt ICs that are depicted in FIG. 1.

An essential element in the 5V Suspend operating mode provided by the system logic controller 24 is that after all the internal data and states of the CPU 12 have been stored into the first preestablished area in the DRAM 26 in response to the first SMI interrupt, the system logic controller 24 prevents overwrit¬ ing the data stored in that area of the DRAM 26 in response to a second fake SMI interrupt. While the preferred embodiment of the present invention prevents overwriting the data through the technique of providing a second preestablished area in the DRAM 26 for storage of the internal data and states of the CPU 12, the 5V Suspend operating mode disclosed herein is compatible with any alternative technique that prevents overwriting the internal data and states of the CPU 12 stored in the first preestablished area of the DRAM 26. Depending upon details of the design of the system logic controller 24, the master clock 144 may be a separate circuit included in the power management unit 128. Alternatively, if the system logic controller 24 includes the real-time clock 118 as in the preferred embodiment depicted in FIG. 2, then the real-time clock 118 may provide the timing signals via the timing signal lines 146 to each timed event comparator 152. The interrupt time register 154 included in each of the timed interval interrupt generators 142a, 142b thru 142n is preferably eight bits long. To permit generation of interrupts by the system logic controller 24 at intervals of time which differ by more than a factor of two hundred and fifty six (256) , lower order bits in the timing signals generated by the master clock 144 are supplied to the timed event comparator 152 included in some of the timed interval interrupt generators 142a, 142b thru 142n, while higher order bits in the timing signals are supplied to . the timed event comparator 152 included in other timed interval interrupt generators 142a, 142b thru 142n. Thus, the timed interval interrupt generators 142a, 142b thru 142n which receive the lower order bits of the timing signals may be used to generate interrupts for which the time interval is compara¬ tively short, while those timed interval interrupt generators 142a, 142b thru 142n which receive the higher order bits of the timing signals are used to generate interrupts for which the time interval is comparatively long.

In current practical application, the system logic control¬ ler 24 may operate an IDE drive through the super I/O chip 54 or may operate a PCMCIA card through the PCMCIA controller 122 at a clock speed between 12 and 24 MHz which is specified by configuration data supplied to the system logic controller 24.

Although the present invention has been described in terms of the presently preferred embodiment, it is to be understood that such disclosure i's purely illustrative and is not to be interpreted as limiting. Consequently, without departing from the spirit and scope of the invention, various alterations,

- modifications, and/or alternative applications of the invention will, no doubt, be suggested to those skilled in the art after having read the preceding disclosure. Accordingly, it is intended that the following claims be interpreted as encompassing all alterations, modifications, or alternative applications as fall within the true spirit and scope of the invention.

Claims

The ClaimsWhat is claimed is:
1. An improved system logic controller for use in a digital computer that includes a central processing unit which is coupled to a CPU bus having CPU address lines and CPU data lines, said system logic controller being coupled to the CPU address lines and to the CPU data lines, and including a CPU interface controller, a DRAM controller, a I/O bus controller, and a peripheral controller; wherein the improvement comprises: a direct port access buffer included in the digital computer that is coupled to the CPU address lines and which stores data for regulating electrical power consumption by the digital computer; a power management unit included in said system logic controller for generating power management signals used in regulating electrical power consumption by the digital computer, said power management unit including a direct port access controller for supplying direct port access control signals to the direct port access buffer; said system logic controller, upon receiving an I/O command from the central processing unit that specifies an I/O operation between the central processing unit and the direct port access buffer, transmitting a hold control signal to the central processing unit requesting that the central processing unit halt operation; the central processing unit, upon receiving the hold control signal from said system logic controller, halting operation and tristating the CPU address lines; after the central processing unit has tristated all the CPU address lines, the direct port access controller transmitting a direct port access control signal to the direct port access buffer which causes an exchange of data between the direct port access buffer and said system logic controller over the CPU address lines; and after data has been exchanged between the direct port access buffer and said system logic controller, said system logic controller transmitting a signal to the central processing unit which causes the central processing unit to resume operation.
2. The improved system logic controller of claim 1 wherein the I/O command received by said system logic controller from the central processing unit is a write command; upon said system logic controller receiving the write command from the central processing unit, said system logic controller reading and storing data placed on the CPU data lines by the central processing unit before said system logic controller transmits the hold control signal to the central processing unit; after said system logic controller transmits the hold control signal to the central processing unit and before said system logic controller exchanges data with the direct port access buffer, said system logic controller receiving a hold acknowledge signal from the central processing unit notifying said system logic controller that central processing unit operation has halted and that all the CPU address lines have been tristated; and said system logic controller then placing the data received from the central processing unit onto the CPU address lines while said direct port access controller transmits the direct port access control signal to the direct port access buffer which causes the direct port access buffer to latch the data present on the CPU address lines into the direct port access buffer.
3. The improved system logic controller of claim 1 wherein the I/O command received by said system logic controller from the central processing unit is a read command; said system logic controller upon receiving the read command from the central processing unit, transmitting the hold control signal from said system logic controller to the central processing unit which causes the central processing unit to immediately halt operating and tristate the CPU address lines; the direct port access control signal transmitted by the direct port access controller to the direct port access buffer causing the direct port access buffer to place data £hen present in the direct port access buffer onto the CPU address lines from which said system logic controller then reads and stores the data present on the CPU address lines; after said system logic controller has stored the data read from the CPU address lines, said system logic control¬ ler placing the data onto the CPU data lines and releases the hold control signal transmitted from said system logic controller to the central processing unit thereby permitting the central processing unit to read the data from the CPU data lines.
4. The improved system logic controller of claim 1 wherein said power management unit further includes a plurality of low- power timed interval interrupt generators each timed interval interrupt generator ^eing adapted for generating a power management timed interrupt for transmission from said system logic controller to the central processing unit, each timed interval interrupt generator including: a timed event comparator which respectively generates the power management timed interrupt, all of said timed event comparators in said power management unit si ulta- neously receiving timing signals generated by a single continuously running master clock, said system logic controller also permitting a computer program executed by the central processing unit to read the timing signals generated by the master clock; and an interrupt time register into which a computer program executed by the central processing unit may caused to be stored time data representing a specific moment in time at which said timed event comparator is to generate a power management timed interrupt, each timed event comparator continuously comparing the timing signals received from the master clock with the time data stored in the interrupt time register and generating a power manage¬ ment timed interrupt when the stored time data equals the timing signals.
5. The improved system logic controller of claim 4 wherein said system logic controller is also coupled to DRAM address lines; the digital computer also including a dynamic random access memory that is coupled to the CPU data lines and to the DRAM address lines; the central processing unit in response to a system management interrupt that specifies a suspend mode of operation, storing all CPU internal data and states to a preestablished area in the dynamic random access memory and then removing electrical power from the central processing unit; and in response to a resume event, restoring electrical power to the central processing unit after which the central processing unit executes another system management interrupt; wherein the improvement further comprises: upon the occurrence of an initial system management interrupt which specifies the suspend mode of operation said system logic controller: a. providing a memory address to a first physical memory SMI data storage area in the dynamic random access memory for storage of the CPU internal data and states in response to the initial system management interrupt, after the CPU internal data and* states have been stored into the first physical memory SMI data storage area, the central process- ing unit executing a SMI power management routine which: i. alters dynamic random access memory addressing by the system logic controller so the CPU internal data and states stored in the first physical memory SMI data storage area cannot be overwrit- ten; and ii. preserves within said system logic controller SMI state information indicating that said system logic controller has caused the CPU internal data and states to be stored into the first physical memory SMI data storage area, ; b. placing the digital computer in a power suspend mode of operation in which said system logic controller removes electrical power from the central processing unit while the system logic controller continues to supply electrical power to the dynamic random access memory and continues to refresh the dynamic random access memory while awaiting an occurrence of a resume event; c. after a resume event occurs, restoring electrical power to the central processing unit thereby resuming execution of a power management routine which, upon detec¬ ting that SMI state information has been stored in said system logic controller, directs said system logic control- Ier to generate a fake system management interrupt to the central processing unit; d. said system logic controller generating the fake system management interrupt thereby causing the central processing unit to resume executing the SMI power manage¬ ment routine which, upon detecting that SMI state informa¬ tion has been preserved within said system logic control¬ ler, restores dynamic random access memory addressing by the system logic controller to the first physical memory SMI data storage area into which CPU internal data and states were stored in response to the initial system management interrupt; and e. terminating the power suspend mode of operation immediately after which execution of the SMI power anage- ment routine by the central processing unit restores the CPU internal data and states to that previously stored in the first physical memory SMI data storage area.
6. The improved system logic controller of claim 5 wherein the digital computer also includes a super I/O chip that includes electronic circuits for providing a hard disk drive interface; said system logic controller being coupled by a first section of an I/O bus to the super I/O chip for exchanging signals with the super I/O chip, and being adapted for being coupled by a second section of the I/O bus for exchanging signals with other I/O cards that may be included in the digital computer, said system logic controller exchanging signals via the I/O bus with the super I/O chip and with other I/O cards that may be included in the digital computer at a slower I/O bus speed; wherein the digital computer further includes: a bidirectional I/O bus section isolation buffer disposed in the I/O bus between the first section of the I/O bus and the second section of the I/O bus for selectively isolating the second section of the I/O bus from the first section of the I/O bus in response to an I/O bus isolation control signal generated by said system logic controller; and wherein the improvement in said system logic controller further comprises: a hard disk access detection circuit for detecting I/O accesses by a computer program executed by the central processing unit to the hard disk drive interface included in the super I/O chip; said system logic controller during I/O accesses to the hard disk drive interface transmitting the I/O bus isolation control signal to the I/O bus section isolation buffer for isolating the second section of the I/O bus from the first section of the I/O bus, and while the I/O bus section isolation buffer isolates the second section of the I/O bus from the first section said system logic controller exchanging signals via the I/O bus with the super I/O chip at a faster CPU bus speed.
7. The improved system logic controller of claim 6 wherein said system logic controller further comprises a PCMCIA control- Ier; the PCMCIA controller being adapted for exchanging PCMCIA control signals with a PCMCIA card inserted into a PCMCIA socket included in the digital computer; while the PCMCIA controller is operating, the PCMCIA controller, in response to a CD signal generated upon insertion of a PCMCIA card into the PCMCIA socket, interrogating the PCMCIA card to determine if the PCMCIA card operates at a first lower voltage or at a second higher voltage; said power management^ unit included in said system logic controller generating power management signals which turn off the PCMCIA controller to reduce electrical power consumption by the digital computer, and subsequently generating power management signals which turn on the PCMCIA controller, such power manage¬ ment signals including a PCMCIA power restoration control signal transmitted from said power management unit to the PCMCIA controller which within the PCMCIA controller simulates an occurrence of the CD signal, whereby the PCMCIA controller deter¬ mines if any PCMCIA card then present in the PCMCIA socket operates at the first lower voltage or at the second higher voltage every time the power management signals turn the PCMCIA controller on.
8. The improved system logic controller of claim 7 wherein said system logic controller is coupled by a first section of the I/O bus to the PCMCIA socket for exchanging PCMCIA data signals with a PCMCIA card inserted in the PCMCIA socket; said PCMCIA controller detecting whether a PCMCIA card inserted into the PCMCIA socket possesses a speed capability for operating at the faster CPU bus speed of the CPU bus or is limited to operating at the slower I/O bus speed of the I/O bus; said system logic controller supplying signals to said PCMCIA controller which permit said PCMCIA controller to selectively operate a PCMCIA card inserted into the PCMCIA socket either at the slower I/O bus speed of the I/O bus or at the faster CPU bus speed of the CPU bus depending upon the speed capability of the PCMCIA card; said system logic controller including a PCMCIA card access detection circuit for detecting I/O accesses by a computer program executed by the central processing unit to a PCMCIA card inserted into the PCMCIA socket, and for transmitting the I/O bus isolation control signal to the I/O bus section isolation buffer for isolating the second section of the I/O bus from the first section of the I/O bus if said PCMCIA controller operates the PCMCIA card at the faster CPU bus speed.
9. The improved system logic controller of claim 1 wherein said system logic controller is also coupled to DRAM address lines; the digital computer also including a dynamic random access memory that is coupled to the CPU data lines and to the DRAM address lines; the central processing unit in response to a system management interrupt that specifies a suspend mode of operation, storing all CPU internal data and states to a preestablished area in the dynamic random access memory and then removing electrical power from the central processing unit; and in response to a resume event, restoring electrical power to the central processing unit after which the central processing unit executes another system management interrupt; wherein the improvement further comprises: upon the occurrence of an initial system management interrupt which specifies the suspend mode of operation said system logic controller: a. providing a memory address to a first physical memory SMI data storage area in the dynamic random access memory for storage of the CPU internal data and states in response to the initial system management interrupt, after the CPU internal data and. states have been stored into the first physical memory SMI data storage area, the central process¬ ing unit executing a SMI power management routine which: i. alters dynamic random access memory addressing by the system logic controller so the CPU internal data and states stored in the first physical memory SMI data storage area cannot be overwrit¬ ten; and ii. preserves within said system logic controller SMI state information indicating that said system logic controller has caused the CPU internal data and states to be stored into the first physical memory SMI data storage area, ; b. placing the digital computer in a power suspend mode of operation in which said system logic controller removes electrical power from the central processing unit while the system logic controller continues to supply electrical power to the dynamic random access memory and continues to refresh the dynamic random access memory while awaiting an occurrence of a resume event; c. after a resume event occurs, restoring electrical power to the central processing unit thereby resuming execution of a power management routine which, upon detec- ting that SMI state information has been stored in said system logic controller, directs said system logic control¬ ler to generate a fake system management interrupt to the central processing unit; d. said system logic controller generating the fake system management interrupt thereby causing the central processing unit to resume executing the SMI power manage¬ ment routine whicli, upon detecting that SMI state informa¬ tion has been preserved within said system logic control¬ ler, restores dynamic random access memory addressing by the system logic controller to the first physical memory SMI data storage area into which CPU internal data and states were stored in response to the initial system management interrupt; and e. terminating the power suspend mode of operation immediately after which execution of the SMI power manage¬ ment routine by the central processing unit restores the CPU internal data and states to that previously stored in the first physical memory SMI data storage area.
10. The improved system logic controller of claim 1 wherein the digital computer also includes a super I/O chip that includes electronic circuits for providing a hard disk drive interface; said system logic controller being coupled by a first section of an I/O bus to the super I/O chip for exchanging signals with the super I/O chip, and being adapted for being coupled by a second section of the I/O bus for exchanging signals with other I/O cards that may be included in the digital computer, said system logic controller exchanging signals via the I/O bus with the super I/O chip and with other I/O cards that may be included in the digital computer at a slower I/O bus speed; wherein the digital computer further includes: a bidirectional I/O bus section isolation buffer disposed in the I/O bus between the first section of the I/O bus and the second section of the I/O bus for selectively isolating the
* second section of the I/O bus from the first section of the I/O bus in response to an I/O bus isolation control signal generated by said system logic controller; and wherein the improvement in said system logic controller further comprises: a hard disk access detection circuit for detecting I/O accesses by a computer program executed by the central processing unit to the hard disk drive interface included in the super I/O chip; said system logic controller during I/O accesses to the hard disk drive interface transmitting the I/O bus isolation control signal to the I/O bus section isolation buffer for isolating the second section of the I/O bus from the first section of the I/O bus, and while the I/O bus section isolation buffer isolates the second section of the I/O bus from the first section said system logic controller exchanging signals via the I/O bus with the super I/O chip at a faster CPU bus speed.
11. The improved system logic controller of claim 1 wherein said system logic controller further comprises a PCMCIA control¬ ler; the PCMCIA controller being adapted for exchanging data with a PCMCIA card inserted into a PCMCIA socket included in the digital computer; while the PCMCIA controller is operating, the PCMCIA controller, in response to a CD signal generated upon insertion of a PCMCIA card into the PCMCIA socket, interrogating the PCMCIA card to determine if the PCMCIA card operates at a first lower voltage or at a second higher voltage; said power management unit included in said system logic controller generating power management signals which turn off the PCMCIA controller to reduce electrical power consumption by the digital computer, and subsequently generating power management signals which turn on the PCMCIA controller, such power management signals including a PCMCIA power restoration control signal transmitted from said power management unit to the PCMCIA controller which within the PCMCIA controller simulates an occurrence of the CD signal, whereby the PCMCIA controller determines if any PCMCIA card then present in the PCMCIA socket operates at the first lower voltage or at the second higher voltage every time the power management signals turn the PCMCIA controller on.
12. The improved system logic controller of claim 1 wherein said system logic controller is adapted for being coupled by a first section of an I/O bus to a PCMCIA socket included in the digital computer for exchanging PCMCIA data signals with a PCMCIA card inserted in a PCMCIA socket, and is also adapted for being coupled by a second section of the I/O bus for exchanging signals with other I/O cards that may be included in the digital computer with which said system logic controller exchanges signals via the I/O bus at a slower I/O bus speed; and wherein the digital computer further includes: a bidirectional I/O bus section isolation buffer disposed in the I/O bus between the first section of the I/O bus and the second section of the I/O bus for selectively isolating the second section of the I/O bus from the first section of the I/O bus in response to an I/O bus isolation control signal generated by said system logic controller; said system logic controller further comprising a PCMCIA controller adapted for exchanging PCMCIA control signals with a PCMCIA card inserted into the PCMCIA socket; said PCMCIA controller detecting whether a PCMCIA card inserted into the PCMCIA socket possesses a speed capability for operating at a faster CPU bus speed of the CPU bus or is limited to operating at the slower I/O bus speed of the I/O bus; said system logic controller including a PCMCIA card access detection circuit for detecting I/O accesses by a computer program executed by the central processing unit to a PCMCIA card inserted into the PCMCIA socket, and supplying signals to said PCMCIA controller which permit said PCMCIA controller to selectively operate a PCMCIA card inserted into the PCMCIA socket either at the slower I/O bus speed of the I/O bus or at the faster CPU bus speed of the CPU bus depending upon the speed capability of the PCMCIA card; said system logic controller transmitting the I/O bus isolation control signal to the I/O bus section isolation buffer for isolating the second section of the I/O bus from the first section of the I/O bus if said PCMCIA controller operates the PCMCIA card at the faster CPU bus speed.
13. An improved system logic controller for use in a digital computer that includes a central processing unit which is coupled to a CPU bus having CPU address lines and CPU data lines; said system logic controller being coupled to the CPU address lines and to the CPU data lines, and including a CPU interface controller, a DRAM controller, a I/O bus controller, and a peripheral controller; wherein the improvement comprises: a power management unit included in said system logic controller for generating power management signals used in regulating electrical power consumption by the digital computer, said power management unit including a plurality of low-power timed interval interrupt generators each timed interval interrupt generator being adapted for generating a power management timed interrupt for transmission from said system logic controller to the central processing unit, each timed interval interrupt generator including: a timed event comparator which respectively generates the power management timed interrupt, all of said timed event comparators in said power management unit simulta¬ neously receiving* timing signals generated by a single continuously running master clock, said system logic controller also permitting a computer program executed by the central processing unit to read the timing signals generated by the master clock; and an interrupt time register into which a computer program executed by the central processing unit may caused to be stored time data representing a specific moment in time at which said timed event comparator is to generate a power management timed interrupt, each timed event comparator continuously comparing the timing signals received from the master clock with the time data stored in the interrupt time register and generating a power manage¬ ment timed interrupt when the stored time data equals the timing signals.
14. The improved system logic controller of claim 13 wherein said power management unit includes the master clock that supplies the timing signals received by all said timed event comparators.
15. The improved system logic controller of claim 13 wherein said system logic controller includes a real time clock that supplies the timing signals received by all said timed event comparators.
16. The improved system logic controller of claim 13 further comprising a timed interrupts register that may be read by a computer program executed by the central processing unit, said timed interrupts register concurrently storing the several power management timed interrupts generated by all said timed event comparators included in said timed interval interrupt generator.
17. The improved system logic controller of claim 13 wherein each timed interval interrupt generator further includes: a plurality of interrupt interval registers into which a computer program executed by the central processing unit may cause to be stored time data representing a duration of time between immediately successive powermanagement timed interrupts; and an adder having a first input which receives from said interrupt interval registers the data representing a duration of time between immediately successive interrupts, said adder also having a second input which receives from said interrupt time register the data representing a specific moment in time at which said timed event comparator is to generate a power management timed interrupt, said adder also having an adder output which supplies a result of any addition performed by said adder to said interrupt time register, said adder also receiving a trigger signal from said timed event comparator every time said timed event comparator generates the power management timed interrupt in response to which said adder adds together the data present in said interrupt interval registers and in said interrupt time register and stores the result of such addition back into said interrupt time register, whereby said timed interval interrupt generator generates a succession of power management timed interrupts each immediately successive pair of which are separated by the same duration of time.
18. An improved system logic controller for use in a digital computer that includes a central processing unit which is coupled to a CPU bus having CPU address lines and CPU data lines; said system logic controller being coupled to the CPU address lines, to the CPU data lines and to DRAM address lines, and including a CPU interface controller, a DRAM controller, a I/O bus controller, and a peripheral controller; the digital computer also including a dynamic random access memory that is coupled to the CPU data lines and to the DRAM address lines; the central processing unit in response to a system management interrupt that specifies a suspend mode of operation, storing all CPU internal data and states to a preestablished area in the dynamic random access memory and then removing electrical power from the central processing unit; and in response to a resume event, restoring electrical power to the central processing unit after which the central processing unit executes another system management interrupt; wherein the improvement comprises: upon the occurrence of an initial system management interrupt which specifies the suspend mode of operation said system logic controller: a. providing a memory address to a first physical memory SMI data storage area in the dynamic random access memory for storage of the CPU internal data and states in response to the initial system management interrupt, after the CPU internal data and states have been stored into the first physical memory SMI data storage area, the central process- ing unit executing a SMI power management routine which: i. alters dynamic random access memory addressing by the system logic controller so the CPU internal data and states stored in the first physical memory SMI data storage area cannot be overwrit- ten; and ii. preserves within said system logic controller SMI state information indicating that said system logic controller has caused the CPU internal data and states to be stored into the first physical memory SMI data storage area, ; b. placing the digital computer in a power suspend mode of operation in which said system logic controller removes electrical power from the central processing unit while the system logic controller continues to supply electrical power to the dynamic random access memory and continues to refresh the dynamic random access memory while awaiting an occurrence of a resume event; c. after a resume event occurs, restoring electrical power to the central processing unit thereby resuming execution of a power management routine which, upon detec¬ ting that SMI state information has been stored in said system logic controller, directs said system logic control- Ier to generate a fake system management interrupt to the central processing unit; d. said system logic controller generating the fake system management interrupt thereby causing the central processing unit to resume executing the SMI power manage¬ ment routine which, upon detecting that SMI state informa¬ tion has been preserved within said system logic control¬ ler, restores dynamic random access memory addressing by the system logic controller to the first physical memory SMI data storage area into which CPU internal data and states were stored in response to the initial system management interrupt; and e. terminating the power suspend mode of operation immediately after which execution of the SMI power manage- ment routine by the central processing unit restores the CPU internal data and states to that previously stored in the first physical memory SMI data storage area.
19. The improved system logic controller of claim 18 wherein said system logic controller: a. alters dynamic random access memory addressing by establishing a memory address to a second physical memory SMI data storage area into which CPU internal data and states will be stored in response to a subsequent system management interrupt thereby pre¬ venting overwriting of the CPU internal data and states stored in response to the initial system management interrupt; and b. upon the occurrence of the fake system management interrupt, causing the then existing CPU internal data and states to be stored into the second physical memory SMI data storage area.
20. An improved system logic controller for use in a digital computer that includes a central processing unit which is coupled to a CPU bus having CPU address lines and CPU data lines, the digital computer also including a super I/O chip that includes electronic circuits for providing a hard disk drive interface; said system logic controller including a CPU interface controller, a DRAM controller, a I/O bus controller, and a peripheral controller, and said system logic controller being coupled to the CPU address lines and to the CPU data lines, and also being adapted for being coupled by a first section of an I/O bus to the super I/O chip for exchanging signals with the super I/O chip, and also being adapted for being coupled by a second section of the I/O bus for exchanging signals with other I/O cards that may be included in the digital computer; said system logic controller exchanging signals via the I/O bus with the super I/O chip and with other I/O cards that may be included in the digital computer at a slower I/O bus speed; wherein the digital computer further includes: a bidirectional I/O bus section isolation buffer disposed in the I/O bus between the first section of the I/O bus and the second section of the I/O bus for selectively isolating the second section of the I/O bus from the first section of the I/O bus in response to an I/O bus isolation control signal generated by said system logic controller; and wherein the improvement in said system logic controller comprises: a hard disk access detection circuit for detecting I/O accesses by a computer program executed by the central processing unit to the hard disk drive interface included in the super I/O chip; said system logic controller during I/O accesses to the hard disk drive interface transmitting the I/O bus isolation control signal to the I/O bus section isolation buffer for isolating the second section of the I/O bus from the first section of the I/O bus, and while the I/O bus section isolation buffer isolates the second section of the I/O bus from the first section said system logic controller exchanging signals via the I/O bus with the super I/O chip at a faster CPU bus speed.
21. The improved system logic controller of claim 20 wherein the hard disk drive interface included in the super I/O chip is an IDE hard disk drive interface.
22. An improved system logic controller for use in a digital computer that includes a central processing unit which is coupled to a CPU bus having CPU address lines and CPU data lines; said system logic controller being coupled to the CPU address lines and to the CPU data lines, and including a CPU interface controller, a DRAM controller, a I/O bus controller, and a peripheral controller; wherein the improvement comprises: both a power management unit and a PCMCIA controller included in said system logic controller; the PCMCIA controller being adapted for exchanging data with a PCMCIA card inserted into a PCMCIA socket included in the digital computer; while the PCMCIA controller is operating, the PCMCIA controller, in response to a CD signal generated upon insertion of a PCMCIA card into the PCMCIA socket, interrogating the PCMCIA card to determine if the PCMCIA card operates at a first lower voltage or at a second higher voltage; said power management unit generating power management signals which turn off the PCMCIA controller to reduce electrical power consumption by the digital computer, and subsequently generating power management signals which turn on the PCMCIA controller, such power management signals including a PCMCIA power restoration control signal transmitted from said power management unit to the PCMCIA controller which within the PCMCIA controller simulates an occurrence of the CD signal, whereby the PCMCIA controller determines if any PCMCIA card then present in the PCMCIA socket operates at the first lower voltage or at the second higher voltage every time the power management signals turn the PCMCIA controller on.
23. An improved system logic controller for use in a digital computer that includes a central processing unit which is coupled to a CPU bus having CPU address lines and CPU data lines; said system logic controller being coupled to the CPU address lines and to the CPU data lines, and including a CPU interface controller, a DRAM controller, a I/O bus controller, and a peripheral controller; wherein the improvement further comprises: said system logic controller being adapted for being coupled by a first section of an I/O bus to a PCMCIA socket included in the digital computer for exchanging PCMCIA data signals with a PCMCIA card inserted in a PCMCIA socket, and also being adapted for being coupled by a second section of the I/O bus for exchanging signals with other I/O cards that may be included in the digital computer with which said system logic controller exchanges signals via the I/O bus at a slower I/O bus speed; and wherein the digital computer further includes: a bidirectional I/O bus section isolation buffer disposed in the I/O bus between the first section of the I/O bus and the second section of the I/O bus for selectively isolating the second section of the I/O bus from the first section of the I/O bus in response to an I/O bus isolation control signal generated by said system logic controller; said system logic controller further comprising a PCMCIA controller adapted for exchanging PCMCIA control signals with a PCMCIA card inserted into the PCMCIA socket; said PCMCIA controller detecting whether a PCMCIA card inserted into the PCMCIA socket possesses a speed capability for operating at a faster CPU bus speed of the CPU bus or is limited to operating at the slower I/O bus speed of the I/O bus; said system logic controller including a PCMCIA card access detection circuit for detecting I/O accesses by a computer program executed by the central processing unit to a PCMCIA card inserted into the PCMCIA socket, and supplying signals to said PCMCIA controller which permit said PCMCIA controller to selectively operate a PCMCIA card inserted into the PCMCIA socket either at the slower I/O bus speed of the I/O bus or at the faster CPU bus speed of the CPU bus depending upon the speed capability of the PCMCIA card; said system logic controller transmitting the I/O bus isolation control signal to the I/O bus section isolation buffer for isolating the second section of the I/O bus from the first section of the I/O bus- if said PCMCIA controller operates the PCMCIA card at the faster CPU bus speed.
24. An improved digital computer that includes a central processing unit which is coupled to a CPU bus having CPU address lines and CPU data lines, said digital computer also including a system logic controller that is coupled to the CPU address lines and to the CPU data lines, the system logic controller including a CPU interface controller, a DRAM controller, a I/O bus controller, and a peripheral controller, wherein the improvement comprises: a direct port access buffer that is coupled to the CPU address lines and which stores data for regulating electrical power consumption by the digital computer; and a power management unit included in said system logic controller for generating power management signals used in regulating electrical power consumption by the digital computer, said power management unit including a direct port access controller for supplying direct port access control signals to the direct port access buffer; said system logic controller, upon receiving an I/O command from the central processing unit that specifies an I/O operation between the central processing unit and the direct port access buffer, transmitting a hold control signal to the central processing unit requesting that the central processing unit halt operation; the central processing unit, upon receiving the hold control signal from said system logic controller, halting operation and tristating the CPU address lines; after the central processing unit has tristated all the CPU address lines, the direct port access controller transmitting a direct port access control signal to the direct port access buffer which causes an exchange of data between the direct port access buffer and said system logic controller over the CPU address lines; and after data has been exchanged between the direct port access buffer and said system logic controller, said system logic controller transmitting a signal to the central processing unit which causes the central processing unit to resume operation.
25. The improved digital computer of claim 24 wherein the I/O command received by said system logic controller from the central processing unit is a write command; upon said system logic controller receiving the write command from the central processing unit, said system logic controller reading and storing data placed on the CPU data lines by the central processing unit before said system logic controller transmits the hold control signal to the central processing unit; after said system logic controller transmits the hold control signal to the central processing unit and before said system logic controller exchanges data with the direct port access buffer, said system logic controller receiving a hold acknowledge signal from the central processing unit notifying said system logic controller that central processing unit operation has halted and that all the CPU address lines have been tristated; and said system logic controller then placing the data received from the central processing unit onto the CPU address lines while said direct port access controller transmits the direct port access control signal to the direct port access buffer which causes the direct port access buffer to latch the data present on the CPU address lines into the direct port access buffer.
26. The improved digital computer of claim 24 wherein the I/O command received by said system logic controller from the central processing unit is a read command; said system logic controller upon receiving the read command from the central processing unit, transmitting the hold control signal from said system logic controller to the central processing unit which causes the central processing unit to immediately halt operating and tristate the CPU address lines; the direct port access control signal transmitted by the direct port access controller to the direct port access buffer causing the direct port access buffer to place data then present in the direct port access buffer onto the CPU address lines from which said system logic controller then reads and stores the data present on the CPU address lines; after said system logic controller has stored the data read from the CPU address lines, said system logic control¬ ler placing the data onto the CPU data lines and releases the hold control signal transmitted from said system logic controller to the central processing unit thereby permitting the central processing unit to read the data from the CPU data lines.
27. The improved digital computer of claim 24 wherein said power management unit further includes a plurality of low-power timed interval interrupt generators each timed interval interrupt generator being adapted for generating a power management timed interrupt for transmission from said system logic controller to the central processing unit, each timed interval interrupt generator including: a timed event comparator which respectively generates the power management timed interrupt, all of said timed event comparators in said power management unit simulta¬ neously receiving timing signals generated by a single continuously running master clock, said system logic controller also permitting a computer program executed by the central processing unit to read the timing signals generated by the master clock; and an interrupt time register into which a computer program executed by the central processing unit may caused to be stored time data representing a specific moment in time at which said timed event comparator is to generate a power management timed interrupt, each timed event comparator continuously comparing the timing signals received from the master clock with the time data stored in the interrupt time register and generating a power manage¬ ment timed interrupt when the stored time data equals the timing signals.
28. The improved digital computer of claim 24 wherein said system logic controller is also coupled to DRAM address lines; the digital computer also including a dynamic random access memory that is coupled to the CPU data lines and to the DRAM address lines; the central processing unit in response to a system management interrupt that specifies a suspend mode of operation, storing all CPU internal data and states to a preestablished area in the dynamic random access memory and then removing electrical power from the central processing unit; and in response to a resume event, restoring electrical power to the central processing unit after which the central processing unit executes another system management interrupt; wherein the improvement further comprises: upon the occurrence of an initial system management interrupt which specifies the suspend mode of operation said system logic controller: a. providing a memory address to a first physical memory SMI data storage area in the dynamic random access memory for storage of the# CPU internal data and states in response to the initial system management interrupt, after the CPU internal data and states have been stored into the first physical memory SMI data storage area, the central process¬ ing unit executing a SMI power management routine which: i. alters dynamic random access memory addressing by the system logic controller so the CPU internal data and states stored in the first physical memory SMI data storage area cannot be overwrit¬ ten; and ii. preserves within said system logic controller SMI state information indicating that said system logic controller has caused the CPU internal data and states to be stored into the first physical memory SMI data storage area, ; b. placing the digital computer in a power suspend mode of operation in which said system logic controller removes electrical power from the central processing unit while the system logic controller continues to supply electrical power to the dynamic random access memory and continues to refresh the dynamic random access memory while awaiting an occurrence of a resume event; c. after a resume event occurs, restoring electrical power to the central processing unit thereby resuming execution of a power management routine which, upon detec¬ ting that SMI state information has been stored in said system logic controller, directs said system logic control- Ier to generate a fake system management interrupt to the central processing unit; d. said system logic controller generating the fake system management' interrupt thereby causing the central processing unit to resume executing the SMI power manage¬ ment routine which, upon detecting that SMI state informa¬ tion has been preserved within said system logic control¬ ler, restores dynamic random access memory addressing by the system logic controller to the first physical memory SMI data storage area into which CPU internal data and states were stored in response to the initial system management interrupt; and e. terminating the power suspend mode of operation immediately after which execution of the SMI power manage¬ ment routine by the central processing unit restores the CPU internal data and states to that previously stored in the first physical memory SMI data storage area.
29. The improved digital computer of claim 24 wherein the digital computer also includes a super I/O chip that includes electronic circuits for providing a hard disk drive interface; said system logic controller being coupled by a first section of an I/O bus to the super I/O chip for exchanging signals with the super I/O chip, and being adapted for being coupled by a second section of the I/O bus for exchanging signals with other I/O cards that may be included in the digital computer, said system logic controller exchanging signals via the I/O bus with the super I/O chip and with other I/O cards that may be included in the digital computer at a slower I/O bus speed; wherein the digital computer further includes: a bidirectional I/O bus section isolation buffer disposed in the I/O bus between 'the first section of the I/O bus and the second section of the I/O bus for selectively isolating the second section of the I/O bus from the first section of the I/O bus in response to an I/O bus isolation control signal generated by said system logic controller; and wherein the improvement in said system logic controller further comprises: a hard disk access detection circuit for detecting I/O accesses by a computer program executed by the central processing unit to the hard disk drive interface included in the super I/O chip; said system logic controller during I/O accesses to the hard disk drive interface transmitting the I/O bus isolation control signal to the I/O bus section isolation buffer for isolating the second section of the I/O bus from the first section of the I/O bus, and while the I/O bus section isolation buffer isolates the second section of the I/O bus from the first section said system logic controller exchanging signals via the I/O bus with the super I/O chip at a faster CPU bus speed.
30. The improved digital computer of claim 24 wherein said system logic controller further comprises a PCMCIA controller; the PCMCIA controller being adapted for exchanging data with a PCMCIA card inserted into a PCMCIA socket included in the digital computer; while the PCMCIA controller is operating, the PCMCIA controller, in response to a CD signal generated upon insertion of a PCMCIA card into the PCMCIA socket, interrogating the PCMCIA card to determine if the PCMCIA card operates at a first lower voltage or at a second higher voltage; said power management unit included in said system logic controller generating power management signals which turn off the PCMCIA controller to reduce electrical power consumption by the digital computer, and subsequently generating power management signals which turn on the PCMCIA controller, such power management signals including a PCMCIA power restoration control signal transmitted from said power management unit to the PCMCIA controller which within the PCMCIA controller simulates an occurrence of the CD signal, whereby the PCMCIA controller determines if any PCMCIA card then present in the PCMCIA socket operates at the first lower voltage or at the second higher voltage every time the power management signals turn the PCMCIA controller on.
31. The improved digital computer of claim 24 wherein said system logic controller is adapted for being coupled by a first section of an I/O bus to a PCMCIA socket included in the digital computer for exchanging PCMCIA data signals with a PCMCIA card inserted in a PCMCIA socket, and is also adapted for being coupled by a second section of the I/O bus for exchanging signals with other I/O cards that may be included in the digital computer with which said system logic controller exchanges signals via the I/O bus at a slower I/O bus speed; and wherein the digital computer further includes: a bidirectional I/O bus section isolation buffer disposed in the I/O bus between the first section of the I/O bus and the second section of the I/O bus for selectively isolating the second section of the I/O bus from the first section of the I/O bus in response to an I/O bus isolation control signal generated by said system logic controller; said system logic controller further comprising a PCMCIA controller adapted for exchanging PCMCIA control signals with a PCMCIA card inserted into the PCMCIA socket; said PCMCIA controller detecting whether a PCMCIA card inserted into the PCMCIA socket possesses a speed capability for operating at a faster CPU bus speed of the CPU bus or is limited to operating at the slower I/O bus speed of the I/O bus; said system logic controller including a PCMCIA card access detection circuit for detecting I/O accesses by a computer program executed by the central processing unit to a PCMCIA card inserted into the PCMCIA socket, and supplying signals to said PCMCIA controller which permit said PCMCIA controller to selectively operate a PCMCIA card inserted into the PCMCIA socket either at the slower I/O bus speed of the I/O bus or at the faster CPU bus speed of the CPU bus depending upon the speed capability of the PCMCIA card; said system logic controller transmitting the I/O bus isolation control signal to the I/O bus section isolation buffer for isolating the second section of the I/O bus from the first section of the I/O bus if said PCMCIA controller operates the PCMCIA card at the faster CPU bus speed.
PCT/US1994/004241 1994-04-18 1994-04-18 An improved system logic controller for digital computers WO1995028671A1 (en)

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US9037807B2 (en) 2001-03-05 2015-05-19 Pact Xpp Technologies Ag Processor arrangement on a chip including data processing, memory, and interface elements
US9075605B2 (en) 2001-03-05 2015-07-07 Pact Xpp Technologies Ag Methods and devices for treating and processing data
US9092595B2 (en) 1997-10-08 2015-07-28 Pact Xpp Technologies Ag Multiprocessor having associated RAM units
US9141390B2 (en) 2001-03-05 2015-09-22 Pact Xpp Technologies Ag Method of processing data with an array of data processors according to application ID
US9170812B2 (en) 2002-03-21 2015-10-27 Pact Xpp Technologies Ag Data processing system having integrated pipelined array data processor
US9250908B2 (en) 2001-03-05 2016-02-02 Pact Xpp Technologies Ag Multi-processor bus and cache interconnection system
US9274984B2 (en) 2002-09-06 2016-03-01 Pact Xpp Technologies Ag Multi-processor with selectively interconnected memory units
US9436631B2 (en) 2001-03-05 2016-09-06 Pact Xpp Technologies Ag Chip including memory element storing higher level memory data on a page by page basis
US9552047B2 (en) 2001-03-05 2017-01-24 Pact Xpp Technologies Ag Multiprocessor having runtime adjustable clock and clock dependent power supply
US9690747B2 (en) 1999-06-10 2017-06-27 PACT XPP Technologies, AG Configurable logic integrated circuit having a multidimensional structure of configurable elements

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Publication number Priority date Publication date Assignee Title
US9092595B2 (en) 1997-10-08 2015-07-28 Pact Xpp Technologies Ag Multiprocessor having associated RAM units
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US9250908B2 (en) 2001-03-05 2016-02-02 Pact Xpp Technologies Ag Multi-processor bus and cache interconnection system
US9436631B2 (en) 2001-03-05 2016-09-06 Pact Xpp Technologies Ag Chip including memory element storing higher level memory data on a page by page basis
US9552047B2 (en) 2001-03-05 2017-01-24 Pact Xpp Technologies Ag Multiprocessor having runtime adjustable clock and clock dependent power supply
US9141390B2 (en) 2001-03-05 2015-09-22 Pact Xpp Technologies Ag Method of processing data with an array of data processors according to application ID
US9170812B2 (en) 2002-03-21 2015-10-27 Pact Xpp Technologies Ag Data processing system having integrated pipelined array data processor
US9274984B2 (en) 2002-09-06 2016-03-01 Pact Xpp Technologies Ag Multi-processor with selectively interconnected memory units

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