JP3351452B2 - Programmable gate array - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a programmable logic device.

[0002]

2. Description of the Related Art FIG. 9 is a diagram showing a configuration of a programmable logic element. As shown in this figure, the programmable logic element is composed of a programmable logic cell 1-1 and a programmable wiring region 1-2. The function of the programmable logic element is
-1 to program logic, and programmable wiring area 1
-2 wiring is realized by a logic circuit formed by connecting programmable logic cells. Hereinafter, a series of operations for forming the logic circuit is referred to as circuit programming, and the logic set in the programmable logic cell 1-1 and the setting data of the programmable wiring area 1-2 are referred to as circuit programmable. Also, an FPGA (Field Programmable Gamut) that can be rewritten as such a programmable logic element.
te Array), which has been put into practical use.

FIG. 10 is a block diagram showing a configuration of the programmable logic cell 1-1. In this figure, a programmable logic cell 1-1 is composed of a programmable logic circuit 2-1 and a latch 2-2.
The logic is calculated in the programmable logic circuit 2-1, and the result and the transition state of the circuit are stored by the latch 2-2 to determine the processing in the next clock. That is, an arbitrary combinational circuit is realized by the programmable logic circuit 2-1 and an arbitrary sequential circuit is realized by the combination of the programmable logic circuit 2-1 and the latch 2-2. The contents of the logical operation in the programmable logic circuit 2-1 are determined by a circuit program.

The programmable logic circuit 2-1 in the programmable logic cell 1-1 and the programmable wiring area 1-
All programmable points in the programmable logic element, such as the wiring connection switch in 2, are assigned with a memory element for maintaining the connection state.
By setting predetermined data in this memory element, the function of the logic circuit is realized. That is, the circuit programming is the operation of writing data to the memory element, and the circuit program is the operation of writing the data to the memory element by one.
This is described in the circuit set. Hereinafter, the memory element for determining the logic circuit is referred to as a program memory. Further, the entire hardware to be programmed is called a circuit realization resource.

Next, the timing of circuit programming in the FPGA and the reprogramming of the logic circuit will be described. Since the programmed logic circuit is fixed when the function is realized, the circuit programming is performed statically before executing the processing. When re-programming a logic circuit by realizing a new function or changing the function, this re-programming is performed after the processing operation of the logic circuit is completely stopped, and the logic circuit is dynamically rewritten during the processing. Is not changed. On the other hand, there are FPGAs that allow reprogramming even while the logic circuit is operating, but the programming speed of the logic circuit is as low as that of a normal FPGA, and there is a surplus of programmable logic cells and programmable logic cells that do not contribute to realizing the function. The logic circuit merely statically realizes a logic circuit different from the operating logic circuit by wiring, and the logic circuits do not have a property of dynamically changing one after another.

[0006]

By the way, in the FPGA in which the logic function can be programmed in the field, both the programmable logic cell and the programmable wiring as shown in FIG. 9 are used so that all kinds of logic circuits can be realized. It has a repetitive structure. for that reason,
When a logic circuit is actually implemented and processing is performed with the logic circuit fixed, a large amount of unused resources for logic implementation, such as unused programmable logic cells and programmable wirings that are not used for implementing the function, remain. Also, due to the structural redundancy inherent in realizing programmability in the field, such as programming mechanisms and program memory, the scale of the logic circuit that can be accommodated in a single FPGA chip is limited to a custom LSI without programmability. And A
SIC (application specific integrated circuit)
It is significantly limited as compared with.

When a large-scale logic circuit is realized using such an FPGA chip, it is difficult to simply expand the resources for realizing the logic in a single FPGA chip, which involves manufacturing difficulties. Realization of the combined logic circuit is achieved. In this case, the wiring between the FPGA chips has a larger signal delay than the internal wiring of the FPGA chip.
It must be stored inside the chip. However, if there are no resources left to accommodate the logic circuit, the logic circuit that could not be accommodated is accommodated in another FPGA chip. Therefore, the accommodation efficiency of the logic circuit in each FPGA chip further decreases, and the number of FPGA chips required to realize all functions increases. Further, when a plurality of FPGA chips are operated at the same time, problems such as power consumption and heat generation occur.

Further, the features of the arithmetic processing using a conventional programmable logic element including an FPGA are that high-speed operation is possible, and that parallel operation of logic circuits is possible by realizing all functions spatially. It is. However, in the actual arithmetic processing, not all the logic circuits operate simultaneously, and usually only a part of the logic circuits performs the effective processing in many cases. In other words, the logic circuits in charge of the respective functions become active or independent and perform processing according to timing, conditions, input signals, or the like. Thus, circuits realized by programmable logic elements are often functionally and temporally independent. Therefore, the conventional circuit configuration method in which all the functions are formed by the programmable logic elements from the beginning has a problem that there is much waste in area.

The present invention has been made in view of the above-mentioned problems, and has as its object to provide a programmable gate array capable of efficiently accommodating a large-scale logic circuit in one chip.

[0010]

According to a first aspect of the present invention, there is provided a programmable gate array comprising a logic realizing resource for realizing a circuit and m independent program memories for storing m types of circuit programs. A register plane comprising n sets of independent registers providing latches for storing operation results and realizing a sequential circuit; and the register and a program memory
A memory table in which a plurality of correspondences with
And the correspondence written in the memory table is
Specify a specific program memory and register by specifying
Select the data, as well as load the contents of the memory for the specific program in <br/> the logic implemented for the resource, the Japanese
Comprising an event management unit that controls so as to assign the constant register as a latch, the event management unit, internal
What is the input timing of the data to be processed among the clocks?
At different clock timings, the program
The circuit program of the memory for RAM
It is characterized by loading into

According to a second aspect of the present invention, in the programmable gate array according to the first aspect of the present invention, the event management unit includes a mechanism that can control the memory plane and the register plane independently of each other. Features.

According to a third aspect of the present invention, in the programmable gate array according to the first or second aspect, there is further provided a means for multiplying the input clock of the data to be processed by a factor of k to obtain an internal clock. I have.

[0013]

According to a fourth aspect of the present invention, there is provided a programmable gate array in which a fixed circuit area including a circuit formed at the time of device manufacture or a circuit realized by a program of a mask programmable gate array and a logic circuit such as an FPGA are statically realized. a programmable gate array region having a mechanism for, are characterized by claims 1 having a changing mechanism of the dynamic logic circuit to a structure of a combination of a programmable gate array 3 described.

[0015]

According to the programmable gate array of the first aspect, the circuit program specified from the memory plane by the instruction from the event management unit is loaded into the shared circuit realizing resource, and the register specified from the register plane is latched. A dynamic circuit configurable gate array (hereinafter, abbreviated as DCGA) configuration that realizes a desired logic circuit by being given to a circuit as a configuration is adopted, so that any logic circuit can be realized. it can. In addition, a mechanism that shares circuit realization resources with all circuits to be switched makes it possible to effectively utilize many of the excess circuit realization resources that would have occurred when one type of circuit was programmed and fixed. it can. Further, the event management unit processes the internal clock.
Timing different from the input timing of
Resource for logic realization of memory contents at clock timing
To load.

Further, since many of the circuit realizing resources are repeatedly used, the absolute amount of hardware actually required for realizing the functions can be reduced, so that a redundant structure for realizing programmability is required. As it is, even a single chip can accommodate a large-scale circuit. Also,
Further, by a mechanism for storing only the circuit program in the memory plane, the circuit can be added by adding a memory. Since the memory can be integrated on a large scale, a large number of circuit programs can be realized in a small area, and an increase in the number of chips required to realize all functions can be suppressed. Also, since the number of chips is reduced,
Both the overall power consumption and the amount of heat generated can be reduced.

According to the programmable gate array of the second aspect, the independent control of the memory plane and the register plane is performed by switching the register plane while keeping the memory plane fixed, so that only the internal state of the same logic circuit is controlled. Since it can be changed, the circuit program can be shared for all circuits having the same processing content. Therefore, it is possible to unify overlapping arithmetic circuits, and it is possible to reduce the absolute amount of hardware for realizing functions. Also, by switching the memory plane with the register plane fixed, it is possible to change only the processing circuit by sharing the processing result. Processing can be performed with a large-scale logic realization resource.

According to the programmable gate array of the third aspect, the application of the k-time clock technique to the DCGA area can be achieved by changing the processing speed inside the device higher than the input speed of the data to be processed. In addition to obtaining the time overhead for processing, dividing the whole circuit into k and processing with k clocks, it is possible to reduce the amount of resources for circuit realization and adjust the phase by using latches while guaranteeing data throughput. I do.

[0019]

According to a fourth aspect of the present invention, there is provided a fixed circuit area including a circuit formed at the time of device manufacture or a circuit realized by a program of a mask programmable gate array, and a static logic circuit such as an FPGA. Gate array (hereinafter referred to as Static Configurable Gate Array: S)
(Abbreviated as CGA) and a dynamic logic circuit change mechanism, so that the optimal circuit implementation means can be selected according to the nature of processing, the frequency of operation, and the degree of programmability required. By selecting, it is possible to accommodate all desired functions at high speed and compactly as compared with a device having a single configuration.

Further, the fixed circuit area is a built-in dedicated fixed circuit, so that a circuit having a high frequency of appearance, processing requiring high-speed processing, and programmability are optimal areas for realizing functions that require only changing parameters. Become. The SCGA area consists of an FPGA that performs static circuit programming before processing and does not change the circuit in operation, so it requires programmability and realizes functions that require continuous processing or frequent processing. This is the optimal area for DCG
Area A consists of a gate array that dynamically changes the circuit and programs the processing circuit on a common resource only when necessary, thus requiring programmability and realizing a function with strong temporal independence. This is the optimal area for

[0022]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing the configuration of the first embodiment. Here, the type m of the circuit program is 3, the set number n of the register is 5, and the multiple k of the clock is k.
Is set to 2, and three types of circuit programs a,
Of the circuits b and c, it is assumed that the circuit b program has two states b1 and b2, and the circuit program c has two states c1 and c2.
A case where the processing is repeatedly executed in the order of b1, c1, b2, and c2 will be described.

In this figure, the memory plane 3-1 is formed by an SRAM whose word width is extended to the bit width of the program memory of the shared circuit realizing resource 3-3, and its capacity is the word width × m. One address is associated with one circuit program. Similarly, the register plane 3-2 is formed by an SRAM having a capacity of word width × n, where one word is a total register amount required for one circuit program, and one address corresponds to one logic circuit.

The event management unit 3-8 is formed by an SRAM memory table 3-9, which stores the address of the memory plane 3-1 and the register plane 3-3.
2 is described. The realization circuit is changed by moving the pointer 3-10. When one of the circuit programs is loaded from the memory plane 3-1 by the instruction of the pointer 3-10 and a latch is allocated from the register plane 3-2, the state of the shared circuit realizing resource 3-3 is determined and the logic circuit is determined. Is realized.

The memory plane 3-1 stores a plurality of circuit programs, and one type of circuit is selected by the selector 3-5 according to an instruction signal 3-4 from the event management unit 3-8, and the shared circuit realizing resource 3 -3. The register plane 3-2 is composed of a plurality of latch sets, and one set of latches is selected by the selector 3-7 according to the instruction signal 3-6 from the event management unit 3-8 and allocated to the shared circuit realizing resource 3-3. Can be

The internal clock of this device is set to twice the frequency of the input data 3-11, and is divided into a programming clock and a logical operation clock. Then, the circuit programming is performed by selecting one of the input data 3-11.
This is performed at the programming clock before the clock. Then, the data to be processed in the next logical operation clock is input to the logical circuit formed on the shared circuit realizing resource 3-3, and the operation is performed. Thereafter, the circuit programming by the programming clock and the operation by the logical operation clock are repeated.

Next, FIG. 2 is a diagram showing the state of the first programming clock. One clock before the input data, the memory plane 3-1 transfers the circuit program a and the register plane 3-
2, the register a is selected, and the circuit a is realized on the shared circuit realizing resource 3-3. FIG.
FIG. 14 is a diagram illustrating a state of a second logical operation clock. The data signal 5-1 to be processed is input to the circuit a determined by the previous programming clock, and a logical operation is performed. The processing result is output to the outside as the output signal 5-2 or stored in the register a.

FIG. 4 is a diagram showing the state of the second programming clock. From memory plane 3-1 to circuit program b, from register plane 3-2 to register b
1 are selected, and a circuit b1 is configured on the shared circuit realizing resource 3-3. FIG. 5 is a diagram showing the state of the second logical operation clock. The data signal 5-1 to be processed is input to the circuit b1, and a logical operation is performed.

Hereinafter, the circuit c1 is formed at each third programming clock, and the logical operation processing is performed at the subsequent logical operation clock. In the fourth programming clock, the circuit b2 is configured, and in the subsequent logical operation clock, the logical operation is performed. In the fifth programming, the circuit c2 is configured, and the logical operation is performed in the subsequent logical operation clock.
Then, at the sixth time, the process returns to the same process as the first time, and thereafter the above-mentioned five states are repeatedly executed in the order of a, b1, c1, b2, and c2.

FIG. 6 is a block diagram showing the configuration of the second embodiment. In FIG. 1, the memory plane 3-1, the register plane 3-2, and the event management unit 3-8 built in the chip are replaced with the memory plane chip 8-
1, the register plane chip 8-2 and the event management chip 8-4 are externally attached.

By using the vacant area, the amount of hardware inside the shared circuit realizing resource chip 8-3 is expanded, so that a larger-scale function can be realized, high-speed operation can be performed, and noise immunity is improved. In other words, by expanding the programmable logic cell, the gate scale achievable by one cell is expanded, and by expanding the programmable wiring region, a wiring with a higher degree of freedom and a smaller delay can be realized. In addition, by configuring the respective chips as separate chips in this way, the flexibility of system expansion can be improved.

As the configuration of the dynamic circuit changeable gate array unit, the following configuration can be realized in addition to the above configuration. 1) Built-in circuit: Shared circuit realizing resource / memory plane External circuit: Register plane / event managing unit 2) Built-in circuit: Shared circuit realizing resource / register plane External circuit: Memory plane / event managing unit 3) Built-in circuit: Shared Circuit realization resource / event management unit External circuit: Memory plane / register plane 4) Built-in circuit: Shared circuit realization resource / event management unit, memory plane External circuit: Register plane 5) Built-in circuit: Shared circuit realization resource / event management Section, register plane External circuit: memory plane

FIG. 7 is a block diagram showing the configuration of the first embodiment of the hybrid programmable device. The fixed circuit area 9-1 is formed in advance at the time of device manufacture, and a commercially available FPGA is used for the SCGA area 9-2. The DCGA area 9-3 has the configuration of the dynamic circuit changeable gate array shown in FIG. Here, a case where an example of a communication processing circuit is realized will be described.

Normally, digital data transmitted using a transmission medium such as an optical fiber is several hundred Mbps to several Gbps.
s high-speed serial data. The communication processing device converts this serial data into parallel data and
Processing is performed using a clock of about 0 MHz,
Performs synchronization processing in byte units. Circuits used for such communication processing require high-speed processing and programmability on the order of parameters. In addition, such a circuit can be constructed faster and more compactly by making it at the time of device fabrication or by using a dedicated fixed circuit such as a program for a gate array than by using an FPGA. In FIG. 7, an 8-bit S / P conversion circuit (serial / parallel conversion circuit) 9-4 is configured in a fixed circuit area 9-1.

In the field of communication processing, processing of various types of maintenance operation information added for accurately transmitting user information is mainly performed. Such information bits of the overhead are usually collected and accommodated in independent time slots in the serial data for each role, so that the timing at which each processing circuit is substantially performing processing is shifted in time. . Such a functionally and temporally independent circuit is realized in the DCGA area 9-3, and the amount of hardware of the entire circuit is reduced.

Normally, communication data is scrambled to reduce transmission errors. Further, a parity operation and a CRC operation are performed for bit error detection / correction. Since the processing method for such an entire data is different for each communication apparatus, the diversity of the device is lost when the processing is implemented as a fixed circuit. In addition, since normal operation is continuous operation, DCGA
Even if it is realized in the area 9-3, the circuit realizing resources cannot be shared, and the area occupied by the circuit increases. Therefore, such a circuit is a conventional FPGA or SCG
It is better to make it compact using the A area 9-2. In this case, the event management unit 9-5 performs not only the switching control of the circuit realized in the DCGA area 9-3 but also the setting of the parameters of the fixed circuit configured in the fixed circuit area 9-1 and the SCGA area 9-2. And execution / stop of processing, and transfer of processing data.

FIG. 8 is a block diagram showing the configuration of a second embodiment of the hybrid configuration programmable device described above. The configuration is such that the fixed circuit area 9-1 shown in FIG. 7 is omitted. It is preferable to select an optimum combination depending on the application to be applied in this way.

[0038]

As described above, the programmable gate array of the present invention has the following effects. (1) By providing a mechanism for dynamically changing the logic circuit programmed in the shared circuit realizing resource by utilizing the functional and temporal independence of the processing, it is wasteful as compared with the conventional FPGA. And accommodate a large-scale circuit.

(2) The logic plane necessary for unification and processing of redundant circuits can be realized by independently controlling the memory plane for storing circuit programs and the register plane for storing operation results and circuit transition states. Resources can be kept small.

(3) The hardware scale and the number of chips required for realizing the functions can be reduced, and the overall power consumption and heat generation can be reduced.

(4) A hybrid programmable device composed of a fixed circuit, a static programmable gate array, and a dynamic programmable gate array is an optimal circuit according to the nature of processing, the frequency of operation, and the degree of required programmability. By selecting the realization means, it is possible to accommodate all desired functions at high speed and compactly as compared with a device having a single configuration.

(5) By applying the clock technology k times inside the chip to the gate array capable of changing the dynamic circuit, the processing speed inside the device can be increased by k times as compared with the input speed of the data to be processed. In this case, a time overhead for changing the circuit program is obtained, and the whole circuit is divided into k and the processing is performed by applying k clocks.
It is possible to reduce resources for realizing a shared circuit and adjust the phase by using a latch.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a first embodiment of a programmable gate array according to the present invention.

FIG. 2 is a diagram showing a first circuit programming method in the first embodiment of the programmable gate array of the present invention.

FIG. 3 is a diagram showing a state of a first logical operation in the first embodiment of the programmable gate array of the present invention.

FIG. 4 is a diagram showing a second circuit programming method in the first embodiment of the programmable gate array of the present invention.

FIG. 5 is a diagram showing a state of a second logical operation in the first embodiment of the programmable gate array of the present invention.

FIG. 6 is a block diagram showing a configuration of a second embodiment of the programmable gate array of the present invention.

FIG. 7 is a block diagram showing a configuration of a first embodiment of a hybrid configuration programmable device of the present invention.

FIG. 8 is a block diagram showing the configuration of a second embodiment of the hybrid configuration programmable device of the present invention.

FIG. 9 is a plan view showing a configuration of a conventional programmable logic element.

FIG. 10 is a block diagram showing a configuration of a conventional programmable logic cell.

[Explanation of symbols]

 3-1 Memory plane 3-2 Register plane 3-3 Shared circuit realizing resources 3-5, 3-7 Selector 3-8, 9-5 Event management unit 3-9 Memory table 3-10 Pointer 8-1 Memory plane chip 8-2 Register plane chip 8-3 Shared circuit realization resource chip 8-4 Event management chip 9-1 Fixed circuit area 9-2 SCGA area 9-3 DCGA area 9-4 S / P conversion circuit

──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-6-188722 (JP, A) JP-A-57-132426 (JP, A) US Patent 5,204,555 (US, A) (58) Fields investigated (Int) .Cl. ⁷ , DB name) H01L 27/118 H01L 27/04 H01L 21/822 H01L 21/8242 H01L 27/108

Claims (4)

(57) [Claims] 1. A logic realizing resource for realizing a circuit,
A memory plane composed of m independent program memories for storing m types of circuit programs, and a register composed of n sets of independent registers providing latches for storing operation results and realizing sequential circuits There are multiple correspondences between the plane, the register and the program memory.
A memory table pre-written therein,
By specifying the correspondence written in the table
Select specific program memory and registers,
With loading the contents of the memory for a particular program in the logic implemented for resources, and a event management unit that controls so as to assign said particular register as a latch, the event management unit, of the internal clock, the processing Target
A clock with a different timing from the data input timing
Circuit timing of the program memory
A programmable gate array , wherein a ram is loaded into the logic realizing resource . 2. The programmable gate array according to claim 1, wherein the event management unit includes a mechanism that can independently control the memory plane and the register plane. 3. The programmable gate array according to claim 1, further comprising means for multiplying the input clock of the data to be processed by k times and making it an internal clock. 4. A circuit or a circuit formed at the time of manufacturing a device.
Implemented by mask programmable gate array program
A fixed circuit area composed of a
(ld Programmable Gate Array)
Programmable gate array area with revealing mechanism
And a dynamic logic circuit changing mechanism.
Combined with the programmable gate array described in 3.
A programmable gate array having a configuration .