JP2006040254A - Reconfigurable circuit and processor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an integrated circuit device having a reconfigurable circuit in which change of a function is possible. <P>SOLUTION: The integrated circuit device 26 is provided with the reconfigurable circuit 12 on which a plurality of threads are simultaneously executed. A RAM provided to a memory part 27 is assigned to the threads to be executed on the reconfigurable circuit 12. A first switching part in a first switching circuit 23 is provided for every RAM, selects output from the reconfigurable circuit 12 according to the threads and supplies it to the RAM. When transfer of data is performed between the threads, assignment of the thread to the RAM is changed after completion of all the thread processing. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a reconfigurable circuit whose function can be changed, and a processing apparatus including the reconfigurable circuit.

  In recent years, development of reconfigurable processors capable of changing hardware operations in accordance with applications has been underway. As an architecture for realizing a reconfigurable processor, there are methods using a DSP (Digital Signal Processor) and an FPGA (Field Programmable Gate Array).

  An FPGA (Field Programmable Gate Array) can design circuit configuration relatively freely by writing circuit data after the LSI is manufactured, and is used for designing dedicated hardware. The FPGA includes a lookup table (LUT) for storing a truth table of a logic circuit, a basic cell composed of an output flip-flop, and a programmable wiring resource that connects the basic cells. In the FPGA, a target logical operation can be realized by writing data stored in the LUT and wiring data.

However, when an LSI is designed using an FPGA, the mounting area is very large and the cost is high compared to an ASIC (Application Specific IC) design. Thus, a method has been proposed in which the circuit configuration is reused by dynamically reconfiguring the FPGA (see, for example, Patent Document 1).
Japanese Patent Laid-Open No. 10-256383

  For example, in satellite broadcasting, image quality may be adjusted by switching broadcast modes depending on the season. In the receiver, a plurality of circuits are built in hardware for each broadcast mode in advance, and the circuit is switched by a selector according to the broadcast mode for reception.

  Therefore, the other broadcast mode circuits of the receiver are idle during that time. When switching and using multiple dedicated circuits, such as mode switching, and the switching interval is relatively long, instead of creating multiple dedicated circuits, the LSI can be reconfigured instantaneously at the time of switching. The structure can be simplified to improve versatility, and at the same time the mounting cost can be reduced.

  In order to meet such needs, the manufacturing industry has attracted attention to dynamically reconfigurable LSIs. In particular, LSIs mounted on mobile terminals such as cellular phones and PDAs (Personal Data Assistance) must be downsized, and if LSIs can be dynamically reconfigured and functions can be switched appropriately according to the application, Mounting area can be reduced.

  The FPGA has a high degree of design freedom in circuit configuration and is general-purpose. On the other hand, in order to enable connection between all the basic cells, it is necessary to include a large number of switches and a control circuit for controlling ON / OFF of the switches. This inevitably increases the mounting area of the control circuit. Further, since a complicated wiring pattern is used for the connection between the basic cells, the wiring tends to be long, and the delay increases because of the structure in which many switches are connected to one wiring.

  For this reason, FPGA based LSIs are often used only for trial manufacture and experiments, and are not suitable for mass production in view of mounting efficiency, performance, cost, and the like. Furthermore, in the FPGA, it is necessary to send configuration information to a large number of basic cells of the LUT method, so that it takes a considerable time to configure the circuit. For this reason, the FPGA is not suitable for applications that require instantaneous switching of the circuit configuration.

  In order to solve these problems, in recent years, an ALU array called ALU (Arithmetic Logic Unit) in which multi-functional elements having a plurality of basic arithmetic functions are arranged in multiple stages has been studied. In the ALU array, processing flows in one direction from the upper stage to the lower stage, so that wiring that connects the ALUs in the horizontal direction is basically unnecessary. Therefore, the circuit scale can be reduced as compared with the FPGA.

  In the ALU array, circuit configuration is executed by feeding back the output of the ALU to the input of the ALU. By executing the circuit configuration at high speed, the processing speed of the ALU array can be increased. In particular, when there are a plurality of threads to be executed, it is preferable to efficiently process the plurality of threads.

  The present invention has been made in view of such circumstances, and an object thereof is to provide a technique for efficiently executing a plurality of threads.

  In order to solve the above problem, an embodiment of the present invention relates to a reconfigurable circuit that includes a plurality of logic circuits that can selectively execute a plurality of arithmetic functions and that can execute a plurality of threads simultaneously.

  In the reconfigurable circuit according to this aspect, a storage unit is provided between the preceding-stage logic circuit and the subsequent-stage logic circuit. During execution of a plurality of threads, the storage unit is connected to the preceding-stage logic circuit at the first timing. The output data is stored and stored in the subsequent logic circuit that executes the same thread as the thread executed by the preceding logic circuit at the first timing at the second timing following the first timing. Data output from the preceding logic circuit is supplied.

  Note that the storage unit may be configured by a data flip-flop circuit or the like. When the configuration of the reconfigurable circuit is switched in one clock, the second timing is one clock from the first timing. The timing may be delayed only.

  The terms “front stage” and “back stage” mean the direction of processing. The output of the preceding stage logic circuit only needs to be processed as the input of the succeeding stage logic circuit, and does not mean the preceding stage and the succeeding stage as a physical positional relationship.

  Note that the reconfigurable circuit may be configured to have a multi-stage connection structure of logic circuits. Even in this case, the terms “front stage” and “rear stage” mean the direction of processing. By providing a storage unit between the preceding and succeeding logic circuits, different threads can be processed in the preceding and succeeding logic circuits at the same time, and a reconfigurable circuit that can execute multiple threads is configured. be able to.

  The first storage unit includes a plurality of storage units, and one of the two threads corresponding to the storage unit is allocated to the storage unit, and the allocation of one thread is performed every predetermined cycle. The assignment to the other thread may be switched.

  The first storage unit includes at least a pair of storage units, and a different thread is allocated to each of the pair of storage units, and the allocation of threads corresponding to each of the pair of storage units is performed every predetermined cycle. May be switched to each other.

  The first storage unit may include an information storage unit having a plurality of storage units, and any one of the storage units included in the information storage unit may store an output of a predetermined thread from the reconfigurable circuit. .

  Note that only one specific thread may be fixedly assigned to any of the storage means provided in the information storage unit.

  Note that at least two or more of the storage means provided in the information storage unit may be allocated to the same address space.

  Note that any one of the storage units provided in the information storage unit may determine whether or not to store the output of a predetermined thread from the reconfigurable circuit, based on a specific address range.

  Another embodiment of the present invention includes a reconfigurable circuit that includes a plurality of logic circuits that can selectively execute a plurality of arithmetic functions, and that can execute a plurality of threads simultaneously, and outputs from the reconfigurable circuit. The present invention relates to a processing apparatus including a first storage unit for storing.

  In the processing apparatus of this aspect, the first storage unit is assigned to a thread that is executed on the reconfigurable circuit. The first storage unit may be configured by storage means such as a RAM. The first storage unit may include storage means such as a plurality of RAMs, or a storage means such as one RAM may be divided into a plurality of storage areas. In the latter case, it is preferable that a plurality of storage areas can be accessed simultaneously. When data is exchanged between threads, it is preferable to change the allocation of threads to the first storage unit at a predetermined timing. By changing the thread assignment, it is possible to achieve efficient data transfer between threads.

  Note that the logic circuit may be an arithmetic logic circuit capable of selectively executing a plurality of types of multi-bit operations.

  It should be noted that any combination of the above components and the expression of the present invention expressed as a method, apparatus, system, and computer program are also effective as an aspect of the present invention.

  According to the present invention, it is possible to provide a technique for efficiently executing a plurality of threads.

  FIG. 1 is a configuration diagram of a processing apparatus 10 according to an embodiment of the present invention. The processing device 10 includes an integrated circuit device 26, a compiling unit 30, a setting data generating unit 32, and a storage unit 34. The integrated circuit device 26 has a function that makes it possible to reconfigure the circuit configuration.

  The integrated circuit device 26 is configured as one chip, and includes a reconfigurable circuit 12, a setting unit 14, a control unit 18, an internal state holding circuit 20, an output circuit 22, a first switching circuit 23, a second switching circuit 25, and a memory unit 27. The third switching circuit 28 and the path portions 24 and 29 are provided.

  The reconfigurable circuit 12 has a pipeline configuration, and the function can be changed by changing the setting of the logic circuit. The reconfigurable circuit 12 according to the present embodiment can simultaneously execute a plurality of threads. A thread is a process that is executed by the reconfigurable circuit 12, and the process of each thread is completed by itself. The plurality of threads may be executed independently of each other, and there may be data passing between the threads. The processing apparatus 10 can simultaneously implement a plurality of types of circuit configurations on the reconfigurable circuit 12.

  The setting unit 14 includes a first circuit setting unit 14 a, a second circuit setting unit 14 b, a third circuit setting unit 14 c, and a circuit processing control unit 16, and configures an intended circuit in the reconfigurable circuit 12. The setting data 40 is supplied. Specifically, the first circuit setting unit 14a, the second circuit setting unit 14b, and the third circuit setting unit 14c supply the circuit processing control unit 16 with setting data 40 for executing different threads. The circuit processing control unit 16 corresponds to each stage of the pipeline of the reconfigurable circuit 12 with the setting data 40 sent from the first circuit setting unit 14a, the second circuit setting unit 14b, and the third circuit setting unit 14c. The reconfigurable unit is supplied in a predetermined order. Thereby, a part of a plurality of types of circuits is configured in each stage of the reconfigurable circuit 12, and a multithread processing function is realized.

  The path units 24 and 29 function as a feedback path and output the output of the reconfigurable circuit 12 to the third switching circuit 28. The setting unit 14 may be configured as a command memory that outputs stored data based on the count value of the program counter. In this case, the control unit 18 controls the output of the program counter. In this sense, the setting data 40 may be called command data.

  The memory unit 27 has a storage area for storing a data signal output from the reconfigurable circuit 12 based on an instruction from the control unit 18. The memory unit 27 may be provided in the reconfigurable circuit 12 or may be provided outside the reconfigurable circuit 12.

  The memory unit 27 includes a plurality of RAMs. During execution of a plurality of threads, each RAM is allocated to a thread executed on the reconfigurable circuit 12. For example, when three threads of thread A, thread B, and thread C are executed simultaneously, the first RAM is assigned to thread A, the second RAM is assigned to thread B, and the third RAM is assigned to thread C. The assignment of threads to the RAM is controlled by the control unit 18.

  In particular, when there is data exchange between threads, the control unit 18 preferably changes the allocation of threads to the RAM at a predetermined timing. For example, when the processing result of the thread A is used by the thread B, the processing of the thread A is finished, and the first RAM storing the processing result is assigned the thread B by the control unit 18 at a subsequent timing. . Thereby, the thread B can efficiently use the processing result of the thread A stored in the first RAM without copying the processing result of the thread A from the first RAM to the second RAM. A first switching circuit 23 is provided in the previous stage of the memory unit 27, and a second switching circuit 25 is provided in the subsequent stage.

  The first switching circuit 23 selects the output from the reconfigurable circuit 12 according to the thread and supplies it to the RAM of the memory unit 27. As a result, thread allocation to the RAM is set. Accordingly, if the switch setting in the first switching circuit 23 is not changed, data from the same thread is stored in a certain RAM. The second switching circuit 25 selects one of the outputs from the plurality of RAMs according to the thread and feeds it back to the input of the reconfigurable circuit 12.

  The second switching circuit 25 includes a plurality of second switching units, and each second switching unit is set to select data for one thread. The data signal stored in the memory unit 27 is transmitted as an input to the reconfigurable circuit 12 through the path unit 29 based on the switch setting in the second switching circuit 25. The operations of the first switching circuit 23, the second switching circuit 25, and the memory unit 27 are controlled by the control unit 18.

  There are two inputs to the reconfigurable circuit 12, that is, the route unit 24 and the route unit 29, but the route unit 24 does not go through the memory unit 27, so that high-speed feedback processing is possible. In particular, when the memory unit 27 performs an operation process at a low speed, the path unit 24 enables feedback processing at a higher speed than the path unit 29.

  In response to the instruction signal from the circuit processing control unit 16, the third switching circuit 28 selectively outputs an external input signal and an input signal from the path units 24 and 29 to the reconfigurable circuit 12. Specifically, a switching instruction is issued from the circuit processing control unit 16 at a predetermined timing determined based on the setting data 40.

  The internal state holding circuit 20 and the output circuit 22 are configured as sequential circuits such as a data flip-flop (D-FF), for example, receiving the output of the reconfigurable circuit 12. The internal state holding circuit 20 is connected to the path unit 24. The memory unit 27 is connected to the path unit 29. The reconfigurable circuit 12 includes a combinational circuit and a flip-flop circuit, and realizes a pipeline operation.

  The reconfigurable circuit 12 includes a logic circuit whose function can be changed. Specifically, the reconfigurable circuit 12 includes a configuration in which logic circuits capable of selectively executing a plurality of arithmetic functions are arranged in a plurality of stages, and further includes an output of a preceding logic circuit string and an input of a subsequent logic circuit string. The connection part which can set the connection relationship with is provided.

  This connection unit also has a function of a state holding circuit (hereinafter also referred to as FF circuit) that holds the output of the preceding logic circuit row, that is, the internal state. The plurality of logic circuits are arranged in a matrix. The function of each logic circuit and the connection relationship between the logic circuits are set based on setting data 40 supplied by the setting unit 14. The setting data 40 is generated by the following procedure.

  A program 36 to be realized by the integrated circuit device 26 is held in the storage unit 34. The program 36 shows an operation description describing the operation of processing in the circuit, and describes a signal processing circuit or a signal processing algorithm in a high-level language such as C language.

  The compiling unit 30 compiles the program 36 stored in the storage unit 34, converts it into a data flow graph (DFG) 38, and stores it in the storage unit 34. The data flow graph 38 expresses the dependency of execution order between operations in a circuit, and shows the flow of operations of input variables and constants in a graph structure. In general, the data flow graph 38 is created so that the calculation proceeds from top to bottom.

  The setting data generation unit 32 generates setting data 40 from the data flow graph 38. The setting data 40 is data for mapping the data flow graph 38 to the reconfigurable circuit 12 and determines the function of the logic circuit in the reconfigurable circuit 12 and the connection relationship between the logic circuits. The setting data generation unit 32 generates setting data 40 for a plurality of divided circuits that are obtained by dividing one target circuit to be generated.

  The setting data generation unit 32 determines the division method of the target circuit based on the logic circuit arrangement structure and the data flow graph 38 in the reconfigurable circuit 12. If it is known in advance that pipeline processing is performed in the reconfigurable circuit 12, a method for dividing the target circuit may be determined based on the arrangement structure of the reconfigurable units in the reconfigurable circuit 12. . The arrangement structure of the reconfigurable circuit 12 may be transmitted from the control unit 18 to the setting data generation unit 32 or may be recorded in the storage unit 34 in advance. In addition, the control unit 18 may instruct the setting data generation unit 32 about the division method of the target circuit.

  By executing the above procedure, the storage unit 34 stores a plurality of setting data 40 for configuring the reconfigurable circuit 12 as a desired circuit. The plurality of setting data 40 represents a plurality of divided circuits obtained by dividing the target circuit. As described above, by generating the setting data 40 of the target circuit to be generated according to the circuit scale of the reconfigurable circuit 12, it is possible to realize the processing apparatus 10 with high versatility. From another point of view, according to the processing apparatus 10 of the embodiment, it is possible to reconfigure a desired circuit using the reconfigurable circuit 12 having a small circuit scale.

  FIG. 2 shows the configuration of the reconfigurable circuit 12. The reconfigurable circuit 12 includes a plurality of logic circuit strings each including a logic circuit 50 that can selectively execute a plurality of arithmetic functions. Specifically, the reconfigurable circuit 12 is configured to include a multi-stage arrangement of logic circuit arrays and a connection unit 52 provided in each stage.

  The connection unit 52 can set an arbitrary connection relationship between the output of the preceding logic circuit and the input of the subsequent logic circuit, or a connection relationship selected from a predetermined combination of connection relationships. The connection unit 52 can hold the output signal of the preceding logic circuit. In the reconfigurable circuit 12, the operation proceeds from the upper stage to the lower stage due to the multistage arrangement structure of the logic circuits.

  The reconfigurable circuit 12 has an ALU (Arithmetic Logic Unit) as the logic circuit 50. The ALU is an arithmetic logic circuit capable of selectively executing a plurality of types of multi-bit operations, and can selectively execute a plurality of types of multi-bit operations such as logical sum, logical product, and bit shift. Each ALU has a selector for setting a plurality of arithmetic functions. In the illustrated example, the ALU has two input terminals and two output terminals.

  As illustrated, the reconfigurable circuit 12 is configured as an X-stage Y-column ALU array in which X ALUs in the vertical direction and Y ALUs in the horizontal direction are arranged. Input variables and constants are input to the first-stage ALU11, ALU12,..., ALU1Y, and a set predetermined calculation is performed. The output of the calculation result is input to the second-stage ALU 21, ALU 22,..., ALU 2Y according to the connection set in the first-stage connection unit 52.

  In the first stage connection section 52, an arbitrary connection relationship between the output of the first ALU column and the input of the second ALU column or a combination of predetermined connection relationships is selected. The connection is configured so that the connection relationship can be realized, and the intended connection is enabled by setting. Hereinafter, the configuration is the same up to the connection part 52 of the Xth stage which is the final stage. The connection unit 52 also has a function as an FF circuit, and the final-stage connection unit 52 may function as the internal state holding circuit 20 illustrated in FIG.

  Note that the reconfigurable circuit 12 of FIG. 2 shows a configuration in which the connection units 52 are provided one by one alternately with the ALU column. By disposing the connection unit 52 at the lower stage of each ALU column, the reconfigurable circuit 12 is divided into X-stage reconfigurable units each including one ALU column.

  Specifically, the one-stage reconfigurable unit includes one-stage ALU row and one-stage connection unit 52. This division is in accordance with the FF circuit included in the connection unit 52. For example, a connection unit 52 is provided for each two-stage ALU column, and a connection unit having no FF circuit is connected between two ALU columns. In this case, it is divided into X / 2-stage reconfigurable units each composed of two ALU rows. In addition, by providing an FF circuit for each ALU column of a predetermined stage, a reconfigurable unit of a desired stage can be configured.

  Circuit configuration is performed in one clock. Specifically, the circuit processing control unit 16 maps the setting data to the reconfigurable circuit 12 every clock. The output of each ALU column is held in the connection unit 52 at the subsequent stage. During the execution of a plurality of threads, the FF circuit of the connection unit 52 stores the data output from the preceding logic circuit, and executes the same thread as the thread executed by the preceding logic circuit at the next clock. The stored data is supplied to the logic circuit.

  In this way, the processing of one thread is executed in the ALU row at the lower stage for each clock. When processing is performed at the final stage, it is lowered one stage at a time from the uppermost ALU column. Thereby, multi-thread processing can be executed, and an efficient circuit configuration can be realized.

  FIG. 3 shows another example of the configuration of the reconfigurable circuit. The reconfigurable circuit 12a shown in FIG. 3 further expands the function of the reconfigurable circuit 12 shown in FIG. In the reconfigurable circuit 12a shown in FIG. 3, in addition to the function of the connection unit 52 of FIG. 2, the connection unit 52a has a function of supplying variables and constants input from the outside to the intended ALU. Yes.

  The connection unit 52a can also directly output the calculation result of the previous ALU to the outside. With this configuration, it is possible to configure various combinational circuits as compared with the configuration of the reconfigurable circuit 12 shown in FIG. 2, and the degree of freedom in design is improved.

  FIG. 4 is a diagram illustrating an example of the data flow graph 38. In the data flow graph 38, the flow of operations of input variables and constants is expressed step by step in a graph structure. In the figure, operators are indicated by circles. The setting data generation unit 32 generates setting data 40 for mapping the data flow graph 38 to the reconfigurable circuit 12.

  In particular, when the data flow graph 38 cannot be mapped to the reconfigurable circuit 12, the data flow graph 38 is divided into a plurality of regions, and setting data 40 for the divided circuit is generated. In the embodiment, a plurality of threads are executed on the reconfigurable circuit 12, but each thread is executed by a reconfigurable unit in the reconfigurable circuit 12.

  Therefore, the setting data generation unit 32 divides the data flow graph 38 into a plurality of regions according to the circuit scale of the reconfigurable unit, and generates setting data 40 for the divided circuit. In order to realize the flow of calculation by the data flow graph 38 on the circuit, the setting data 40 specifies the logic circuit to which the calculation function is assigned, defines the connection relationship between the logic circuits, and further defines input variables, input constants, and the like. Data. Therefore, the setting data 40 includes selection information supplied to a selector that selects the function of each logic circuit 50, connection information for setting the connection of the connection unit 52, necessary variable data, constant data, and the like.

  FIG. 5 is a diagram for explaining setting data 40 of a plurality of circuits obtained by dividing one target circuit 42 to be generated. The target circuit 42 includes three target circuits A, B, and C that execute independent operations. The target circuit A, the target circuit B, and the target circuit C constitute independent threads, and are divided according to the circuit scale of the reconfigurable unit.

  In this example, each target circuit is divided into three divided circuits. That is, the target circuit A is divided into a divided circuit A_0, a divided circuit A_1, and a divided circuit A_2, the target circuit B is divided into a divided circuit B_0, a divided circuit B_1, and a divided circuit B_2, and the target circuit C is divided into a divided circuit C_0. And divided circuit C_1 and divided circuit C_2. The setting data generation unit 32 generates setting data 40 for each divided circuit.

  Each target circuit is divided according to the flow of calculation in the data flow graph 38. In the data flow graph 38, when the calculation flow is expressed in a direction from the top to the bottom, the data flow graph 38 is cut from the top at a predetermined interval, and the cut portion is set as a dividing circuit. The interval to be cut according to the flow is determined to be equal to or less than the number of stages of the reconfigurable unit in the reconfigurable circuit 12. The target circuit 42 may be divided in the horizontal direction of the data flow graph 38. The width to be divided in the horizontal direction is determined to be equal to or less than the number of logic circuits in the reconfigurable circuit 12 per stage.

  For example, when the reconfigurable circuit 12 is configured by three stages of ALU columns and the connection unit 52 is provided at each stage, the reconfigurable unit includes one stage of ALU columns. At this time, the division circuit of each target circuit represents one stage of data flow graph.

  Therefore, in the example of FIG. 5, each target circuit is represented by a three-stage data flow graph 38. The actual circuit scale of the target circuit is often represented by a data flow graph 38 having several tens or more stages. However, in the present specification, for convenience of explanation, a case where the divided circuit shown in FIG. explain.

  FIG. 6 is a diagram illustrating a processing flow of the target circuit A configured on the reconfigurable circuit. In the reconfigurable circuit 12, one mapping process can be executed in one clock. Here, a reconfigurable circuit 12 composed of three stages of ALU rows (reconfigurable units) is assumed.

  At the first clock, the dividing circuit A_0 is generated in the first-stage ALU column, and the FF circuit in the first-stage connection unit 52 stores the data output from the dividing circuit A_0. At the second clock, the dividing circuit A_1 is generated in the second-stage ALU column, and the FF circuit in the first-stage connection unit 52 supplies the data stored at the first clock to the generated dividing circuit A_1.

  At the third clock, the dividing circuit A_2 is generated in the third-stage ALU column, and the FF circuit in the second-stage connection unit 52 supplies the data stored at the second clock to the generated dividing circuit A_2. In the embodiment, since the target circuit A is composed of three divided circuits, the divided circuit A_2 outputs data, and the thread of processing of the target circuit A is completed. When the target circuit A is composed of four or more divided circuits, the output of the divided circuit A_2 is fed back and supplied to the first ALU column.

  Thus, one thread is processed for each reconfigurable unit configured in each stage of the reconfigurable circuit 12. As apparent from FIG. 6, when the reconfigurable circuit 12 is used only for processing of one thread, an ALU sequence that does not operate is generated. Therefore, in this embodiment, in order to use the reconfigurable circuit 12 effectively, another thread is executed in an empty ALU string. Thereby, multi-thread processing can be realized.

  FIG. 7 is a diagram illustrating a flow of a multi-thread operation realized on the reconfigurable circuit. Each thread is executed independently of each other. The data transfer between the reconfigurable units in the reconfigurable circuit 12 is as described with reference to FIG.

  At the first clock, the dividing circuit A_0 is generated in the first ALU column of the reconfigurable circuit 12. At the second clock, the dividing circuit B_0 is generated in the first ALU column, and the dividing circuit A_1 is generated in the second ALU column. At the third clock, the dividing circuit C_0 is generated in the first ALU column, the dividing circuit B_1 is generated in the second ALU column, and the dividing circuit A_2 is generated in the third ALU column.

  At the third clock, the processing of the target circuit A, that is, the execution of the thread A is completed. At the fourth clock, the dividing circuit A_0 is generated in the first ALU column, the dividing circuit C_1 is generated in the second ALU column, and the dividing circuit B_2 is generated in the third ALU column. At the fourth clock, the processing of the target circuit B, that is, the execution of the thread B is completed, and a new thread A is executed.

  At the fifth clock, the dividing circuit B_0 is generated in the first ALU column, the dividing circuit A_1 is generated in the second ALU column, and the dividing circuit C_2 is generated in the third ALU column. At the fifth clock, the processing of the target circuit C, that is, the execution of the thread C is completed, and a new thread B is executed. At the sixth clock, the dividing circuit C_0 is generated in the first ALU column, the dividing circuit B_1 is generated in the second ALU column, and the dividing circuit A_2 is generated in the third ALU column. At the sixth clock, the execution of the thread A is completed, and a new thread C is executed. Thereafter, each thread is similarly processed for each clock.

  As described above, the reconfigurable circuit 12 executes a plurality of threads at the same time, so that the hardware resources of the reconfigurable circuit 12 can be effectively used and the processing speed of the original target circuit 42 as a whole can be increased. Can be

  FIG. 8 shows a detailed configuration of the integrated circuit device 26. FIG. 8 shows a configuration mainly for realizing multithread processing, specifically, a configuration related to input / output of the reconfigurable circuit 12. Here, the reconfigurable circuit 12 is shown in which halfway output from the connection parts 52a of each stage and halfway input from the memory part 27 as shown in FIG. In FIG. 8, for convenience of explanation, “52” is used as the reference numeral of the connection unit. The configurations denoted by the same reference numerals as those in FIGS. 1, 3 and 4 have the same structure and function.

  The memory unit 27 includes a plurality of RAMs 27a, 27b, and 27c. Each RAM stores an output from the reconfigurable circuit 12. In this embodiment, each RAM is assigned to a thread executed on the reconfigurable circuit 12.

  That is, one RAM stores data from one thread and supplies data necessary for execution of the thread to the ALU on the reconfigurable circuit 12. Therefore, it is preferable that there are as many RAMs as there are threads executed at the same time.

  The first switching circuit 23 includes a first switching unit 23a, a first switching unit 23b, and a first switching unit 23c. The first switching units 23a, 23b, and 23c are provided corresponding to the RAMs 27a, 27b, and 27c, respectively. The first switching units 23a, 23b, and 23c select the output from the reconfigurable circuit 12 according to the thread, and supply the selected RAM 27a, 27b, and 27c to the corresponding RAM 27a, 27b, and 27c. Each first switching unit is connected to an output line of the connection unit 52 in all stages.

  When the number of threads to be executed simultaneously is three, one thread is executed in any ALU column, and therefore each first switching unit starts from the thread to which the corresponding RAM is allocated. Data is selected and supplied to the RAM.

  The second switching circuit 25 includes a second switching unit 25a, a second switching unit 25b, and a second switching unit 25c. Each of the second switching units 25a, 25b, and 25c is provided corresponding to a thread. Each of the second switching units 25a, 25b, and 25c selects one of the outputs from the RAMs 27a, 27b, and 27c according to the thread and supplies the selected one to the input of the reconfigurable circuit 12. Specifically, the second switching unit 25 a selects data necessary for the processing of the thread A and outputs the data to the route unit 29.

  Similarly, the second switching unit 25b selects data necessary for processing of the thread B and outputs the data to the path unit 29, and the second switching unit 25c selects data necessary for processing of the thread C to select the path unit. 29. As a result, the data supplied from the path unit 29 can be associated with the thread, and the input setting and function setting of the reconfigurable circuit 12 can be facilitated.

  FIG. 9 is a diagram illustrating an example of data exchange between threads. For example, the thread A is executed in response to input from the outside or input by setting data. The thread B uses the processing result of the thread A, and the thread C uses the processing result of the thread B and outputs its own processing result. Since each thread performs independent processing, it can be executed in multiple threads as shown in FIG.

  Consider the allocation of RAM to threads. When the RAM is arbitrarily assigned to the thread, it is necessary to determine which thread the data stored in each RAM is. In addition, the timing for reading and writing data must be determined appropriately.

  Since each thread A, B, and C is mapped and operated on the reconfigurable circuit 12 independently of the other threads, if the RAM is arbitrarily assigned to the thread, the data The control of reading and writing becomes very complicated. The operations of the above components are executed by the compiling unit 30 and converted into DFG. However, it is necessary to consider all complicated conditions such as that a plurality of data cannot be read simultaneously from one RAM. Therefore, it is certain that the compilation program becomes complicated.

  On the other hand, let us consider a case in which the thread A is fixedly assigned to the RAM 27a, the thread B is assigned to the RAM 27b, and the thread C is fixedly assigned to the RAM 27c. Since the processing result of the thread A is used in the processing of the thread B, the thread B reads the processing result from the RAM 27a to which the thread A is assigned. On the other hand, data from the thread A is written in the RAM 27a. When the processing result of the thread A is stored at the address X of the RAM 27a, there is no problem if the timing at which the thread B reads is earlier than the timing at which the thread A writes data to the address X.

  However, if the timing at which the thread A writes data is earlier, the thread B will read the newly written data and cannot read the correct processing result.

  In this case, when the processing result of the thread A is written in the RAM 27a, the operation of the thread A is temporarily interrupted, and the data used in the thread B may be copied to the RAM 27b for the thread B.

  Similarly, when the processing result of the thread B is written in the RAM 27b, the operation of the thread B is interrupted, and the data used in the thread C is copied to the RAM 27c for the thread C. Thereby, it is possible to avoid a situation where necessary data is overwritten and lost.

  At this time, copying of data is performed by feeding back to the input of the reconfigurable circuit 12 via the path unit 29 and transferring the data to another RAM. During this time, the ALU is inefficient because it is used for an operation different from the original thread processing. In the following, a method for executing multithread processing more efficiently will be described. Specifically, this is dealt with by changing the allocation of threads to the RAM in a time-sharing manner.

  FIG. 10 shows the assignment of threads to a plurality of RAMs in the memory unit 27 and the state of the RAM storage area. In the figure, an arrow entering the RAM indicates a flow of data written from the reconfigurable circuit 12, and an arrow exiting the RAM indicates a flow of data fed back to the reconfigurable circuit 12.

  Further, for example, A → B indicates an area for storing a processing result of the thread A to be delivered to the thread B. Further, for example, A_area indicates a temporary area allocated for the thread A, and is an area for storing intermediate results necessary for executing processing.

  The state of the storage area of the RAM shown in FIGS. 10A to 10E shows the state when all threads are finished. In the above example, a simple thread that ends in 3 clocks has been described. However, in reality, a thread that requires about several hundred clocks is assumed. For example, if thread A requires 120 clocks, thread B requires 150 clocks, and thread C requires 100 clocks, it takes at least 150 clocks for all threads to finish.

  Since data is exchanged between threads, in order to execute each thread reliably, each thread may be executed with 150 clocks as a unit time. In this embodiment, this 150 clock is set as a unit time, and a change in thread assignment to the RAM is executed every 150 clocks.

  Hereinafter, this reference time is expressed as a cycle. The cycle is set to be equal to or longer than the processing time of the thread that takes the longest time among the processing times of the threads that are executed simultaneously. Therefore, the processing of a plurality of threads that are executed at the same time is terminated during one cycle.

  FIG. 10A shows the state of the first cycle. In the first cycle, thread A is assigned to RAM 27a, thread B is assigned to RAM 27b, and thread C is assigned to RAM 27c. In the first cycle, an area (A → B) for storing the processing result to be delivered to the thread B in the next and subsequent cycles and an area (A_area) for storing the intermediate result of the thread A are set in the RAM 27a. Note that (N) written before A → B indicates a processing result generated in the Nth cycle.

  Similarly, an area (B → C) for storing the processing result to be delivered to the thread C in the next and subsequent cycles and an area (B_area) for storing the intermediate result of the thread B are set in the RAM 27b. In addition, an area (C_area) for storing the intermediate result and processing result of the thread C is set in the RAM 27c.

  FIG. 10B shows the state of the second cycle. In the second cycle, thread B is assigned to RAM 27a, thread C is assigned to RAM 27b, and thread A is assigned to RAM 27c. The assignment of threads to the RAM is executed by the control unit 18. The control unit 18 changes the thread assignment for each cycle so that data from a thread different from the previous cycle is stored in the RAM.

  Note that the order in which the thread assignment is changed is determined based on the data delivery relationship between threads shown in FIG. As shown in FIG. 9, when the processing result of thread A is handed over to thread B, the RAM allocated to thread A in the previous cycle is determined to be allocated to thread B in the current cycle. Therefore, the thread B can easily use the processing result of the thread A stored in the RAM allocated to itself in the current cycle.

  That is, since the RAM 27a stores the processing result to be delivered from the thread A in the previous cycle, the thread B can use this processing result for its own processing. Similarly, the RAM allocated to the thread B in the previous cycle is allocated to the thread C in the current cycle.

  As shown in the figure, the control unit 18 changes the allocation of threads to all the RAMs at the same time. This timing is a timing after the execution of all the threads is completed as described above. At this time, by cyclically changing the thread assignment, the compiling process can be facilitated, and the data delivery according to the relationship between threads shown in FIG. 9 can be efficiently performed. In this way, the processing apparatus 10 can be speeded up by efficiently and cyclically changing the allocation of threads to the RAM.

  In the second cycle, the RAM 27a stores the processing result of the thread A generated in the previous cycle (A → B), and stores the processing result to be delivered to the thread C in the next and subsequent cycles (B → C). ) And an area (B_area) for storing an intermediate result of the thread B is set. The processing result of the thread A and the intermediate result of the thread B are read to the input of the reconfigurable circuit 12 for the execution of the thread B. If the processing result of the thread A is read and then it is known that the thread B will not use it, the area (A → B) storing the processing result of the thread A is released, and the data You may allow writing.

  Similarly, an area for storing the processing result of the thread B generated in the previous cycle (B → C) and an area for storing the intermediate result of the thread C and the processing result (C_area) are set in the RAM 27b. The processing result of the thread B and the intermediate result of the thread C are read to the input of the reconfigurable circuit 12 for the execution of the thread C. If the processing result of the thread B is read and it is known that the thread C does not use it thereafter, the area (B → C) storing the processing result of the thread B is released, and the data You may allow writing.

  Further, an area (A → B) for storing the processing result to be delivered to the thread B in the next and subsequent cycles and an area (A_area) for storing the intermediate result of the thread A are set in the RAM 27c. The intermediate result of the thread A is read to the input of the reconfigurable circuit 12 for the execution of the thread A.

  FIG. 10C shows the state of the third cycle. In the third cycle, thread C is assigned to RAM 27a, thread A is assigned to RAM 27b, and thread B is assigned to RAM 27c. In the third cycle, an area for storing the processing result of the thread B generated in the previous cycle (B → C) and an area for storing the intermediate result of the thread C and the processing result (C_area) are set in the RAM 27a. .

  Note that, in the RAM 27a, the area (A → B) set in the second cycle is used as C_area in this example because data reading is completed in the second cycle. Thereby, the RAM 27a can be used efficiently.

  Similarly, an area (A → B) for storing the processing result to be delivered to the thread B in the next and subsequent cycles and an area (A_area) for storing the intermediate result of the thread A are set in the RAM 27b. In the RAM 27b, the area (B → C) set in the second cycle is used as A_area in this example because the data reading is completed in the second cycle.

  Further, the RAM 27c has an area for storing the processing result of the thread A generated in the previous cycle (A → B), an area for storing the processing result to be delivered to the thread C in the next and subsequent cycles (B → C), An area (B_area) for storing an intermediate result of thread B is set.

  FIG. 10D shows the state of the fourth cycle. In the fourth cycle, as in the first cycle, thread A is allocated to the RAM 27a, thread B is allocated to the RAM 27b, and thread C is allocated to the RAM 27c. In the fourth cycle, an area (A → B) for storing the processing result to be delivered to the thread B in the next and subsequent cycles and an area (A_area) for storing the intermediate result of the thread A are set in the RAM 27a.

  Similarly, an area (A → B) for storing the processing result of the thread A generated in the previous cycle and an area (B → C) for storing the processing result to be delivered to the thread C in the next and subsequent cycles are stored in the RAM 27b. An area (B_area) for storing the intermediate result of thread B is set. In addition, an area (B → C) for storing the processing result of the thread B generated in the previous cycle and an area (C_area) for storing the intermediate result of the thread C and the processing result are set in the RAM 27c.

  FIG. 10E shows the state of the fifth cycle. In the fifth cycle, as in the second cycle, thread B is allocated to the RAM 27a, thread C is allocated to the RAM 27b, and thread A is allocated to the RAM 27c. Note that the state of the storage area of the RAM is also the same as the state of the second cycle shown in FIG. Thereafter, the state shown in FIGS. 10B, 10C, and 10D is cyclically repeated, and the process shown in FIG. 9 is continued.

  FIG. 11 is a diagram illustrating another example of data transfer between threads. For example, the thread A is executed in response to input from the outside or input by setting data. Thread B uses the processing result of thread A, and thread C outputs the processing result of itself using the processing result of thread A and the processing result of thread B. Each thread performs independent processing and can be executed in multiple threads as shown in FIG. Similar to the processing shown with reference to FIGS. 9 and 10, in multithread processing, thread allocation to the RAM is changed in a time-sharing manner.

  12 and 13 show the assignment of threads to a plurality of RAMs in the memory unit 27 and the state of the RAM storage area. In the figure, an arrow entering the RAM indicates a flow of data written from the reconfigurable circuit 12, and an arrow exiting the RAM indicates a flow of data fed back to the reconfigurable circuit 12.

  Further, for example, A → B indicates an area for storing a processing result of the thread A to be delivered to the thread B. Further, for example, A_area indicates a temporary area allocated for the thread A, and is an area for storing intermediate results necessary for executing processing. The states of the RAM storage areas shown in FIGS. 12A to 12D and FIGS. 13A to 13D show the states when all the threads are finished. Changes in thread assignment in FIGS. 12 and 13 are executed by the control unit 18.

  FIG. 12A shows the state of the first cycle. In the first cycle, thread A is assigned to RAM 27a, thread B is assigned to RAM 27b, and thread C is assigned to RAM 27c. In the first cycle, an area (A → B) for storing processing results to be delivered to the thread B in the next and subsequent cycles in the RAM 27a, and an area (A → B) for storing processing results to be delivered to the thread C in the next and subsequent cycles. C) and an area (A_area) for storing an intermediate result of the thread A is set.

  Similarly, an area (B → C) for storing the processing result to be delivered to the thread C in the next and subsequent cycles and an area (B_area) for storing the intermediate result of the thread B are set in the RAM 27b. In addition, an area (C_area) for storing the intermediate result and processing result of the thread C is set in the RAM 27c.

  FIG. 12B shows the state of the second cycle. In the second cycle, thread B is assigned to RAM 27a, thread C is assigned to RAM 27b, and thread A is assigned to RAM 27c. In the second cycle, the RAM 27a stores the processing result of the thread A generated in the previous cycle (A → B), (A → C), and the processing result to be delivered to the thread C in the next and subsequent cycles. To be stored (B → C) and an area (B_area) for storing the intermediate result of the thread B are set.

  The processing result of the thread A to be delivered to the thread B and the intermediate result of the thread B are read to the input of the reconfigurable circuit 12 for the execution of the thread B. Since the processing result of the thread A stored in the area (A → C) is used in the next cycle, writing to the area (A → C) is prohibited.

  If the processing result of the thread A stored in the area (A → B) is read and then it is known that the thread B will not use it, the area (A → B) is released. Data writing may be allowed.

  Similarly, an area for storing the processing result of the thread B generated in the previous cycle (B → C) and an area for storing the intermediate result of the thread C and the processing result (C_area) are set in the RAM 27b. The processing result of the thread B and the intermediate result of the thread C are read to the input of the reconfigurable circuit 12 for the execution of the thread C.

  If the processing result of the thread B is read and it is known that the thread C does not use it thereafter, the area (B → C) storing the processing result of the thread B is released, and the data You may allow writing.

  In addition, an area for storing the processing result to be delivered to the thread B in the next and subsequent cycles (A → B), an area for storing the processing result to be delivered to the thread C in the subsequent and subsequent cycles (A → C), An area (A_area) for storing an intermediate result of the thread A is set. The intermediate result of the thread A is read to the input of the reconfigurable circuit 12 for the execution of the thread A.

  FIG. 12C shows the state of the third cycle. In the third cycle, thread C is assigned to RAM 27a, thread A is assigned to RAM 27b, and thread B is assigned to RAM 27c. In the third cycle, an area for storing the processing result of the thread B generated in the previous cycle (B → C) and an area for storing the processing result of the thread A generated in the previous cycle (A →) are stored in the RAM 27a. C), an area (C_area) for storing the intermediate result of thread C and the processing result is set.

  Note that, in the RAM 27a, the area (A → B) set in the second cycle is used as C_area in this example because data reading is completed in the second cycle. Thereby, the RAM 27a can be used efficiently.

  Similarly, in the RAM 27b, an area for storing a processing result to be delivered to the thread B in the next and subsequent cycles (A → B), an area for storing a processing result to be delivered to the thread C in the next and subsequent cycles (A → C), An area (A_area) for storing an intermediate result of the thread A is set. In the RAM 27b, the area (B → C) set in the second cycle is used as A_area in this example because the data reading is completed in the second cycle.

  In addition, the RAM 27c stores the processing result of the thread A generated in the previous cycle (A → B) and (A → C), and the processing storing the processing result to be delivered to the thread C in the next and subsequent cycles ( B → C) and an area (B_area) for storing the intermediate result of thread B is set.

  FIG. 12D shows the state of the fourth cycle. In the fourth cycle, as in the first cycle, thread A is allocated to the RAM 27a, thread B is allocated to the RAM 27b, and thread C is allocated to the RAM 27c. In the fourth cycle, the RAM 27a stores the processing result to be delivered to the thread B in the next and subsequent cycles (A → B), and stores the processing result to be delivered to the thread C in the next and subsequent cycles (A → C). ) And an area (A_area) for storing the intermediate result of the thread A is set.

  Similarly, an area for storing the processing result of the thread A generated in the previous cycle (A → B) and (A → C) and an area for storing the processing result to be delivered to the thread C in the next and subsequent cycles are stored in the RAM 27b. (B → C) and an area (B_area) for storing an intermediate result of the thread B are set.

  Further, the RAM 27c stores an area (B → C) for storing the processing result of the thread B generated in the previous cycle, an area (A → C) for storing the processing result of the thread A generated in the previous cycle, An area (C_area) for storing the intermediate result of thread C and the processing result is set.

  FIG. 13A shows the state of the fifth cycle. In the fifth cycle, as in the second cycle, thread B is allocated to the RAM 27a, thread C is allocated to the RAM 27b, and thread A is allocated to the RAM 27c. In the fifth cycle, the RAM 27a stores the processing result of the thread A generated in the previous cycle (A → B), (A → C), and the processing result to be delivered to the thread C in the next and subsequent cycles. To be stored (B → C) and an area (B_area) for storing the intermediate result of the thread B are set.

  Similarly, an area for storing the processing result of the thread B generated in the previous cycle (B → C) and an area for storing the processing result of the thread A generated in the previous cycle (A → C) are stored in the RAM 27b. An area (C_area) for storing the intermediate result of thread C and the processing result is set.

  In addition, an area for storing the processing result to be delivered to the thread B in the next and subsequent cycles (A → B), an area for storing the processing result to be delivered to the thread C in the subsequent and subsequent cycles (A → C), An area (A_area) for storing an intermediate result of the thread A is set.

  FIG. 13B shows the state of the sixth cycle. In the sixth cycle, as in the third cycle, the thread C is allocated to the RAM 27a, the thread A is allocated to the RAM 27b, and the thread B is allocated to the RAM 27c. Note that the state of the storage area of the RAM is also the same as the state of the third cycle shown in FIG.

  FIG. 13C shows the state of the seventh cycle. In the seventh cycle, as in the fourth cycle, thread A is allocated to the RAM 27a, thread B is allocated to the RAM 27b, and thread C is allocated to the RAM 27c. Note that the state of the storage area of the RAM is also the same as the state of the fourth cycle shown in FIG.

  FIG. 13D shows the state of the eighth cycle. In the eighth cycle, as in the fifth cycle, the thread B is allocated to the RAM 27a, the thread C is allocated to the RAM 27b, and the thread A is allocated to the RAM 27c. Note that the state of the storage area of the RAM is also the same as the state of the fourth cycle shown in FIG. Thereafter, the state shown in FIG. 12C, FIG. 12D, and FIG. 13A is cyclically repeated, and the process shown in FIG. 11 is continued.

  Further, the relationship between threads shown in FIG. 9 or FIG. 11 is the case where there is no feedback data from other threads to the thread A. FIGS. 14A and 14B are diagrams illustrating an example of data transfer between threads when feedback data to the thread A exists.

  Even when feedback data to the thread A exists, an efficient reconfigurable circuit can be obtained by changing the allocation of threads to the RAM for each cycle as described with reference to FIGS. Twelve configurations can be realized.

  In addition, by realizing a configuration in which there is no data transfer contention among the threads, a data transfer arbitration circuit can be eliminated. As a result, it is possible to provide a technology capable of downsizing the circuit and reducing power consumption.

  FIG. 15 is a diagram illustrating another example of the configuration illustrated in FIG. In FIG. 8, when the processing result of the thread A is delivered to the thread B, the RAM allocated to the thread A in the previous cycle is allocated to the thread B in the current cycle. When the processing result of the thread B is delivered to the thread C, the RAM assigned to the thread B in the previous cycle is assigned to the thread C in the current cycle.

  As described above, when the first switching unit 23 sequentially switches the threads assigned to the RAM for each cycle (switching in the order of thread A → thread B → thread C), the processing result of one thread in the RAM. Is handed over to the other thread. For this reason, the first switching unit 23 can transfer data from the one thread (here, thread A) to the other thread (here, thread C) at most (number of threads−1) times (here, twice). ) Must be switched, which increases the processing time. In order to eliminate this point, FIG. 15 has the following configuration. This will be described in detail below.

  As shown in FIG. 15, the integrated circuit device 26 includes a reconfigurable circuit 12, a first switching unit 23, a third switching unit 28, a thread AB storage unit 60, a thread BC storage unit 70, And a thread CA storage unit 80.

  The first switching unit 23 illustrated in FIG. 8 corresponds to the first switching circuit 23 and the fourth switching unit (fourth switching units 61, 71, 81) illustrated in FIG. That is, the first switching circuit 23 shown in FIG. 8 executes selection of each thread output from the reconfigurable circuit 12 and selection of a thread corresponding to each of the RAM 27, but the first switching circuit 23 shown in FIG. The switching circuit 23 selects each thread output from the reconfigurable circuit 12, and the fourth switching unit (fourth switching units 61, 71, 81) shown in FIG. 15 selects a thread corresponding to each RAM. Is running.

  For example, the first switching unit 23a selects the output of the thread A, the first switching unit 23b selects the output of the thread B, and the first switching unit 23c selects the output of the thread C.

  The fourth switching unit 61 supplies the output of the thread A or thread B corresponding to each of the RAM 64a and RAM 64b. The fourth switching unit 71 supplies the output of the thread B or thread C corresponding to each of the RAM 74a and RAM 74b. Further, the fourth switching unit 81 supplies the output of the thread C or thread A corresponding to each of the RAM 84a and RAM 84b.

  Further, the second switching unit 25 shown in FIG. 8 corresponds to the fifth switching unit (fifth switching units 65, 75, 85) shown in FIG. The description common to the configuration shown in FIG. 8 is omitted.

  The storage unit 60 includes a fourth switching unit 61, a RAM 62, a RAM 63, a RAM 64 a and a RAM 64 b (a pair of storage units), a fifth switching unit 65, a sixth switching unit 66, and a sixth switching unit 67. I have.

  Only the thread A is fixedly assigned to the RAM 62. Similarly, only the thread B is fixedly assigned to the RAM 63. Here, in the present embodiment, each of the RAM 62, the RAM 64a, and the RAM 64b is configured to be capable of commonly storing the output of a predetermined thread (here, thread A) from the reconfigurable circuit 12, and is configured as an information storage unit. Is configured. Each of the RAM 63, the RAM 64a, and the RAM 64b is configured to be able to store the output of a predetermined thread (here, thread B) from the reconfigurable circuit 12 in common, and constitutes an information storage unit.

  One of the two threads is allocated to the RAM 64a, and the allocation of one thread can be switched to the other thread every predetermined cycle. Similarly, one of the two threads is allocated to the RAM 64b, and the allocation of one thread can be switched to the other thread every predetermined cycle. The switching of the thread assignment is executed by the fourth switching unit 61 and the fifth switching unit 65. That is, the fourth switching unit 61 switches thread assignment on the input side of the RAM 64a and RAM 64b, and the fifth switching unit 65 switches thread assignment on the output side of the RAM 64a and RAM 64b.

  For example, when one of the threads A and B is assigned to the RAM 64a, the assignment of the thread A can be switched to the other thread B after a predetermined cycle has elapsed. Further, after a predetermined cycle elapses, the assignment of the thread B can be switched to the other thread A.

  When different threads are assigned to the RAM 64a and RAM 64b, the assignment of threads corresponding to the RAM 64a and RAM 64b may be switched to each other every predetermined cycle. The switching of the thread assignment is executed by the fourth switching unit 61 and the fifth switching unit 65.

  For example, when the thread A is assigned to the RAM 64a and the thread B is assigned to the RAM 64b, the thread A corresponding to the RAM 64a is switched to the thread B assignment after a predetermined cycle, and the RAM 64b The corresponding thread B assignment is switched to thread A assignment. Further, after a predetermined cycle elapses, the assignment of the thread B corresponding to the RAM 64a is switched to the assignment of the thread A, and the assignment of the thread A corresponding to the RAM 64b is changed to the assignment of the thread B.

  Therefore, when the output of the thread A of the first switching unit 23a and the output of the thread B of the first switching unit 23b are input, the fourth switching unit 61 outputs the output of the thread A of the first switching unit 23a to the RAM 64a. And the output of the thread B of the first switching unit 23b is output to the RAM 64b.

  Further, after a predetermined cycle elapses, the assignment of the thread A corresponding to the RAM 64a is switched to the assignment of the thread B, and the assignment of the thread B corresponding to the RAM 64b is changed to the assignment of the thread A. Then, the fourth switching unit 61 outputs the output of the thread B of the first switching unit 23b to the RAM 64a, and outputs the output of the thread A of the first switching unit 23a to the RAM 64b.

  When the thread A is assigned to the RAM 64a and the thread B is assigned to the RAM 64b, the fifth switching unit 65 processes the output of the RAM 64a through the sixth switching unit 66 and corresponds to the thread A in the reconfigurable circuit 12 The output of the RAM 64b is output to the process corresponding to the thread B in the reconfigurable circuit 12 through the sixth switching unit 67.

  Further, after the predetermined cycle has elapsed, the assignment of the thread A corresponding to the RAM 64a is switched to the assignment of the thread B, and the assignment of the thread B corresponding to the RAM 64b is switched to the assignment of the thread A. 65 outputs the output of the RAM 64a to the process corresponding to the thread B in the reconfigurable circuit 12 through the sixth switching unit 67, and the output of the RAM 64b corresponds to the thread A in the reconfigurable circuit 12 through the sixth switching unit 66. Output to processing.

  The sixth switching unit 66 selects and outputs one of the outputs of the RAM 62 and the fifth switching unit 65. The sixth switching unit 67 selects and outputs one of the outputs of the RAM 63 and the fifth switching unit 65.

  Here, each of the thread A, the thread B, and the thread C has a plurality of address spaces. In the present embodiment, it is assumed that the thread A has an address space A-1 and an address space A-2. It is assumed that the thread B has an address space B-1 and an address space B-2. It is assumed that the thread C has an address space C-1 and an address space C-2. Numbers 001 to 200 are allocated to each address space. Hereinafter, the relationship among the thread, the address space, and the RAM will be described in detail.

  First, the RAM 62 is allocated (fixedly) from 001 to 100 in the address space A-1 of the thread A. When the RAM 64a is allocated to the thread A, the RAM 64a is allocated from the 101st to the 200th in the address space A-1 of the thread A. When the RAM 64b is allocated to the thread A, the RAM 64b is allocated from the 101st to the 200th in the address space A-1 of the thread A.

  That is, the processing performed on the address space A-1 of the thread A is determined by the address range, the processing on the address space A-1 from 001 to 100 is performed on the RAM 62, and the processing on the address space A-1 is 101. To No. 200 are performed on the RAM 64a or the RAM 64b in accordance with the assignment of threads corresponding to the RAM.

  The RAM 63 is allocated (fixedly) from 001 to 100 in the address space B-2 of the thread B. When the RAM 64a is allocated to the thread B, the RAM 64a is allocated from the 101st to the 200th in the address space B-2 of the thread B. When the RAM 64b is allocated to the thread B, the RAM 64b is allocated from the 101st to the 200th in the address space B-2 of the thread B.

  That is, the processing performed on the address space B-2 of the thread B is determined by the address range, the processing on the address space B-2 from 001 to 100 is performed on the RAM 63, and the processing on the address space B-2 is 101. To No. 200 are performed on the RAM 64a or the RAM 64b in accordance with the assignment of threads corresponding to the RAM.

  Similarly, the processing performed on the address space B-1 of the thread B is determined by the address range, and the processing on the address space B-1 from 001 to 100 is performed on the RAM 72. The processing from No. 101 to No. 200 is performed on the RAM 74a or RAM 74b according to the assignment of threads corresponding to the RAM.

  Further, the processing performed on the address space C-2 of the thread C is determined by the address range, the processing on the address space C-2 from 001 to 100 is performed on the RAM 73, and the processing of the address space C-2 The processing from No. 101 to No. 200 is performed on the RAM 74a or RAM 74b according to the assignment of threads corresponding to the RAM.

  Further, the processing performed by the thread C on the address space C-1 is determined by the address range, and the processing on the address space C-1 from 001 to 100 is performed on the RAM 82. Processing from No. 101 to No. 200 is performed on the RAM 84a or the RAM 84b in accordance with the assignment of threads corresponding to the RAM.

  Further, the processing performed on the address space A-2 of the thread A is determined by the address range, the processing on the address space A-2 from 001 to 100 is performed on the RAM 83, and the processing of the address space A-2 Processing from No. 101 to No. 200 is performed on the RAM 84a or the RAM 84b in accordance with the assignment of threads corresponding to the RAM.

  Data is exchanged between threads due to the relationship between the thread, the address space, and the RAM. For example, when the RAM 64a is allocated to the thread A and the RAM 64b is allocated to the thread B, the processing for the address space A-1 of the thread A is performed on the RAM 62 or the RAM 64a, and the address space B-2 of the thread B is performed. The processing for is performed on the RAM 63 or the RAM 64b.

  Further, when the RAM 64a is assigned to the thread B and the RAM 64b is assigned to the thread A after a predetermined cycle has elapsed, the processing for the address space A-1 of the thread A is performed on the RAM 62 or the RAM 64b, and the thread B Processing for the address space B-2 is performed on the RAM 63 or the RAM 64a.

  That is, the RAM 64a and the RAM 64b are areas used for data exchange between the thread A and the thread B, and data is transferred between the thread A and the thread B by switching the threads allocated to these RAMs. Communicate with each other.

  For example, when data is exchanged between the thread A and the thread B, the data that the thread A passes to the thread B is written from the 101st to the 200th in the address space A-1, and the thread B passes to the thread A. Data is written from address 101 to address 200 in address space B-2. At this time, when the RAM 64a is assigned to the thread A and the RAM 64b is assigned to the thread B, the data that the thread A passes to the thread B is written to the RAM 64a, and the data that the thread B passes to the thread A is written to the RAM 64b. Will be written.

  Then, after a predetermined cycle elapses, when the RAM 64b is assigned to the thread A and the RAM 64a is assigned to the thread B, the thread A writes the data of the thread B written in the RAM 64b and the addresses 101 to 200 in the address space A-1. The thread B reads the data of the thread A read from the number area and written to the RAM 64a from the areas 101 to 200 in the address space B-2. Thereby, data can be exchanged between the thread A and the thread B only by switching the threads corresponding to the RAM 64a and the RAM 64b once each other.

  In this embodiment, a thread (for example, thread A) has two address spaces (for example, address space A-1 and address space A-2), and one address space (for example, address space A). -1) is divided into two areas (for example, an area fixedly assigned to the thread A (001 to 100) and an area for exchanging data with the thread B (101 to 200)). However, it is not limited to this.

  For example, an area fixedly assigned to thread A (001 to 100), an area for exchanging data with thread B (101 to 200), and an area for exchanging data with thread C (number 100) You may have the address space divided into three (201 to 300).

  Thread B and thread C are assigned to the storage unit 70. The storage unit 70 includes a fourth switching unit 71, a RAM 72, a RAM 73, a RAM 74 a and a RAM 74 b, a fifth switching unit 75, a sixth switching unit 76, and a sixth switching unit 77. Since the storage unit 70 has the same function as the storage unit 60 described above, detailed description thereof is omitted.

  A thread C and a thread A are allocated to the storage unit 80. The storage unit 80 includes a fourth switching unit 81, a RAM 82, a RAM 83, a RAM 84 a and a RAM 84 b, a fifth switching unit 85, a sixth switching unit 86, and a sixth switching unit 87. Since the storage unit 80 has the same function as the storage unit 60 described above, a detailed description thereof is omitted.

  Note that FIG. 15 shows a configuration in which three threads exist, but the configuration is not limited to this, and a configuration in which four or more threads exist may be used. For example, when there are four threads, the storage unit (for AB) assigned to thread A and thread B, the storage unit (for AC) assigned to thread A and thread C, the thread A and thread D are assigned. Storage unit (for AD), storage unit assigned to thread B and thread C (for BC), storage unit assigned to thread B and thread D (for BD), storage unit assigned to thread C and thread D (for CD) 6) will be provided.

  Note that the present invention is not limited to each RAM shown in FIG. 15, and may include RAMs other than the RAMs shown in FIG. Specifically, a RAM to which threads are fixedly assigned may be provided in addition to the RAMs shown in FIG. For example, it is assumed that the thread A newly has an address space A-3 in addition to the address space A-1 and the address space A-2 described above. The RAM to which the thread A is fixedly allocated is allocated to the address space A-3.

  According to the configuration shown in FIG. 15, the fourth switching unit and the fifth switching unit allocate predetermined threads to the respective RAMs (for example, the RAM 64a and the RAM 64b) in the storage units 60, 70, and 80. Each cycle can be switched to each other. As a result, the fourth switching unit and the fifth switching unit switch the processing result of one thread (for example, thread A) in the storage units 60, 70, and 80 by one switching to the other thread (for example, thread B). At the same time, the processing result of the other thread (for example, thread B) can be handed over to one thread (for example, thread A) with one switching.

  Further, not only between the thread A and the thread B but also between the thread B and the thread C, and between the thread C and the thread A, the processing result of one thread can be switched by one switching. At the same time, the processing result of the other thread can be transferred to one thread by switching once, so that data can be simultaneously transferred between arbitrary threads. Therefore, the waiting time until the processing result of each thread is used can be shortened, and the processing time can be significantly reduced as compared with the configuration shown in FIG.

  Further, in the configuration shown in FIG. 8, one of the address spaces of one thread is only an area used for data transfer between threads. The processing result of the thread used by can not be stored. On the other hand, in the configuration shown in FIG. 15, each address space has not only an area for passing data between threads but also an area that is fixedly assigned to the thread. However, the processing result of the thread used by the same thread in the next cycle can be stored.

  For example, in the configuration shown in FIG. 8, the address space is used for transferring data between threads, and cannot store the processing results of threads used by the same thread in the next cycle. For this reason, the processing result of the thread used by the same thread in the next cycle is stored in another address space.

  On the other hand, the configuration shown in FIG. 15 has a storage unit for storing the processing result of the thread used by the same thread in the next cycle in both of the two address spaces of one thread. For this reason, even when there are two processing results of threads used by the same thread in the next cycle, it is possible to simultaneously store the two calculation results in different address spaces.

  In the above, this invention was demonstrated based on the Example. It is to be understood by those skilled in the art that the embodiments are exemplifications, and that various modifications are possible in the combination of each component and each processing process, and such modifications are within the scope of the present invention. For example, the integrated circuit device 26 shown in FIG. 8 has a configuration that enables intermediate input to the reconfigurable circuit 12 or intermediate output from the reconfigurable circuit. It can also be applied to configurations without this.

  For example, the array of ALUs in the reconfigurable circuit 12 is not limited to a multistage array that allows connection only in the vertical direction, but may be a mesh-like array that allows connection in the horizontal direction. In the above description, the connection for connecting the logic circuits by skipping the stages is not provided, but the connection connection for skipping such stages may be provided.

  Further, FIG. 1 shows a case where the processing apparatus 10 has one reconfigurable circuit 12, but it may have a plurality of reconfigurable circuits 12.

  In the configuration shown in FIG. 8, the integrated circuit device 26 includes the memory unit 27 including the first switching circuit 23 and a plurality of RAMs. In the following modified example, the memory unit 27 may have one RAM having a plurality of input / output ports that can be accessed simultaneously instead of having a plurality of RAMs. In this case, the storage area of the RAM is divided into a plurality of parts, and each of the divided storage areas is assigned to a thread executed on the reconfigurable circuit 12. Each of the plurality of input / output ports corresponds to each divided storage area.

  The RAM is divided using, for example, a bit value at a predetermined position of the address. For example, the first input / output port is associated with a storage area in which the most significant 2 bits of the address is “00”, and the second input / output port is stored in which the most significant 2 bits of the address is “01”. The third input / output port is associated with a storage area in which the most significant 2 bits of the address are “10”.

  By associating each of the plurality of threads with each input / output port, the thread is associated with the divided storage area. Other configurations such as the reconfigurable circuit 12, the second switching circuit 25, and the control unit 18 are the same as those in the above-described embodiment.

  That is, although a plurality of RAMs exist in the embodiment, in this modification, one RAM in the embodiment corresponds to one storage area divided in the RAM. When using 2 bits in the address, it is possible to divide the storage area into four at the maximum. However, if it is necessary to further divide the storage area, 3 bits or more in the address are used. Use.

  As described above, the first switching circuit 23 and the memory unit 27 shown in FIG. 8 may be replaced with one RAM having a plurality of input / output ports. As described above, by using the RAM that enables simultaneous writing and / or reading of a plurality of data as the memory unit 27, the same effect as described in the embodiment can be obtained, and the first switching circuit can be obtained. Since 23 can be omitted from the integrated circuit device 26, the circuit scale can be reduced.

  Note that the reconfigurable circuit 12 is not limited to the one described in this embodiment, and includes a programmable device such as a CPU, DSP, or FPGA. For thread execution, for example, only a case where a plurality of threads are executed on one circuit as shown in FIG. 2 has been described. However, individual circuits exist, and each circuit has a different thread. Are executed at the same time.

  It should be understood that the embodiments disclosed herein are illustrative and non-restrictive in every respect. The scope of the present invention is defined by the terms of the claims, rather than the description above, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.

It is a block diagram of the processing apparatus which concerns on an Example. It is a block diagram of a reconfigurable circuit. It is another block diagram of a reconfigurable circuit. It is a figure which shows the example of a data flow graph. It is a figure for demonstrating the setting data of the some circuit which can divide | segment the target circuit which should be produced | generated. It is a figure which shows the flow of a process of the target circuit comprised on a reconfigurable circuit. It is a figure which shows the flow of the multithread operation | movement implement | achieved on a reconfigurable circuit. It is a figure which shows the detailed structure of an integrated circuit device. It is a figure which shows an example of the delivery of the data between threads. It is a figure which shows the allocation of the thread | sled to several RAM in a memory part, and the state of the storage area of RAM. It is a figure which shows another example of the delivery of the data between threads. It is a figure which shows the allocation of the thread | sled to several RAM in a memory part, and the state of the storage area of RAM. It is a figure which shows the allocation of the thread | sled to several RAM in a memory part, and the state of the storage area of RAM. It is a figure which shows the example of the delivery of the data between threads when the feedback data to a thread exists. It is a figure which shows the other example of a detailed structure of an integrated circuit device.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 10 ... Processing apparatus, 12 ... Reconfigurable circuit, 14 ... Setting part, 16 ... Circuit processing control part, 18 ... Control part, 20 ... Internal state holding circuit, 22 ... Output circuit, 23 ... 1st switching circuit, 24 ... Path unit, 25 ... second switching circuit, 26 ... integrated circuit device, 27 ... memory unit, 28 ... third switching circuit, 29 ... path unit, 30 ... compilation unit, 32 ... setting data generation unit, 34 ... storage unit, 36 ... Program, 38 ... Data flow graph, 40 ... Setting data, 50 ... Logic circuit, 52 ... Connector

Claims (18)

A reconfigurable circuit having a plurality of logic circuits capable of selectively executing a plurality of arithmetic functions and capable of simultaneously executing a plurality of threads,
A storage unit is provided between the preceding logic circuit and the succeeding logic circuit,
During execution of the plurality of threads, the storage unit stores data output from the preceding logic circuit at a first timing, and at a second timing following the first timing, the first Reconfigurable, wherein the stored data output from the preceding logic circuit is supplied to the succeeding logic circuit that executes the same thread as that executed by the preceding logic circuit at the timing circuit. A reconfigurable circuit having a plurality of logic circuits capable of selectively executing a plurality of arithmetic functions and capable of simultaneously executing a plurality of threads;
A first storage unit that stores an output from the reconfigurable circuit;
The processing apparatus, wherein the first storage unit is assigned to a thread that is executed on the reconfigurable circuit. The first storage unit includes a plurality of storage units,
The processing apparatus according to claim 2, wherein a thread allocated to each of at least a part of the plurality of storage units is changed every predetermined cycle.   4. The apparatus according to claim 2, further comprising: a first switching unit that selects an output from the reconfigurable circuit according to a thread and supplies the output to the first storage unit. 5. Processing equipment.   5. The second switching unit according to claim 2, further comprising a second switching unit that selects one of the outputs from the plurality of storage units according to a thread and supplies the selected output to the input of the reconfigurable circuit. The processing apparatus in any one. The first storage unit includes a plurality of storage units,
One of the two threads corresponding to the storage unit is allocated to the storage unit, and the allocation of the one thread can be switched to the other thread every predetermined cycle. The processing apparatus according to any one of claims 2 to 5. The first storage unit includes at least a pair of storage means,
The pair of storage means is assigned with a different thread, and the assignment of threads corresponding to each of the pair of storage means is switched to each other every predetermined cycle. Item 6. The processing device according to any one of Items 5 to 6. The first storage unit includes an information storage unit having a plurality of storage means,
8. The processing apparatus according to claim 2, wherein one of the storage units provided in the information storage unit stores an output of a predetermined thread from the reconfigurable circuit. 9.   9. The processing apparatus according to claim 8, wherein only one specific thread is fixedly assigned to any of the storage means provided in the information storage unit.   10. The processing apparatus according to claim 8, wherein each of the storage means provided in the information storage unit is assigned to the same address space.   The storage unit provided in the information storage unit determines whether or not to store the output of the predetermined thread from the reconfigurable circuit based on a specific address range. The processing apparatus according to claim 8. The storage area of the first storage unit is divided into a plurality of areas,
The processing apparatus according to claim 2, wherein a thread allocated to each of the divided storage areas is changed every predetermined cycle.   13. The system further comprises a switching unit that selects one of the divided outputs from the plurality of storage areas according to a thread and supplies the selected output to the input of the reconfigurable circuit. The processing apparatus in any one of.   The reconfigurable circuit stores data output from the preceding-stage logic circuit between the preceding-stage logic circuit and the subsequent-stage logic circuit, and is the same as the thread executed by the preceding-stage logic circuit. The processing apparatus according to claim 2, further comprising a second storage unit that supplies stored data to the subsequent logic circuit that executes a thread. A control unit that controls assignment of threads to the first storage unit;
15. The control unit according to claim 2, wherein the control unit changes assignment of a thread to the first storage unit, and stores data from a different thread in the first storage unit. Processing equipment.   The processing apparatus according to claim 15, wherein the control unit simultaneously changes the allocation of threads to the plurality of storage units or the plurality of divided storage areas.   The processing apparatus according to claim 15, wherein the control unit cyclically changes thread allocation to the first storage unit.   The process according to claim 15, wherein the control unit changes the correspondence between the first storage unit and the thread at a timing after execution of all threads is completed. apparatus.

Images