JP2009140514A - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device, capable of efficiently performing operation, and moreover, without increasing the manufacturing cost and the power consumption. <P>SOLUTION: The semiconductor device includes a first arithmetic engine which performs first operation for each cycle and outputs first data showing the result of the first operation and a first valid signal, showing a first value or a second value for every cycle; a second arithmetic engine which performs second operation for each cycle, and outputs second data showing the result of the second operation and a second valid signal, showing the first value or the second value for every cycle; and a buffer between arithmetic engines which is used to exchange the first data and the second data between the first arithmetic engine and the second arithmetic engine, and writes the first data or the second data, when the first valid signal or the second valid signal shows the first value, a code for the semiconductor device is generated. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a semiconductor device using dynamic reconfigurable circuit technology.

  In recent years, even in portable devices that require low cost and low power consumption, functions have become more complex and diversified, and high performance has been required. In order to achieve both high performance and low power consumption, development of dedicated hardware is inevitable, but its development and manufacturing costs are increasing year by year. As a means for reducing these, a semiconductor device using a dynamic reconfigurable circuit technique has attracted attention (for example, see Non-Patent Document 1).

  A semiconductor device using dynamic reconfigurable circuit technology is the same device as a normal processor that performs operations according to instructions given by software or the like, but differs from a normal processor in the following points. That is, the semiconductor device using the dynamic reconfigurable circuit technology can read and change the setting of the arithmetic unit corresponding to the instruction from the storage device during its operation. The contents of the storage device can be dynamically rewritten, and various operations can be performed with one instruction by dynamically rewriting the settings of the arithmetic unit stored in the storage device appropriately according to the usage status of the semiconductor device. it can. Thus, it is different from a normal processor in that the correspondence between the instruction and the setting of the arithmetic unit can be dynamically changed.

  In an ordinary processor in which the setting of the instruction and the arithmetic unit cannot be dynamically changed, the setting of the arithmetic unit is encoded so that different settings of the arithmetic unit correspond to different instructions, and this is set as an “instruction”. When the types of settings that can be realized by the arithmetic unit are increased for performance improvement, the bit width of the instruction increases, and the size of a storage device such as a memory necessary for storing the instruction also increases. As a result, the manufacturing cost increases, and the amount of power consumed when decoding the encoded arithmetic unit setting from the command also increases.

  On the other hand, in the semiconductor device using the dynamic reconfigurable circuit technology, the correspondence between the instruction and the setting of the arithmetic unit can be changed dynamically. The bit width of an instruction necessary for changing the setting of the arithmetic unit does not increase so much even if the type of setting that can be realized by the arithmetic unit increases.

  Therefore, a semiconductor device using the dynamic reconfigurable circuit technology is advantageous in terms of manufacturing cost and power consumption as compared with a semiconductor device such as a normal processor having equivalent arithmetic processing performance.

  In order to improve the performance of a semiconductor device using dynamic reconfigurable circuit technology, it is necessary to have a plurality of arithmetic units in such a semiconductor device and to control the setting changes of these arithmetic units independently. It is. In addition, it is also necessary to be able to transfer data after the calculation between the calculators and to change settings for the data transfer.

  In such a semiconductor device, when one arithmetic processing is performed in a flow work equation using a plurality of arithmetic units, when one arithmetic unit attempts to pass the arithmetic result to another arithmetic unit, There may be a situation where the computing unit that receives the computation result is not ready to receive it yet. In such a case, it is necessary to stop the processing of the arithmetic unit that is going to pass the calculation result, and also stop the processing of all the arithmetic units that are working before the arithmetic unit to be stopped in the flow work. is there. This stop process is called pipeline interlock process.

  In a semiconductor device using the conventional dynamic reconfigurable circuit technology, a pipeline interlock mechanism is not realized. For this reason, the number of arithmetic units and the number of buffers used for data transfer between arithmetic units are increased so that even if complicated arithmetic processing occurs, the situation where pipeline interlock processing is necessary does not occur so much. ing. More complicated arithmetic processing that cannot avoid the occurrence of pipeline interlock processing is divided into a plurality of arithmetic processing and executed sequentially.

“Reconfigurable System”, Ohm, page 141-208

  Since the pipeline interlock mechanism has not been realized, the number of arithmetic units and the number of buffers are increased in the semiconductor device using the conventional dynamic reconfigurable circuit technology in order to avoid pipeline interlock processing. There is a problem that the manufacturing cost increases due to this.

  Further, if a complicated arithmetic process is divided into a plurality of arithmetic processes and sequentially executed in order to avoid the pipeline interlock process, the arithmetic cannot be performed efficiently.

  As a method of changing complicated arithmetic processing to arithmetic processing that does not require pipeline interlock processing, the arithmetic unit that performs data transfer performs useless operations that are not related to the arithmetic processing, so that the timing of data transfer It is conceivable to adjust. However, this method has a problem of increase in power consumption accompanying execution of useless operations, and is not adopted in a semiconductor device using dynamic reconfigurable circuit technology mounted on a device that requires low power consumption. .

  The present invention has been made in view of the above, and an object of the present invention is to provide a semiconductor device that can efficiently perform an operation without increasing manufacturing cost and power consumption.

  A semiconductor device according to an aspect of the present invention performs a first calculation for each cycle, first data indicating a result of the first calculation, and a first value indicating a first value or a second value. A first operation engine that outputs a valid signal for each cycle; a second operation for each cycle; second data indicating a result of the second operation; and the first value or the A second valid engine that outputs a second valid signal indicating a second value for each cycle, and the first data and the second data between the first compute engine and the second compute engine. If the first valid signal or the second valid signal indicates the first value, the first data or the second data can be written. And the first valid signal or the first If valid signal indicates the second value comprises a buffer between the first data or calculation engine for prohibiting the writing of the second data.

  According to the present invention, it is possible to provide a semiconductor device that can efficiently perform an operation without increasing manufacturing cost and power consumption.

1 is a block diagram illustrating a semiconductor device according to an embodiment. Diagram showing the buffer between calculation engines Diagram showing the calculation engine The figure which shows the data register which the buffer between arithmetic engines has Diagram showing code transfer control unit Diagram showing code layout in code memory The figure which shows the arithmetic unit which the arithmetic engine has The figure which shows the arithmetic unit which the arithmetic unit has The figure which shows the output controller which the arithmetic engine has The figure which shows another output controller which a calculation engine has The figure which shows the input controller which the arithmetic engine has Flow chart showing the code generation procedure Diagram showing data dependency graph A flowchart showing the procedure of node scheduling processing Flow chart showing spill process Diagram showing data dependency graph after node replacement Flow chart showing the procedure of code output processing Timing chart when the semiconductor device is executed according to the code generated from the data dependence graph

  A semiconductor device 1 according to an embodiment is shown in FIG. The semiconductor device 1 is a reconfigurable device that performs data processing in response to an instruction from an external device such as a processor, and includes five arithmetic engines 11A to 11E, an arithmetic engine buffer 12, a code memory 13, and code transfer control. A device 14 and a data memory 15 are included. The data processing here is a general term for a series of operations performed by individual operations performed by the operation engines 11A to 11E.

  The code memory 13 is connected to the calculation engines 11A to 11E and the code transfer control device 14. The data memory 15 is connected to the input of the calculation engine 11A and is connected to the output of the calculation engine 11E. The arithmetic engine buffer 12 is connected to the inputs of the arithmetic engines 11B to 11E and is connected to the outputs of the arithmetic engines 11A to 11D.

  The calculation engines 11A to 11E are data processing engines capable of dynamically changing calculation settings. The calculation engines 11A to 11E perform calculation on the data input to the calculation engines 11A to 11E while changing the setting according to the code transferred from the code memory 13 before the start of data processing, and indicate the result of the calculation. The data is output to the inter-arithmetic engine buffer 12 together with a Valid signal.

  A detailed configuration of the buffer between the arithmetic engines is shown in FIG. The inter-arithmetic engine buffer 12 has eight data registers 120A to 120H, and is used for data exchange between the arithmetic engines. The arithmetic engines 11A to 11E select one of the data registers 120A to 120H according to the code and use it for reading and writing. However, at the time of writing to the inter-arithmetic engine buffer 12, if the Valid signal from the arithmetic engines 11A to 11D is 0, the writing is not performed.

  The code memory 13 stores codes used by the arithmetic engines 11A to 11E. The processor or the like transfers the code from the main storage device to the code memory 13 before the semiconductor device 1 starts data processing.

  The code transfer control device 14 has a function of sequentially reading codes from the code memory 13 after receiving a code transfer completion notification from a processor or the like and transferring them to the operation engines 11A to 11E, respectively.

  The data memory 15 temporarily stores data given by the semiconductor device 1 at the start of data processing, and intermediate results or final results of data processing by the semiconductor device 1. In addition, initial input data is written into the data memory 15 by an external device such as a processor before the start of data processing. The semiconductor device 1 can continue the data processing using the intermediate result of the data processing held in the data memory 15 as input data again. The final result held in the data memory 15 is read from the data memory 15 by an external device such as a processor and written to the main storage device.

  In this embodiment, the number of arithmetic engines 11A to 11E is five and the number of data registers 120A to H is eight. However, these numbers are changed according to the processing capability required for the semiconductor device 1. May be.

  A detailed configuration of the arithmetic engine 11A is shown in FIG. The arithmetic engine 11A includes an input controller 110, arithmetic units 113A to 113E, data pipeline registers 114A to E, control pipeline registers 115A to E, an output controller 116, a final context ID latch 117, and a multiplexer 118. Have.

  The input controller 110, the arithmetic units 113A to 113E, and the output controller 116 are connected to the code memory 13 and the code transfer control device 114. Codes respectively sent from the code memory 13 to the arithmetic engines 11A to 11E are stored in internal storage units of the input controller 110, the arithmetic units 113A to 113E, and the output controller 116 according to the tag values sent simultaneously from the code transfer control device 114. Each part used in each is divided and stored.

  The input controller 110 is also connected to the data memory 15. The input controller 110 sequentially interprets the codes stored in the internal storage unit, outputs an input A selection signal and an input B selection signal indicating the reference position of the input data, and reads data from the data memory 15.

  The input controller 110 is also connected to the control pipeline register 115A and the multiplexer 118, interprets the same code in order, and outputs a context ID and a Valid bit. At this time, the multiplexer 118 selects the value of the context ID output from the input controller 110 when the Valid bit is 1, and selects the value set in the final context ID latch 117 when the Valid bit is 0. This value is set in the control pipeline register 115A together with the Valid bit. The value selected by the multiplexer 118 is also set in the final context ID latch 117. The final context ID latch 117 is set to 0 at the start of data processing.

  The control pipeline registers 115A to 115D are connected to the control pipeline registers 115B to 115E, respectively. The control pipeline register 115E is connected to the output controller 116, so that a pipeline for controlling the operation of the arithmetic units 113A to 113E is obtained. It is composed. Therefore, the value of the context ID and the Valid bit set in the control pipeline register 115A by the input controller 110 in a certain cycle is sequentially transferred to the control pipeline registers 115B to 115E and the output controller 16 every cycle from the next cycle. Is done. Such transfer is called pipeline transfer.

  The arithmetic units 113A to 113E are connected to the control pipeline registers 115A to 115E, respectively. The outputs of the arithmetic units 113A to 113D are connected to the inputs of the arithmetic units 113B to 113E via the data pipeline registers 114A to 114D, respectively, thereby constituting a data pipeline for calculating data. The input of the arithmetic unit 113A is connected to the data memory 15. Further, the output of the arithmetic unit 113E is connected to the inter-arithmetic engine buffer 12 via the data pipeline register 114D.

  The arithmetic units 113A to 113E can change the arithmetic setting, read the code from the internal storage unit using the context ID set in the control pipeline register 115A to E for each cycle as an address, and select the code based on the code. The calculation setting is changed according to the set information. Then, an operation is performed on the data set in the input A data signal and the input B data signal in the cycle according to the changed setting, and the operation results are written in the data pipeline registers 114A to 114E, respectively. However, when the Valid bit set in the control pipeline registers 115A to 115E is 0, the operation result is not written to the data pipeline registers 114A to 114E.

  As described above, in the arithmetic engine 11, when the Valid bit output from the input controller 110 is 0, the setting information indicated by the context ID stored in the final context ID latch 117 is used as the setting of the arithmetic unit 113. Therefore, while the Valid bit is 0, the setting of the arithmetic unit 113 does not change. In addition, since the value of the data pipeline register 114 does not change while the Valid bit is 0, the output result of the arithmetic unit 113 that performs an operation using the valid bit as an input also does not change. As described above, in the semiconductor device 1, the change in the signal line that occurs when the Valid bit is 0 is reduced, so that the power consumed by the arithmetic unit 113 and the data pipeline register 114 is not used in the pipeline interlock. This is smaller than the dynamically reconfigurable circuit.

  The output controller 116 is connected to the inter-engine buffer 12. The output controller 116 reads the code from the internal storage unit using the context ID output from the control pipeline register 115E as an address, and outputs an output selection signal indicating the output position of the data according to the code. Further, the Valid bit set in the control pipeline register 115E is output as it is as a Valid signal.

  The arithmetic engines 11B to 11E are different from the arithmetic engine 11A in connection relation with other devices constituting the semiconductor device 1, but the internal configuration is the same as that of the arithmetic engine 11A. The input controller 110 and the arithmetic unit 113A included in the arithmetic engines 11B to 11E are connected to the inter-arithmetic engine buffer 12. The output controller 116 and the data pipeline register 114E included in the arithmetic engine 11E are connected to the data memory 15.

  Although the number of the arithmetic units 113 of the arithmetic engines 11A to 11E is five, it may be changed according to the processing capability required for the semiconductor device 1. Further, the number of the arithmetic units 113 may be different for each of the arithmetic engines 11A to 11E.

  Next, the flow from the start to the end of processing in the semiconductor device 1 will be described. The processing of the semiconductor device 1 can be broadly divided into two types: initialization processing before data processing and data processing.

  First, the initialization process will be described.

  An external device such as a processor stores input data to the semiconductor device 1 in the data memory 15, and stores a code defining the operation of the arithmetic engines 11 </ b> A to 11 </ b> E in the code memory 13.

  When the storage of the code in the code memory 13 is completed, the external device such as a processor notifies the semiconductor device 1 of the completion of the code transfer by a pulse signal. When the code transfer control device 14 receives a code transfer completion notification from the semiconductor device 1, the code transfer control device 14 sequentially reads the codes from the code memory 13 and transfers them to each of the operation engines 11 </ b> A to 11 </ b> E together with a tag indicating the storage location.

  The codes transferred to the arithmetic engines 11A to 11E are divided and stored in the storage units inside the input controller 110, the arithmetic units 113A to E, and the output controller 116 for each part used.

  When the code transfer control device 14 completes the code transfer to the operation engines 11A to 11E, it notifies the external device such as a processor of the completion of the operation preparation.

  An external device such as a processor notifies the semiconductor device 1 of the start of data processing by a pulse signal after receiving a notification of completion of calculation preparation.

  Next, data processing will be described.

  The input controller 110 interprets the code stored in the internal storage unit for each cycle, and outputs a context ID and a Valid bit for each cycle according to the code. Then, as described above, either one of the context ID output by the input controller 110 according to the Valid bit and the context ID stored in the final context ID latch 117 is selected, and the context ID is combined with the Valid bit and the arithmetic units 113A to 113E and It is transferred to the output controller 116 in a pipeline manner. The input controller 110 outputs an input A selection signal and an input B selection signal for each cycle according to the code.

  The data memory 15 and the computation engine buffer 12 read data according to the input A selection signal and the input B selection signal output by the input controller 110 of the computation engines 11A to 11E for each cycle, and the data of the computation unit 113A of the computation engines 11A to E The data is set in the input A data signal and the input B data signal.

  The arithmetic units 113A to 113E read the code from the internal storage unit using the context ID as an address for each cycle, and change the arithmetic setting according to one piece of setting information selected by the code. Then, an operation is performed on the data set in the input A data signal and the input B data signal in the cycle according to the changed setting. The operation result is transferred in a pipeline manner to the data memory 15 or the inter-operation engine buffer 12 via the data pipeline registers 114A to 114E. However, when the Valid bit is 0, the operation result is not written to the data pipeline registers 114A to 114E.

  For each cycle, the output controller 116 reads a code from the internal storage unit using the context ID as an address, and outputs an output selection signal indicating the data output position according to the code. Further, the Valid bit set in the control pipeline register 115E is output as it is as a Valid signal.

  The data memory 15 and the inter-engine buffer 12 write the value set in the data pipeline register 114E at a location specified by the output selection signal every cycle. However, this writing is performed only when the Valid signal is 1, and when the Valid signal is 0, writing is not performed.

  When the input controllers 110 of the arithmetic engines 11A to 11E have interpreted all the codes, the semiconductor device 1 notifies the external device such as a processor of completion of data processing. Thus, the data processing ends.

  An external device such as a processor reads out the calculation result of the semiconductor device 1 stored in the data memory 15 after a predetermined cycle or more has elapsed after receiving the notification of completion of data processing. This prescribed cycle is the number of cycles obtained by adding the number of arithmetic units 113 included in the arithmetic engine 11 that has finally interpreted the code and the number of cycles required for writing data to the data memory 15.

  Next, the data register 120, the code transfer control unit 14, the arithmetic unit 113, the output controller 116, and the input controller 110 that realize data processing in the semiconductor device 1 as described above will be described in detail.

  An implementation example of the data register 120 is shown in FIG. The data register 120 includes a data latch 1200, AND logics 1201A to 1201D, an OR logic 1202, and a multiplexer 1203. Data is stored in the data latch 1200.

  The AND logics 1201A to 1201D respectively input the ANDs of the decoders A to D outputs and the Valid A to D signals to the OR logic 1202. Thereby, only when the Valid signal from at least one of the arithmetic engines 11A to 11D is 1, and the output selection signal selects the data register 120 (that is, the outputs of the decoders A to D are 1), The OR logic 1202 outputs 1; otherwise, it outputs 0. An output signal from the OR logic 1202 is used as a write enable signal for the data latch 1200. For this reason, when the Valid signal is 0, data is not written to the data register 120.

  The multiplexer 1203 selects the write data A to D from the arithmetic engines 11A to 11D when the Valid A to D signals are 1. For example, when the ValidA signal is 1, the write data A from the arithmetic engine 11A is selected. When the ValidB signal is 1, the write data B from the arithmetic engine 11B is selected. The same applies to the Valid C to D signals. Data selected by the multiplexer 1203 is written into the data latch 1200. The operation when the Valid A to D signals are all 0 or when two or more of the Valid A to D signals are 1 is undefined. However, when the Valid A to D signals are all 0, data is not written into the data latch 1200 as described above.

  An implementation example of the code transfer control unit 14 is shown in FIG. The code transfer control unit 14 includes a memory ID register 140, an address register 141, a code address register 142, incrementers 143A to C, multiplexers 144A to D, a valid latch 145, and a comparator 146.

  As shown in FIG. 6, it is assumed that codes are continuously arranged in the code memory 13 for each type of code storage memory included in the arithmetic engines 11A to 11E. It is assumed that an End bit is added to each code. The value of the End bit is 1 only in the case of a code corresponding to the end of a continuous code for each type of memory, and 0 in the case of other codes.

  The code transferred from the code memory 13 to the arithmetic engines 11A to 11E includes a memory ID indicating the type of memory for storing the code, an address indicating where the memory is stored, and A valid bit indicating validity is added by the code transfer control unit 14. The values of the memory ID, address, and valid bit are stored in the memory ID register 140, address register 141, and valid latch 145, respectively. A set of a memory ID, an address, and a Valid bit is called a code tag.

  The code address register 142 stores an address used when reading a code from the code memory 13.

  Before an external device such as a processor notifies the semiconductor device 1 of the completion of code transfer, the code address register 142 stores the leading address of the code memory 13 storing a code required for data processing via the external bus in advance. Write in.

  When the semiconductor device 1 receives the code transfer completion notification, the initial value 0 is selected by the multiplexers 144A-B and stored in the memory ID register 140 and the address register 141. Further, 1 is selected by the multiplexer 144D and set in the Valid latch 145.

  From the next cycle, the values of the memory ID register 140, the address register 141, and the valid latch 145 are added to the code sent from the code memory 13 and transferred to the arithmetic engines 11A to 11E. At the end of the cycle, the values of the address register 141 and the code address register 142 are incremented by 1 by the incrementers 143B to 143C, respectively.

  When a code whose End bit is 1 is transferred from the code memory 13, the value of the memory ID register 140 is incremented by 1 by the incrementer 143A at the end of the cycle, and 0 is selected by the multiplexer 144B and the address register 141 The value is reset to 0.

  Thereafter, the same processing is repeated until the value of the memory ID register 140 becomes the maximum value +1 of the effective memory ID. When the value of the memory ID becomes the maximum value +1 of the valid memory ID, 0 is set in the Valid latch 145, and the code transfer to the arithmetic engines 11A to 11E is completed.

  An implementation example of the arithmetic unit 113 is shown in FIG. The arithmetic unit 113 includes an arithmetic unit 1130 capable of dynamically changing settings, a control table memory 1131, setting information registers 1132A to 1132D, and a multiplexer 1133.

  The setting information registers 1132A to 1132D store setting information used by the computing unit 1130 in data processing. The number of setting information registers 1132 may be changed according to the application. In the control table memory 1131, selection signal values of the setting information registers 1132 </ b> A to 1132 </ b> D are stored in order from the top by the number of types of context IDs used in data processing.

  The setting information registers 1132A to 1132D and the control table memory 1131 are updated with codes transferred from the code memory 13 in initialization. When the Valid bit added to the code by the code transfer control device 14 is 1 and the memory ID added to the code matches the memory ID indicating the setting information registers 1132A to 1132D and the control table memory 1131, the memory ID Are written in the control table memory 1131 or the setting information registers 1132A to 1132D that coincide with each other. When a code is written in the control table memory 1131, an address added to the code by the code transfer control device 14 is used as a write address.

  An implementation example of the computing unit 1130 is shown in FIG. The arithmetic unit 1130 includes four 8-bit ALUs and four shifters, respectively, and can be set to perform different operations in units of 8 bits with respect to two 32-bit inputs. As described above, the setting of the calculator 1130 can be changed dynamically. This calculation result is set as one of 32-bit outputs. The arithmetic unit 1130 includes a crossbar, and the result of changing the arrangement order of the four 8-bit outputs from the shifter is one of the 32-bit outputs.

  In this example, the setting information of the arithmetic unit 1130 is 1 bit for the input mode for determining whether one of the inputs of the ALU is to be a direct value, 8 bits for the direct value, and 2 bits for the ALU setting per 8-bit operation. It consists of 16 bits in total, 3 bits for the value and 2 bits for the crossbar setting. The arithmetic unit 1130 as a whole has 64-bit setting information.

  The arithmetic unit 1130 reads the value from the control table memory 1131 using the context ID transmitted from the input controller 110 as an address, selects one of the setting information registers 1132A to 1132D as the selection signal of the multiplexer 1133, and from there The setting information is read and applied to the calculator 1130. This realizes an operation of changing the calculation setting for each context ID.

  An implementation example of the output controller 116 included in the arithmetic engine 11E is shown in FIG. The output controller 116 included in the arithmetic engine 11E includes base address registers 1160A to 1160B, a control table memory 1161, an adder 1162, and a multiplexer 1163.

  Base address registers 1160A to 1160B store base addresses used when calculating an output address to the data memory 15. The number of base address registers 1160 may be an arbitrary number of 1 or more. The control table memory 1161 stores a selection signal value for selecting the base address registers 1160A-B and an offset in pairs. The initial setting of the base address registers 1160A-B and the control table memory 1161 is performed by the same method as the initialization of the setting information memory 1132 of the arithmetic unit 113.

  The output controller 116 of the arithmetic engine 11E refers to the control table memory 1161 using the context ID transmitted from the input controller 110 as an address, and selects the base address registers 1160A to 1160B that store base addresses used for address calculation. The selection signal value and the offset for reading are read from the control table memory 1161. The read selection signal value becomes the selection signal of the multiplexer 1163, and any one of the base address registers 1160A to 1160B is selected, and the base address stored therein is read. The read base address is output to the outside as an output selection signal, and the adder 1162 adds the offset. The addition result is written back to the selected base address register 1160. However, when 0 is input as the Valid bit, the base address register 1160 is not updated.

  On the other hand, the output controller 116 included in the calculation engines 11A to 11D is different from the output controller 116 included in the calculation engine 11E as illustrated in FIG. In the control table memory 1161 of the output controller 116 included in the arithmetic engines 11A to 11D, the value of the selection signal for selecting one of the data registers 12A to 12H of the inter-arithmetic engine buffer 12 used for output is used for data processing. Stored in correspondence with the number of context IDs.

  The output controller 116 included in the arithmetic engines 11A to 11D reads the value of the selection signal from the control table memory 1161 using the context ID transmitted from the input controller 110 as an address, and outputs it as an output selection signal.

  FIG. 11 is a diagram illustrating an implementation example of the input controller 110 included in the calculation engines 11A to 11E. The input controller 110 includes an input A selection unit 1100, an input B selection unit 1101, a context information memory 1102, a context ID latch 1103, a data processing end latch 1104, an incrementer 1105, a multiplexer 1106, and latches 1107A to 1107A. B and timing latches 1108A-B.

  The input A selection unit 1100 and the input B selection unit 1101 are circuits for generating an input A selection signal and an input B selection signal, respectively. In the case of the input controller 110 included in the calculation engine 11A, these are the same as the output controller 116 included in the calculation engine 11E, and in the case of the input controller 110 included in the calculation engines 11B to E, the calculation engines 11A to 11D. The output selection signal is used as the input A to B selection signal. The Valid signal is not output.

  The context information memory 1102 stores context information including a Valid bit and a data processing end bit by the number of context IDs used in data processing.

  The context ID latch 1103 stores the value of the context ID to be output. When the context ID is output, the value of the context ID latch 1103 is incremented by 1 by the incrementer 1105.

  The data processing end latch 1104 is a latch that stores a signal indicating whether or not the data processing is completed. In the initial state of the semiconductor device 1, the value of this latch is 1 which means the completion of data processing.

  Next, the operation of the input controller 110 will be described.

  When an external device such as a processor notifies the semiconductor device 1 of the start of data processing, the data processing end latch 1104 is set to zero. In this cycle, the context ID latch 1103 indicates 0, and the context information stored at address 0 of the context information memory 1102 is read. The Valid bit and the data end bit included in the read context information are set in the latches 1107A to B, respectively.

  In the next cycle, the input A selection unit 1100 and the input B selection unit 1101 select the input A selection signal and the input B respectively according to the context ID stored in the context ID latch 1103 and the Valid bit stored in the latch 1107A. Output a signal. The context ID and valid bit have the timing at which they arrive at the arithmetic unit 113A and the timing at which the input A data and input B data read by the input A selection signal and the input B selection signal respectively arrive at the arithmetic unit 113A. After the timings are adjusted by the timing latches 1108A-B so as to be equal, they are output to the arithmetic unit 113A. At the end of the cycle, the value of the context ID latch 1103 is incremented by 1 by the incrementer 1105. Similarly, while 0 is read from the context information memory 113 as the data processing end bit, the context ID and the Valid bit are output for each cycle.

  When 1 is read from the context information memory 113 as the data processing end bit, the context ID and the Valid bit are output, and the data processing end latch 1104 is set to 1.

  After the next cycle, 1 is output as the data processing completion signal, and since the data processing end latch 1104 is 1, the Valid bit is 0. This state is a state where the data processing is completed in the arithmetic engine 11.

  As described above, the arithmetic engines 11A to 11E output both the data and the Valid signal at the same timing by pipeline transfer. The inter-arithmetic engine buffer 12 writes only the data received when the Valid signal is 1 to the buffer (corresponding to the data register 120).

  Here, the input controller 110 is controlled by software according to the code stored in the context information memory 1102 so that 0 can be output as the Valid signal in a cycle in which it can be predicted that there is no buffer available in the inter-arithmetic engine buffer 12. For example, in a configuration that does not have a pipeline interlock mechanism, the semiconductor device 1 can perform operations efficiently even if the number of arithmetic units and the number of buffers of the inter-arithmetic engine buffer 12 are reduced.

  When the number of buffers included in the inter-arithmetic engine buffer 12 is small, conventional dynamic reconfigurable circuit technology that does not use pipeline interlocks for the power consumed by the operation of temporarily storing the operation results in these buffers. It becomes possible to make it smaller as compared with a semiconductor device using the. Further, an increase in manufacturing cost can be suppressed.

  Further, in the present embodiment, the arithmetic engines 11A to 11E include a final context ID latch 117 that stores the context ID output in the immediately preceding cycle, and a multiplexer 118. When the Valid bit output from the input controller 110 is 0, the context ID stored in the final context ID latch 117 is selected by the multiplexer 118 and output to the arithmetic unit 113 together with the Valid bit by pipeline transfer. To control. The output result of the arithmetic unit 113 is not written to the data pipeline register 114 when the Valid bit is 0. For this reason, while the Valid bit is 0, the input / output data signal and the setting signal of the arithmetic unit 113 do not change from the state where the Valid bit was 1 at the end.

  Therefore, not only the inter-arithmetic engine buffer 12 but also the power consumed by the arithmetic unit 113 and the data pipeline register 114 in the arithmetic engine 11 are compared with the conventional dynamic reconfigurable circuit that does not use the pipeline interlock. It can be made smaller.

  As described above, efficient calculation and reduction of power consumption can be achieved by software control of the input controller 110. The code for that purpose needs to be created in advance by another semiconductor device or the like and stored in the code memory 13 and transferred and stored in advance in the context information memory 1102 by the code transfer control device 14 before starting data processing. . In the following, a compiler that creates the code of the input controller 110 in advance will be described.

  This compiler can be realized as a computer program, for example, a data dependence graph showing how calculation results are transferred between the calculation engines 11A to 11E, and the number of pipeline stages of the calculation engines 11A to 11E. A storage unit for inputting and storing the number of cycles required for reading and writing the data memory, a code stored in the context information memory 1102 of the input controller 110 with reference to the information stored in the storage unit, and an arithmetic engine A code generation unit that generates a code stored in the control table memory 1161 included in 11A to 11D. The data dependence graph data is prepared in advance by the user, for example.

  One feature of the semiconductor device 1 of the present embodiment is that the number of buffers of the inter-arithmetic engine buffers 12 necessary for realizing a given performance can be reduced. For this reason, the compiler must also be able to generate code correctly even when the number of buffers of the inter-arithmetic engine buffer 12 is small.

  For this purpose, in the compiling method described in detail below, the order in which the operation engines 11A to 11E execute a plurality of given operations is determined as follows. That is, rather than an operation in which no data that is input to the operation is generated, a part of the data that is input to the operation is already calculated, and a part of the data is stored in the inter-engine buffer 12. The operation as written is preferentially executed. By doing so, the data retention time in the inter-engine buffer 12 can be reduced as much as possible. Such a compiling method is different from the conventional compiling method which presupposes that the inter-operation engine buffer 12 has many buffers.

  Hereinafter, the compiling method according to the present embodiment will be described in detail.

  The compiler outputs code stored in the context information memory 1102 included in the operation engines 11A to 11E and code stored in the control table memory 1161 included in the operation engines 11A to 11D. For this reason, the above-described code generation unit analyzes a data dependence graph representing a data dependence relationship between input and output for a plurality of computations performed by the computation engines 11A to 11E. As described above, the data dependence graph represents how calculation results are transferred between the calculation engines 11A to 11E.

  The code generation unit specifies from the data dependence graph an operation in which a part of data to be input to a certain operation has already been calculated and a part of the data is written in the inter-operation engine buffer 12 And a scheduling unit that determines the order of operations performed by the operation engines 11A to 11E so that such operations are executed with priority, and according to this order, each of the operation engines 11A to 11E performs operations in each cycle. If each of the calculation engines 11A to 11E performs a calculation, 1 is output as the Valid bit from the corresponding input controller 110, and if the calculation is not performed, the corresponding input controller And a generation unit that generates a code for outputting 0 as a Valid bit from 110. The code generation unit also generates a code that defines which calculation setting the calculation engines 11A to 11E should use for each cycle.

  A more specific processing procedure for code generation follows, for example, the procedure shown in the flowchart of FIG.

  FIG. 13 shows an example of the data dependence graph. One node of the data dependence graph corresponds to one calculation executed by the calculation engine 11. The arrow in the data dependence graph indicates that the result of the operation corresponding to the node connected to the source of the arrow is used as the input of the operation corresponding to the node connected to the end of the arrow. The data dependence graph of this example has the following restrictions. That is, it is assumed that the number of nodes that are input to an arbitrary node is at most two, and the output of an arbitrary node is always used only as an input of one node. A label of any of A to E for identifying the calculation engines 11A to 11E that execute the calculation is given to the node of the data dependence graph. Further, an ID (for example, a number starting from 0) is assigned to each label node.

  A method for obtaining which calculation setting should be used for each cycle by the calculation engines 11A to 11E from the data dependence graph of FIG. 13 will be described with reference to the flowchart of FIG.

  For ease of explanation, it is assumed that the latency of the operation engines 11A to 11E is 1, and the inter-operation engine buffer 12 has only two data registers 120A to 120B. This method can also be applied when the number of data registers 120 is greater than two. The present invention can also be applied when the latency of the arithmetic engines 11A to 11E is 2 or more. Here, the latency of the calculation engine 11 refers to the number of cycles necessary for the calculation engine 11 to complete the calculation. For example, if the number of arithmetic units 113 of the arithmetic engine 11 is five, the latency is five.

  First, initialization processing is performed in step S0. The processed node set is emptied, and the data dependence graph of FIG. The use start time and the useable time of the data registers 120A to 120B are set to 0, and the use time of the arithmetic engines 11A to 11E is set to L. L is the number of cycles required for reading and writing the data memory, and is 1 here. For each node N of the data dependency graph, another node N ′ that outputs to the same node as the node N is specified. Node N 'is registered in the item of node N in the node pair table. If the node N ′ does not exist, the item of the node N is emptied. When the node N ′ exists, it is expressed as “the node N and the node N ′ are a pair”. Then empty the spill node stack.

  In step S1, it is checked whether a priority processing node exists in the graph G. A priority processing node is a node that is not included in the processed node set, has two input nodes, and only one of the input nodes is included in the processed node list. This priority processing node corresponds to an operation in which a part of data serving as an operation input has already been calculated and the operation result is written in the inter-operation engine buffer 12. The feature of step S1 is that such calculation is processed preferentially. At this point in time, the processed node set does not include even one node, so the process proceeds to step S2.

  In step S2, it is checked whether a processable node exists in the graph G. A processable node is a node that is not included in the processed node set and that all of the input nodes are included in the processed node list or does not have an input node. In this example, there are nodes A0 to A3 that are processable nodes, so the process proceeds to step S3.

  In step S3, the deepest processable node N in the graph G is obtained. In this example, the nodes A0 to A3 all have the same depth, so one arbitrary node is selected. Here, for example, it is assumed that the node A0 is selected.

  In step S4, it is determined whether the processable node N obtained in step S3 can be scheduled. “Schedulable” means that the processable node N does not have an output, or at least one of the data registers 120 that can be used for the result output of the processable node N is another node that is an input of the node N. It means being used for the result output or satisfying the condition that the usable time is not infinite. Here, when the node N ′ that is a pair of the node N exists and the node N ′ is included in the processed node set, the data register 120 used for the result output of the node N ′ It cannot be used for result output. At this point, since the processed node set is empty, the node A0 can be scheduled. Proceed to step 5.

  In step S5, the node N is scheduled. The scheduling process in step S5 is performed according to a flowchart as shown in FIG. 14, for example.

  First, in step S5A, it is checked whether there is a node serving as an input for the node N. In this example, since the node A0 has no input node, the process proceeds to step S5B.

  Next, in step S5B, out of the data registers 120 that can be used for the result output of the node N, one register R having the minimum usable time is selected. However, if the node N has no output, the register R is arbitrarily selected. At this time, the usable times of the data registers 120A to 120B are all 1, so either one may be used. Here, the data register 120A is used.

  Next, in step S5C, the value obtained by adding the latency of the arithmetic engine 11 to the executable time of the node N is compared with the available time of the register R. The executable time of the node N is the later of the usable time of the data register 120 used by any input node of the node N for the result output and the usable time of the arithmetic engine 11. When the node N has no input node, the executable time of the node N is equal to the usable time of the arithmetic engine 11. If the node N has no output, the process always proceeds to step S5D. In this example, the usable time of the data register 120A is smaller, so the process proceeds to step S5D.

  In step S5D, the execution time of node N is set as the executable time of node N obtained in step S5C, and the available time of the calculation engine 11 is obtained by adding 1 to the execution time of node N. Further, the use start time of the register R is obtained by adding the latency of the arithmetic engine 11 to the execution time of the node N, and the useable time of the register R is infinite. Also, let N be the node that owns the register R. However, when the node N has no output, the use start time and the usable time of the register R are not updated. In this example, the execution time of A0 is 1, the usable time of the arithmetic engine 11A is 2, the usage start time of the data register 120A is 2, and the usable time of the data register 120A is infinite. The node owned by the data register 120A is A0.

  In step S5E, a set of registers R from which nodes N and N output the result is added to the processed node set. In this example, a set of the node A0 and the data register 120A is added to the processed node set.

  When step S5 is completed as described above, the process returns to step S1. A series of steps performed from the start of step S1 to returning to step S1 will be referred to as iteration.

  In the next iteration I1, since the priority processing node B0 is found in step S1, the process proceeds from step S1 to step S6.

  In step S6, the graph G is first stacked on the top of the graph stack. Next, among the input nodes of the priority processing node obtained in step S1, the maximum connected subgraph G of the graph G including the input node N ′ that is not included in the processed node set and does not include the priority processing node. Ask for '. G ′ is called a priority processing graph. Then, the priority processing graph G ′ is set in the graph G. In this example, the priority processing graph G ′ is a graph including only the node A1. The process returns from step S6 to step S1 and proceeds to iteration I2. In this example, in the iteration I2, the process proceeds from step S1 to S2 and S3, and the node A1 becomes the deepest processable node.

  In step S4, since the node A0 which is a pair of the node A1 uses the data register 120A for the result output, only the data register 120B can be used for the result output of the node A1. Since the usable time of the data register 120B is 0, the node A1 can be scheduled, and the process proceeds to step S5. In step S5, the process proceeds from step S5A to S5B, S5C, S5D, and S5E, as in the case of node A0. The execution time of node A1 is 2, the usable time of computing engine 11A is 3, and the use start time of data register 120B. 3, the usable time of the data register 120B is infinite, and the owning node of the data register 120B is the node A1. A set of the node A1 and the data register 120B is added to the processed node set. Processing proceeds to iteration I3.

  In iteration I3, the process proceeds from step S1 to S2, and since there is no longer any processable node in the graph G, the process proceeds to step S7.

  In step S7, it is checked whether the graph stack is empty. If not empty, the process proceeds to step S8, where a graph is extracted from the top of the graph stack and set in the graph G. In this example, since the graph is stacked in the iteration I1, the process proceeds to step S8, where the graph is extracted from the graph stack and set in the graph G. The graph G at this time is the same as that shown in FIG.

  In step S10, it is checked whether the spill node stack is empty. When the spill node stack is not empty and the node existing in the graph G is stacked at the top of the spill node stack, spill correspondence is required. Since the spill node stack is empty at this point, the process proceeds to iteration I4.

  In iteration I4, the process proceeds from step S1 to S2 and S3, and node B0 is the deepest processable node. Since both of the data registers 120A-B can be used for the result output of the node B0 and they are used for the result output of the nodes A1 and A2 which are the inputs of the node B0, the node B0 can be scheduled. .

  In step S5, since the node B0 has an input node, the process proceeds from step S5A to S5F. In step S5F, for the processable node N having the deepest depth obtained in step S3, the data register 120 used for the result output and its use start time are obtained for each input node. Then, a value obtained by adding 1 to the maximum value of the obtained use start time is set as all the available data register use times. In this example, the usable times of the data registers 120A to 120B are 4 respectively.

  In step S5B, since the usable times of the data registers 120A to 120B are equal, either one may be selected. Here, it is assumed that the data register 120A is selected. Hereinafter, the process proceeds from step S5C to S5D and S5E, the execution time of the node B0 is 4, the usable time of the arithmetic engine 11B is 5, the usage start time of the data register 120A is 5, and the usable time of the data register 120A is Infinite, the node owned by the data register 120A is B0. A set of the node B0 and the data register 120A is added to the processed node set. Processing proceeds to iteration I5.

  In iteration I5, node E0 is preferentially processed in step S1, step S6 is processed, and the process proceeds to iteration I6.

  In iteration I6, the process proceeds from step S1 to S2, S3, S4, and node A2 is scheduled in step S5. In step S5, the process proceeds from step S5A to S5B. In step S5C, the usable time of the data register 120B is equal to or greater than the executable time +1 of the node A2, so the process proceeds to step S5G.

  In step S5G, a value obtained by subtracting the latency of the arithmetic engine 11 that executes node N from the usable time of register R obtained in step S5C is set as the execution time of node N. Other values are obtained in the same manner as in step S5D. In this example, the execution time of A2 is 3, the usable time of the arithmetic engine 11A is 4, the usage start time of the data register 120B is 4, and the usable time of the data register 120B is infinite. The owned node of the data register 120B is A2. Proceed to iteration 7.

  In iteration 7, the process proceeds from step S1 to S6, and the graph G becomes a graph of only the node A3.

  In iteration 8, the process proceeds from step S1 to S2 and S3. At step S4, node A3 is to be scheduled. Since both data registers 120A and 120B have infinite usable time, node A3 cannot be scheduled. is there. The process proceeds to step S9.

  The procedure of the spill process in step S9 is shown in the flowchart of FIG. First, in step S9A, one of the data registers 12A to 12B to be written back to the data memory 15 is selected. This write back is called register spill processing. When there is a node N ′ that is a pair of nodes N that cannot be scheduled, a data register 12 that is not used for outputting the result of the node N ′ is selected. If there is no node N ′ which is a pair of nodes N, an arbitrary data register 12 is selected. In this example, the data register 12A is selected.

  In step S9B, the time for performing the register spill process in the arithmetic engine 11E is obtained. The usable time of the arithmetic engine 11E is compared with the use start time of the data register 12 to be written back to the data memory plus 1, and the larger one is the time for register spill processing. Further, the execution time of a node (data saving node) newly added to the graph as representing data saving performed by the arithmetic engine 11E and the usable time of the data register 12 are set as the time for performing the register spill processing. In this example, time 6 is the time for performing the register spill process, and the execution time of the data saving node E1 and the usable time of the data register 12A are 6.

  In step S9C, a set of a time obtained by adding 2 × L to the time when register spill processing is performed and the owning node of the data register 12 is stacked on the spill stack. In this example, a set of node B0 and time 8 is stacked on the spill stack. Proceed to step S5.

  In step S5, since the use start time of the data register 12A has been updated to 6, the execution time of A3 is 5, the useable time of the arithmetic engine 11A is 6, the use start time of the data register 120A is 6, and the data register 120A The usable time of is infinite. The node owned by the data register 120A is A3. Processing proceeds to iteration 9.

  In iteration 9, the process proceeds from step S1 to S2, S7, and S8. In step S10, the spill stack is not empty, but the graph G extracted from the graph stack in step S8 does not include the node B0 at the top of the spill stack.

  In iteration 10, the process proceeds from step S1 to S2, S3, S4, and S5. The execution time of the node B1 is 7, the usable time of the arithmetic engine 11B is 8, the usage start time of the data register 120B is 8, and the usable time of the data register 120B is infinite. The node that owns the data register 120B is B1. Proceed to iteration 11.

  In iteration 11, the process proceeds from step S1 to S2, S7, and S8. In step S10, it is determined that spill handling is necessary, and the process proceeds to step S11.

  In step S11, a node / time pair is first taken out from the top of the spill stack. Then, the usable time of the arithmetic engine 11A is set as the extracted time. Further, a maximum connected subgraph (that is, a priority processing graph) G ′ that includes the extracted node and does not include the output of the node is obtained from the graph G. This priority processing graph G 'is replaced with a node of the arithmetic engine 11A for data restoration. In this example, the usable time of the arithmetic engine 11A is 8, and the updated data dependence graph is as shown in FIG. Proceed to iteration 12.

  In the iteration 12, the process proceeds from step S1 to S2, S3, S4, and S5, and the data restoration node A4 generated in the iteration 11 is scheduled. The execution time of the node A4 is 8, the usable time of the arithmetic engine 11A is 9, the usage start time of the data register 120A is 9, and the usable time of the data register 120A is infinite. The node owned by the data register 120A is A4. Processing proceeds to iteration 13.

  In iteration 13, the process proceeds from step S1 to S2, S3, S4, and S5, the execution time of node E0 is 10, and the usable time of computing engine 11E is 11.

  In the next iteration 14, the process proceeds from step S1 to S2 and S7. Since the graph stack is empty, the process proceeds to step S12 for finally outputting a code.

  The procedure of the code output process in step S12 is shown in the flowchart of FIG. First, in step S12A, a variable C indicating an address is initialized to zero.

  In step S12B, the context information stored at the address C in the context information memory 1102 included in each of the arithmetic engines 11A to 11E is initialized. By this initialization, the Valid bit and the data processing end bit are each initialized to 0.

  In step S12C, for all nodes N included in the processed node set, all nodes whose execution time is C are obtained. If there is even one such node, the process proceeds to step S12E, and if none exists, the process proceeds to step S12F.

  In step S12E, for each node N found in step S12C, the Valid bit stored in the address C of the context information memory 1102 included in the arithmetic engine 11 that executes the node N is updated to 1. When the node N has an output, the value indicating the register R is used as the value of the selection signal for selecting one of the data registers 12A to 12H of the inter-arithmetic engine buffer 12, and the operation for executing the node N The data is stored in the address C of the control table memory 1161 included in the engine 11. Further, all the nodes N found in step S12C are deleted from the processed node set.

  In step S12F, it is determined whether the processed node set is empty. If not empty, the process proceeds to step S12H, updates the address C to C + 1, and returns to step S12B. If it is empty, the process proceeds to step S12G.

  In step S12G, the data processing end bit stored at address C in the context information memory 1102 of the input controller 110 of the arithmetic engines 11A to 11E is set to 1, and the code generation is completed.

  FIG. 18 shows a timing chart when the semiconductor device 1 is executed according to the code generated from the data dependence graph of FIG. 13 by the compiling method described above. In FIG. 18, in each cycle in which the calculation result of the calculation engine 11 is output together with a Valid bit of 1, a label (see FIG. 13) corresponding to the calculation is shown. FIG. 18 also shows in which cycle the value of the data register 120 changes.

  Note that the present invention is not limited to the above-described embodiment as it is, and can be embodied by modifying the constituent elements without departing from the scope of the invention in the implementation stage. In addition, various inventions can be formed by appropriately combining a plurality of components disclosed in the embodiment. For example, some components may be deleted from all the components shown in the embodiment. Furthermore, constituent elements over different embodiments may be appropriately combined.

1 ... Semiconductor device;
11A to E: Calculation engine;
110 ... input controller;
1100: Input A selection unit;
1101 ... Input B selection unit;
1102 ... Context information memory;
1103 Context ID latch;
1104 ... data processing end latch;
1105: Incrementer;
1106: multiplexer;
1107A-B ... latch;
1108A-B ... timing latch;
113A to E: arithmetic unit;
1130: computing unit;
1131: Control table memory;
1132A to D: Setting information register;
1133: multiplexer;
114A to E: Data pipeline register;
115A to E: Control pipeline register;
116 ... output controller;
1160A-B ... Base address register;
1161 ... Control table memory;
1162 ... Adder;
1163: multiplexer;
117 ... Final context ID latch;
118 ... multiplexer;
12 ... Inter-engine buffer;
120A to H: Data register;
1200 ... data latch;
1201A to D ... AND logic;
1202 ... OR logic;
1203 ... multiplexer;
13: Code memory;
14: Code transfer control device;
140 ... memory ID register;
141: Address register;
142 ... code address register;
143A-C: Incrementer;
144A to D: Multiplexer;
145 ... Valid latch;
146 ... comparator;
15 ... Data memory

Claims (6)

A first operation is performed for each cycle, and first data indicating a result of the first operation and a first valid signal indicating the first value or the second value are output for each cycle. 1 arithmetic engine,
The second calculation is performed for each cycle, and the second data indicating the result of the second calculation and the second valid signal indicating the first value or the second value are calculated for each cycle. A second computing engine to output;
Used to pass the first data and the second data between the first arithmetic engine and the second arithmetic engine, wherein the first valid signal or the second valid signal is If the first value is indicated, the first data or the second data can be written, and if the first valid signal or the second valid signal indicates the second value. A buffer between operation engines that prohibits writing of the first data or the second data,
The first calculation engine is:
A first storage for storing a first code for determining a value of the first valid signal;
A first controller that obtains a value of the first valid signal from the first code and outputs the value for each cycle;
The second calculation engine is:
A second storage unit for storing a second code for determining a value of the third valid signal;
Generating a value of the second valid signal from the second code, and generating a first controller and a second code used in a semiconductor device including a second controller that outputs the value for each cycle A compiler that
From the data dependence graph showing the dependence of the first data and the second data passed between the first computation engine and the second computation engine, the first computation is performed for each cycle. A determination unit that determines whether each of the engine and the second calculation engine performs a calculation;
If the first arithmetic engine performs an operation, the first controller outputs the first value, and if the first arithmetic engine does not perform an operation, the first controller causes the first controller to output the first value. A code that outputs a value of 2 is generated as the first code,
If the second calculation engine performs the calculation, the second controller outputs the first value, and if the second calculation engine does not perform the calculation, the second controller causes the second controller to output the first value. And a code generation unit that generates a code that outputs a value of 2 as the second code. The determination unit identifies, from the data dependence graph, an operation in which a part of data to be input to a certain operation has already been calculated and a part of the data is written in the inter-arithmetic engine buffer. A specific part,
And a scheduling unit that determines the order of the operations of the first and second arithmetic engines so that the operation specified by the specifying unit is executed with priority. The compiler according to claim 1. A first operation is performed for each cycle, and first data indicating a result of the first operation and a first valid signal indicating the first value or the second value are output for each cycle. 1 arithmetic engine,
The second calculation is performed for each cycle, and the second data indicating the result of the second calculation and the second valid signal indicating the first value or the second value are calculated for each cycle. A second computing engine to output;
Used to pass the first data and the second data between the first arithmetic engine and the second arithmetic engine, wherein the first valid signal or the second valid signal is If the first value is indicated, the first data or the second data can be written, and if the first valid signal or the second valid signal indicates the second value. A buffer between operation engines that prohibits writing of the first data or the second data,
The first calculation engine is:
A first storage for storing a first code for determining a value of the first valid signal;
A first controller that obtains a value of the first valid signal from the first code and outputs the value for each cycle;
The second calculation engine is:
A second storage unit for storing a second code for determining a value of the third valid signal;
Generating a value of the second valid signal from the second code, and generating a first controller and a second code used in a semiconductor device including a second controller that outputs the value for each cycle There is a code generation method to
The decision part
From the data dependence graph showing the dependence of the first data and the second data passed between the first computation engine and the second computation engine, the first computation is performed for each cycle. Determining whether each of the engine and the second computing engine performs computations;
The code generator
If the first arithmetic engine performs an operation, the first controller outputs the first value, and if the first arithmetic engine does not perform an operation, the first controller causes the first controller to output the first value. If a code that outputs a value of 2 is generated as the first code and the second arithmetic engine performs an operation, the second controller outputs the first value, and the second A code generating method comprising: generating, as the second code, a code that causes the second controller to output the second value if the calculation engine of (2) does not perform the calculation. A first operation is performed for each cycle, and first data indicating a result of the first operation and a first valid signal indicating the first value or the second value are output for each cycle. 1 arithmetic engine,
The second calculation is performed for each cycle, and the second data indicating the result of the second calculation and the second valid signal indicating the first value or the second value are calculated for each cycle. A second computing engine to output;
Used to pass the first data and the second data between the first arithmetic engine and the second arithmetic engine, wherein the first valid signal or the second valid signal is If the first value is indicated, the first data or the second data can be written, and if the first valid signal or the second valid signal indicates the second value. A buffer between operation engines that prohibits writing of the first data or the second data,
The first calculation engine is:
A first storage for storing a first code for determining a value of the first valid signal;
A first controller that obtains a value of the first valid signal from the first code and outputs the value for each cycle;
The second calculation engine is:
A second storage unit for storing a second code for determining a value of the third valid signal;
Generating a value of the second valid signal from the second code, and generating a first controller and a second code used in a semiconductor device including a second controller that outputs the value for each cycle There is a code generation program that
On the computer,
From the data dependence graph showing the dependence of the first data and the second data passed between the first computation engine and the second computation engine, the first computation is performed for each cycle. A procedure for determining whether each of the engine and the second calculation engine performs a calculation;
If the first arithmetic engine performs an operation, the first controller outputs the first value, and if the first arithmetic engine does not perform an operation, the first controller causes the first controller to output the first value. If a code that outputs a value of 2 is generated as the first code and the second arithmetic engine performs an operation, the second controller outputs the first value, and the second A code generation program for executing a procedure for generating, as the second code, a code that causes the second controller to output the second value if the calculation engine of (2) does not perform the calculation. A first setting information register for storing first setting information identifiable by a first setting ID;
The first setting information is read from the first setting information register in accordance with the first setting ID for each cycle, and the first calculation is performed while changing the setting in accordance with the first setting information. A first calculation engine that outputs first data indicating a result of the calculation and a first valid signal indicating the first value or the second value for each cycle;
A second setting information register for storing second setting information identifiable by a second setting ID;
The second setting information is read from the second setting information register in accordance with the second setting ID for each cycle, and a second calculation is performed while changing the setting in accordance with the second setting information. A second calculation engine that outputs second data indicating a result of the calculation and a second valid signal indicating the first value or the second value for each cycle;
Used to pass the first data and the second data between the first arithmetic engine and the second arithmetic engine, wherein the first valid signal or the second valid signal is If the first value is indicated, the first data or the second data can be written, and if the first valid signal or the second valid signal indicates the second value. A buffer between operation engines that prohibits writing of the first data or the second data,
The first calculation engine is:
A first storage for storing a first code for determining a value of the first valid signal;
A first controller that obtains a value of the first valid signal from the first code and outputs the value for each cycle;
The second calculation engine is:
A second storage unit for storing a second code for determining a value of the third valid signal;
A second controller that obtains the value of the second valid signal from the second code and outputs the value for each cycle; and the first code and the second code used in a reconfigurable device comprising: A compiler that generates
From the data dependence graph showing the dependence of the first data and the second data passed between the first computation engine and the second computation engine, the first computation is performed for each cycle. A determination unit that determines whether each of the engine and the second calculation engine performs a calculation;
If the first arithmetic engine performs an operation, the first controller outputs the first value, and if the first arithmetic engine does not perform an operation, the first controller causes the first controller to output the first value. A code that outputs a value of 2 is generated as the first code,
If the second calculation engine performs the calculation, the second controller outputs the first value, and if the second calculation engine does not perform the calculation, the second controller causes the second controller to output the first value. A code generation unit that generates a code that outputs a value of 2 as the second code. The determination unit identifies, from the data dependence graph, an operation in which a part of data to be input to a certain operation has already been calculated and a part of the data is written in the inter-arithmetic engine buffer. A specific part,
6. The scheduling unit according to claim 5, further comprising: a scheduling unit that determines an order of operations of the first and second arithmetic engines so that the operation specified by the specifying unit is preferentially executed. Compiler.

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