JP7393519B2 - Arithmetic device and method - Google Patents

Description

Cross-reference to related applications

This application is based on patent application No. 2020-042169 filed on March 11, 2020, and claims the benefit of priority thereto, and all contents of that patent application are referred to , incorporated herein by reference.

The present disclosure relates to an arithmetic device and an arithmetic method.

Conventionally, an arithmetic device is equipped with a plurality of functional units that are arithmetic units that process instructions, and performs pipeline processing (hereinafter also referred to as "multi-stage arithmetic pipeline") with the plurality of functional units for a series of input instructions. is used.

For example, Patent Document 1 discloses a configuration in which pipeline processing is performed by a plurality of functional units such as a multiplier MUL and an adder ADD. In the configuration described in Patent Document 1, the multiplier MUL multiplies each data of a set of elements corresponding to the values "a" and "b" input at the same time and sequentially outputs the multiplier to the adder ADD, and the adder ADD outputs the multiplier MUL. The multiplied value and the output of the previous adder ADD are sequentially added.

JP2012-69081A

Here, an arithmetic unit that performs instructions (operations) by chaining using a multi-stage arithmetic pipeline requires overhead for starting and falling of the pipeline, and performs complex operations that combine addition, multiplication, etc. When doing so, there were cases where the pipeline was started and stopped multiple times. Furthermore, when executing a complex calculation, there may be a functional unit that waits for the completion of calculations by other functional units before performing the calculation. That is, chaining using a pipeline may not be able to perform efficient calculations.

An object of the present disclosure is to provide an arithmetic device and an arithmetic method that can more efficiently perform chaining operations using a pipeline.

An arithmetic device according to an aspect of the present disclosure is an arithmetic device that includes a pipeline including a plurality of functional units having the same function and performs arithmetic operations by chaining, and determines whether or not there is a functional unit that is not executing an instruction. and a determination unit that is capable of being executed in parallel with the execution of an instruction by any of the functional units for the functional unit that is not executing the instruction when any of the functional units is executing the instruction. and a control unit that executes the instructions.

According to the present invention, calculations by chaining using a pipeline can be performed more efficiently.

The above objects and other objects, features and advantages of the present disclosure will become more apparent from the following detailed description with reference to the accompanying drawings. The drawing is
FIG. 1 is a schematic configuration diagram of an arithmetic device according to an embodiment. FIG. 2 is a schematic diagram showing chaining of the embodiment. FIG. 3 is a schematic diagram showing chaining of the embodiment. FIG. 4 is a flowchart showing the flow of chaining calculation processing according to the embodiment.

Embodiments of the present disclosure will be described below with reference to the drawings. Note that the embodiment described below shows an example of implementing the present disclosure, and the present disclosure is not limited to the specific configuration described below. In implementing the present disclosure, specific configurations depending on the embodiments may be adopted as appropriate.

FIG. 1 is a schematic configuration diagram of an arithmetic device 10 of this embodiment. The arithmetic device 10 of this embodiment includes a pipeline including a plurality of functional units 12, and performs arithmetic operations by chaining.

The functional unit 12 includes, for example, an LD that copies data from memory to a register, an ST that copies data from a register to memory, an ADD (adder) that has an addition function, an MUL (multiplier) that has a multiplication function, and a division function. It is an arithmetic unit such as a DIV (divider) that has a DIV (divider). These plurality of functional units 12 are included in a multi-pipe vector calculator (hereinafter referred to as "vector calculator") 20 that executes pipeline processing.

Next, pipeline processing by the arithmetic device 10 of this embodiment will be explained.

First, as an example, the number of pipeline stages (hereinafter referred to as "pipeline stage number") is four stages, and the number of functional units 12 is five (LD, ST, ADD, MUL, DIV). Assume 20. In the following description, the hardware state of the vector arithmetic unit 20 with four pipeline stages will be referred to as a default mode.

This default mode can be reconfigured into mode 1 and mode 2, which have fewer pipeline stages. In mode 1, the number of pipeline stages is two, and the number of functional units 12 is eight (LD, ST, two ADD, two MUL, and two DIV). In mode 2, the number of pipeline stages is one, and the number of functional units 12 is 14 (LD, ST, 4 ADDs, 4 MULs, and 4 DIVs). In this way, in mode 1 and mode 2, which have fewer stages than the default mode, there are a plurality of functional units 12 having the same functions, such as ADD, MUL, and DIV.

Note that in the arithmetic device 10 of this embodiment, all variations of hardware modes (combinations of the number of pipeline stages and the number of functional units 12) are defined in advance, as an example, and the current hardware mode is determined by a flag value. It is held in a dedicated register (mode register). The hardware mode is then set by a dedicated control command.

In this way, the arithmetic device 10 of this embodiment can reconfigure the pipeline including a plurality of functional units 12 having the same function from the default mode. Then, when the functional unit 12 is executing an instruction, the arithmetic device 10 of this embodiment causes other functional units 12 that are not executing an instruction to execute an instruction that can be executed in parallel. Therefore, the arithmetic device 10 of this embodiment has a function (Out-of-Order) that determines whether or not another functional unit 12 is executing an instruction when a certain functional unit 12 is executing an instruction. function).

In order to implement the Out-of-Order function, the functional unit 12 of this embodiment has a state register that holds an identifier that identifies whether an instruction is being executed. Based on this state register, the arithmetic unit 10 determines which functional units 12 are not executing an instruction, and allocates an instruction to each functional unit 12. In this embodiment, as an example, the state register of the functional unit 12 that is executing an instruction is "1", and the state register of the functional unit 12 that is not executing an instruction is "0".

Note that since the total number of functional units 12 contributing to an operation (the product of the number of pipeline stages and the number of corresponding functional units 12) is constant, the state register has enough bits to hold the total number of functional units 12. All you need is a number. In the above example, the maximum number of pipeline stages is four, and there are three types of functional units 12 (ADD, MUL, DIV) having the same function, so the state register may be 3×4=12 bits. Note that in order to execute the Out-of-Order function, it is necessary to determine whether or not the functional units 12 of the LD and ST are being executed, so the LD and ST also have state registers of 1 bit each. However, the state registers of LD and ST only need to have 1 bit each, regardless of the number of pipeline stages.

Next, as an example, with reference to FIG. 2, a case will be described in which the operation "((A+B)+C)×D" is chained in mode 1. In mode 1, as described above, the number of functional units 12 for ADD, MUL, and DIV is two each. Note that the vector register width corresponding to each value (A, B, C, D) in FIG. 2 and FIG. 3 described later is fixed, and is, for example, 64 bits or 32 bits.

In mode 1, first, a process (ADD instruction) for writing the operation result of "A+B" to a register (intermediate register) is issued. At the time of issuance of the ADD instruction, none of the functional units 12 is executing the instruction yet, so the state registers of all the functional units 12 are "0". By issuing the ADD command here, the state register of the functional unit 12 corresponding to the first ADD is set to "1".

Then, in the next instruction cycle, an ADD instruction that adds "C" to the result of the first ADD instruction is issued without waiting for the completion of the first ADD instruction. Since the state register of the second ADD is "0", it is determined that there is an ADD that is not executing an instruction, so the state register of the second ADD is set to "1" and chaining with the first ADD instruction is performed. will be held.

Furthermore, in the next instruction cycle, a multiplication instruction of "D" for "(A+B)+C" is issued without waiting for the completion of the two preceding ADD instructions. At this time, the MUL state register is "0", so the first MUL state register is set to "1", and chaining with the previous two ADD instructions is performed.

Next, with reference to FIG. 3, a case will be described in which the calculation "(A+B)×(C+D)" is chained in mode 1. First, the operations "(A+B)" and "(C+D)" can be executed independently. Therefore, one ADD performs the operation of "(A+B)", and the operation instruction of "(C+D)" is performed by another ADD. That is, these two ADD commands are issued simultaneously without waiting for each other to complete. Therefore, in mode 1, these two ADD instructions can be allocated simultaneously as hardware resources.

In the example of FIG. 3, one MUL functional unit 12 becomes vacant. Here, if the next instruction (subsequent instruction) includes a MUL instruction that has no dependency on the chaining operation described above, the MUL instructions can be executed simultaneously. As a result, the operating rate of the arithmetic function unit can be made higher than in the default mode, and higher effective performance can be achieved even with the same hardware resources (number of arithmetic units) as before.

Further, the functional unit 12 of this embodiment includes a mask register 30 (see FIGS. 2 and 3) that indicates the execution state of an instruction. Then, the functional unit 12 that executes the next instruction using the operation results of the plurality of other functional units 12 executes the next instruction after the mask register 30 of the plurality of other functional units 12 indicates the completion of instruction execution. Execute.

More specifically, the mask register 30 is provided corresponding to the vector register length, and "0" is rewritten to "1" according to the degree of progress of the calculation. When the calculations in each functional unit 12 are completed, all mask registers 30 are set to "1". Then, by AND (logical product) of the mask registers 30 of the plurality of functional units 12 that have executed the previous instruction, it is determined whether or not the calculation by the plurality of functional units 12 has been completed. That is, the functional unit 12 that executes the next instruction does not perform an operation until the multiple functional units 12 that execute the previous instruction complete their operations.

That is, in the example of FIG. 3, when the operation "A+B" is completed, all the register areas become "1", and when the operation "C+D" is completed, all the register areas become "1". Then, when the calculation of "A+B" and the calculation of "C+D" are completed, the calculation of "(A+B)×(C+D)" is started.

As a result, even if multiple functional units 12 execute the previous instruction asynchronously, the functional unit 12 that executes the next instruction will wait for the execution of the instructions by the multiple functional units 12 to be completed before performing the calculation. , the next instruction can be executed without causing an error.

Note that if the number of stages in the pipeline that executes the next instruction is greater than the number of stages in the pipeline that executes the previous instruction, for example, if the first pipeline has two stages and the second pipeline has four stages, , as described above, the degree of progress of the previous pipeline instruction (operation) is determined by the mask register 30. Therefore, even if a chaining operation is performed by a combination of pipelines with different numbers of stages, instructions can be executed without causing an error.

In this way, the arithmetic device 10 of the present embodiment can control the start-up and fall of the pipeline by reconfiguring the four-stage pipeline into a pipeline with a smaller number of stages (two-stage pipeline). Overhead can be reduced. At this time, the two-stage pipeline includes a plurality (at least two) of functional units 12 having the same function.

Specifically, when performing the operation “((A+B)+C)×D” using the four-stage pipeline described above, after performing the operation “A+B=E” by chaining, “(E+C)×D” ” needs to be performed with new chaining. Therefore, in a four-stage pipeline, it is necessary to start and fall the pipeline twice, which requires overhead for two times. In addition, when the calculation result of "A + B = E" is temporarily stored in memory and the calculation of "(E + C) x D" is performed, it is necessary to read out the calculation result "E" from the memory and process it. was inefficient.

On the other hand, a two-stage pipeline has two functional units 12 (ADD, MUL, DIV) each having the same function. When a certain functional unit 12 is executing an instruction, the presence or absence of another functional unit 12 that is not executing the instruction is determined (Out-of-Order function), and the other functional unit 12 that is not executing the instruction is determined. Executable instructions are executed in parallel with the instruction execution by a certain functional unit 12.

As a result, in a two-stage pipeline, the operation "((A+B)+C)×D" can be performed by chaining once, and the pipeline startup and fall (overhead) can be done only once. . In addition, the two-stage pipeline does not require the process of temporarily storing the calculation results in memory, as is the case with the four-stage pipeline, so more efficient processing is possible.

Therefore, by reducing the number of pipeline stages and creating a pipeline that includes a plurality of functional units 12 having the same function as in this embodiment, the overhead time required for starting and falling of the pipeline can be reduced. can be reduced, making it possible to improve the efficiency of calculations.

In order to execute such pipeline chaining, the arithmetic device 10 of this embodiment includes an execution determination section 22 and a control section 24, as shown in FIG.

The execution determination unit 22 is a component that executes an Out-of-Order function, and determines whether there is a functional unit 12 that is not executing an instruction. Note that the execution determination unit 22 determines which functional units 12 are not executing an instruction based on the state register.

The control unit 24 causes the functional units 12 that are not currently executing instructions to execute executable instructions. The control unit 24 of this embodiment, when any of the functional units 12 is executing an instruction, instructs the functional units 12 that are not executing the instruction in parallel with the execution of the instruction by any of the functional units 12. Execute executable instructions.

Note that the arithmetic device 10 performs control according to the number of pipeline stages, in other words, according to the mode. For example, a four-stage pipeline (default mode) does not perform the Out-of-Order function, and a two-stage or one-stage pipeline (Mode 1 or Mode 2) performs the Out-of-Order function. In other words, the Out-of-Order function is executed on a pipeline comprising multiple functional units 12 having the same function. Note that the mode is appropriately selected depending on the series of calculations to be performed by the vector calculator 20.

Further, the present invention is not limited to this, and the Out-of-Order function may be executed even in the default mode. That is, not only the functional units 12 having the same function but also the functional units 12 that are not dependent on each other in all the different functional units 12 (LD, ST, MUL, ADD, DIV) may be executable at the same time.

Note that the arithmetic device 10 of this embodiment stores instructions waiting for execution by the functional unit 12 in the instruction standby buffer 14. If there is a functional unit 12 that can execute the instructions stored in the instruction standby buffer 14, the instructions are sequentially read from the instruction standby buffer 14 and executed by the functional unit 12. This makes it possible to efficiently allocate instructions to functional units 12 that are not currently executing instructions.

FIG. 4 is a flowchart showing the flow of chaining calculation processing for executing the Out-of-Order function. This chaining calculation process is executed by a program stored in a recording medium included in the calculation device 10. When this program is executed, a method corresponding to the program is executed.

Note that the chaining calculation process shown in Figure 4 executes the Out-of-Order function, so by checking the mode register before executing the chaining calculation process, the Out-of-Order function can be executed. It is determined whether the mode is executable. If the mode is not one in which the Out-of-Order function can be executed, normal chaining calculation processing that does not execute the Out-of-Order function is executed. or reconfiguring the Out-of-Order functionality into a viable mode.

First, in step S100, the execution determination unit 22 checks the state register of each functional unit 12 and determines whether there is any functional unit 12 that is not executing an instruction (Out-of-Order function). Note that the presence or absence of the functional unit 12 here refers to the functional unit 12 that can execute a given command. For example, if the given instruction is an ADD instruction, the execution determination unit 22 determines whether there is a functional unit 12 that can execute this ADD instruction.

In the next step S102, if there is a functional unit 12 that is not executing an instruction, the process moves to step S106, whereas if there is no functional unit 12 that is not executing an instruction, the process moves to step S104.

In step S104, since there is no functional unit 12 capable of executing the instruction, the instruction is queued in the instruction standby buffer 14 as an instruction waiting to be executed, and the process returns to step S100.

In step S106, the control unit 24 allocates the command to the functional unit 12 that is not currently executing the command.

In the next step S108, the control unit 24 sets the state register of the functional unit 12 to which the instruction is assigned to "1".

In the next step S110, the functional unit 12 executes the assigned instruction.

In the next step S112, the control unit 24 determines whether the functional unit 12 has completed the execution of the assigned command, and if the determination is affirmative, the process moves to step S114, and if the determination is negative, the process moves to step S116. Transition. Note that if there are a plurality of functional units 12 executing the command, it is determined in step S112 whether or not the command execution has been completed for each functional unit 12.

In step S114, the control unit 24 sets the state register of the functional unit 12 that has completed the instruction to "0", and proceeds to step S116.

In step S116, the control unit 24 determines whether there is a next command, and if there is a next command, the process returns to step S100 and executes each step in response to the next command.

On the other hand, if it is determined in step S116 that there is no next instruction, this means that all of the input series of arithmetic instructions have been completed, and the main chaining ends.

In this way, the arithmetic device 10 of the present embodiment is configured such that when any functional unit 12 is executing an instruction, any functional unit 12 executes an instruction with respect to a functional unit 12 that is not executing an instruction. Executes executable instructions in parallel. Thereby, the arithmetic device 10 of this embodiment can more efficiently perform chaining operations using a pipeline.

Although the present disclosure has been described above using the above embodiments, the technical scope of the present disclosure is not limited to the range described in the above embodiments. Various changes or improvements can be made to the embodiments described above without departing from the gist of the disclosure, and forms with such changes or improvements are also included within the technical scope of the present disclosure.

For example, in the embodiment described above, a four-stage pipeline is reconfigured into a two-stage pipeline or a one-stage pipeline, but the present disclosure is not limited thereto. For example, a pipeline with five or more stages may be reconfigured into a pipeline with fewer stages. Further, without the concept of pipeline reconfiguration, the vector calculator 20 may be configured with a fixed two-stage pipeline, for example.

Claims (5)

An arithmetic device (10) comprising a pipeline each comprising a plurality of functional units (12) of a plurality of types and performing arithmetic operations by chaining,
a determination unit (22) that determines the presence or absence of the functional unit that is not executing an instruction;
When any of the functional units is executing an instruction, causing the functional unit that is not executing the instruction to execute the instruction that can be executed in parallel with the execution of the instruction by any of the functional units. A control unit (24) that reconfigures the pipeline to have a smaller number of stages;
A calculation device comprising: The functional unit includes a mask register (30) that indicates the execution state of the instruction,
The functional unit that executes the next instruction using the operation results of the plurality of other functional units executes the next instruction after the mask registers of the plurality of other functional units indicate completion of execution of the instruction. The arithmetic device according to claim 1, which executes the arithmetic operation. The functional unit is set with an identifier that identifies whether or not the instruction is being executed;
The determination unit determines the functional unit that is not executing the instruction based on the identifier.
The arithmetic device according to claim 1 or claim 2. the instructions awaiting execution by the functional unit are stored in a storage medium (14);
If there is a functional unit capable of executing the instructions stored in the storage medium, the instructions are sequentially read from the storage medium and executed by the functional unit;
An arithmetic device according to any one of claims 1 to 3. An arithmetic method using chaining using a pipeline each comprising a plurality of functional units each having a plurality of types of functions, the method comprising:
a first step of determining the presence or absence of the functional unit that is not executing an instruction;
When any of the functional units is executing an instruction, causing the functional unit that is not executing the instruction to execute the instruction that can be executed in parallel with the execution of the instruction by any of the functional units. The second step is to reconfigure the pipeline to have a smaller number of stages.
A calculation method having.

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