JPH08250685A - Programmable gate array - Google Patents

Abstract

PURPOSE: To effectually accomodate a large-scaled logical circuit on one chip by cont rolling the operation in an event control unit such that memory contents are loaded to a logic realizing resource and a register is allocated as a latch. CONSTITUTION: A circuit is realized with a logic realizing resource 3-3. A memory plane 3-1 comprises independent (m) program memories for storing (m) kinds of circuit programs. A register plane 3-2 comprises (m) sets of independent registers providing a latch for storage of calculation results and realization of a sequential circuit. An event control unit 3-8 controls a combination of (m) program memories and (n) sets of registers. The operation is control led such that a memory and a register designated by the combination are selected, and memory contents are loaded to the logic realizing resource 3-3 and a register is allocated as a latch. Hereby, a large-scaled circuit can be accomodated.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a programmable logic device structure.

[0002]

2. Description of the Related Art FIG. 9 is a diagram showing a configuration of a programmable logic element. As shown in this figure, the programmable logic element is composed of a programmable logic cell 1-1 and a programmable wiring region 1-2. The function of the programmable logic element is the programmable logic cell 1
Program logic to -1, programmable wiring area 1
-2 wiring is realized by a logic circuit formed by connecting programmable logic cells. Hereinafter, a series of operations for forming this logic circuit will be referred to as circuit programming, and logic set in the programmable logic cell 1-1 and setting data in the programmable wiring area 1-2 will be referred to as circuit programmable. In addition, rewritable FPGA (Field Programmable Ga) as such a programmable logic element
te Array), which has been put to practical use.

Next, FIG. 10 is a block diagram showing the configuration of the programmable logic cell 1-1. In this figure, the programmable logic cell 1-1 is composed of a programmable logic circuit 2-1 and a latch 2-2.
The logic is operated in the programmable logic circuit 2-1, and the result and the transition state of the circuit are stored by the latch 2-2 to determine the processing at the next clock. That is, the arbitrary combinational circuit is realized by the programmable logic circuit 2-1 and the arbitrary sequential circuit is realized by the combination of the programmable logic circuit 2-1 and the latch 2-2. The contents of the logical operation in the programmable logic circuit 2-1 are determined by the circuit program.

A programmable logic circuit 2-1 in the programmable logic cell 1-1 and a programmable wiring area 1-
All programmable points in the programmable logic element, such as the inter-wiring connection switch in 2, are assigned memory elements for holding the connection state,
The function of the logic circuit is realized by setting predetermined data in this memory element. That is, the circuit programming is an operation of writing data in the memory element, and the circuit program is a writing state of the memory element.
It is described by the circuit set. Hereinafter, the memory element for determining the logic circuit will be referred to as a program memory. Also, the entire hardware that is the subject of the program is called a circuit implementation resource.

Next, the timing of circuit programming and reprogramming of the logic circuit in the FPGA will be described. Since the programmed logic circuit is fixed when the function is realized, the circuit programming is statically performed before the processing is executed. When a logic circuit is reprogrammed by implementing a new function or changing a function, this reprogramming is performed after the processing operation of the logic circuit is completely stopped, and the logic circuit is dynamically changed during the processing. Is never changed. On the other hand, there is an FPGA that enables reprogramming even while the logic circuit is operating, but the programming speed of the logic circuit is as low as that of a normal FPGA, and an excess of programmable logic cells and programmable logic cells that do not contribute to the realization of the function. The wiring is merely a static implementation of a logic circuit that is separate from the operating logic circuit, and the logic circuit does not change dynamically one after another.

[0006]

By the way, in the FPGA whose logic function can be programmed in the field, both the programmable logic cell and the programmable wiring are uniform as shown in FIG. 9 so that all kinds of logic circuits can be realized. It has a repeating structure. for that reason,
When actually implementing a logic circuit and fixing the logic circuit for processing, a large amount of unused resources for logic implementation such as programmable logic cells and programmable wiring that are not used for function implementation remain. In addition, because of the structural redundancy inherent in realizing programmability in the field, such as the programming mechanism and program memory, the scale of the logic circuit that can be accommodated in the FPGA single chip is a custom LSI with no programmability. Or A
SIC (application specific integrated circuit)
Compared with etc., it will be extremely limited.

When a large-scale logic circuit is realized using such an FPGA chip, it is difficult to simply expand the resources for logic realization in a single FPGA chip, which makes it difficult to manufacture a large number of FPGA chips. Realization of a combined logic circuit is achieved. In this case, the wiring between the FPGA chips has a larger signal delay than the internal wiring of the FPGA chip.
Must be stored inside the chip. However, if there is not enough resources left to accommodate the logic circuit, the logic circuit that cannot be accommodated will be accommodated in another FPGA chip. Therefore, the accommodation efficiency of the logic circuit in each FPGA chip is further reduced, and the number of FPGA chips required to realize all the functions is increased. In addition, when a plurality of FPGA chips are operated simultaneously, problems such as power consumption and heat generation also occur.

Further, the characteristic of the arithmetic processing using the conventional programmable logic element including FPGA is that high speed operation is possible, and that the parallel operation of the logic circuit is possible by spatially realizing all the functions. Is. However, in actual arithmetic processing, not all logic circuits operate at the same time, and usually only some logic circuits perform effective processing in many cases. That is, the logic circuits in charge of the respective functions are activated singly or in a plural number according to the timing, the condition, the input signal, etc., and perform the processing. As described above, the circuit realized by the programmable logic element is often functionally and temporally independent. Therefore, the conventional circuit configuration method in which all the functions are formed by programmable logic elements from the beginning has a problem that there is much waste in area.

The present invention has been made in view of the above problems, and an object of the present invention is to provide a programmable gate array capable of efficiently storing a large-scale logic circuit in one chip.

[0010]

A programmable gate array according to a first aspect of the present invention is a memory comprising a logic realization resource for realizing a circuit and m independent program memories for storing m kinds of circuit programs. A register plane composed of a plane and n sets of independent registers that provide latches for storing operation results and realizing a sequential circuit, and managing a combination of the m program memories and the n sets of registers. And an event management unit that selects a memory and a register designated by the combination, loads the contents of the memory into the logic realization resource, and controls the register to be allocated as a latch. I am trying.

According to a second aspect of the present invention, there is provided the programmable gate array according to the first aspect, wherein the event management section has a mechanism for independently controlling the memory plane and the register plane. It has a feature.

A programmable gate array according to a third aspect of the present invention is the programmable gate array according to the first or second aspect of the present invention, further comprising means for multiplying an input clock of the data to be processed by k times to obtain an internal clock. There is.

In a programmable gate array according to a fourth aspect of the present invention, in the invention according to the third aspect, the event management section uses the internal clock with a clock timing different from an input timing of the data to be processed. It is characterized in that the content of is loaded into the logic realization resource.

According to a fifth aspect of the programmable gate array of the present invention, a fixed circuit area constituted by a circuit built in during device manufacturing or a circuit realized by a program of a mask programmable gate array, and a static logic circuit such as FPGA are realized. A programmable gate array region having a mechanism for operating the programmable gate array and a programmable gate array having a mechanism for dynamically changing a logic circuit are combined.

[0015]

According to the programmable gate array of claim 1, the circuit program specified from the memory plane is loaded into the shared circuit realization resource according to the instruction from the event management unit, and the register specified from the register plane is latched. A dynamic circuit changeable gate array (hereinafter referred to as DCGA) configuration that realizes a desired logic circuit by being given to the circuit as is adopted, so that any logic circuit can be realized. it can. In addition, a mechanism for sharing circuit realization resources by all circuits to be switched makes it possible to effectively utilize most of the surplus circuit realization resources that have occurred when one type of circuit was programmed and fixed. it can.

Furthermore, since many circuit realization resources are repeatedly used, it is possible to reduce the absolute amount of hardware that is actually required for function realization. Therefore, a redundant structure for realizing programmability is provided. As it is, it becomes possible to accommodate a large-scale circuit even in a single chip. Also,
Further, the circuit can be added by adding the memory by the mechanism that saves only the circuit program in the memory plane. Since the memory can be integrated on a large scale, a large number of circuit programs can be realized in a small area, and an increase in the number of chips required to realize all the functions can be suppressed. Also, because the number of chips is suppressed,
It is possible to reduce both the total power consumption and the heat generation amount.

According to another aspect of the programmable gate array of the present invention, the independent control of the memory plane and the register plane is performed by switching the register plane while fixing the memory plane so that only the internal state of the same logic circuit can be controlled. Since it can be changed, the circuit program can be shared for all circuits having the same processing content. Therefore, overlapping arithmetic circuits can be integrated, and the absolute amount of hardware for realizing the function can be suppressed. In addition, by switching the memory plane while fixing the register plane, it is possible to share the processing result and change only the processing circuit. Therefore, even complex or large-scale logical operations can be divided into small circuit units and It can be processed with a large-scale logic realization resource.

According to the programmable gate array of the third aspect, the application of the k-times clock technique to the DCGA area is performed by changing the circuit program by increasing the processing speed inside the device higher than the input speed of the data to be processed. In addition to obtaining the time overhead for this purpose, by dividing the entire circuit into k and performing processing with k clocks, it is possible to reduce the amount of resources for circuit implementation and adjust the phase by latching while maintaining the data throughput. To do.

According to another aspect of the programmable gate array of the present invention, the event management unit loads the contents of the memory into the logic realization resource at a clock timing of the internal clock which is different from the input timing of the data to be processed.

According to the programmable gate array of the present invention, a fixed circuit region composed of a circuit built in during device manufacturing or a circuit realized by a program of a mask programmable gate array, and a static logic circuit such as FPGA. Programmable gate array (hereinafter Static Configurable Gate Array: S
Since a hybrid configuration with a CGA area) and a dynamic logic circuit change mechanism is adopted, an optimal circuit realization method is selected according to the nature of processing, the frequency of operations, and the degree of required programmability. By selecting, it becomes possible to accommodate all desired functions at high speed and compactly as compared with a device having a single configuration.

Further, since the fixed circuit area is a built-in dedicated fixed circuit, it is the most suitable area for realizing a function having a high frequency of occurrence, processing requiring high-speed processing, and good programmability by changing parameters. Become. The SCGA area is composed of an FPGA that statically performs circuit programming before processing and does not change the circuit in operation. Therefore, it requires programmability and realizes functions that require continuous processing or frequent processing. It is the optimum area for. DCG
The area A is composed of a gate array that dynamically changes the circuit and programs the processing circuit on a common resource only when necessary. Therefore, it requires programmability and realizes a function with strong temporal independence. It is the optimum area for.

[0022]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing the configuration of the first embodiment. Here, the type m of the circuit program is 3, the number n of sets of registers is 5, and a multiple k of the clock.
2 and three types of circuit programs a,
Of b and c, the circuit b program has two states b1 and b2, and the circuit program c has two states c1 and c2.
A case where the processes are repeatedly executed in the order of b1, c1, b2, c2 will be described.

In this figure, the memory plane 3-1 is formed by an SRAM whose word width is expanded to the bit width of the program memory of the shared circuit realizing resource 3-3, and its capacity is word width × m. One address is associated with one circuit program. Similarly, the register plane 3-2 is formed by an SRAM having a capacity of word width × n, with 1 word as a total register amount required for one circuit program, and one address corresponds to one logic circuit.

The event management unit 3-8 is formed by a memory table 3-9 of SRAM, and the address of the memory plane 3-1 and the register plane 3 are stored in this table.
The correspondence of the address of -2 is described. The change of the realization circuit is performed by moving the pointer 3-10. When one of the circuit programs is loaded from the memory plane 3-1 according to the instruction of the pointer 3-10 and the latch is assigned from the register plane 3-2, the state of the shared circuit realization resource 3-3 is determined and the logic circuit is determined. Is realized.

The memory plane 3-1 stores a plurality of circuit programs, and one type of circuit is selected by the selector 3-5 in response to the instruction signal 3-4 from the event management unit 3-8 so that the shared circuit realization resource 3 can be obtained. -3 is loaded. The register plane 3-2 is composed of a plurality of latch sets, and one set of latches is selected by the selector 3-7 by the instruction signal 3-6 from the event management unit 3-8 and assigned to the shared circuit realization resource 3-3. To be

The internal clock of this device is set to twice the frequency of the input data 3-11, and is divided into a programming clock and a logical operation clock. And the circuit programming is 1 of the input data 3-11.
It is performed by the programming clock before the clock. Then, the data to be processed at the next logical operation clock is input to the logical circuit formed on the shared circuit realization resource 3-3 to perform the operation. Then, thereafter, circuit programming by the programming clock and calculation by the logical operation clock are repeated.

Next, FIG. 2 is a diagram showing the state of the first programming clock. One clock before the input data, the memory plane 3-1 to the circuit program a, the register plane 3-in accordance with the instruction of the event management unit 3-8.
The register a is selected from 2 respectively, and the circuit a is realized on the shared circuit realization resource 3-3. Also, in FIG.
It is a figure which shows the state of the logic operation clock of the time. The data signal 5-1 to be processed is input to the circuit a determined by the previous programming clock and logical operation is performed. The processing result is output as the output signal 5-2 or stored in the register a.

FIG. 4 is a diagram showing the state of the second programming clock. Circuit plane b from memory plane 3-1 and register b from register plane 3-2
1 is selected, and the circuit b1 is configured on the shared circuit realization resource 3-3. FIG. 5 is a diagram showing the state of the second logical operation clock. The data signal 5-1 to be processed is input to the circuit b1 and logical operation is performed.

Hereinafter, the circuit c1 is formed in each third programming clock, and the logical operation processing is performed in the subsequent logical operation clock. The circuit b2 is configured in the fourth programming clock, the logical operation processing is performed in the subsequent logical operation clock, and the circuit c2 is configured in the fifth programming clock, and the logical operation processing is performed in the subsequent logical operation clock.
Then, at the sixth time, the processing returns to the same as the first time, and thereafter, the above-mentioned five kinds of states are repeatedly executed in the order of a, b1, c1, b2, c2.

Next, FIG. 6 is a block diagram showing the configuration of the second embodiment. The memory plane 3-1, the register plane 3-2, and the event management unit 3-8 which are built in the chip in FIG.
1, the register plane chip 8-2, and the event management chip 8-4 are externally attached.

With this, the amount of hardware in the shared circuit realization resource chip 8-3 is expanded by using the vacant area, so that a larger-scale function can be realized and high-speed operation can be performed, and the noise immunity is improved. That is, by expanding the programmable logic cell, the gate scale that can be realized by one cell is expanded, and by expanding the programmable wiring region, it is possible to realize wiring with a higher degree of freedom and a smaller delay. In addition, the flexibility of system expansion can be improved by configuring them as separate chips.

Further, as the structure of the gate array unit capable of changing the dynamic circuit, the following structure can be realized in addition to the above structure. 1) Internal circuit: Shared circuit realization resource / memory plane External circuit: Register plane / event management unit 2) Internal circuit: Shared circuit realization resource / register plane External circuit: Memory plane / event management unit 3) Internal circuit: Shared Circuit realization resource / event management unit External circuit: memory plane / register plane 4) Internal circuit: Shared circuit realization resource / event management unit, memory plane External circuit: register plane 5) Internal circuit: Shared circuit realization resource / event management Part, register plane External circuit: memory plane

Next, FIG. 7 is a block diagram showing the configuration of the first embodiment of the hybrid programmable device. The fixed circuit area 9-1 is built in advance at the time of manufacturing the device, and a commercially available FPGA is used for the SCGA area 9-2. The DCGA area 9-3 has the configuration of the dynamic circuit changeable gate array shown in FIG. Note that, here, a case where an example of the communication processing circuit is realized will be described.

Usually, digital data sent using a transmission medium such as an optical fiber is several hundred Mbps to several Gbp.
It is s high-speed serial data. The communication processing device converts the serial data into parallel data and
Processing is performed using a clock of 0 MHz, and at the same time 1
Performs synchronization processing in byte units. A circuit used for such communication processing is required to have high-speed processing and programmability to the extent of parameters. Further, such a circuit can be constructed at high speed and more compactly by forming it at the time of manufacturing the device or by using it as a dedicated fixed circuit such as a program for the gate array, rather than by using FPGA. In FIG. 7, an 8-bit S / P conversion circuit (serial / parallel conversion circuit) 9-4 is configured in the fixed circuit area 9-1.

In the field of communication processing, the processing of various types of maintenance and operation information added in order to accurately transmit the user's information is central. Such overhead information bits are normally stored in independent time slots in the serial data for each role, so that the timing at which each processing circuit substantially performs processing is shifted in time. . Such a functionally and temporally independent circuit is realized in the DCGA area 9-3, and the hardware amount of the entire circuit is reduced.

Usually, communication data is scrambled in order to reduce errors in transmission. Also, parity calculation and CRC calculation are performed for bit error detection / correction. Since the processing method of such arithmetic processing for the entire data is different for each communication device, if it is built as a fixed circuit, the variety of devices is lost. Also, during normal processing operation, continuous operation is performed, so DCGA
Even if it is realized in the region 9-3, the circuit realization resources cannot be shared, and the area occupied by the circuit becomes large. Therefore, such a circuit is a conventional FPGA or SCG.
It is better to use the A region 9-2 to make it compact. In this case, the event management unit 9-5 not only controls the switching of the circuit realized in the DCGA area 9-3, but also sets the parameter of the fixed circuit configured in the fixed circuit area 9-1 or the SCGA area 9-2. And execution / stop of processing, passing of processing data, etc.

Next, FIG. 8 is a block diagram showing the configuration of the second embodiment of the hybrid configuration programmable device described above. The fixed circuit area 9-1 shown in FIG. 7 is omitted. It is preferable to select the optimum combination depending on the application applied in this way.

[0038]

As described above, the programmable gate array of the present invention has the following effects. (1) It is more wasteful than the case of realizing with a conventional FPGA by providing a mechanism for dynamically changing a logic circuit programmed in a shared circuit realizing resource by utilizing the functional / temporal independence of processing. It can accommodate large scale circuits.

(2) The memory plane for storing the circuit program and the register plane for storing the operation result and the transition state of the circuit can be controlled independently of each other, thereby realizing the logic realization necessary for the unification of the duplicated circuits and the processing. It is possible to keep the amount of resources for use small.

(3) It is possible to reduce the hardware scale and the number of chips required to realize the function, and it is possible to reduce the overall power consumption and heat generation amount.

(4) A programmable device having a hybrid structure composed of a fixed circuit, a static programmable gate array, and a dynamic programmable gate array is an optimum circuit according to the nature of processing, the frequency of operations, and the required degree of programmability. By selecting the realization means, it is possible to accommodate all the desired functions at high speed and compactly as compared with a device having a single configuration.

(5) By applying the k-times internal clock technology to the dynamic circuit changeable gate array, the internal processing speed of the device can be increased by k times the input speed of the data to be processed. In this case, a time overhead for changing the circuit program is obtained, and the entire circuit is divided into k parts and the processing is performed by applying k clocks, so that the data throughput is guaranteed.
It is possible to reduce the resources for realizing the shared circuit and adjust the phase by the latch.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a first embodiment of a programmable gate array of the present invention.

FIG. 2 is a diagram showing a first circuit programming method in the first embodiment of the programmable gate array of the present invention.

FIG. 3 is a diagram showing a state of a first logical operation in the first embodiment of the programmable gate array of the present invention.

FIG. 4 is a diagram showing a second circuit programming method in the first embodiment of the programmable gate array of the present invention.

FIG. 5 is a diagram showing a situation of a second logical operation in the first embodiment of the programmable gate array of the present invention.

FIG. 6 is a block diagram showing a configuration of a second embodiment of the programmable gate array of the present invention.

FIG. 7 is a block diagram showing a configuration of a first embodiment of a hybrid configuration programmable device of the present invention.

FIG. 8 is a block diagram showing a configuration of a second embodiment of a hybrid configuration programmable device of the present invention.

FIG. 9 is a plan view showing a configuration of a conventional programmable logic element.

FIG. 10 is a block diagram showing a configuration of a conventional programmable logic cell.

[Explanation of symbols]

 3-1 Memory plane 3-2 Register plane 3-3 Shared circuit implementation resource 3-5, 3-7 Selector 3-8, 9-5 Event management unit 3-9 Memory table 3-10 Pointer 8-1 Memory plane chip 8-2 Register plane chip 8-3 Shared circuit realization resource chip 8-4 Event management chip 9-1 Fixed circuit area 9-2 SCGA area 9-3 DCGA area 9-4 S / P conversion circuit

Claims (5)

[Claims] 1. A logic realization resource for realizing a circuit,
A memory plane composed of m independent program memories for storing m types of circuit programs, and a register composed of n sets of independent registers for providing latches for storing operation results and realizing a sequential circuit. Managing a combination of a plane, the m program memories and the n sets of registers, selecting a memory and a register designated by the combination, and loading the contents of the memory into the logic realization resource; A programmable gate array, comprising: an event management unit that controls the register to be assigned as a latch. 2. The programmable gate array according to claim 1, wherein the event management unit includes a mechanism that enables independent control of the memory plane and the register plane. 3. The programmable gate array according to claim 1, further comprising means for multiplying an input clock of the data to be processed by k times to obtain an internal clock. 4. The event management unit is configured to load the contents of the memory into the logic realization resource at a clock timing of the internal clock that is different from the input timing of the processing target data. 4. The programmable gate array according to claim 3, which is characterized in that. 5. A fixed circuit area composed of a circuit built in during device manufacturing or a circuit realized by a program of a mask programmable gate array, and an FPGA (Fie
5. A combination of a programmable gate array region having a mechanism for statically realizing a logic circuit such as an ld Programmable Gate Array) and a programmable gate array according to claim 1 having a mechanism for dynamically changing a logic circuit. A programmable gate array characterized by being present.