EP1523769A1 - Anordnung mit einem halbleiterchip und dessen träger sowie verfahren zur bond-drahtverbindung - Google Patents
Anordnung mit einem halbleiterchip und dessen träger sowie verfahren zur bond-drahtverbindungInfo
- Publication number
- EP1523769A1 EP1523769A1 EP03787714A EP03787714A EP1523769A1 EP 1523769 A1 EP1523769 A1 EP 1523769A1 EP 03787714 A EP03787714 A EP 03787714A EP 03787714 A EP03787714 A EP 03787714A EP 1523769 A1 EP1523769 A1 EP 1523769A1
- Authority
- EP
- European Patent Office
- Prior art keywords
- contact
- carrier
- semiconductor chip
- nailhead
- wire
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistors
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistors electrically connecting electric components or wires to printed circuits
- H05K3/328—Assembling printed circuits with electric components, e.g. with resistors electrically connecting electric components or wires to printed circuits by welding
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
- H05K3/4007—Surface contacts, e.g. bumps
- H05K3/4015—Surface contacts, e.g. bumps using auxiliary conductive elements, e.g. pieces of metal foil, metallic spheres
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
- H10W70/01—Manufacture or treatment
- H10W70/05—Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers
- H10W70/095—Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers of vias therein
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/11—Printed elements for providing electric connections to or between printed circuits
- H05K1/111—Pads for surface mounting, e.g. lay-out
- H05K1/112—Pads for surface mounting, e.g. lay-out directly combined with via connections
- H05K1/113—Via provided in pad; Pad over filled via
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/04—Soldering or other types of metallurgic bonding
- H05K2203/049—Wire bonding
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/071—Connecting or disconnecting
- H10W72/0711—Apparatus therefor
- H10W72/07141—Means for applying energy, e.g. ovens or lasers
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/071—Connecting or disconnecting
- H10W72/075—Connecting or disconnecting of bond wires
- H10W72/07511—Treating the bonding area before connecting, e.g. by applying flux or cleaning
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/071—Connecting or disconnecting
- H10W72/075—Connecting or disconnecting of bond wires
- H10W72/07521—Aligning
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/071—Connecting or disconnecting
- H10W72/075—Connecting or disconnecting of bond wires
- H10W72/07531—Techniques
- H10W72/07532—Compression bonding, e.g. thermocompression bonding
- H10W72/07533—Ultrasonic bonding, e.g. thermosonic bonding
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/50—Bond wires
- H10W72/531—Shapes of wire connectors
- H10W72/536—Shapes of wire connectors the connected ends being ball-shaped
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/50—Bond wires
- H10W72/531—Shapes of wire connectors
- H10W72/5363—Shapes of wire connectors the connected ends being wedge-shaped
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/50—Bond wires
- H10W72/531—Shapes of wire connectors
- H10W72/5366—Shapes of wire connectors the bond wires having kinks
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/50—Bond wires
- H10W72/541—Dispositions of bond wires
- H10W72/5434—Dispositions of bond wires the connected ends being on auxiliary connecting means on bond pads, e.g. on other bond wires
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/50—Bond wires
- H10W72/551—Materials of bond wires
- H10W72/552—Materials of bond wires comprising metals or metalloids, e.g. silver
- H10W72/5522—Materials of bond wires comprising metals or metalloids, e.g. silver comprising gold [Au]
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/50—Bond wires
- H10W72/551—Materials of bond wires
- H10W72/552—Materials of bond wires comprising metals or metalloids, e.g. silver
- H10W72/5524—Materials of bond wires comprising metals or metalloids, e.g. silver comprising aluminium [Al]
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/50—Bond wires
- H10W72/59—Bond pads specially adapted therefor
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W90/00—Package configurations
- H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
- H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
- H10W90/754—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked insulating package substrate, interposer or RDL
Definitions
- Arrangement comprising a semiconductor chip and a carrier provided with a plated through-hole as well as a wire connecting a connection pad of the semiconductor chip to the plated-through hole, and method for producing such an arrangement
- the invention relates to an arrangement comprising a semiconductor chip and a carrier provided with a contact point and a wire connecting a terminal pad of the semiconductor chip with the contact point, wherein a first nailhead contact is formed on the contact point, the first end of the. Wire is connected to a second nailhead contact with the terminal pad of the semiconductor chip and the second end of the wire by means of a wedge contact with the first nailhead contact.
- the invention also relates to a method for producing such an arrangement.
- the object of the invention is to enable as simple and cost-effective as possible a connection of a wire, in particular a gold or aluminum wire with a carrier surface, which has only a low degree of metallization at the point to be bonded.
- the invention teaches a nailhead contact directly onto a support surface at the site of a via contact. without further surface metallization being present there. Only the through-hole forming hole through the carrier is metallized. By applying the nailhead contact on the surface of the carrier at the location of this hole, a sufficiently good connection is made to the metallization in the hole, so that by means of the Wedge contact applied to the nailhead contact, a connection to the other surface of the carrier or to a metal layer between two insulating carrier layers is made. Thus, a contact pad on the carrier is replaced in accordance with the invention by the first nailhead contact. This advantageously saves expensive substrate area; the circuit can be switched off.
- a further advantage of the arrangement according to the invention or of the method according to the invention is that, by dispensing with the customary bonding pads on the carrier surface, a process step in the production of printed conductors on the carrier surface can be dispensed with. This leads to a cost reduction due to the saving of gold paste commonly used for this purpose.
- the carrier is to be formed with a ceramic.
- the carrier may also be a PC board (printed circuit board).
- the carrier may be both of an insulating layer, so that the through-connection extends from one carrier surface to the other, but it may also consist of two or more insulating layers, wherein metallizations in the form of lines and / or ground planes are arranged between the layers and the vias at least partially extend only to these intermetallicizations.
- FIG. 1 An arrangement according to the invention.
- a carrier 1 is formed with two insulating layers, between which metallized surfaces and / or conductor tracks 2 are arranged.
- a semiconductor chip 3 is arranged on a surface of the carrier 1.
- the carrier layer, on which the semiconductor chip 3 is arranged leads a through-connection 9, by means of which the metallized surface o- of the conductor track 2 can be contacted.
- no contact pad is provided on the carrier surface but a first nailhead contact 4 is applied, from which the wire has been severed.
- a connection pad (not shown in detail) of the semiconductor chip 3 is a second
- Nailhead contact 5 generates, starting from which the semiconductor chip 3 with the through-connection 9 connecting wire 6 to the first nailhead contact 4 extends and is connected there by means of a wedge contact 7 with this.
- the first nail head contact 4 is pressed somewhat into the hole in the carrier layer of the through-connection 9, so that good contact with the metallization of the hole is achieved.
- the invention is not limited to multi-layer application
- the capillary 8 of the bonding tool is also shown to indicate the inventive method.
Landscapes
- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Wire Bonding (AREA)
Abstract
Description
Claims
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| DE10233607 | 2002-07-24 | ||
| DE10233607A DE10233607B4 (de) | 2002-07-24 | 2002-07-24 | Anordnung mit einem Halbleiterchip und einem mit einer Durchkontaktierung versehenen Träger sowie einem ein Anschlusspad des Halbleiterchips mit der Durchkontaktierung verbindenden Draht und Verfahren zum Herstellen einer solchen Anordnung |
| PCT/DE2003/002465 WO2004017400A1 (de) | 2002-07-24 | 2003-07-22 | Anordnung mit einem halbleiterchip und dessen träger sowie verfahren zur bond-drahtverbindung |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| EP1523769A1 true EP1523769A1 (de) | 2005-04-20 |
Family
ID=30128330
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| EP03787714A Withdrawn EP1523769A1 (de) | 2002-07-24 | 2003-07-22 | Anordnung mit einem halbleiterchip und dessen träger sowie verfahren zur bond-drahtverbindung |
Country Status (6)
| Country | Link |
|---|---|
| US (1) | US7053489B2 (de) |
| EP (1) | EP1523769A1 (de) |
| JP (1) | JP4308765B2 (de) |
| AU (1) | AU2003258458A1 (de) |
| DE (1) | DE10233607B4 (de) |
| WO (1) | WO2004017400A1 (de) |
Families Citing this family (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20070216026A1 (en) * | 2006-03-20 | 2007-09-20 | Adams Zhu | Aluminum bump bonding for fine aluminum wire |
| US8021931B2 (en) * | 2006-12-11 | 2011-09-20 | Stats Chippac, Inc. | Direct via wire bonding and method of assembling the same |
| US20080191367A1 (en) * | 2007-02-08 | 2008-08-14 | Stats Chippac, Ltd. | Semiconductor package wire bonding |
| DE102015221979A1 (de) * | 2015-11-09 | 2017-05-11 | Robert Bosch Gmbh | Kontaktieranordnung für ein Leiterplattensubstrat und Verfahren zum Kontaktieren eines Leiterplattensubstrats |
| DE102016109349A1 (de) * | 2016-05-20 | 2017-11-23 | Infineon Technologies Ag | Chipgehäuse, verfahren zum bilden eines chipgehäuses und verfahren zum bilden eines elektrischen kontakts |
Family Cites Families (19)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS60136356A (ja) * | 1983-12-26 | 1985-07-19 | Hitachi Ltd | 半導体装置 |
| US4868634A (en) * | 1987-03-13 | 1989-09-19 | Citizen Watch Co., Ltd. | IC-packaged device |
| US5258647A (en) * | 1989-07-03 | 1993-11-02 | General Electric Company | Electronic systems disposed in a high force environment |
| JP2757574B2 (ja) * | 1991-03-14 | 1998-05-25 | 日本電気株式会社 | 低誘電率ハイブリッド多層セラミック配線基板の製造方法 |
| JPH0636356A (ja) * | 1992-07-22 | 1994-02-10 | Hitachi Ltd | 光ディスク原盤の製造方法 |
| DE4318061C2 (de) * | 1993-06-01 | 1998-06-10 | Schulz Harder Juergen | Verfahren zum Herstellen eines Metall-Keramik-Substrates |
| US6111306A (en) * | 1993-12-06 | 2000-08-29 | Fujitsu Limited | Semiconductor device and method of producing the same and semiconductor device unit and method of producing the same |
| US5874354A (en) * | 1995-09-26 | 1999-02-23 | Siemens Aktiengesellschaft | Method for electrically connecting a semiconductor chip to at least one contact surface and smart card module and smart card produced by the method |
| JPH09330943A (ja) * | 1996-06-13 | 1997-12-22 | Shinko Electric Ind Co Ltd | 半導体装置及びその製造方法 |
| JP3344235B2 (ja) * | 1996-10-07 | 2002-11-11 | 株式会社デンソー | ワイヤボンディング方法 |
| US6133072A (en) * | 1996-12-13 | 2000-10-17 | Tessera, Inc. | Microelectronic connector with planar elastomer sockets |
| JP3042441B2 (ja) * | 1997-03-12 | 2000-05-15 | 日本電気株式会社 | 低温焼成ガラスセラミックス基板とその製造方法 |
| KR100309957B1 (ko) * | 1997-09-08 | 2002-08-21 | 신꼬오덴기 고교 가부시키가이샤 | 반도체장치 |
| DE19809081A1 (de) * | 1998-03-04 | 1999-09-16 | Bosch Gmbh Robert | Verfahren und Kontaktstelle zur Herstellung einer elektrischen Verbindung |
| JP2000068309A (ja) * | 1998-08-21 | 2000-03-03 | Misuzu Kogyo:Kk | 半導体装置の実装方法 |
| JP2000133672A (ja) * | 1998-10-28 | 2000-05-12 | Seiko Epson Corp | 半導体装置及びその製造方法、回路基板並びに電子機器 |
| JP3855532B2 (ja) * | 1999-05-12 | 2006-12-13 | 株式会社デンソー | Icチップと回路基板との接続方法 |
| US6465882B1 (en) * | 2000-07-21 | 2002-10-15 | Agere Systems Guardian Corp. | Integrated circuit package having partially exposed conductive layer |
| JP3854054B2 (ja) * | 2000-10-10 | 2006-12-06 | 株式会社東芝 | 半導体装置 |
-
2002
- 2002-07-24 DE DE10233607A patent/DE10233607B4/de not_active Expired - Fee Related
-
2003
- 2003-07-22 JP JP2004528420A patent/JP4308765B2/ja not_active Expired - Fee Related
- 2003-07-22 AU AU2003258458A patent/AU2003258458A1/en not_active Abandoned
- 2003-07-22 WO PCT/DE2003/002465 patent/WO2004017400A1/de not_active Ceased
- 2003-07-22 EP EP03787714A patent/EP1523769A1/de not_active Withdrawn
-
2005
- 2005-01-20 US US11/039,284 patent/US7053489B2/en not_active Expired - Lifetime
Non-Patent Citations (1)
| Title |
|---|
| See references of WO2004017400A1 * |
Also Published As
| Publication number | Publication date |
|---|---|
| DE10233607B4 (de) | 2005-09-29 |
| DE10233607A1 (de) | 2004-02-12 |
| JP2006502564A (ja) | 2006-01-19 |
| JP4308765B2 (ja) | 2009-08-05 |
| WO2004017400A1 (de) | 2004-02-26 |
| US7053489B2 (en) | 2006-05-30 |
| US20050127497A1 (en) | 2005-06-16 |
| AU2003258458A1 (en) | 2004-03-03 |
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Legal Events
| Date | Code | Title | Description |
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Free format text: ORIGINAL CODE: 0009012 |
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| 17P | Request for examination filed |
Effective date: 20041203 |
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| AX | Request for extension of the european patent |
Extension state: AL LT LV MK |
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| DAX | Request for extension of the european patent (deleted) | ||
| RBV | Designated contracting states (corrected) |
Designated state(s): FR IT |
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| REG | Reference to a national code |
Ref country code: DE Ref legal event code: 8566 |
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| 17Q | First examination report despatched |
Effective date: 20060721 |
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| RAP1 | Party data changed (applicant data changed or rights of an application transferred) |
Owner name: CONTINENTAL AUTOMOTIVE GMBH |
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| STAA | Information on the status of an ep patent application or granted ep patent |
Free format text: STATUS: THE APPLICATION IS DEEMED TO BE WITHDRAWN |
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| 18D | Application deemed to be withdrawn |
Effective date: 20110201 |