EP1456872A1 - Procede de depot de couches de semi-conducteurs des groupes iii et v sur un substrat ne faisant pas partie des groupes iii et v - Google Patents

Procede de depot de couches de semi-conducteurs des groupes iii et v sur un substrat ne faisant pas partie des groupes iii et v

Info

Publication number
EP1456872A1
EP1456872A1 EP02792976A EP02792976A EP1456872A1 EP 1456872 A1 EP1456872 A1 EP 1456872A1 EP 02792976 A EP02792976 A EP 02792976A EP 02792976 A EP02792976 A EP 02792976A EP 1456872 A1 EP1456872 A1 EP 1456872A1
Authority
EP
European Patent Office
Prior art keywords
layer
iii
substrate
masking
particular according
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP02792976A
Other languages
German (de)
English (en)
Inventor
Holger JÜRGENSEN
Alois Krost
Armin Dadgar
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Aixtron SE
Original Assignee
Aixtron SE
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from DE10206751A external-priority patent/DE10206751A1/de
Application filed by Aixtron SE filed Critical Aixtron SE
Publication of EP1456872A1 publication Critical patent/EP1456872A1/fr
Withdrawn legal-status Critical Current

Links

Classifications

    • C—CHEMISTRY; METALLURGY
    • C30—CRYSTAL GROWTH
    • C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
    • C30B25/00—Single-crystal growth by chemical reaction of reactive gases, e.g. chemical vapour-deposition growth
    • C30B25/02—Epitaxial-layer growth
    • C—CHEMISTRY; METALLURGY
    • C30—CRYSTAL GROWTH
    • C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
    • C30B25/00—Single-crystal growth by chemical reaction of reactive gases, e.g. chemical vapour-deposition growth
    • C30B25/02—Epitaxial-layer growth
    • C30B25/18—Epitaxial-layer growth characterised by the substrate
    • C—CHEMISTRY; METALLURGY
    • C30—CRYSTAL GROWTH
    • C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
    • C30B29/00—Single crystals or homogeneous polycrystalline material with defined structure characterised by the material or by their shape
    • C30B29/10—Inorganic compounds or compositions
    • C30B29/40—AIIIBV compounds wherein A is B, Al, Ga, In or Tl and B is N, P, As, Sb or Bi
    • C—CHEMISTRY; METALLURGY
    • C30—CRYSTAL GROWTH
    • C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
    • C30B29/00—Single crystals or homogeneous polycrystalline material with defined structure characterised by the material or by their shape
    • C30B29/10—Inorganic compounds or compositions
    • C30B29/40—AIIIBV compounds wherein A is B, Al, Ga, In or Tl and B is N, P, As, Sb or Bi
    • C30B29/403—AIII-nitrides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/0237—Materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/0237—Materials
    • H01L21/02373—Group 14 semiconducting materials
    • H01L21/02381—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/0237—Materials
    • H01L21/0242—Crystalline insulating materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02439—Materials
    • H01L21/02455—Group 13/15 materials
    • H01L21/02458—Nitrides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02439—Materials
    • H01L21/02455—Group 13/15 materials
    • H01L21/02463—Arsenides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02494—Structure
    • H01L21/02496—Layer structure
    • H01L21/02502—Layer structure consisting of two layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02538—Group 13/15 materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02612—Formation types
    • H01L21/02617—Deposition types
    • H01L21/02636—Selective deposition, e.g. simultaneous growth of mono- and non-monocrystalline semiconductor materials
    • H01L21/02639—Preparation of substrate for selective deposition
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02612—Formation types
    • H01L21/02617—Deposition types
    • H01L21/02636—Selective deposition, e.g. simultaneous growth of mono- and non-monocrystalline semiconductor materials
    • H01L21/02647—Lateral overgrowth

Definitions

  • the invention relates to a method for depositing III-V semiconductor layers on a non-III-V substrate, in particular sapphire, silicon, silicon oxide substrate or another silicon-containing substrate, in a process chamber of a reactor made of gaseous starting materials a III-V layer, in particular a buffer layer, is deposited on a III-V seed layer.
  • III-V semiconductors for example gallium arsenide or indium phosphide or mixed crystals, leads to a high defect density of the grown layer due to the lattice mismatch that is usually present.
  • the gallium arsenide or indium phosphide layer is deposited according to the invention in the MOCVD process / in which gaseous starting materials, for example TMG, TMI, TMAl, arsine or phosphine NH3 are introduced into the process chamber of a reactor, where the silicon substrate is located on a heated substrate holder ,
  • gaseous starting materials for example TMG, TMI, TMAl, arsine or phosphine NH3
  • the object of the invention is to provide a method by means of which the defect density of the grown layer can be reduced.
  • the masking layer is deposited as a quasi-monolayer. This creates a quasi-monolayer.
  • the masking layer preferably consists of a different semiconductor material than the seed layer or the layer deposited thereon, for example the buffer layer.
  • the masking layer can consist of Si x N or SiO x . But it can also consist of metal. As a result of the deposition of this masking layer on the generally less than 100 nm thick seed layer, the seed layer is covered except for randomly distributed island areas.
  • the masking layer After the masking layer has been deposited, a very thin layer is formed on the III-V seed layer or on the substrate, on which no III-V material grows. The majority of the surface is masked. However, this layer or mask is not closed, but rather forms island-shaped free spaces in which a free III-V surface of the germ layer is present. These island-like III-V surface sections form germ zones for the III-V buffer layer to be deposited thereafter.
  • the buffer layer is deposited from one or more gaseous III material and one or more gaseous V material. The germ growth initially occurs only in the area of the free 111 V surfaces, i.e. on the islands, at locations that are at a distance from one another.
  • this layer (buffer layer) are initially selected so that essentially lateral growth takes place. The germs therefore initially grow towards each other until an essentially closed layer has formed. With this method, areas with a very low defect density are formed over a large area. After the surface has been closed, the growth parameters can be changed such that the growth takes place primarily in the vertical direction.
  • a seed layer denoted by k made of, for example, gallium arsenide, aluminum nitride, aluminum gallium nitride, gallium aluminum arsenide or the like is deposited on the silicon substrate.
  • a masking layer of, for example, silicon nitride or silicon oxide is then deposited onto this seed layer k in the manner described above.
  • any layer on which further germination of the III-V material is suppressed during the subsequent deposition of the buffer layer is suitable as a masking layer.
  • the actual buffer layer is then deposited on the masked seed layer. This is shown in drawing 2.
  • the growth there initially takes place only in the lateral direction. The individual islands enlarge towards each other. There is increased lateral growth. The germs can coalize so quickly.
  • dislocated facets can also be used, for example, to bend in the lateral direction. New dislocations then only form in the coalescence regions of the laterally growing layers. For a low defect density, a large distance between the crystal nuclei or
  • Drawing 3 shows the complete III-V layer with c.
  • the seed layer itself serves to uniformly argue the substrate and, in the case of non-polar substrates, to orient the crystal growing thereon. This is not necessary when using the insulating sapphire as a substrate, and an in-situ Si _, N v mask deposited directly on the substrate can also be used here to improve the crystallographic properties. Such a masking cannot be controlled in the case of silicon-containing substrates such as SiC or SiGe layers and in particular in the case of pure silicon, because the substrate is completely nitrided or oxidized too quickly and the seed layer is necessary to specify the polarity.
  • this can also be carried out at lower temperatures than at the later growth temperatures and / or with starting materials, such as Aluminum, which have a lower mobility.
  • starting materials such as Aluminum, which have a lower mobility.
  • a generally undesirable island growth of the seed layer can thus be avoided and the polarity or orientation for the subsequent layer growth can be specified.
  • aluminum-containing seed layers are also particularly suitable in order to improve the crystal orientation.
  • a variant of the invention provides that a plurality of masking layers are deposited within the buffer layer.
  • the masking layer is applied in situ, ie immediately after the application of a III-V layer in the same process chamber, without the substrate being covered or removed from the process chamber.
  • the layers can be produced in a variety of ways. For example, only oxygen can be introduced into the process chamber to produce a masking layer. Oxide formation then occurs. This is particularly advantageous if the III-V layer contains aluminum. An aluminum oxide masking layer then forms. Silicon can also be deposited together with oxygen. Metallic masks can also be used. For example, tungsten can be used.
  • An amorphous masking layer has the effect of interrupting the crystal periodicity.
  • the masking layer can also be achieved by degradation of the semiconductor surface, for example at high temperatures.
  • the openings of the masking layers can be a distance of several hundred Have nanometers up to a few micrometers. As the growth starts from the openings, the layers above the masks grow in single crystals until the individual germs touch. In this case, the germs grow almost without dislocations up to the coalescence points. There may again be dislocations.
  • a mask is deposited again on a first region of a buffer layer.
  • This buffer layer section then acts to a certain extent as a seed layer for a III-V semiconductor layer to be deposited thereon.
  • This layer sequence can be repeated many times, which leads overall to a reduction in the dislocation density.
  • the process is then also carried out in such a way that the process parameters are set in each case after the deposition of a masking layer in such a way that lateral growth initially preferably takes place so that the gaps close.

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  • Engineering & Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Power Engineering (AREA)
  • Materials Engineering (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Metallurgy (AREA)
  • Organic Chemistry (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Inorganic Chemistry (AREA)

Abstract

L'invention concerne un procédé de dépôt de couches de semi-conducteurs des groupes III et V sur un substrat ne faisant pas partie des groupes III et V, en particulier un substrat de saphir, de silicium ou d'oxyde de silicium ou bien un autre substrat contenant du silicium. Selon ledit procédé, dans la chambre de traitement d'un réacteur, une couche d'un élément du groupe III ou du groupe V, en particulier une couche tampon, est déposée, à partir d'une matière de départ gazeuse, sur le substrat ou sur une couche de germination d'éléments des groupes III et V. Pour que la densité de défauts de la surcroissance soi réduite, il est prévu qu'une couche de masquage, constituée d'une matière sensiblement amorphe, soit déposée directement sur la couche de germination d'éléments des groupes III-V ou directement sur le substrat, cette couche de masquage recouvrant non complètement ou sensiblement non complètement la couche de germination. Cette couche de masquage peut être une quasi-monocouche et constituée de différents matériaux.
EP02792976A 2001-12-21 2002-12-11 Procede de depot de couches de semi-conducteurs des groupes iii et v sur un substrat ne faisant pas partie des groupes iii et v Withdrawn EP1456872A1 (fr)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
DE10163715 2001-12-21
DE10163715 2001-12-21
DE10206751A DE10206751A1 (de) 2001-12-21 2002-02-19 Verfahren zum Abscheiden von III-V-Halbleiterschichten auf einem Nicht -III-V-Substrat
DE10206751 2002-02-19
PCT/EP2002/014096 WO2003054939A1 (fr) 2001-12-21 2002-12-11 Procede de depot de couches de semi-conducteurs des groupes iii et v sur un substrat ne faisant pas partie des groupes iii et v

Publications (1)

Publication Number Publication Date
EP1456872A1 true EP1456872A1 (fr) 2004-09-15

Family

ID=26010858

Family Applications (1)

Application Number Title Priority Date Filing Date
EP02792976A Withdrawn EP1456872A1 (fr) 2001-12-21 2002-12-11 Procede de depot de couches de semi-conducteurs des groupes iii et v sur un substrat ne faisant pas partie des groupes iii et v

Country Status (6)

Country Link
US (1) US7128786B2 (fr)
EP (1) EP1456872A1 (fr)
JP (1) JP2005513799A (fr)
AU (1) AU2002358678A1 (fr)
TW (1) TW561526B (fr)
WO (1) WO2003054939A1 (fr)

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SAKAI S. ET AL: "A new method of reducing dislocation density in GaN layer grown on sapphire substrate by MOVPE", JOURNAL OF CRYSTAL GROWTH, vol. 221, 1 December 2000 (2000-12-01), pages 334 - 337, XP004226879 *
See also references of WO03054939A1 *

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TW561526B (en) 2003-11-11
WO2003054939A1 (fr) 2003-07-03
US20050022725A1 (en) 2005-02-03
US7128786B2 (en) 2006-10-31
AU2002358678A1 (en) 2003-07-09

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