TW561526B - Method for depositing III-V semiconductor layers on a non-III-V substrate - Google Patents

Method for depositing III-V semiconductor layers on a non-III-V substrate Download PDF

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TW561526B
TW561526B TW091124715A TW91124715A TW561526B TW 561526 B TW561526 B TW 561526B TW 091124715 A TW091124715 A TW 091124715A TW 91124715 A TW91124715 A TW 91124715A TW 561526 B TW561526 B TW 561526B
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Holger Jurgensen
Alois Krost
Armin Dadgar
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Aixtron Ag
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    • C—CHEMISTRY; METALLURGY
    • C30—CRYSTAL GROWTH
    • C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
    • C30B25/00—Single-crystal growth by chemical reaction of reactive gases, e.g. chemical vapour-deposition growth
    • C30B25/02—Epitaxial-layer growth
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    • C30B25/00—Single-crystal growth by chemical reaction of reactive gases, e.g. chemical vapour-deposition growth
    • C30B25/02—Epitaxial-layer growth
    • C30B25/18—Epitaxial-layer growth characterised by the substrate
    • C—CHEMISTRY; METALLURGY
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    • C30B29/00—Single crystals or homogeneous polycrystalline material with defined structure characterised by the material or by their shape
    • C30B29/10—Inorganic compounds or compositions
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    • C—CHEMISTRY; METALLURGY
    • C30—CRYSTAL GROWTH
    • C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
    • C30B29/00—Single crystals or homogeneous polycrystalline material with defined structure characterised by the material or by their shape
    • C30B29/10—Inorganic compounds or compositions
    • C30B29/40—AIIIBV compounds wherein A is B, Al, Ga, In or Tl and B is N, P, As, Sb or Bi
    • C30B29/403—AIII-nitrides
    • H—ELECTRICITY
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/0237—Materials
    • H01L21/02373—Group 14 semiconducting materials
    • H01L21/02381—Silicon, silicon germanium, germanium
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
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    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
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    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02439—Materials
    • H01L21/02455—Group 13/15 materials
    • H01L21/02458—Nitrides
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02439—Materials
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    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02494—Structure
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    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
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    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02612—Formation types
    • H01L21/02617—Deposition types
    • H01L21/02636—Selective deposition, e.g. simultaneous growth of mono- and non-monocrystalline semiconductor materials
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    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02612—Formation types
    • H01L21/02617—Deposition types
    • H01L21/02636—Selective deposition, e.g. simultaneous growth of mono- and non-monocrystalline semiconductor materials
    • H01L21/02647—Lateral overgrowth

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Description

561526
、本發明係有關一種在非第丨丨丨—v族基板上沉積第丨丨丨—v族 半V體薄膜之方法，該基板尤其是藍寶石、矽、氧化矽基 板或其他含矽基板，其使一反應器反應室中的氣態材料沉 積在一第III-V族晶芽層上而構成一第V族層，尤其是 一緩衝層。 、 由於成本之考量 曰 v你干等筱隹兵Μ /土、似丄叼麻 曰:成長為目前之趨勢，因矽基板的價格明顯低於第丨丨〗_ν ii板=其、是砷化鎵基板，且有必要與其他矽電子技術 二！二，半導· ’例如坤化鎵或碌化銦或其混合 現晶格不匹配而導致成長層具有高缺陷 申化嫁或填化姻層白勺沉積* _CVD法， ”將虱恶材料，例如TMG、TMI、τ ΝΗ3,輸入一；5虛口口 — 〜丄 曱化氧或麟化氫、
. 燕 反應為之反應室中，該處之一加埶其此广L 放置一矽基板。 …、基板座上 法本發明之目的在於提供一種降低成長層缺陷密度之方 ^由申請專利範圍中所述之本發明而 專利蚝圍第1項所述，在第n Nv族晶芽層上t。如申請 =完全或幾乎*完全覆蓋且基本上由非晶系^沉積—層 ^層。此#料應儘量具有阻止、4構成的覆 J:月：覆蓋層以類似翠層設置，…單成層長構之特 同於晶芽層或其上沉㈣，例如緩衝屛：：盖層 :料=。覆蓋層_以或叫構成，但^之：導體 成。錢蓋層沉積於厚度通常小於⑽由金屬構 日曰牙層上，晶
第4頁 561526 五、發明說明（2) t散的島區外皆被覆蓋。覆蓋層沉積後第m-v ==或沒有成長出第⑴巧族材料的基板上因此出現 構成U面的大部分皆被覆蓋。言亥覆蓋層並不密封而 ^。曰Λ 成猶後欲沉積之第⑴，緩衝層的晶芽 種氣，積後以一或多種氣態第hi族材料及一或多 之Γ材料沉積一緩衝層。晶芽成長首先只在露出 居成县失上表面處，亦即在彼此分離的島區。（緩衝） Γ吏成長首ΐ基本上只為橫向。晶芽於是首先 陷穷产^直至層減為止。此方法可產生具極低缺 積範圍…密封後可改變成長參數，使成 砷=中弋基板上沉積一層被標示為'之晶芽層，其例如由 ^ ^ ί k ^ ^ ^ls ° ^ ^ ^ ^ 砂# ^彳卜^ 上所芽覆蓋層，其例如由氮化 體其切氣體及-含氮氣 反覆蓋層基本上為在猶後緩 覆：：：抑制第iii_v族材料⑨-步形成晶芽之所有 顯：於該被覆蓋的晶芽層上沉積真正的緩衝層。其 大不^ ^ 。、§亥處之成長只在橫向上。各島朝向彼此而增 ^ '為橫向的。晶芽可快速聚結。此外，視晶體種 ==疋，可，斜晶面使排列錯置偏轉到橫向上。故新的錯 +只產^於橫向成長層的聚結區。為達到低缺陷密度因此 而使晶牙或覆蓋層窗口的距離大。該距離可為數泣m。
561526
五、發明說明（3) 圖3中以c表示完整的第ιιΐ-ν族層。 、晶芽層本身的作用在於使基板均勻生成晶芽，並在基板 為$極性時使基板上成長的晶體為定向。故其在使用絕緣 ，寶石作為基板時為不必要，而可在基板上直接沉積一層 臨場（In-situ)之SixNy覆蓋層以改善結晶特性。使用含石夕曰 基板，例如Si C或Si Ge層，尤其是純矽時，此種覆蓋層不 可被控制，因基板太快被完全氮化或氧化，故需要晶芽層 以定出極性。 為均勻地生成晶芽，可在低溫下或稍後所使用之成長溫 度下及/或使用具較低流動性的材料，例如鋁，而製作晶 芽層。如此可避免對晶芽層不利的島成長，而定出後續03層 成長^極性或方向。此外，為第丨丨ϊ族氮化物層時，含銘θ 之晶芽層特別適於改善結晶方向。 本發明另一實施例在緩衝層之内沉積多層覆蓋層。此處 覆蓋層亦為臨場塗佈，亦即於塗佈第丨丨丨—V族層後在同一 反2室中直接塗佈覆蓋層，而不遮蔽基板或將基板移出反 應至。该覆蓋層可以不同方式製作。例如只將氧輸入反應 室中，而生成一氧化物。第丨丨丨-V族層含鋁時，如此為特u 別有利，故生成一氧化鋁覆蓋層。亦可使矽與氧一起沉 積。亦可使用金屬覆蓋層，例如鎢。 / 、非晶系覆蓋層會中斷晶體週期性。高溫下半導體表面的 退化亦可得到覆蓋層。覆蓋層窗口的距離可由數百太米至 數微米。由於成長由窗口開始，故層在覆蓋層上單2成 長直至各曰曰芽自行接觸。此處晶芽之成長除了聚結處之
561526 五、發明說明（4) 外幾乎無錯置。該處可重新產生錯置。 緩衝層之一第一部份上被重新沉積一層覆蓋層。該部分 緩衝層於是構成稍後所沉積第I I I - V族半導體層的晶芽 層。可多次重複製作此種疊層而減少錯置密度。沉積一覆 蓋層後可調整製程參數，使得成長優先為橫向而密封窗 v 〇 所有揭示特徵本身皆具有發明性質。本發明揭示之特徵 完全包含於本案之申請專利範圍中。
C:\2D-CODE\92-Ol\91124715.ptd 第 7 頁 561526 圖式簡單說明 圖1為於石夕基板上形成一晶芽層後，再沈積一不完全之 覆蓋層之剖面圖。 圖2為於晶芽層上沈積一橫向成長之緩衝層之剖面圖。 圖3為形成一完整之第I I I -V族緩衝層之剖面圖。
91124715.ptd 第8頁

Claims (1)

  1. 561526 六、申請專利範圍 1 ·、種在非第I I I _ V族基板上沉積第Π I - V族半導體薄膜 之方 忒基板尤其是監寶石、石夕、氧化石夕基板或其他含 =反族Λ使一反應器反應室中的氣態材料沉積在二第3 成甘4Γ牙層上而構成一第1 1 1 —V族層，尤其是一緩衝 :不二=為，在第族晶芽層或基板上直 — 或幾乎不完全覆蓋且基本上由非晶系材料構成的 其中覆盍層是一似單 其中覆蓋層由不同於 〇 其中覆蓋層是SixNy或 其中覆蓋層是一金 其中調整成長參數使 2 ·如申請專利範圍第1項之方法5 層。 3 ·如申請專利範圍第1項之方法 晶芽層或緩衝層之半導體材盖5 4 ·如申請專利範圍第丨項之 S i C»x。 万法’ 5·如申請專利範圍第丨項 屬。 ^法’ 6·如申請專利範圍第丨項之 得層成長首先只為橫向法’其中| 7.如申請專利範圍第i項之至方層/封為止。 1 00 nm。 去，其中晶芽層厚度小於 8 ·如申凊專利範圍第1項之 積多層覆蓋層。 法’其中在緩衝層之内沉 9 ·如申请專利範圍第丨項之 覆蓋層被循環沉積。 '’其中該部分緩衝層及 1 0 ·如申請專利範圍第〗 、之方法，其中覆蓋層具—阻止
    ms C:\2D-CODE\92-Ol\91124715.ptd 561526 六、申請專利範圍 第I I I - V族層沉積之表面。 11. 如申請專利範圍第1項之方法，其中晶芽層及/或緩 衝層含鋁，覆蓋層藉輸入氧而產生。 12. 如申請專利範圍第1項之方法，其中沉積使用MOCVD 法、CVD法或其臨場部分。 1 3.如申請專利範圍第1項之方法，其中沉積使用VPE或 MBE 法。 1 4.如申請專利範圍第1項之方法，其中緩衝層上沉積元 件薄膜。 1 5.如申請專利範圍第1 4項之方法，其中由元件薄膜製 . 程元件。
    C:\2D-CODE\92-Ol\91124715.ptd 第10頁
TW091124715A 2001-12-21 2002-10-24 Method for depositing III-V semiconductor layers on a non-III-V substrate TW561526B (en)

Applications Claiming Priority (2)

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DE10163715 2001-12-21
DE10206751A DE10206751A1 (de) 2001-12-21 2002-02-19 Verfahren zum Abscheiden von III-V-Halbleiterschichten auf einem Nicht -III-V-Substrat

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US (1) US7128786B2 (zh)
EP (1) EP1456872A1 (zh)
JP (1) JP2005513799A (zh)
AU (1) AU2002358678A1 (zh)
TW (1) TW561526B (zh)
WO (1) WO2003054939A1 (zh)

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Publication number Priority date Publication date Assignee Title
US7172745B1 (en) * 2003-07-25 2007-02-06 Chien-Min Sung Synthesis of diamond particles in a metal matrix
DE10335080A1 (de) 2003-07-31 2005-03-03 Osram Opto Semiconductors Gmbh Verfahren zur Herstellung einer Vielzahl von optoelektronischen Halbleiterchips und optoelektronischer Halbleiterchip
DE10335081A1 (de) * 2003-07-31 2005-03-03 Osram Opto Semiconductors Gmbh Verfahren zur Herstellung einer Vielzahl von optoelektronischen Halbleiterchips und optoeleketronischer Halbleiterchip
EP1583139A1 (en) 2004-04-02 2005-10-05 Interuniversitaire Microelectronica Centrum vzw ( IMEC) Method for depositing a group III-nitride material on a silicon substrate and device therefor
US9406505B2 (en) * 2006-02-23 2016-08-02 Allos Semiconductors Gmbh Nitride semiconductor component and process for its production
WO2007122669A1 (ja) 2006-03-29 2007-11-01 Fujitsu Limited 多結晶ＳｉＣ基板を有する化合物半導体ウエハ、化合物半導体装置とそれらの製造方法
TWI334164B (en) * 2006-06-07 2010-12-01 Ind Tech Res Inst Method of manufacturing nitride semiconductor substrate and composite material substrate
TWI325641B (en) 2006-09-04 2010-06-01 Huga Optotech Inc Light emitting device and methods for forming the same
US20080083431A1 (en) * 2006-10-06 2008-04-10 Mark Schwarze Device and method for clearing debris from the front of a hood in a mechanized sweepers
US7825432B2 (en) * 2007-03-09 2010-11-02 Cree, Inc. Nitride semiconductor structures with interlayer structures
US8362503B2 (en) * 2007-03-09 2013-01-29 Cree, Inc. Thick nitride semiconductor structures with interlayer structures
US8841436B2 (en) * 2007-03-15 2014-09-23 University Hospitals Cleveland Medical Center Screening, diagnosing, treating and prognosis of pathophysiologic status by RNA regulation
US8962453B2 (en) * 2007-07-10 2015-02-24 Nxp B.V. Single crystal growth on a mis-matched substrate
US7732306B2 (en) * 2007-07-26 2010-06-08 S.O.I.Tec Silicon On Insulator Technologies Methods for producing improved epitaxial materials
WO2009049020A2 (en) 2007-10-11 2009-04-16 Valence Process Equipment, Inc. Chemical vapor deposition reactor
US8803189B2 (en) * 2008-08-11 2014-08-12 Taiwan Semiconductor Manufacturing Company, Ltd. III-V compound semiconductor epitaxy using lateral overgrowth
TWI425558B (zh) 2008-08-11 2014-02-01 Taiwan Semiconductor Mfg 形成電路結構的方法
EP2412006A1 (en) * 2009-02-05 2012-02-01 S.O.I.Tec Silicon on Insulator Technologies Epitaxial methods and structures for forming semiconductor materials
US8178427B2 (en) * 2009-03-31 2012-05-15 Commissariat A. L'energie Atomique Epitaxial methods for reducing surface dislocation density in semiconductor materials
DE102009050234A1 (de) † 2009-10-21 2011-05-05 Von Ardenne Anlagentechnik Gmbh Verfahren zur Beschichtung eines Substrats mit einer TCO-Schicht und Dünnschichtsolarzelle
WO2013139887A1 (de) * 2012-03-21 2013-09-26 Freiberger Compound Materials Gmbh Verfahren zur herstellung von iii-n-einkristallen, und iii-n-einkristall
DE102012107001A1 (de) * 2012-07-31 2014-02-06 Osram Opto Semiconductors Gmbh Verfahren zur Herstellung eines optoelektronischen Halbleiterchips und optoelektronischer Halbleiterchip
KR101464854B1 (ko) * 2013-01-14 2014-11-25 주식회사 엘지실트론 반도체 기판
JP6567685B2 (ja) 2015-03-24 2019-08-28 イラミーナ インコーポレーテッド 生物学的又は化学的な解析用のサンプルを撮像する方法、キャリヤ組立体、及びシステム
US9520394B1 (en) 2015-05-21 2016-12-13 International Business Machines Corporation Contact structure and extension formation for III-V nFET
KR102369676B1 (ko) 2017-04-10 2022-03-04 삼성디스플레이 주식회사 표시 장치의 제조장치 및 표시 장치의 제조방법
EP3696300A1 (de) * 2019-02-18 2020-08-19 Aixatech GmbH Verfahren zur herstellung eines verbundmaterialkörpers insbesondere für die verwendung bei der herstellung von elektronischen oder optoelektronischen bauelementen

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3321369B2 (ja) * 1996-09-27 2002-09-03 日本碍子株式会社 表面弾性波装置およびその基板およびその製造方法
EP2234142A1 (en) * 1997-04-11 2010-09-29 Nichia Corporation Nitride semiconductor substrate
FR2769924B1 (fr) * 1997-10-20 2000-03-10 Centre Nat Rech Scient Procede de realisation d'une couche epitaxiale de nitrure de gallium, couche epitaxiale de nitrure de gallium et composant optoelectronique muni d'une telle couche
US6051849A (en) * 1998-02-27 2000-04-18 North Carolina State University Gallium nitride semiconductor structures including a lateral gallium nitride layer that extends from an underlying gallium nitride layer
US6160833A (en) * 1998-05-06 2000-12-12 Xerox Corporation Blue vertical cavity surface emitting laser
JP3550070B2 (ja) * 1999-03-23 2004-08-04 三菱電線工業株式会社 ＧａＮ系化合物半導体結晶、その成長方法及び半導体基材
JP4145437B2 (ja) * 1999-09-28 2008-09-03 住友電気工業株式会社 単結晶ＧａＮの結晶成長方法及び単結晶ＧａＮ基板の製造方法と単結晶ＧａＮ基板
US6475882B1 (en) * 1999-12-20 2002-11-05 Nitride Semiconductors Co., Ltd. Method for producing GaN-based compound semiconductor and GaN-based compound semiconductor device
US6841808B2 (en) * 2000-06-23 2005-01-11 Toyoda Gosei Co., Ltd. Group III nitride compound semiconductor device and method for producing the same

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