WO2003054939A1 - Verfahren zum abscheiden von iii-v-halbleiterschichten auf einem nicht-iii-v-substrat - Google Patents
Verfahren zum abscheiden von iii-v-halbleiterschichten auf einem nicht-iii-v-substrat Download PDFInfo
- Publication number
- WO2003054939A1 WO2003054939A1 PCT/EP2002/014096 EP0214096W WO03054939A1 WO 2003054939 A1 WO2003054939 A1 WO 2003054939A1 EP 0214096 W EP0214096 W EP 0214096W WO 03054939 A1 WO03054939 A1 WO 03054939A1
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- WIPO (PCT)
- Prior art keywords
- layer
- iii
- substrate
- masking
- particular according
- Prior art date
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Classifications
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- C—CHEMISTRY; METALLURGY
- C30—CRYSTAL GROWTH
- C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
- C30B25/00—Single-crystal growth by chemical reaction of reactive gases, e.g. chemical vapour-deposition growth
- C30B25/02—Epitaxial-layer growth
-
- C—CHEMISTRY; METALLURGY
- C30—CRYSTAL GROWTH
- C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
- C30B25/00—Single-crystal growth by chemical reaction of reactive gases, e.g. chemical vapour-deposition growth
- C30B25/02—Epitaxial-layer growth
- C30B25/18—Epitaxial-layer growth characterised by the substrate
-
- C—CHEMISTRY; METALLURGY
- C30—CRYSTAL GROWTH
- C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
- C30B29/00—Single crystals or homogeneous polycrystalline material with defined structure characterised by the material or by their shape
- C30B29/10—Inorganic compounds or compositions
- C30B29/40—AIIIBV compounds wherein A is B, Al, Ga, In or Tl and B is N, P, As, Sb or Bi
-
- C—CHEMISTRY; METALLURGY
- C30—CRYSTAL GROWTH
- C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
- C30B29/00—Single crystals or homogeneous polycrystalline material with defined structure characterised by the material or by their shape
- C30B29/10—Inorganic compounds or compositions
- C30B29/40—AIIIBV compounds wherein A is B, Al, Ga, In or Tl and B is N, P, As, Sb or Bi
- C30B29/403—AIII-nitrides
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02367—Substrates
- H01L21/0237—Materials
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02367—Substrates
- H01L21/0237—Materials
- H01L21/02373—Group 14 semiconducting materials
- H01L21/02381—Silicon, silicon germanium, germanium
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02367—Substrates
- H01L21/0237—Materials
- H01L21/0242—Crystalline insulating materials
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02436—Intermediate layers between substrates and deposited layers
- H01L21/02439—Materials
- H01L21/02455—Group 13/15 materials
- H01L21/02458—Nitrides
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02436—Intermediate layers between substrates and deposited layers
- H01L21/02439—Materials
- H01L21/02455—Group 13/15 materials
- H01L21/02463—Arsenides
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02436—Intermediate layers between substrates and deposited layers
- H01L21/02494—Structure
- H01L21/02496—Layer structure
- H01L21/02502—Layer structure consisting of two layers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02518—Deposited layers
- H01L21/02521—Materials
- H01L21/02538—Group 13/15 materials
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02612—Formation types
- H01L21/02617—Deposition types
- H01L21/02636—Selective deposition, e.g. simultaneous growth of mono- and non-monocrystalline semiconductor materials
- H01L21/02639—Preparation of substrate for selective deposition
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02612—Formation types
- H01L21/02617—Deposition types
- H01L21/02636—Selective deposition, e.g. simultaneous growth of mono- and non-monocrystalline semiconductor materials
- H01L21/02647—Lateral overgrowth
Definitions
- the invention relates to a method for depositing III-V semiconductor layers on a non-III-V substrate, in particular sapphire, silicon, silicon oxide substrate or another silicon-containing substrate, in a process chamber of a reactor made of gaseous starting materials a III-V layer, in particular a buffer layer, is deposited on a III-V seed layer.
- III-V semiconductors for example gallium arsenide or indium phosphide or mixed crystals, leads to a high defect density of the grown layer due to the lattice mismatch that is usually present.
- the gallium arsenide or indium phosphide layer is deposited according to the invention in the MOCVD process / in which gaseous starting materials, for example TMG, TMI, TMAl, arsine or phosphine NH3 are introduced into the process chamber of a reactor, where the silicon substrate is located on a heated substrate holder ,
- gaseous starting materials for example TMG, TMI, TMAl, arsine or phosphine NH3
- the object of the invention is to provide a method by means of which the defect density of the grown layer can be reduced.
- the masking layer is deposited as a quasi-monolayer. This creates a quasi-monolayer.
- the masking layer preferably consists of a different semiconductor material than the seed layer or the layer deposited thereon, for example the buffer layer.
- the masking layer can consist of Si x N or SiO x . But it can also consist of metal. As a result of the deposition of this masking layer on the generally less than 100 nm thick seed layer, the seed layer is covered except for randomly distributed island areas.
- the masking layer After the masking layer has been deposited, a very thin layer is formed on the III-V seed layer or on the substrate, on which no III-V material grows. The majority of the surface is masked. However, this layer or mask is not closed, but rather forms island-shaped free spaces in which a free III-V surface of the germ layer is present. These island-like III-V surface sections form germ zones for the III-V buffer layer to be deposited thereafter.
- the buffer layer is deposited from one or more gaseous III material and one or more gaseous V material. The germ growth initially occurs only in the area of the free 111 V surfaces, i.e. on the islands, at locations that are at a distance from one another.
- this layer (buffer layer) are initially selected so that essentially lateral growth takes place. The germs therefore initially grow towards each other until an essentially closed layer has formed. With this method, areas with a very low defect density are formed over a large area. After the surface has been closed, the growth parameters can be changed such that the growth takes place primarily in the vertical direction.
- a seed layer denoted by k made of, for example, gallium arsenide, aluminum nitride, aluminum gallium nitride, gallium aluminum arsenide or the like is deposited on the silicon substrate.
- a masking layer of, for example, silicon nitride or silicon oxide is then deposited onto this seed layer k in the manner described above.
- any layer on which further germination of the III-V material is suppressed during the subsequent deposition of the buffer layer is suitable as a masking layer.
- the actual buffer layer is then deposited on the masked seed layer. This is shown in drawing 2.
- the growth there initially takes place only in the lateral direction. The individual islands enlarge towards each other. There is increased lateral growth. The germs can coalize so quickly.
- dislocated facets can also be used, for example, to bend in the lateral direction. New dislocations then only form in the coalescence regions of the laterally growing layers. For a low defect density, a large distance between the crystal nuclei or
- Drawing 3 shows the complete III-V layer with c.
- the seed layer itself serves to uniformly argue the substrate and, in the case of non-polar substrates, to orient the crystal growing thereon. This is not necessary when using the insulating sapphire as a substrate, and an in-situ Si _, N v mask deposited directly on the substrate can also be used here to improve the crystallographic properties. Such a masking cannot be controlled in the case of silicon-containing substrates such as SiC or SiGe layers and in particular in the case of pure silicon, because the substrate is completely nitrided or oxidized too quickly and the seed layer is necessary to specify the polarity.
- this can also be carried out at lower temperatures than at the later growth temperatures and / or with starting materials, such as Aluminum, which have a lower mobility.
- starting materials such as Aluminum, which have a lower mobility.
- a generally undesirable island growth of the seed layer can thus be avoided and the polarity or orientation for the subsequent layer growth can be specified.
- aluminum-containing seed layers are also particularly suitable in order to improve the crystal orientation.
- a variant of the invention provides that a plurality of masking layers are deposited within the buffer layer.
- the masking layer is applied in situ, ie immediately after the application of a III-V layer in the same process chamber, without the substrate being covered or removed from the process chamber.
- the layers can be produced in a variety of ways. For example, only oxygen can be introduced into the process chamber to produce a masking layer. Oxide formation then occurs. This is particularly advantageous if the III-V layer contains aluminum. An aluminum oxide masking layer then forms. Silicon can also be deposited together with oxygen. Metallic masks can also be used. For example, tungsten can be used.
- An amorphous masking layer has the effect of interrupting the crystal periodicity.
- the masking layer can also be achieved by degradation of the semiconductor surface, for example at high temperatures.
- the openings of the masking layers can be a distance of several hundred Have nanometers up to a few micrometers. As the growth starts from the openings, the layers above the masks grow in single crystals until the individual germs touch. In this case, the germs grow almost without dislocations up to the coalescence points. There may again be dislocations.
- a mask is deposited again on a first region of a buffer layer.
- This buffer layer section then acts to a certain extent as a seed layer for a III-V semiconductor layer to be deposited thereon.
- This layer sequence can be repeated many times, which leads overall to a reduction in the dislocation density.
- the process is then also carried out in such a way that the process parameters are set in each case after the deposition of a masking layer in such a way that lateral growth initially preferably takes place so that the gaps close.
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- Engineering & Computer Science (AREA)
- Chemical & Material Sciences (AREA)
- Manufacturing & Machinery (AREA)
- General Physics & Mathematics (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Materials Engineering (AREA)
- Crystallography & Structural Chemistry (AREA)
- Metallurgy (AREA)
- Organic Chemistry (AREA)
- Chemical Kinetics & Catalysis (AREA)
- General Chemical & Material Sciences (AREA)
- Inorganic Chemistry (AREA)
Abstract
Description
Claims
Priority Applications (5)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR10-2004-7009668A KR20040070255A (ko) | 2001-12-21 | 2002-12-11 | 비 ⅲ-ⅴ 기판상의 ⅲ-ⅴ 반도체층 증착방법 |
EP02792976A EP1456872A1 (de) | 2001-12-21 | 2002-12-11 | Verfahren zum abscheiden von iii-v-halbleiterschichten auf einem nicht-iii-v-substrat |
AU2002358678A AU2002358678A1 (en) | 2001-12-21 | 2002-12-11 | Method for depositing iii-v semiconductor layers on a non iii-v substrate |
JP2003555567A JP2005513799A (ja) | 2001-12-21 | 2002-12-11 | Iii−v半導体皮膜を非iii−v基板に沈積する方法 |
US10/872,914 US7128786B2 (en) | 2001-12-21 | 2004-06-21 | Process for depositing III-V semiconductor layers on a non-III-V substrate |
Applications Claiming Priority (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
DE10163715.2 | 2001-12-21 | ||
DE10163715 | 2001-12-21 | ||
DE10206751A DE10206751A1 (de) | 2001-12-21 | 2002-02-19 | Verfahren zum Abscheiden von III-V-Halbleiterschichten auf einem Nicht -III-V-Substrat |
DE10206751.1 | 2002-02-19 |
Related Child Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US10/872,914 Continuation US7128786B2 (en) | 2001-12-21 | 2004-06-21 | Process for depositing III-V semiconductor layers on a non-III-V substrate |
Publications (1)
Publication Number | Publication Date |
---|---|
WO2003054939A1 true WO2003054939A1 (de) | 2003-07-03 |
Family
ID=26010858
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/EP2002/014096 WO2003054939A1 (de) | 2001-12-21 | 2002-12-11 | Verfahren zum abscheiden von iii-v-halbleiterschichten auf einem nicht-iii-v-substrat |
Country Status (6)
Country | Link |
---|---|
US (1) | US7128786B2 (de) |
EP (1) | EP1456872A1 (de) |
JP (1) | JP2005513799A (de) |
AU (1) | AU2002358678A1 (de) |
TW (1) | TW561526B (de) |
WO (1) | WO2003054939A1 (de) |
Cited By (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7327036B2 (en) | 2003-12-22 | 2008-02-05 | Interuniversitair Microelektronica Centrum (Imec) | Method for depositing a group III-nitride material on a silicon substrate and device therefor |
WO2010089623A1 (en) * | 2009-02-05 | 2010-08-12 | S.O.I.Tec Silicon On Insulator Technologies | Epitaxial methods and structures for forming semiconductor materials |
US7896965B2 (en) * | 2003-07-31 | 2011-03-01 | Osram Opto Semiconductors Gmbh | Method for the production of a plurality of optoelectronic semiconductor chips and optoelectronic semiconductor chip |
US8017416B2 (en) | 2003-07-31 | 2011-09-13 | Osram Opto Semiconductors Gmbh | Method for the production of a plurality of opto-electronic semiconductor chips and opto-electronic semiconductor chip |
WO2014019752A1 (de) * | 2012-07-31 | 2014-02-06 | Osram Opto Semiconductors Gmbh | Verfahren zur herstellung eines optoelektronischen halbleiterchips und optoelektronischer halbleiterchip |
EP2171747B1 (de) * | 2007-07-26 | 2016-07-13 | Soitec | Verfahren zur herstellung verbesserter epitaktischer materialien |
EP2314732B2 (de) † | 2009-10-21 | 2016-08-03 | VON ARDENNE GmbH | Verfahren zur Beschichtung eines Substrats mit einer TCO-Schicht und Dünnschichtsolarzelle |
EP3696300A1 (de) * | 2019-02-18 | 2020-08-19 | Aixatech GmbH | Verfahren zur herstellung eines verbundmaterialkörpers insbesondere für die verwendung bei der herstellung von elektronischen oder optoelektronischen bauelementen |
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US7172745B1 (en) * | 2003-07-25 | 2007-02-06 | Chien-Min Sung | Synthesis of diamond particles in a metal matrix |
US9406505B2 (en) * | 2006-02-23 | 2016-08-02 | Allos Semiconductors Gmbh | Nitride semiconductor component and process for its production |
WO2007122669A1 (ja) | 2006-03-29 | 2007-11-01 | Fujitsu Limited | 多結晶SiC基板を有する化合物半導体ウエハ、化合物半導体装置とそれらの製造方法 |
TWI334164B (en) * | 2006-06-07 | 2010-12-01 | Ind Tech Res Inst | Method of manufacturing nitride semiconductor substrate and composite material substrate |
TWI325641B (en) | 2006-09-04 | 2010-06-01 | Huga Optotech Inc | Light emitting device and methods for forming the same |
US20080083431A1 (en) * | 2006-10-06 | 2008-04-10 | Mark Schwarze | Device and method for clearing debris from the front of a hood in a mechanized sweepers |
US7825432B2 (en) * | 2007-03-09 | 2010-11-02 | Cree, Inc. | Nitride semiconductor structures with interlayer structures |
US8362503B2 (en) * | 2007-03-09 | 2013-01-29 | Cree, Inc. | Thick nitride semiconductor structures with interlayer structures |
EP2126141A4 (de) * | 2007-03-15 | 2010-08-11 | Univ Cleveland Hospitals | Screening, diagnose, behandlung und prognose pathophysiologischer zustände durch rna-regulation |
US8962453B2 (en) * | 2007-07-10 | 2015-02-24 | Nxp B.V. | Single crystal growth on a mis-matched substrate |
CN101802254B (zh) | 2007-10-11 | 2013-11-27 | 瓦伦斯处理设备公司 | 化学气相沉积反应器 |
US8803189B2 (en) * | 2008-08-11 | 2014-08-12 | Taiwan Semiconductor Manufacturing Company, Ltd. | III-V compound semiconductor epitaxy using lateral overgrowth |
US8377796B2 (en) | 2008-08-11 | 2013-02-19 | Taiwan Semiconductor Manufacturing Company, Ltd. | III-V compound semiconductor epitaxy from a non-III-V substrate |
US8178427B2 (en) * | 2009-03-31 | 2012-05-15 | Commissariat A. L'energie Atomique | Epitaxial methods for reducing surface dislocation density in semiconductor materials |
PL2815421T3 (pl) * | 2012-03-21 | 2018-06-29 | Freiberger Compound Materials Gmbh | SPOSÓB WYTWARZANIA MATRYC lll-N I ICH DALSZEJ OBÓRKI I MATRYCA lll-N |
KR101464854B1 (ko) * | 2013-01-14 | 2014-11-25 | 주식회사 엘지실트론 | 반도체 기판 |
EP3274692B1 (de) | 2015-03-24 | 2022-08-10 | Illumina, Inc. | Verfahren zur bildgebung von proben zur biologischen oder chemischen analyse |
US9520394B1 (en) | 2015-05-21 | 2016-12-13 | International Business Machines Corporation | Contact structure and extension formation for III-V nFET |
KR102369676B1 (ko) | 2017-04-10 | 2022-03-04 | 삼성디스플레이 주식회사 | 표시 장치의 제조장치 및 표시 장치의 제조방법 |
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JP3321369B2 (ja) * | 1996-09-27 | 2002-09-03 | 日本碍子株式会社 | 表面弾性波装置およびその基板およびその製造方法 |
ATE550461T1 (de) * | 1997-04-11 | 2012-04-15 | Nichia Corp | Wachstumsmethode für einen nitrid-halbleiter |
US6051849A (en) * | 1998-02-27 | 2000-04-18 | North Carolina State University | Gallium nitride semiconductor structures including a lateral gallium nitride layer that extends from an underlying gallium nitride layer |
US6160833A (en) * | 1998-05-06 | 2000-12-12 | Xerox Corporation | Blue vertical cavity surface emitting laser |
JP3550070B2 (ja) * | 1999-03-23 | 2004-08-04 | 三菱電線工業株式会社 | GaN系化合物半導体結晶、その成長方法及び半導体基材 |
JP4145437B2 (ja) * | 1999-09-28 | 2008-09-03 | 住友電気工業株式会社 | 単結晶GaNの結晶成長方法及び単結晶GaN基板の製造方法と単結晶GaN基板 |
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-
2002
- 2002-10-24 TW TW091124715A patent/TW561526B/zh not_active IP Right Cessation
- 2002-12-11 JP JP2003555567A patent/JP2005513799A/ja active Pending
- 2002-12-11 WO PCT/EP2002/014096 patent/WO2003054939A1/de active Application Filing
- 2002-12-11 AU AU2002358678A patent/AU2002358678A1/en not_active Abandoned
- 2002-12-11 EP EP02792976A patent/EP1456872A1/de not_active Withdrawn
-
2004
- 2004-06-21 US US10/872,914 patent/US7128786B2/en not_active Expired - Fee Related
Patent Citations (1)
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US6325850B1 (en) * | 1997-10-20 | 2001-12-04 | CENTRE NATIONAL DE LA RECHERCHé SCIENTIFIQUE (CNRS) | Method for producing a gallium nitride epitaxial layer |
Non-Patent Citations (4)
Title |
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CHEN Y ET AL: "DISLOCATION REDUCTION IN GAN FILMS VIA LATERAL OVERGROWTH FROM TRENCHES", APPLIED PHYSICS LETTERS, AMERICAN INSTITUTE OF PHYSICS. NEW YORK, US, vol. 75, no. 14, 4 October 1999 (1999-10-04), pages 2062 - 2064, XP000875610, ISSN: 0003-6951 * |
See also references of EP1456872A1 * |
STRITTMATTER A ET AL: "MASKLESS EPITAXIAL LATERAL OVERGROWTH OF GAN LAYERS ON STRUCTURED SI(111) SUBSTRATES", APPLIED PHYSICS LETTERS, AMERICAN INSTITUTE OF PHYSICS. NEW YORK, US, vol. 78, no. 6, 5 February 2001 (2001-02-05), pages 727 - 729, XP001001018, ISSN: 0003-6951 * |
ZHELEVA T S ET AL: "DISLOCATION DENSITY REDUCTION VIA LATERAL EPITAXY IN SELECTIVELY GROWN GAN STRUCTURES", APPLIED PHYSICS LETTERS, AMERICAN INSTITUTE OF PHYSICS. NEW YORK, US, vol. 71, no. 17, 27 October 1997 (1997-10-27), pages 2472 - 2474, XP000726159, ISSN: 0003-6951 * |
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US7896965B2 (en) * | 2003-07-31 | 2011-03-01 | Osram Opto Semiconductors Gmbh | Method for the production of a plurality of optoelectronic semiconductor chips and optoelectronic semiconductor chip |
US8017416B2 (en) | 2003-07-31 | 2011-09-13 | Osram Opto Semiconductors Gmbh | Method for the production of a plurality of opto-electronic semiconductor chips and opto-electronic semiconductor chip |
US7327036B2 (en) | 2003-12-22 | 2008-02-05 | Interuniversitair Microelektronica Centrum (Imec) | Method for depositing a group III-nitride material on a silicon substrate and device therefor |
EP2171747B1 (de) * | 2007-07-26 | 2016-07-13 | Soitec | Verfahren zur herstellung verbesserter epitaktischer materialien |
WO2010089623A1 (en) * | 2009-02-05 | 2010-08-12 | S.O.I.Tec Silicon On Insulator Technologies | Epitaxial methods and structures for forming semiconductor materials |
EP2314732B2 (de) † | 2009-10-21 | 2016-08-03 | VON ARDENNE GmbH | Verfahren zur Beschichtung eines Substrats mit einer TCO-Schicht und Dünnschichtsolarzelle |
WO2014019752A1 (de) * | 2012-07-31 | 2014-02-06 | Osram Opto Semiconductors Gmbh | Verfahren zur herstellung eines optoelektronischen halbleiterchips und optoelektronischer halbleiterchip |
US9293640B2 (en) | 2012-07-31 | 2016-03-22 | Osram Opto Semiconductors Gmbh | Method for producing an optoelectronic semiconductor chip and optoelectronic semiconductor chip |
EP3696300A1 (de) * | 2019-02-18 | 2020-08-19 | Aixatech GmbH | Verfahren zur herstellung eines verbundmaterialkörpers insbesondere für die verwendung bei der herstellung von elektronischen oder optoelektronischen bauelementen |
Also Published As
Publication number | Publication date |
---|---|
AU2002358678A1 (en) | 2003-07-09 |
JP2005513799A (ja) | 2005-05-12 |
TW561526B (en) | 2003-11-11 |
US20050022725A1 (en) | 2005-02-03 |
US7128786B2 (en) | 2006-10-31 |
EP1456872A1 (de) | 2004-09-15 |
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