Classifications

• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
  • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
  • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
  • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
  • H01L29/42312—Gate electrodes for field effect devices
  • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
  • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
  • H01L29/42324—Gate electrodes for transistors with a floating gate
  • H01L29/42336—Gate electrodes for transistors with a floating gate with one gate at least partly formed in a trench
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
  • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
  • H01L29/66007—Multistep manufacturing processes
  • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
  • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
  • H01L29/66409—Unipolar field-effect transistors
  • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
  • H01L29/66825—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a floating gate
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
  • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
  • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
  • H01L29/76—Unipolar devices, e.g. field effect transistors
  • H01L29/772—Field effect transistors
  • H01L29/78—Field effect transistors with field effect produced by an insulated gate
  • H01L29/788—Field effect transistors with field effect produced by an insulated gate with floating gate
  • H01L29/7887—Programmable transistors with more than two possible different levels of programmation

Definitions

• Flash memory cell with a buried floating gate and method for operating such a flash memory cell.
• the present invention relates to a programmable read-only memory cell with a channel layer arranged between a selection gate and a floating gate according to the preamble of patent claim 1.
• Programmable read-only memory cells based on the principle of a flash memory, in contrast to dynamic memory cells (DRAMs), can hold the stored information even without an external power supply.
• DRAMs dynamic memory cells
• FET field effect transistor
• floating gate floating gate
• flash memories are not used everywhere.
• the significantly slower programming and erasing times of this type of memory compared to the programming and erasing times of volatile memory inhibit the spread of the flash memory cells.
• design problems arise due to the different technology sequence of the two memory cell types.
• US 60 52 311 “Electrically Erasable Programmable Read only Flash Memory” and US 60 11 288 “Flash Memory Cell with vertical Channels and Source / Drain Bus Lines” show flash memory cells with a reduced lateral extent. Both memory cells each have a floating gate formed in a trench between the source and drain regions of the respective memory cell and a selection gate arranged above the floating gate. The channels run below or to the side of the floating gate.
• the object of the invention is to provide a flash memory cell which enables a higher storage density and a faster write and erase operation. Furthermore, it is an object of the invention to provide methods for operating such a flash memory cell.
• the flash memory cell has a channel layer arranged between the floating and the selection gate, which connects the source and the drain electrode to one another.
• the floating gate arranged under the selection gate is at least partially arranged in a trench formed in the substrate. By extending the trench vertically the substrate, the diameter of the floating gate and thus also the effective chip area of the memory cell can be minimized.
• the memory cell for the write / erase and read operation has two separate oxide layers.
• each of the two oxide layers and thus also the write / erase or read operation associated with the respective oxide layer can be optimized separately, and in addition to an improved tunnel oxide layer, shorter write and erase times are also possible.
• the channel layer is formed as an epitaxial layer.
• the channel layer can be made so thin that a maximum control effect of the selection and floating gate is achieved.
• the buried floating gate forms the inner electrode
• a first diffusion region forms the outer electrode
• an insulator layer formed between the floating gate and the first diffusion region forms the dielectric of a trench capacitor extending into the substrate. Since the trench capacitor is designed in accordance with a trench capacitor of a DRAM memory cell, process steps can be saved in the production of combined applications, in which flash and DRAM memory cells are produced together on one semiconductor wafer. In addition, due to the adapted dimensions of both types of memory cell, these combined applications eliminate the design problems that are common with conventional flash memory cells.
• the floating gate forms the inner electrode of a trench capacitor and the charging or discharging of the If the floating gate takes place capacitively via a first diffusion region forming the outer electrode of the trench capacitor, the coupling area between the floating gate and the first diffusion region turns out to be particularly large. As a result, the floating gate can be capacitively charged or discharged particularly effectively.
• the first diffusion regions of adjacent memory cells of a row of the arrangement perpendicular to the word line direction overlap with one another. This creates a second bit line along the row of memory cells, via which each memory cell can be programmed or erased.
• FIG. 1 shows a cross section through a flash memory cell according to the invention with a buried floating gate
• FIG. 3 shows a matrix-type arrangement of flash memory cells according to the invention with second bit lines formed by overlapping the first diffusion regions.
• Figure 1 illustrates the structure of a flash memory cell MC according to the invention.
• the memory cell MC has a floating gate FG buried within a substrate 10 and a field effect transistor formed above the buried floating gate FG.
• the illustrated embodiment of the invention shows a "normally on" memory cell, the Field effect transistor is turned on with an uncharged floating gate FG.
• the floating gate FG is completely embodied in a substrate 10
• Trench TR accommodates and forms the inner electrode of a trench capacitor 20.
• a thin insulator layer 21 is formed within the trench TR.
• the insulator layer 21 completely covers the bottom and the side walls of the trench TR with a uniform layer thickness and extends to the substrate surface.
• the first diffusion region 22 has an n-type doping and is used for capacitive charging or discharging of the floating gate FG.
• the trench TR is completely surrounded by the first diffusion region 22 except for its uppermost region.
• the first diffusion region 22 is trough-shaped within the substrate 10 and extends from a level below the trench TR to a level just below the substrate surface.
• the first diffusion regions 22 of a row of a matrix-like arrangement of flash memory cells MC overlap one another and form a second bit line BL2 for writing to and erasing the flash memory cell MC.
• a second diffusion region 23 is provided outside the first diffusion region 22, which differs from the substrate Surface extends below the first diffusion region 22 and laterally beyond the flash memory cell MC.
• the second diffusion region 23 is shown in FIG. 1 as a trough which contains only a single memory cell MC.
• the second diffusion region 23, as indicated in FIGS. 2A to 2C, also extends to further memory cells MC of a matrix-like arrangement.
• the second diffusion region 23 is completely formed within a third diffusion region 24 which is trough-shaped or flat in the substrate 10.
• the second diffusion region 23 has a p-type doping and the third diffusion region has an n-type doping.
• the special arrangement of the diffusion regions 22, 23, 24 forms a “tripple well” arrangement, the first diffusion region 22 and the third diffusion region 24 being formed on the basis of barrier layers which form at the pn junctions between the diffusion regions 22, 23, 24 are electrically isolated from each other regardless of their respective charge states.
• the n-doped source / drain electrodes S, D with the first and second diffusion regions form a similar arrangement
• the first diffusion region 22 is separated from the source / drain electrodes S, D electrically isolated.
• a thin insulator layer TOX is formed at the level of the substrate surface, which completely covers the floating gate FG.
• the insulator layer TOX forms the tunnel oxide of the flash memory cell MC, through which the floating gate FG, which forms the inner electrode of the trench capacitor 20, is charged or discharged during write or erase operations.
• the thickness of the tunnel oxide layer TOX is selected so that on the one hand the charge on the floating gate FG is sufficiently well insulated from a conductive channel layer EPI of the FET, on the other hand a sufficient chend high tunnel current is guaranteed during write or erase operations of the memory cell MC.
• a field effect transistor is formed on the substrate surface above the buried floating gate FG, the source electrode S of which is arranged on one side and the drain electrode D on the other side of the memory trench TR.
• a channel layer EPI extends between the source and drain electrodes S, D and electrically connects the two electrodes S, D to one another.
• the channel layer EPI preferably covers the entire tunnel layer TOX, the upper partial areas of the insulator layer 21 designed as an ONO layer and partial areas of the substrate surface bordering on the trench TR.
• the channel layer EPI preferably consists of epitaxial silicon and has an n-doping.
• a selection gate CG is formed above the channel layer EPI.
• the selection gate CG and the channel layer EPI are separated from one another by an intermediate gate oxide layer GOX.
• the gate oxide layer GOX which is designed as a thin insulator layer, covers the entire channel layer EPI and partial areas of the two source / drain electrodes S, D.
• a word line WL is formed, which lines the memory cells MC of a column in FIG Matrix-shaped arrangement of memory cells MC interconnects. The word line WL is used for addressing the memory cells MC in the y direction.
• the substrate surface is covered with a further insulator layer 11, in which the entire FET structure is also embedded.
• a first and a second contact 30, 31 are formed in the insulator layer 11, the second contact 31 preferably being connected to a first bit line BL1.
• the first bit line BL1 (not shown) is preferably orthogonal to the word lines WL in FIG. 3 shown matrix-shaped arrangement of memory cells MC and is used for addressing in the x direction.
• FIG. 2A schematically shows the writing process of an analog flash memory cell MC shown in FIG. 1.
• the floating gate FG is charged negatively.
• electrons migrate from the channel layer EPI in the floating gate FG and tunnel through it under a high electric field which is generated by the space formed between the channel layer EPI and the first diffusion region 22 tensile stress Up ro g ram, the tunnel oxide film TOX.
• the source / drain electrodes S, D are preferably placed together at a negative potential - ⁇ pr ogram.
• a positive potential ⁇ 0N to the selection gate CG, a conductive n-channel 32 is generated within the channel layer EPI, as a result of which the channel layer EPI, which forms one of the two tunnel electrodes, also has the source / drain potential - ⁇ pr ⁇ gram. is brought.
• the second tunnel electrode forms the first diffusion region 22.
• the first diffusion region 22 is set to a positive potential + ⁇ pr ogram by a second bit line BL2.
• the second bit line BL2 is formed by the overlap regions 22a of the first diffusion regions 22 of immediately adjacent memory cells MC of a row of the arrangement perpendicular to the word line direction, as shown in FIG. 3.
• the capacitive interaction between the first diffusion region 22 and the floating gate FG in the floating gate FG is so large that such a high positive potential is induced in the floating gate FG that electrons can tunnel through the tunnel oxide layer TOX.
• the tunneling electrons negatively charge the floating gate FG. Since the floating gate FG is electrically rically isolated, the electrons remain within the floating gate FG even after the supply voltage has been switched off.
• the electrical field strengths that occur in the reading mode of the memory cell MC between the channel layer EPI and the floating gate FG are generally not sufficient to do this
• the information unit (bit) written in the memory cell MC is therefore ideally retained indefinitely or until the intended discharge of the memory cell.
• FIG. 2B schematically shows the erase operation of the flash memory cell MC shown in FIG. 2A.
• the trench capacitor 20 is discharged again. Electrons from the floating gate FG tunnel electrons tunneled through the tunnel oxide layer TOX into the channel layer EPI. The electrons are drawn by a high tensile stress U er ase, which is formed between the first diffusion region 22 and the channel layer EPI.
• U er ase the high tensile stress
• the source and drain electrodes S, D are placed together at a positive electrical potential + ⁇ er a se . Analogous to the write operation shown in FIG.
• a conductive n-channel 32 is generated in the erase operation in the channel layer EPI by applying a positive electrical potential ⁇ 0N to the selection gate CG.
• the channel layer EPI which forms a tunnel electrode, also receives the positive electrical potential + ⁇ e rase-
• the diffusion region 22 forming the second tunnel electrode is turned to a negative potential - ⁇ erase via the second bit line BL2, which is shown in FIG placed. Due to the high capacitive interaction between the first diffusion region 22 and the floating gate FG, a sufficiently high negative potential is induced in the upper region of the floating gate FG, so that electrons are transmitted through the
• FIG. 2C schematically shows the read operation of the flash memory cell MC.
• the conductivity of the channel layer EPI between the selection gate and the floating gate CG, FG is evaluated.
• the memory cell MC is assigned one of the two logical data units “1” or “0” depending on the charge state of the floating gate FG and the resulting conductance of the channel 32.
• the channel 32 is blocked when the trench capacitor 20 is charged and opened when the trench capacitor 20 is discharged.
• a read voltage U read is generated between the source and drain electrodes S, D, the source electrode S preferably having a ground potential das gr0 and the drain electrode D having a positive one Potential + ⁇ re ad is placed.
• the selection gate CG and the first diffusion region 22 preferably receive the same electrical potential + ⁇ read as the drain electrode D.
• the channel 32 Due to the influence field, which is generated by the electrical potential + ⁇ read of the selection gate CG, the channel 32 is open with an uncharged floating gate FG. This results in a detectable current flow in the channel layer EPI due to the read voltage U read present between the source and drain electrodes S, D.
• the floating gate FG has a negative charge
• the channel 32 within the channel layer EPI is cut off by the influence field of the negative charge. This reduces the conductivity of the channel layer EPI.
• the state of charge of the memory cell MC is then determined using a significantly reduced or completely prevented current flow between the source and drain electrodes S, D is detected.
• the conductivity of the channel layer EPI which corresponds to the charge state of the memory cell MC, is determined in both cases by a conventional evaluation circuit, which in the simplest case checks whether a current flows between the source and drain electrodes S, D. If this is the case, an information unit "1" or "0" is assigned to the memory cell MC, depending on the memory cell concept. Otherwise, the respective complementary information unit is assigned to the memory cell MC.
• FIG. 3 shows a top view of a matrix-like arrangement of flash memory cells MC.
• the memory cells MC are each arranged in four columns and rows running perpendicular to one another, a trench isolation STI being formed between two immediately adjacent rows of the arrangement, which electrically separates the memory cells MC of a column from one another.
• Each of the memory cells MC of the arrangement is designed analogously to the flash memory cell MC shown in FIG. 1 and in each case has a floating gate FG formed in a trench TR of the substrate 10.
• the floating gate FG is electrically insulated from a first diffusion region 22 by an insulator layer 21.
• a channel layer EPI is arranged above each of the floating gate FG, the floating gate FG being separated from the channel layer EPI by a thin tunnel oxide layer TOX.
• Each channel layer EPI is preferably designed as an epitaxial layer and connects two source / gate electrodes S, G to one another, which are arranged on both sides of the channel layer EPI.
• Each of the source / drain electrodes S, D is in each case assigned to two immediately adjacent memory cells MC of a row of the arrangement that runs perpendicular to the word line direction.
• each memory cell MC has a selection gate CG which is Layer EPI is separated by a thin gate oxide layer GOX.
• the memory cells MC within the matrix-like arrangement are each addressed in the y direction by a word line WL.
• the word line WL contacts all the selection gates CG of the memory cells MC of a column of the arrangement.
• First bit lines BL1 (not shown in FIG. 3) are arranged orthogonally to the word lines WL and in each case contact the source / drain electrodes S, D of the memory cells MC of a row of the arrangement.
• the first diffusion regions 22 of each memory cell MC each have an overlap region 22a with the first diffusion regions 22 of the two immediately adjacent memory cells MC of the respective line of the arrangement which is perpendicular to the word line direction.
• the electrically conductive connection produced in this way forms a second bit line BL2, via which information is written into the memory cell MC or deleted from the memory cell MC.
• the first diffusion region 22 receives a positive or negative electrical potential + ⁇ pr og ram via the second bit line BL2 assigned to the respective memory cell MC,
• each memory cell MC of the matrix arrangement can be addressed individually using the word lines WL and the first bit lines BL1.
• the respective second bit line BL2 is additionally required to carry out the write or erase operation of the respective memory cell MC.

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• Engineering & Computer Science (AREA)
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• Power Engineering (AREA)
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• Ceramic Engineering (AREA)
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• General Physics & Mathematics (AREA)
• Computer Hardware Design (AREA)
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• Semiconductor Memories (AREA)

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• 2001
  • 2001-09-24 DE DE10146978A patent/DE10146978A1/de not_active Withdrawn
• 2002
  • 2002-09-05 KR KR1020047004189A patent/KR100776080B1/ko not_active IP Right Cessation
  • 2002-09-05 EP EP02800068A patent/EP1430540A1/de not_active Withdrawn
  • 2002-09-05 JP JP2003533354A patent/JP4021410B2/ja not_active Expired - Fee Related
  • 2002-09-05 WO PCT/EP2002/009920 patent/WO2003030268A1/de active Application Filing
  • 2002-09-16 TW TW091121157A patent/TW565932B/zh not_active IP Right Cessation
• 2004
  • 2004-03-24 US US10/808,219 patent/US7064377B2/en not_active Expired - Fee Related

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