EP1430540A1

EP1430540A1 - Flash memory cell with entrenched floating gate and method for operating said flash memory cell

Info

Publication number: EP1430540A1
Application number: EP02800068A
Authority: EP
Inventors: Peter Hagemeyer; Wolfram Langheinrich
Original assignee: Infineon Technologies AG
Current assignee: Infineon Technologies AG
Priority date: 2001-09-24
Filing date: 2002-09-05
Publication date: 2004-06-23
Also published as: KR100776080B1; JP4021410B2; US20040228187A1; TW565932B; US7064377B2; KR20040035867A; WO2003030268A1; JP2005505139A; DE10146978A1

Abstract

The invention relates to a programmable read-only memory cell (MC) with a floating gate (FG) arranged in a trench, an epitaxial channel layer (EPI), embodied on the floating gate (FG), which connects a source electrode (S) with a drain electrode (D) and a selection gate (CG) arranged above the channel layer (EPI).

Description

Flash memory cell with a buried floating gate and method for operating such a flash memory cell.

The present invention relates to a programmable read-only memory cell with a channel layer arranged between a selection gate and a floating gate according to the preamble of patent claim 1.

Programmable read-only memory cells based on the principle of a flash memory, in contrast to dynamic memory cells (DRAMs), can hold the stored information even without an external power supply.

Conventional flash memories usually consist of a field effect transistor (FET) with an additional floating gate (floating gate), which is located between the selection gate (control gate) of the FET and a channel layer connecting the two source / drain regions of the FET is trained .

Here, in the programming mode of the memory cell, a specific charge is applied to the floating gate isolated from its surroundings. Then the conductivity of the channel layer and thus the switching state of the FET is determined. Depending on whether the charged floating gate closes or opens the channel of the FET, a distinction is made between "normally on" and "normally off" memory cells. Reading a flash memory cell is particularly easy, since only the conductivity of the channel is checked for this.

Despite these advantages over volatile memories, flash memories are not used everywhere. In particular, the significantly slower programming and erasing times of this type of memory compared to the programming and erasing times of volatile memory inhibit the spread of the flash memory cells. In addition, in the case of combined memories, where in addition to the flash memory cells, for example, DRAM memory cells are also produced on a chip, design problems arise due to the different technology sequence of the two memory cell types.

US 60 52 311 “Electrically Erasable Programmable Read only Flash Memory” and US 60 11 288 “Flash Memory Cell with vertical Channels and Source / Drain Bus Lines” show flash memory cells with a reduced lateral extent. Both memory cells each have a floating gate formed in a trench between the source and drain regions of the respective memory cell and a selection gate arranged above the floating gate. The channels run below or to the side of the floating gate.

The object of the invention is to provide a flash memory cell which enables a higher storage density and a faster write and erase operation. Furthermore, it is an object of the invention to provide methods for operating such a flash memory cell.

The object is achieved by a flash memory cell according to claim 1 and by methods according to claims 10, 11 and 12. Further advantageous embodiments of the invention are specified in the dependent claims.

According to the invention, the flash memory cell has a channel layer arranged between the floating and the selection gate, which connects the source and the drain electrode to one another.

The floating gate arranged under the selection gate is at least partially arranged in a trench formed in the substrate. By extending the trench vertically the substrate, the diameter of the floating gate and thus also the effective chip area of the memory cell can be minimized.

According to a further advantageous embodiment of the invention, the memory cell for the write / erase and read operation has two separate oxide layers. As a result, each of the two oxide layers and thus also the write / erase or read operation associated with the respective oxide layer can be optimized separately, and in addition to an improved tunnel oxide layer, shorter write and erase times are also possible.

According to a further advantageous embodiment of the invention, the channel layer is formed as an epitaxial layer. As a result, the channel layer can be made so thin that a maximum control effect of the selection and floating gate is achieved.

According to a further embodiment of the invention, the buried floating gate forms the inner electrode, a first diffusion region forms the outer electrode and an insulator layer formed between the floating gate and the first diffusion region forms the dielectric of a trench capacitor extending into the substrate. Since the trench capacitor is designed in accordance with a trench capacitor of a DRAM memory cell, process steps can be saved in the production of combined applications, in which flash and DRAM memory cells are produced together on one semiconductor wafer. In addition, due to the adapted dimensions of both types of memory cell, these combined applications eliminate the design problems that are common with conventional flash memory cells.

Due to the structure of the flash memory cell according to the invention, in which the floating gate forms the inner electrode of a trench capacitor and the charging or discharging of the If the floating gate takes place capacitively via a first diffusion region forming the outer electrode of the trench capacitor, the coupling area between the floating gate and the first diffusion region turns out to be particularly large. As a result, the floating gate can be capacitively charged or discharged particularly effectively.

According to a further advantageous embodiment of the invention, the first diffusion regions of adjacent memory cells of a row of the arrangement perpendicular to the word line direction overlap with one another. This creates a second bit line along the row of memory cells, via which each memory cell can be programmed or erased.

Advantageous refinements and developments of the invention are characterized in the subclaims. The problem to be solved with the invention and the invention itself are explained in more detail below with reference to drawings. Show it:

1 shows a cross section through a flash memory cell according to the invention with a buried floating gate,

2A to 2C the operation of the flash memory cell according to the invention from Figure 1 in a write, an erase and a read operation, and

3 shows a matrix-type arrangement of flash memory cells according to the invention with second bit lines formed by overlapping the first diffusion regions.

Figure 1 illustrates the structure of a flash memory cell MC according to the invention. The memory cell MC has a floating gate FG buried within a substrate 10 and a field effect transistor formed above the buried floating gate FG. The illustrated embodiment of the invention shows a "normally on" memory cell, the Field effect transistor is turned on with an uncharged floating gate FG.

In order to reduce the chip area, the floating gate FG is completely embodied in a substrate 10

Trench TR accommodates and forms the inner electrode of a trench capacitor 20.

A thin insulator layer 21 is formed within the trench TR. The insulator layer 21 completely covers the bottom and the side walls of the trench TR with a uniform layer thickness and extends to the substrate surface.The insulator layer 21, which is preferably designed as an ONO layer (oxide-nitride-oxide), serves as the dielectric of the trench capacitor 20 and isolates the floating gate FG from a first diffusion region 22 forming the outer electrode of the trench capacitor 20.

In the exemplary embodiment shown, the first diffusion region 22 has an n-type doping and is used for capacitive charging or discharging of the floating gate FG. In order to achieve the greatest possible coupling capacity between the floating gate FG and the first diffusion region 22, the trench TR is completely surrounded by the first diffusion region 22 except for its uppermost region. The first diffusion region 22 is trough-shaped within the substrate 10 and extends from a level below the trench TR to a level just below the substrate surface.

As can be seen from FIG. 3, the first diffusion regions 22 of a row of a matrix-like arrangement of flash memory cells MC overlap one another and form a second bit line BL2 for writing to and erasing the flash memory cell MC.

A second diffusion region 23 is provided outside the first diffusion region 22, which differs from the substrate Surface extends below the first diffusion region 22 and laterally beyond the flash memory cell MC. The second diffusion region 23 is shown in FIG. 1 as a trough which contains only a single memory cell MC. Preferably, the second diffusion region 23, as indicated in FIGS. 2A to 2C, also extends to further memory cells MC of a matrix-like arrangement. The second diffusion region 23 is completely formed within a third diffusion region 24 which is trough-shaped or flat in the substrate 10. The second diffusion region 23 has a p-type doping and the third diffusion region has an n-type doping. The special arrangement of the diffusion regions 22, 23, 24 forms a “tripple well” arrangement, the first diffusion region 22 and the third diffusion region 24 being formed on the basis of barrier layers which form at the pn junctions between the diffusion regions 22, 23, 24 are electrically isolated from each other regardless of their respective charge states. The n-doped source / drain electrodes S, D with the first and second diffusion regions form a similar arrangement

22, 23. Here too, due to barrier layers that form at the pn junctions between the diffusion regions 22, 23 and the source / drain electrodes S, D, the first diffusion region 22 is separated from the source / drain electrodes S, D electrically isolated.

Above the floating gate FG, a thin insulator layer TOX is formed at the level of the substrate surface, which completely covers the floating gate FG. The insulator layer TOX forms the tunnel oxide of the flash memory cell MC, through which the floating gate FG, which forms the inner electrode of the trench capacitor 20, is charged or discharged during write or erase operations. The thickness of the tunnel oxide layer TOX is selected so that on the one hand the charge on the floating gate FG is sufficiently well insulated from a conductive channel layer EPI of the FET, on the other hand a sufficient chend high tunnel current is guaranteed during write or erase operations of the memory cell MC.

A field effect transistor is formed on the substrate surface above the buried floating gate FG, the source electrode S of which is arranged on one side and the drain electrode D on the other side of the memory trench TR. A channel layer EPI extends between the source and drain electrodes S, D and electrically connects the two electrodes S, D to one another. The channel layer EPI preferably covers the entire tunnel layer TOX, the upper partial areas of the insulator layer 21 designed as an ONO layer and partial areas of the substrate surface bordering on the trench TR. The channel layer EPI preferably consists of epitaxial silicon and has an n-doping.

A selection gate CG is formed above the channel layer EPI. The selection gate CG and the channel layer EPI are separated from one another by an intermediate gate oxide layer GOX. The gate oxide layer GOX, which is designed as a thin insulator layer, covers the entire channel layer EPI and partial areas of the two source / drain electrodes S, D. Above the selection gate CG, a word line WL is formed, which lines the memory cells MC of a column in FIG Matrix-shaped arrangement of memory cells MC interconnects. The word line WL is used for addressing the memory cells MC in the y direction.

The substrate surface is covered with a further insulator layer 11, in which the entire FET structure is also embedded. For contacting the source / drain electrodes S, D, a first and a second contact 30, 31 are formed in the insulator layer 11, the second contact 31 preferably being connected to a first bit line BL1. The first bit line BL1 (not shown) is preferably orthogonal to the word lines WL in FIG. 3 shown matrix-shaped arrangement of memory cells MC and is used for addressing in the x direction.

FIG. 2A schematically shows the writing process of an analog flash memory cell MC shown in FIG. 1. During a write operation, the floating gate FG is charged negatively. For this purpose, electrons migrate from the channel layer EPI in the floating gate FG and tunnel through it under a high electric field which is generated by the space formed between the channel layer EPI and the first diffusion region 22 tensile stress Up _ro g _ram, the tunnel oxide film TOX.

To generate the necessary tensile stress U _prθ g _ra m, the source / drain electrodes S, D are preferably placed together at a negative potential -Φ _pr ogram. By applying a positive potential Φ _0N to the selection _gate CG, a conductive n-channel 32 is generated within the channel layer EPI, as a result of which the channel layer EPI, which forms one of the two tunnel electrodes, also has the source / drain potential -Φ _prθ gram. is brought. The second tunnel electrode forms the first diffusion region 22. To generate the tensile stress U _program , the first diffusion region 22 is set to a positive potential + Φ _pr ogram by a second bit line BL2. The second bit line BL2 is formed by the overlap regions 22a of the first diffusion regions 22 of immediately adjacent memory cells MC of a row of the arrangement perpendicular to the word line direction, as shown in FIG. 3.

Due to the large coupling area of the trench capacitor, the capacitive interaction between the first diffusion region 22 and the floating gate FG in the floating gate FG is so large that such a high positive potential is induced in the floating gate FG that electrons can tunnel through the tunnel oxide layer TOX.

The tunneling electrons negatively charge the floating gate FG. Since the floating gate FG is electrically rically isolated, the electrons remain within the floating gate FG even after the supply voltage has been switched off. The electrical field strengths that occur in the reading mode of the memory cell MC between the channel layer EPI and the floating gate FG are generally not sufficient to do this

Unload floating gate FG again via the tunnel oxide layer TOX.

The information unit (bit) written in the memory cell MC is therefore ideally retained indefinitely or until the intended discharge of the memory cell.

FIG. 2B schematically shows the erase operation of the flash memory cell MC shown in FIG. 2A. To erase the information unit of the memory cell, the trench capacitor 20 is discharged again. Electrons from the floating gate FG tunnel electrons tunneled through the tunnel oxide layer TOX into the channel layer EPI. The electrons are drawn by a high tensile stress U _er ase, which is formed between the first diffusion region 22 and the channel layer EPI. For this purpose, the source and drain electrodes S, D are placed together at a positive electrical potential + Φ _er a _se . Analogous to the write operation shown in FIG. 1A, a conductive n-channel 32 is generated in the erase operation in the channel _layer EPI by applying a positive electrical potential Φ _0N to the selection _gate CG. As a result, the channel layer EPI, which forms a tunnel electrode, also receives the positive electrical potential + Φ _e rase- The diffusion region 22 forming the second tunnel electrode, on the other hand, is turned to a negative potential -Φ _erase via the second bit line BL2, which is shown in FIG placed. Due to the high capacitive interaction between the first diffusion region 22 and the floating gate FG, a sufficiently high negative potential is induced in the upper region of the floating gate FG, so that electrons are transmitted through the

Tunnel the tunnel oxide layer EPI. Hereby the floating Gate FG completely discharged again and the memory cell MC returned to the "Normally on" state.

FIG. 2C schematically shows the read operation of the flash memory cell MC. When reading the information stored in the memory cell MC, the conductivity of the channel layer EPI between the selection gate and the floating gate CG, FG is evaluated. The memory cell MC is assigned one of the two logical data units “1” or “0” depending on the charge state of the floating gate FG and the resulting conductance of the channel 32. In the "normally on" memory cell MC shown here, the channel 32 is blocked when the trench capacitor 20 is charged and opened when the trench capacitor 20 is discharged.

To read the flash memory cell MC, a _read voltage U _{read is} generated between the source and drain electrodes S, D, the source electrode S preferably _{having a} ground potential _{das gr0} and the drain electrode D having a positive one Potential + Φ _re ad is placed. The selection gate CG and the first diffusion region 22 preferably receive the same electrical potential + Φ _read as the drain electrode D.

Due to the influence field, which is generated by the electrical potential + Φ _{read of} the selection gate CG, the channel 32 is open with an uncharged floating gate FG. This results in a detectable current flow in the channel layer EPI due to the _read voltage U _{read present} between the source and drain electrodes S, D.

If, on the other hand, the floating gate FG has a negative charge, the channel 32 within the channel layer EPI is cut off by the influence field of the negative charge. This reduces the conductivity of the channel layer EPI. The state of charge of the memory cell MC is then determined using a significantly reduced or completely prevented current flow between the source and drain electrodes S, D is detected.

The conductivity of the channel layer EPI, which corresponds to the charge state of the memory cell MC, is determined in both cases by a conventional evaluation circuit, which in the simplest case checks whether a current flows between the source and drain electrodes S, D. If this is the case, an information unit "1" or "0" is assigned to the memory cell MC, depending on the memory cell concept. Otherwise, the respective complementary information unit is assigned to the memory cell MC.

FIG. 3 shows a top view of a matrix-like arrangement of flash memory cells MC. The memory cells MC are each arranged in four columns and rows running perpendicular to one another, a trench isolation STI being formed between two immediately adjacent rows of the arrangement, which electrically separates the memory cells MC of a column from one another. Each of the memory cells MC of the arrangement is designed analogously to the flash memory cell MC shown in FIG. 1 and in each case has a floating gate FG formed in a trench TR of the substrate 10. The floating gate FG is electrically insulated from a first diffusion region 22 by an insulator layer 21. A channel layer EPI is arranged above each of the floating gate FG, the floating gate FG being separated from the channel layer EPI by a thin tunnel oxide layer TOX. Each channel layer EPI is preferably designed as an epitaxial layer and connects two source / gate electrodes S, G to one another, which are arranged on both sides of the channel layer EPI. Each of the source / drain electrodes S, D is in each case assigned to two immediately adjacent memory cells MC of a row of the arrangement that runs perpendicular to the word line direction. Above the channel layer EPI, each memory cell MC has a selection gate CG which is Layer EPI is separated by a thin gate oxide layer GOX.

The memory cells MC within the matrix-like arrangement are each addressed in the y direction by a word line WL. The word line WL contacts all the selection gates CG of the memory cells MC of a column of the arrangement.

First bit lines BL1 (not shown in FIG. 3) are arranged orthogonally to the word lines WL and in each case contact the source / drain electrodes S, D of the memory cells MC of a row of the arrangement.

The first diffusion regions 22 of each memory cell MC each have an overlap region 22a with the first diffusion regions 22 of the two immediately adjacent memory cells MC of the respective line of the arrangement which is perpendicular to the word line direction. The electrically conductive connection produced in this way forms a second bit line BL2, via which information is written into the memory cell MC or deleted from the memory cell MC. For this purpose, as can be seen from the description of FIGS. 2A and 2B, the first diffusion region 22 receives a positive or negative electrical potential + Φ _pr og _ram via the second bit line BL2 assigned to the respective memory cell MC,

—Φerase •

To carry out a read operation, each memory cell MC of the matrix arrangement can be addressed individually using the word lines WL and the first bit lines BL1. The respective second bit line BL2 is additionally required to carry out the write or erase operation of the respective memory cell MC.

The features of the invention disclosed in the preceding description, the claims and the drawings can be used both individually and in any combination for the realization. the invention in its various embodiments.

Claims

claims

1. Programmable read-only memory cell (MC) with a source and a drain electrode (S, D), with a channel layer (EPI) formed between the source and drain electrodes (S, D), with one of the channel layer ( EPI) separate floating gate (FG) and a selection gate (CG) separate from the channel layer (EPI), characterized in that the selection gate (CG) and the floating gate (FG) are arranged essentially opposite one another on both sides of the channel layer (EPI), and that an insulator layer (TOX, GOX) is arranged between the floating gate (FG) and the channel layer (EPI) and between the selection gate (CG) and the channel layer (EPI).

2. Programmable read-only memory cell (MC) according to claim

1, characterized in that the floating gate (FG) is at least partially arranged in a trench (TR) of a substrate (10), that the trench (TR) is formed between the source and drain electrodes (S, D), and that the floating gate (FG) is electrically insulated from the substrate (10).

3. Programmable read-only memory cell (MC) according to claim 2, so that the floating gate (FG) is isolated from the substrate (10) by a thin insulator layer (21), which is preferably designed as an oxide-nitride-oxide layer.

4. Programmable read-only memory cell (MC) according to one of claims 2 or 3, characterized in that a trench capacitor (20) is formed in the substrate (10), the inner electrode of which by the floating gate (FG) and whose outer electrode is formed by a first diffusion region (22).

5. Programmable read-only memory cell (MC) according to claim 4, characterized in that the first diffusion region (22) is formed within a second diffusion region (23) and the second diffusion region is completely formed within a third diffusion region (24), the second diffusion region (23 ) has a doping that is complementary to the first diffusion region (22) and the third diffusion region (24).

6. Programmable read-only memory cell (MC) according to one of claims 4 or 5, characterized in that the first diffusion area (22) of the read-only memory cell (MC) with the first diffusion areas (22) of the two directly adjacent to the word line direction immediately adjacent read-only memory cells (MC) of a matrix-like arrangement of read-only memory cells (MC) has an overlap area (22a), and that the overlap area (22a) forms an electrically conductive connection between the first diffusion areas (22) of the read-only memory cells (MC) in a row.

7. Programmable read-only memory cell (MC) according to any one of claims 1 to 6, that the channel layer (EPI) is designed as an epitaxial layer.

8. Programmable read-only memory cell (MC) according to one of claims 1 to 7, characterized in that the channel layer (EPI) has an n-doping.

9. Programmable read-only memory cell (MC) according to one of claims 1 to 8, d a d u r c h g e k e n n z e i c h n e t that the source and the drain electrode (S, D) are at least partially formed on the surface of the substrate (10).

10. A method for describing a programmable read-only memory cell (MC) according to one of claims 4 to 9, characterized in that a channel (32) by applying an electrical voltage (U _ON ) between the selection gate (CG) and the source and / or drain -Electrode (S, D) in the channel layer (EPI) is opened, and that a further electrical voltage (U _progra m) is applied between the first diffusion region (22) and the channel layer (EPI), the source and / or the drain electrode (S, D) to a negative electrical potential (-Φp _ro gram) - the first diffusion region (22) to a positive electrical potential (+ Φ _pr ogram) and the selection gate (CG) to a positive electrical potential ( + Φ _0N ).

11. A method for deleting information of a programmable read-only memory cell (MC) according to one of claims 4 to 10, characterized in that a channel (32) by applying an electrical voltage (U _0N ) between the selection _gate (CG) and the source and / or drain electrode (S, D) is opened, and that a further electrical voltage (U _erase ) is applied between the first diffusion region (22) and the channel layer (EPI), the source and / or the drain electrode ( S, D) to a positive electrical potential (+ Φ _e rase) / the first diffusion region (22) to a negative electrical potential (-Φ _era se) and the selection gate (CG) to a positive electrical potential (+ ΦON) ,

12. A method for reading information from a programmable read-only memory cell (MC) according to one of claims 4 to 11, characterized in that an electrical voltage (U _rea d) is applied between the source and drain electrodes (S, D) that the source electrode (S) is connected to ground potential (Φground), the drain electrode (D), the selection gate (CG) and the first diffusion region (22) to a positive electrical potential (+ Φ _rea d) that the Conductivity of the channel layer (EPI) dependent on the charge state of the read-only memory cell (MC) is determined with the aid of an evaluation circuit, and that the read-only memory cell (MC) is assigned information which depends on the conductivity of the channel (32).