EP1240670A1

EP1240670A1 - Non-volatile nor semiconductor memory device and method for the programming thereof

Info

Publication number: EP1240670A1
Application number: EP99968315A
Authority: EP
Inventors: Elard Stein Von Kamienski; Peter Wawer; Christoph Ludwig; Christoph Kutter; Georg Georgakos; Andreas Liebelt; Jakob Kriz; Kai Huckels
Original assignee: Infineon Technologies AG
Current assignee: Infineon Technologies AG
Priority date: 1999-12-20
Filing date: 1999-12-20
Publication date: 2002-09-18
Also published as: WO2001047019A1; US6654281B2; US20030007386A1

Abstract

The invention relates to a non-volatile NOR semiconductor memory device and method for the programming thereof, whereby a number of single transistor memory cells (SZ), arranged in the form of a matrix, may be controlled by either word lines (WL) or by bit lines (BL). Each single transistor memory cell (SZ), thus possesses both a source line (S1, S2) and a drain line (D1, D2), by means of which a selective control of the respective source and drain regions (D, S) is achieved. The leak current can thus be optimally reduced in the semiconductor memory device with minimal space requirement.

Description

description

Nonvolatile NOR semiconductor memory device and method for programming it

The present invention relates to a nichtflüchti ^¬ ge NOR semiconductor memory device and a method for programming and more particularly to a Flash EEPROM memory having a novel NOR gate transistor field Architecture, customers.

Most computer units or computers currently use magnetic disk drives for storing larger amounts of data. However, such disk drives or mechanical storage devices require a relatively large space and have a large number of moving parts. As a result, they are prone to malfunction and consume considerable amounts of electricity. In addition, the future computer units or computers as well as other digital devices such as digital cameras or palm devices or PTAs will become smaller and smaller, which is why conventional mechanical storage devices are unsuitable.

As an alternative to such conventional mechanical memory devices, non-volatile semiconductor memory devices, such as are known, for example, as flash memories, EEPROM, EPROM and the like, have recently become increasingly popular. The so-called NAND and NOR semiconductor memory devices are known as the most important representatives of such electrically erasable and electrically programmable memory devices. In both semiconductor memory devices, the memory cells have so-called single-transistor memory cells, a drain region and a source region usually being formed in a semiconductor substrate, and an insulated charge-storing layer and an insulated control layer arranged above it being located above the channel section located therebetween. To the Programming such a single transistor cell, relatively high voltages are applied to the control layer and the drain region, while the source region is usually grounded. Under such circumstances, charge carriers are introduced into the charge storage layer by means of channel injection, injection of hot charge carriers and / or Fowler-Nordheim tunnels. The charge carriers remain in the charge storage layer and permanently change the switching behavior of the respective field effect transistor.

While in the NAND semiconductor memory devices described above, a multiplicity of single-transistor memory cells are connected to one another in series and are controlled via a common selection gate, the respective single-transistor memory cells in NOR semiconductor memory devices are organized in parallel or in an atrix shape. whereby each memory cell can be selected individually.

The present invention relates exclusively to such NOR semiconductor memory devices.

FIG. 1 shows a simplified representation of an equivalent circuit diagram of a nonvolatile NOR semiconductor memory device according to the prior art. According to FIG. 1, a large number of single-transistor memory cells SZ are arranged in a matrix, ie in rows and columns. As has already been described above, each single-transistor memory cell SZ consists of spaced-apart drain and source regions D and S, which are formed in a semiconductor substrate. A control layer CG is in each case connected line by line to an associated word line WL1, WL2 and WL3. In contrast, the drain regions D of the respective one-transistor memory cells SZ are connected to a respective bit line BL1 and BL2 in columns. The source regions S of the non-volatile NOR semiconductor memory device are all connected to ground or are all connected to one another, which is why Such a NOR semiconductor memory device is referred to as a memory device with “common source * architecture”.

However, the disadvantage of such conventional semiconductor memory devices is the relatively high power consumption during a programming process. This current consumption or current consumption is essentially determined from the sum of a programming current of the selected (i.e. to be programmed) memory cells and from a leakage current from non-selected memory cells. The leakage current of the non-selected memory cells is far below a respective leakage or programming current of a selected memory cell for each individual memory cell, but the sum of the leakage currents of all unselected memory cells is, in particular in the case of large arrays or memory cell fields, of a similar magnitude to the programming current for the selected memory cell.

The object of the invention is therefore to create a non-volatile NOR semiconductor memory device and a method for programming it, in which a leakage current in the non-selected memory cells and thus a total current consumption is reduced.

According to the invention, this object is achieved with regard to the semiconductor memory device by the features of patent claim 1 and with regard to the method by the measures of patent claims 9, 10 and 11.

In particular through the use of selectively controllable source lines and drain lines for respective bit lines, a selective control of the respective source regions is made possible, whereby the power consumption during programming or the occurrence of leakage currents can be significantly reduced. The respective source and drain lines are preferably meandering, zigzag or wave-shaped _/ which results in a substantial saving of space and enables highly integrated semiconductor memory devices.

A further reduction in the space requirement results from the formation of the source and drain lines in different electrically conductive layers.

When programming the non-volatile NOR

Semiconductor memory devices are preferably applied to predetermined voltages both on the source line and on the drain line. As an alternative to this, however, the programming voltages can also be applied only to the drain lines or source lines, while their associated source lines or drain lines are floating or have a floating voltage.

Advantageous embodiments of the invention are characterized in the subclaims.

The invention is described below using exemplary embodiments with reference to the drawing.

Show it:

1 shows a simplified representation of an equivalent circuit diagram of a non-volatile NOR semiconductor memory device according to the prior art;

FIG. 2 shows a simplified representation of an equivalent circuit diagram of the non-volatile NOR semiconductor storage device according to the invention;

FIG. 3 shows a simplified illustration of a layout of the NOR semiconductor memory device according to the invention in accordance with a first exemplary embodiment; FIG. 4 shows a simplified sectional view along a section A / A ^λ in FIG. 3;

FIG. 5 shows a simplified sectional view along a section B / B ^λ in FIG. 3;

FIG. 6 shows a simplified illustration of a layout of the NOR semiconductor memory device according to the invention in accordance with a second exemplary embodiment; and

FIG. 7 shows a simplified sectional view along a section C / C in FIG. 6.

FIG. 2 shows a simplified representation of an equivalent circuit diagram of a non-volatile NOR semiconductor memory device according to the present invention. The same reference numerals designate the same or similar elements, which is why their description is omitted below.

The non-volatile NOR semiconductor memory device according to the invention in turn consists of a large number of single-transistor memory cells SZ arranged in a matrix in a semiconductor substrate, which are controlled via a large number of word lines WL1, WL2 and WL3 and a large number of bit lines BL1 and BL2. In contrast to conventional NOR semiconductor memory device having "common source ^* architecture can use the one-transistor memory cells SZ according to the present invention are a Sour- celeitung Sl, S2 and so on and driven via a drain line Dl, D2, etc. selectively. This selective control is carried out, for example, via a respective bit line controller BLC, which realizes, so to speak, the common bit lines BL1 and BL2 etc. Due to the selective control of the respective source regions S of respective single-transistor memory cells SZ, the non-inventive volatile NOR semiconductor memory device preferably referred to as SNOR flash (selective NOR).

To program the one-transistor memory cell SZ, a voltage of -9 V to the control layer CG is for example applied through the word line WLl, while the dazugehö ^¬ membered source and drain regions S and D via the associated source-drain lines Sl and Dl to a potential of for example +6 V. In this way, a "1 ^* is written to the one-transistor memory cell SZ or loaded the charge storing layer positively. Since a lateral field, in particular between the source region S and the drain region D, is greatly reduced due to the equally high voltages (+6 V), there is a leak current which is substantially lower than in the prior art, particularly in the non-selected one-transistor memory cells of the word lines WL2 and WL3 to observe. According to FIG. 2, the unselected word lines WL2, WL3, ... have a voltage of 0V. However, this voltage of the unselected word lines WL2, WL3,... Is preferably at a voltage which corresponds to the arithmetic mean (for example 3 V) of a voltage of the selected bit line BL1 and a voltage of the non-selected bit line, which results in a leakage current can further reduce.

In particular, a gate-induced drain leakage current (GIDL, gate induced drain leakage) is to be considered as leakage current, which in the case of the SNOR architecture shown in FIG. 2 is significantly reduced compared to the conventional NOR architecture with a common source line (common source) according to FIG. 1 is. In Figure 1 namely because of the common potential in the source regions S strong lateral fields between the source and drain are generated in the non-selected memory cells (WL2, WL3), which are several orders of magnitude above that in the SNOR architecture according to the invention. The current consumption, especially during a programming process (writing, erasing), is thus sentlich reduced since a 7Anteil particular gateindu ^¬ ed drain leakage currents in the unselected memory cells is substantially reduced. A construction of very large arrays or memory cell arrays can therefore be implemented in a simple manner with the SNOR architecture according to the invention.

FIG. 3 shows a simplified illustration of a layout of the NOR semiconductor memory device according to the invention in accordance with a first exemplary embodiment. The same reference symbols again designate the same or similar elements, which is why their detailed description is omitted below.

According to FIG. 3, the single-transistor memory cells SZ are formed in active areas AA of a semiconductor substrate.

Such active areas AA are preferably formed by means of diffusion or implantation and, according to FIG. 3, have an essentially strip-like structure. The plurality of stripe-shaped active areas AA arranged in columns are overlaid row by row by likewise stack-shaped layer stacks, an uppermost layer representing the control layer CG of the single-transistor memory cells SZ. Each crossing point of such a stripe-shaped active region AA with a stripe-shaped control layer CG thus represents a field-effect transistor or a single-transistor memory cell SZ. Contacts Kl are formed for contacting respective drain regions D and source regions S, which are arranged essentially in a straight line, however, they can also extend into an adjacent isolation area 2 (STI, shallow trench isolation). The source lines S1, S2 etc. as well as the drain lines D1, D2 etc. are now located in a further layer, which preferably represents a first metallization layer. The drain lines D1, D2 are in this case connected to the associated drain regions D of the active region via corresponding contacts Kl AA in connection, the source lines S1, S2 in the same way via corresponding contact Kl are connected to the associated source areas S.

According to FIG. 3, the source regions S of a single-transistor memory cell SZ are each connected to the source regions S of an adjacent single-transistor memory cell SZ. In the same way, the drain regions D of adjacent single-transistor memory cells are connected directly to one another, which results in a particularly space-saving design. To further reduce the area of the single-transistor memory cell SZ, the source lines S1, S2 and the drain lines D1, D2 are preferably designed in a wave shape. However, they can also be meandering or zigzag-shaped, provided that this saves space and the respective contacts K1 can be switched on.

To further reduce the area requirement, the source and drain lines S1, S2, D1 and D2 are arranged essentially parallel to one another. In this way, a highly integrable memory device is obtained which has an optimized cell width of only B = 4F.

FIG. 4 shows a simplified sectional view of the single-transistor memory cell SZ along a section A / A ^x in FIG. 3. Accordingly, the single-transistor memory cell SZ consists of a non-volatile semiconductor memory cell which is formed in a substrate 1 or an active region AA of the substrate 1 , The drain region D is spaced from the source region S by a channel region, on the surface of which a first insulating layer II, a charge-storing layer FG (floating gate), a second insulating layer 12 and the final control layer CG (control gate) are formed. The drain region D and the source region S are contacted via contacts K1. A further insulating layer or passivation layer 3 isolates each layer stack or each single-transistor memory cell SZ from its neighboring one. FIG. 5 shows a further simplified sectional view of the NOR semiconductor memory device according to the invention along a section B / B ^Λ in FIG. shallow trench isolation) isolated from each other. The contacts can be placed slightly offset on the active areas AA and partially extend into the trench insulation 2. The source and drain lines S1, S2, D1 and D2 are formed in accordance with FIG. 5 in a first metallization level or electrically conductive layer 4 and are each at the same level. It is essential for the present invention that only the drain lines D1 and D2 are connected to the associated contacts K, while the associated source lines S1 and S2, spaced from the further insulating layer 3, have no contact with the active area AA and are laterally offset are. Accordingly, the source and drain lines are preferably formed in the common electrically conductive layer 4, which can also represent, for example, a highly doped polysilicon layer. A significant advantage when using such electrically conductive layers, for example in comparison to conventional buried layers in the semiconductor substrate 1, is that the resistance is significantly reduced, which in particular improves the access times and the access speed to the semiconductor memory device.

According to FIGS. 3 to 5, the source and drain lines S1 to D2 are thus formed in the same electrically conductive layer 4. However, the source and drain lines S1 to D2 can also be implemented in different layers, which is described below with reference to FIG. 6.

FIG. 6 shows a simplified illustration of a layout of the NOR semiconductor memory device according to a second embodiment. κ> ÜJ M IV) h- ¹ t— ^■

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P P- a. P> P rt <Φ P P P Φ 1 P- Φ Φ iQ

1 α φ 1 φ "p- P & 1 P Ω 1 P P P-

XP 1 1 α tr P φ

cn C rt P rt rt iQ CΛ P α P \ S __ _^ CΛ>

Φ Φ p- PJ Φ P- Φ Ω P- P- P- tr ¹ Φ P- ^ Φ a. Ω P- iQ P tr Ω Φ Ω O: P- Φ φ P X-> rt err Φ P tr tr cn cn P rt Φ

P rt P- P P CΛ fu: rt M et Ω φ cn α

Q. P- CΛ P Ό P P P P tr Ω cn P-

P- cn P- ^ Q CΛ φ wa Pi a N tr rt Ω P φ O PJ φ Φ Ό P- rt u3 P- i> ⁾ P- P>: tr Φ tr PPP φ Ω φ a P Ω P Φ P -

P ⁾⁾ P P- tr P α z P ^J P tr? a

P P a z Ω Φ cn P φ Φ rt Φ tr

Ω Φ Hl ^ φ tr PO tr P CΛ PPP ⁾ Φ tr P- cn P Φ Φ P Φ iQ Φ P- _^ ~. If he Φ α P P- cn P P- φ N • _^ Hl Ω

P- φ Φ r Φ N P Φ Ω Z rt P • tr

P an Φ P φ PP tr P tr ¹ tz PP

Ω P P- P P P p- & Φ • o Φ P- tr Φ tr φ <Ω P- CL Ω φ er Q. Φ

O: a P o Φ tr P Φ φ tr P Φ HPP er tr (D: P ⁾ PP rt 3 tr PPPN Φ

Φ CΛ P P N P Hl Φ <! <P cn a Ω P- P

P Ω Ϊ cn P Σ. P PJ P O Φ P- α a tr Φ Φ

Φ tr rt iQ iQ P- Q Ö>. P P Ω P> Φ P P

P P- Φ cn φ Φ rt cn tr tr P cn rt

Ω P tr ≤ P CΛ rt Φ rt O P- Φ d w tr P P- Φ N <P- Φ CΛ Hi P X Ω a P er rt P-. he P- Φ tr cn P- tr o

Φ Φ P CΛ N φ Φ Φ p: he α tr iQ

P P r | Φ φ tu z P- P P Ω N cn Φ O

Φ 3 rt. 3 cn et tr s: Ω P- P

P 2. Hi • P- φ et rt • tr P P-

P- P ⁾ P 3 ^

^ <tr P ⁾ Z P- P- φ N 3

P) φ Go σ * U o P L_l- P Φ ^ Q α Ω o P-

P rt P- α f P Φ tr P Φ P- tr CΛ a Φ cn N φ Φ P P> P> P φ rt O rt P

• <! P cn P- O a Φ - 't <

Φ P- w • Ω X-> Ω P X CD: Φ er tu φ P Φ tr φ tr • PJ & <. α φ P

P- • Pi P r rt <! N Φ P- a Hi

3 P- CΛ P- P ≤ P o tr PJ P iQ J

^ u φ P rt φ P φ P- P tr P P CΛ tr

Φ o tr Φ i P- Ω φ x- ^> P- P o P rt X-> PPP CΛ Φ rt tr ^ P- a «Ω P Φ

• <P O P φ rt rt iQ P P s: cn PJ iQ P P P Φ Φ Φ Φ Ω

Φ P- P P 3 φ cn P P P φ Φ er

PP ^J P- Ω P- PP ⁾ tr CΛ rt P 1 P ⁾

P- Φ cn Φ rt P 1 Ό CΛ • ü Λ φ N rt N 1 P P> CΛ Φ Ω Φ P P-

P P- z 5. P P- P O P- tr P> Φ. > P

P φ l_J Φ P P- Ω Hl Φ Ω P P CΛ P- P

, P- φ P- P Ω tr P- tr φ Hi rt a Φ

O: cn rt rt 0- tr rt tr Ω Φ P- φ 1 P

P Ω Φ o φ rt Pi Φ tr P cr P ^

P tr P Ω P σ Hi - ^> 1 Φ Φ 1 P- Φ P-

Φ P- Φ tr PP ^J p: P P- φ ^ 3

P o PSP ⁾ p: Ω Φ a ω ω tr Φ P- Ω tr P- 1 φ O Φ Z

1 φ 1 P tr rt P 1 P φ

1 1 1 P- 1 a

Claims

claims

1. Non-volatile NOR semiconductor memory device with a plurality of single-transistor memory cells (SZ) formed in a semiconductor substrate (1) and consisting of drain regions (D) and source regions (S) spaced apart from one another, a first insulating layer (II) and a charge-storing one Layer (FG), a second insulating layer (12), and a control layer (CG); a plurality of word lines (WL1 to WL3) for driving the single transistor memory cells (SZ) line by line; and a plurality of bit lines (BLl, BL2) for driving the single transistor memory cell (SZ) in columns, characterized in that the word lines (WL1 to WL3) are essentially formed by the control layer (CG) and the bit lines (BLl, BL2 ) one source line each (Sl,

S2) and a drain line (Dl, D2), which enable selective control of the respective drain and source regions (D, S) of the single-transistor memory cell (SZ).

2. Non-volatile NOR semiconductor memory device according to claim 1, so that the respective source and drain lines (Sl, S2, Dl, D2) are meandering, zigzag or wave-shaped.

3. Non-volatile NOR semiconductor memory device according to claim 1 or 2, characterized in that the respective source and drain lines (Sl, S2, Dl, D2) are formed in a common electrically conductive layer (4).

4. Non-volatile NOR semiconductor memory device according to claim 1 or 2, so that the respective source and drain lines (Sl, S2, Dl, D2) are formed in different electrically conductive layers (4, 6).

5. Non-volatile NOR semiconductor memory device according to claim 3, so that the respective source and drain lines (Sl, S2, Dl, D2) are arranged essentially parallel to one another.

6. Non-volatile NOR semiconductor memory device according to claim 4, so that the respective source and drain lines (Sl, S2, Dl, D2) are arranged substantially overlapping.

7. Non-volatile NOR semiconductor memory device according to one of the claims 1 to 6, characterized by drain / source contacts (Kl, K2) which are used to establish a connection between the drain / source lines (Dl, D2, Sl, S2) with the drain / Source areas (D, S) of the respective single-transistor memory cells (SZ) are arranged essentially in a straight line.

8. Non-volatile NOR semiconductor memory device according to one of claims 1 to 7, d a d u r c h g e k e n n z e i c h n e t that the respective source and drain lines (Sl, S2, Dl, D2) are formed in one and / or more metallization layers.

9. A method for programming a memory cell in a non-volatile NOR semiconductor memory device according to one of claims 1 to 8, comprising the steps: a) applying a predetermined gate voltage (-9V) to a predetermined word line (WLl); b) applying a predetermined source voltage (+ 6V) to a predetermined source line (S1); and c) applying a predetermined drain voltage (+ 6V) to a predetermined drain line (Dl) which substantially corresponds to the source voltage.

10. A method for programming a memory cell in a non-volatile NOR semiconductor memory device according to one of claims 1 to 8, comprising the steps of: a) applying a predetermined gate voltage (-9V) to a predetermined word line (WL1); b) floating the electrical potential of the predetermined source line (S1); and c) applying a predetermined drain voltage (+ 6V) to a predetermined drain line (Dl).

11. A method for programming a memory cell in a non-volatile NOR semiconductor memory device according to one of claims 1 to 8, comprising the steps of: a) applying a predetermined gate voltage (-9V) to a predetermined word line (WL1); b) applying a predetermined source voltage (+ 6V) to a predetermined source line (S1); and c) floating the electrical potential of the predetermined drain line (Dl).

12. The method according to claim 9, d a d u r c h g e k e n e z e i c h n e t that a potential difference between the predetermined source and drain line (Sl, Dl) at no time has a higher potential difference than in a read mode.