JPH0982929A - Semiconductor integrated circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To arbitrarily set a plurality of power supply potentials in an internal logic circuit region, and enable commonly having a plurality of different power supply system circuits in each power supply system, by installing a plurality of power supply terminals which supply a common potential and different potentials, and a power supply changeover circuit which supplies a desired potential to an internal logic circuit out of the terminals. SOLUTION: In order to select power supplies of VDD1 and VDD2, an inverter 26 for control is put in the VDD1 side of a switching signal, and the power supplies VDD1 and VDD2 are selected. By the respective changeover switches 25 of VDD1 and VDD2, a selected power supply is inputted. In this case, in order to prevent a current from flowing from a high potential to a low potential, an input power supply is fed to an internal logic circuit from the output parts of diodes 27. By commonly having a plurality of different power supply system circuits in this manner, flexibility is imparted to a logic circuit, it is miniaturized, and application efficiency of the internal logic circuit can be improved.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multi-power semiconductor integrated circuit, and more particularly to a multi-power gate array (G / A).

[0002]

2. Description of the Related Art VDD1 and VD of a conventional multi-power supply integrated circuit
FIG. 7 shows a configuration diagram in which the power source D2 is used. VDD1
It is composed of a system power supply, a VDD2 system power supply, VSS, an internal logic circuit, and the like. Internal logic circuits such as an internal logic circuit that logically operates in the VDD1 system and an internal logic circuit that operates in the VDD2 system are completely separated by the operating power supply potential (for simplification, the ground wiring, which is a common potential, is omitted. ). Therefore, it is impossible to change each power supply potential in the semiconductor integrated circuit, and the power supply potential supplied from the outside is changed when the power supply potential is changed.

The power supply potential in each internal logic circuit is only one potential (VDD1). Therefore, it is impossible to change the power supply potential for each internal logic circuit.

A conventional G / A internal logic circuit area has a structure as shown in FIG. 5, in which N wells (WELL) for supplying VDD1 and VDD2 and PWELL for supplying VSS are alternately arranged. Lateral VDD1 and VD
One D2 and VSS wiring is provided for each WELL1 column, and a plurality of vertical VDD1, VDD2, and VSS wirings are provided at equal intervals.

In the case of the conventional dual power supply G / A, a logic circuit operating with a single power supply of VDD1 is formed in a region 53 at the center of the internal logic circuit region, and a region 51 at the upper side of the internal logic circuit region is formed.
A level shifter is formed in the area 52 on the lower side.

Normally, the logic circuit has N in the internal logic circuit area.
A pair of WELL and PWELL is configured in ROW units with 1 ROW.

The level shifter uses VDD1 data and VD
This is a logic circuit that interfaces D2 system data and is required to perform dual power supply operation. Unlike a normal logic circuit, the NWELL supplied with the second power supply system VDD2 on the upper and lower sides of the internal logic circuit area is used, and the VDD1 system NWELL and the VDD2 system NWELL are used.
And PWELL.

FIG. 6 shows a configuration diagram of a conventional G / A that operates with two power supplies of VDD1 and VDD2. The level shifter 61 is provided on the upper side of the internal logic circuit area, the level shifter 62 is provided on the lower side, and the user circuit 63 is provided at the center. VDD1 by the power supply wiring 64 and VDD2 are supplied to the level shifters 61 and 62 by the power supply wiring 65. VDD1 is supplied by the wiring 64.

The VDD1 system data is directly input / output between the outside of the G / A and the user circuit 63, and the VDD2 system data is interfaced by the level shifters 61 and 62.
Input / output is performed between the outside of the G / A and the user circuit 63.

FIG. 7 shows an overall view of a conventional G / A which operates with two power supplies of VDD1 and VDD2. The internal logic circuit that operates at VDD1 and the internal logic circuit that operates at VDD2 are completely separated for each operating power supply potential.

[0011]

However, in the above-mentioned prior art, the user circuit is composed of a single power source, and the different power source is provided in the internal logic circuit area only by performing the different power source interface with the outside of the G / A by the level shifter. I couldn't configure a user circuit that works with.

In the prior art, the power supply potential could not be changed in the internal logic circuit, and there was only one type of power supply potential. Therefore, if the operating speed of a specific circuit block is sacrificed in the internal logic circuit to operate at a low voltage and the overall current consumption is kept low, or conversely, the operating speed of a specific circuit block is secured, the overall current consumption will decrease. Was getting bigger.

Further, when the same integrated circuit is used for a plurality of purposes and a plurality of power supply potentials, the input power switching circuit section is complicated.

Therefore, the present invention solves such a problem, and an object of the present invention is to provide a multiple power source G / A capable of forming a logic circuit operating with multiple power sources in one chip. .

Another object of the present invention is to solve the above problems and to provide a semiconductor integrated circuit in which the power supply potential can be easily changed within one chip.

Another object of the present invention is to solve the above problems and to provide a semiconductor integrated circuit in which the power supply potential can be easily changed for each logic circuit.

[0017]

In the semiconductor integrated circuit of the present invention, R constituting a logic circuit is formed in the internal logic circuit area.
It is characterized by comprising an OW and a plurality of different power supply systems, and the power supply system supplied for each ROW is different.

The semiconductor integrated circuit of the present invention is characterized in that the NWELL forming the ROW is divided into a plurality of parts in the internal logic circuit area.

The semiconductor integrated circuit of the present invention is characterized in that power is supplied to the ROW from power supply lines of different power supplies in the vertical direction.

In the semiconductor integrated circuit of the present invention, in the input power supply circuit section, the input power supply is composed of a plurality of input power supplies and a plurality of switching signals, and the above-mentioned plurality of input power supplies are internally supplied by the plurality of switching signals. It is characterized by being arbitrarily selected.

The semiconductor integrated circuit of the present invention is characterized in that each of the internal logic circuits has the above-mentioned input power supply switching unit.

The semiconductor integrated circuit of the present invention is characterized in that the input power supply switching section has a current flow prevention circuit.

The semiconductor integrated circuit of the present invention is characterized in that a plurality of different power supplies are supplied in the vertical or horizontal direction within the internal logic circuit area.

The semiconductor integrated circuit of the present invention is characterized in that a plurality of different power supplies are supplied in the vertical and horizontal directions within the internal logic circuit area.

[0025]

FIG. 1 shows a first embodiment of the present invention. In FIG. 1, a VDD1 system user circuit 11 and a VDD2 system user circuit 12 are provided in ROW units in the internal logic circuit area.
Also, the level shifter 13 is configured so that the power supply wiring 14 supplies VDD1 to the user circuit 11 and the level shifter 13, and the power supply wiring 15 supplies VDD2 to the user circuit 12 and the level shifter 13.

User circuit 11 and user circuit 12
Are arranged on the upper and lower sides of the internal logic circuit area, and G / A
Input and output of external VDD1 system data and VDD2 system data.

The level shifter 13 is arranged in the middle of the user circuit 11 and the user circuit 12, and has VDD1 system data and V1.
Interfaces with DD2 data.

The user circuit 11 and the user circuit 12 are individually configured by wiring the wiring 14 and the wiring 15 vertically and horizontally in the internal logic circuit area, and the level shifter 13 requiring two power supplies can be arranged anywhere in the internal logic circuit. Can be placed.

In FIG. 1, VDD1 or VDD is added to the NWELL of each ROW in the internal logic circuit area as shown in FIG.
This is a configuration in which the two power supply wirings can be freely wired. Therefore, by freely selecting the power supply to each ROW, it is possible to mix circuits of different power supply systems in the internal logic circuit area.

In FIG. 1, the user circuit 11 and the user circuit 12 have the same power supply system circuit integrated into one, but the same power supply system circuit is divided into ROW units and arranged in different locations. The same applies in the case. Even the level shifter 13 can be freely arranged in the internal logic circuit area.

Further, in FIG. 1, two power sources VDD1 and VDD2 are used, but this also applies to the case where three or more power sources are supplied.

A second embodiment of the present invention is shown in FIG. This is a configuration in which one ROW NWELL is divided into two,
The VDD1 system user circuit 31 is arranged in the upper left of the internal logic circuit region, the key VDD2 system user circuit 32 is arranged in the lower side of the internal logic circuit region, and the level shifter 33 is arranged in the upper right region of the internal logic circuit region.

VDD1 and V in units of divided NWELL
Since the power of the DD2 can be supplied, the use efficiency of the internal logic circuit area can be improved.

Further, in the configuration diagram of FIG. 3, since there are portions in which different power supply circuits of the user circuit 31 and the user circuit 32 are mixed in one ROW, both power supplies of VDD1 and VDD2 are wired in the horizontal direction. Rather than wiring in the vertical direction to supply power, power can be supplied more efficiently.

The NWELL of FIG. 3 can be divided into three or more as shown in FIG. 4, and the same applies when the NWELL is divided into three or more. Therefore, the use efficiency of the internal logic circuit area is improved, and the vertical power supply wiring becomes effective.

FIG. 8 shows a configuration diagram of the dual power source G / A. In this embodiment, only two types of power supply systems, VDD1 and VDD2, are described, but the same applies to two or more types of power supplies.

It is composed of a power input VDD1 and a power input VDD2, and a switching signal for selecting one of them.
By arbitrarily changing the potential of the switching signal, VDD
Either 1 or VDD2 is selected and supplied to the inside of the integrated circuit.

FIG. 9 is a detailed view of the input power supply circuit section of FIG. In order to select the power source of VDD1 and VDD2, the control inverter 26 is provided on the VDD1 side of the switching signal. With this control inverter 26, VD
The power supplies for D1 and VDD2 are selected. Also VDD1, V
A changeover switch 25 is inserted in each of the DD2s, and VDD1 and VDD2 power supply inputs can be selected.

A diode 27 is connected so that a current does not flow from a high potential to a low potential when the VDD1 or VDD2 input power source is selected. The input power from the output of the diode 27 is supplied to the internal logic circuit.

FIG. 10 is a detailed diagram in which the power supply circuit section of FIG. 9 is put in each logic circuit section. It has a power supply circuit unit similar to that shown in FIG. The power output from the power supply circuit section is supplied to the logic circuit.

[0041]

As described above, according to the present invention, since a plurality of power supply potentials to be supplied can be arbitrarily set in the internal logic circuit area, a plurality of different power supply system circuits operating in each power supply system can be shared. There is an effect. Therefore, the logic circuit can be configured with flexibility, and there is an effect that the logic circuit is downsized and the use efficiency of the internal logic circuit is improved.

Further, there is an effect that it is possible to easily give a high potential only to a logic circuit portion requiring a high speed and a low potential only to a logic circuit portion which consumes a large amount of current. Speed according to the intended use,
There is an effect that the power supply potential can be changed depending on which one of the current consumption charges is emphasized. Since the difference in current consumption of the semiconductor integrated circuit during operation or half operation of the semiconductor integrated circuit can be arbitrarily changed to the power supply potential, there is an effect that a low power consumption type integrated circuit can be produced.

[Brief description of drawings]

FIG. 1 is a configuration diagram of a dual power supply G / A showing a first embodiment of the present invention.

FIG. 2 is a configuration diagram of a WELL according to the first embodiment of the present invention.

FIG. 3 is a configuration diagram of a dual power source G / A showing a second embodiment of the present invention.

FIG. 4 is a configuration diagram of a WELL according to a second embodiment of the present invention.

FIG. 5 is a configuration diagram of a WELL showing a conventional example.

FIG. 6 is a configuration diagram of a dual power source G / A showing a conventional example.

FIG. 7 is a configuration diagram of a dual power source G / A showing a conventional example.

FIG. 8 is a configuration diagram of a dual power source G / A showing a third embodiment of the present invention.

FIG. 9 is a power supply circuit diagram of a dual power supply G / A showing a fourth embodiment of the present invention.

FIG. 10 is an internal logic circuit diagram of a dual power supply G / A showing a fifth embodiment of the present invention.

[Explanation of symbols]

 11, 12, 31, 32, 63 User circuit 13, 33, 61, 62 Level shifter 14, 15, 34, 35, 64, 65 Wiring 51, 52, 53 Area 20 VDD1 21 VDD2 22 Internal logic circuit section 23 VSS 24 Power supply Changeover signal 25 Changeover switch 26 Control inverter 27 Current flow prevention diode 28 Power supply circuit section 29 Logic circuit section

Claims (7)

[Claims] 1. A plurality of power supply terminals, each of which is supplied with a potential different from a common potential, and a power supply switching selection circuit which supplies a desired potential from the plurality of power supply terminals to an internal logic circuit. Semiconductor integrated circuit. 2. The internal logic circuit includes a first basic cell row in which a plurality of basic cells are arranged in a row, and a second basic cell row in which a plurality of basic cells is arranged in a row. 2. The semiconductor integrated circuit according to claim 1, wherein the power supply switching circuit is arranged in the internal logic circuit area. 3. The semiconductor integrated circuit according to claim 1, wherein the power supply switching circuit includes a backflow prevention diode between the plurality of power supply terminals. 4. The first basic cell array and the second basic cell array.
4. The semiconductor device according to claim 3, further comprising a power supply switching circuit different from that of the basic cell column of claim 1, and being supplied with different potentials from the first basic cell column and the second basic cell column, respectively. Integrated circuit. 5. The first basic cell array and the second basic cell array.
5. The semiconductor integrated circuit according to claim 4, wherein the well is formed in a well different from that of the basic cell column. 6. A first power supply line that supplies a first potential different from the common potential to the first basic cell column, and a second power line that differs from the common potential to the second basic cell column.
6. The semiconductor integrated circuit according to claim 5, further comprising: a second power supply line for supplying the potential of 1., wherein the first power supply line and the second power supply line are arranged orthogonal to each other. 7. A first power supply line that supplies a first potential different from the common potential to the first basic cell column, and a second power line that differs from the common potential to the second basic cell column.
7. The semiconductor integrated circuit according to claim 6, further comprising a second power supply line for supplying the potential of 1., wherein the first power supply line and the second power supply line are arranged substantially parallel to each other.