Classifications

• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
  • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
  • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
  • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
  • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
• • C—CHEMISTRY; METALLURGY
  • C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
  • C25F—PROCESSES FOR THE ELECTROLYTIC REMOVAL OF MATERIALS FROM OBJECTS; APPARATUS THEREFOR
  • C25F3/00—Electrolytic etching or polishing
  • C25F3/16—Polishing
• • B—PERFORMING OPERATIONS; TRANSPORTING
  • B23—MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
  • B23H—WORKING OF METAL BY THE ACTION OF A HIGH CONCENTRATION OF ELECTRIC CURRENT ON A WORKPIECE USING AN ELECTRODE WHICH TAKES THE PLACE OF A TOOL; SUCH WORKING COMBINED WITH OTHER FORMS OF WORKING OF METAL
  • B23H5/00—Combined machining
  • B23H5/06—Electrochemical machining combined with mechanical working, e.g. grinding or honing
  • B23H5/08—Electrolytic grinding
• • B—PERFORMING OPERATIONS; TRANSPORTING
  • B24—GRINDING; POLISHING
  • B24B—MACHINES, DEVICES, OR PROCESSES FOR GRINDING OR POLISHING; DRESSING OR CONDITIONING OF ABRADING SURFACES; FEEDING OF GRINDING, POLISHING, OR LAPPING AGENTS
  • B24B37/00—Lapping machines or devices; Accessories
  • B24B37/04—Lapping machines or devices; Accessories designed for working plane surfaces
• • H—ELECTRICITY
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  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
  • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
  • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
  • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
  • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
  • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
  • H01L21/321—After treatment
  • H01L21/32115—Planarisation
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
  • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
  • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
  • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
  • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
  • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
  • H01L21/321—After treatment
  • H01L21/32115—Planarisation
  • H01L21/3212—Planarisation by chemical mechanical polishing [CMP]
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
  • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
  • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
  • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
  • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
  • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
  • H01L21/321—After treatment
  • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
  • H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
  • H01L21/32134—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by liquid etching only
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
  • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
  • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
  • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
  • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
  • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
  • H01L21/321—After treatment
  • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
  • H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
  • H01L21/32135—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only
  • H01L21/32136—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
  • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
  • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
  • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
  • H01L21/7684—Smoothing; Planarisation
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
  • H01L2924/0001—Technical content checked by a classifier
  • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Definitions

• This invention relates generally to semiconductor devices, and more particularly to a method to planarize a metal damascene structure using a combination of planarizing methods and electropolishing.
• transistor and interconnection elements Semiconductor devices are manufactured or fabricated on semiconductor wafers using a number of different processing steps to create transistor and interconnection elements.
• conductive (e.g., metal) trenches, vias, or the like are formed in dielectric materials as part of the semiconductor device.
• the trenches and vias couple electrical signals and power between transistors, internal circuit of the semiconductor devices, and circuits external to the semiconductor device.
• the semiconductor wafer may undergo, for example, masking, etching, and deposition processes to form the desired electronic circuitry of the semiconductor devices.
• multiple masking and etching steps can be performed to form a pattern of recessed areas in a dielectric layer on a semiconductor wafer that serve as trenches and vias for the interconnection lines.
• a deposition process may then be performed to deposit a metal layer over the semiconductor wafer to deposit metal both in the trenches and vias and also on the non-recessed areas of the dielectric layer.
• the metal deposited on the non-recessed areas of the semiconductor wafer is removed.
• CMP chemical mechanical polishing
• a wafer assembly is positioned on a CMP pad located on a platen or web.
• the wafer assembly includes a substrate having one or more layers and/or features, such as interconnection elements formed in a dielectric layer.
• a force is then applied to press the wafer assembly against the CMP pad.
• the CMP pad and the substrate assembly are moved against and relative to one another while applying the force to polish and planarize the surface of the wafer.
• a polishing solution often referred to as polishing slurry, is dispensed on the CMP pad to facilitate the polishing.
• the polishing slurry typically contains an abrasive and is chemically reactive to selectively remove from the wafer the unwanted material, for example, a metal layer, more rapidly than other materials, for example, a dielectric material.
• CMP may be used to achieve global and local planarization of a surface on the wafer.
• CMP may be used to remove a layer of material in order to expose an underlying structure or layer.
• CMP methods can have several deleterious effects on the underlying semiconductor structure because of the relatively strong mechanical forces involved. For example, as interconnection geometries move to .13 microns and below, there can exist a large difference between the mechanical properties of the conductive materials, for example copper, and the low k films used in typical damascene processes..
• the Young Modulus of a low k dielectric film may be greater than 10 orders of magnitude lower than that of copper. Consequently, the relatively strong mechanical force applied on the dielectric films and copper in a CMP process, among other things, can cause stress related defects on the semiconductor structure that include delamination, dishing, erosion, film lifting, scratching, or the like.
• a method for forming a semiconductor structure. The method includes forming a dielectric layer with recessed areas and non-recessed areas on the semiconductor wafer, forming a conductive layer over the dielectric layer to cover the recessed areas and non-recessed areas, planarizing the surface of the conductive layer to reduce variations in the topology of the surface of the conductive layer, and then electropolishing the conductive layer to expose the non-recessed areas.
• Figs. 1A and IB illustrate an exemplary electropolishing process of a semiconductor device
• Figs. 2 A through 2D illustrate an exemplary planarizing and electropolishing process of a semiconductor device
• Fig. 3 illustrates a flow chart of an exemplary damascene process
• Figs. 4A and 4B illustrate exemplary topologies of a metal layer formed on a semiconductor structure that may be planarized and polished;
• Fig. 5 illustrates a cross-sectional view of an exemplary chemical mechanical polishing apparatus
• Fig. 6 illustrates a cross-sectional view of an exemplary electropolishing apparatus.
• CMP Chemical mechanical polishing
• electropolishing is a process to polish metal (e.g., copper) that provides a relatively stress free polishing method.
• metal e.g., copper
• electropolishing is an isotropic etching process, in that it etches a metal layer at approximately the same rate despite differences in height.
• Figs. 1A and IB illustrate an exemplary process flow of an electropolishing method to polish a semiconductor structure that has a non-planar topology.
• Fig. 1 A illustrates a dielectric layer 102 patterned with recessed and non-recessed areas formed over substrate 100.
• a barrier/seed layer 105 has been formed over the dielectric layer 102 and substrate 100.
• metal layer 106 has been deposited, for example, via electroplating, over barrier/seed layer 105 and covering the recessed and non-recessed areas of the dielectric layer 102.
• Metal layer 106 has a non-planar topology that includes a hump 108 and a recess 112 located over various structures in the dielectric layer.
• the non-planar topology of metal layer 106 can be caused, for example, by the plating chemistry in an electroplating process.
• metal layer 106 is typically polished back to the surface of the non-recessed areas such that metal layer 106 within the recessed areas, i.e., the trenches, is isolated to form metal interconnection lines.
• references to planar are not intended to require or suggest that the top surface of metal layer 106 be absolutely planar with the top surface of the non-recessed area; rather, it is intended to convey that the level of the top surface of metal layer 106 is made more even with the level of the top surface of the recessed area. Thus, it is generally advantageous to reduce the variation between the level of the top surface of metal layer 106 and the level of the top surface of the recessed area.
• metal layer 106 is electropolished. Additionally, as depicted in Fig. 1 A, assume that the profile or general shape of the topology of metal layer 106 is non-planar prior to electropolishing. As noted above, electropolishing is an isotropic etching process. As such, as depicted in Fig. IB, the non-planar profile or general shape of the topology of metal layer 106 can remain after electropolishing.
• Fig. 1 A assume that the topology of metal layer 106 includes hump 108 and concave portion 112 prior to electropolishing.
• Fig. IB assume that hump 108 and concave portion 112 (Fig. 1A) remain as residue 110 and recess 114 after electropolishing.
• Residue 110 is a region of metal layer 106 at a height H above the dielectric layer 102. Residue 110 can cause an electrical short circuit between interconnection lines formed in the trench regions below residue 110.
• Recess 114 is a recess or trench in metal layer 106 where the surface of metal layer 106 within the trench is at a depth R below the surface of the dielectric layer 102.
• Recess 114 results in metal or copper loss within the trench that can cause a reduction of the conductance of the formed interconnection lines.
• it is advantageous to reduce the variation in the height of the surface of metal layer 106 above or below the surface of the non-recessed areas.
• a metal layer formed over a patterned dielectric layer is planarized prior to electropolishing the metal layer to isolate interconnection lines.
• One advantage to planarizing the metal layer prior to electropolishing the metal layer back is that the metal interconnection lines can be formed in the dielectric layer with less damage to the structure underlying the metal layer than conventional planarizing techniques, and thus increase the reliability of the interconnection elements since most damage to the structure occurs when recessed metal is exposed to the CMP pad.
• Figs. 2A through 2D illustrate an exemplary process flow of a method to planarize and electropolish an exemplary semiconductor structure including a metal layer 106 with a non-planar topology.
• Fig. 2 A illustrates a cross-section view of an exemplary semiconductor structure with recessed areas 102r and non- recessed areas 102n formed in a dielectric layer 102. The recessed areas 102r and non-recessed areas 102n form a pattern of interconnection lines in dielectric layer 102.
• Dielectric layer 102 can be conventionally deposited and formed on substrate layer 100 using any conventional deposition method, such as thermal or plasma chemical vapor deposition, spin-on, sputtering, or the like.
• dielectric layer 102 can be patterned through known patterning methods such as photomasking, photolithography, microlithography, or the like.
• the dielectric material may be, for example, silicon dioxide (SiO2).
• SiO2 silicon dioxide
• Low k value materials i.e., less than approximately 3.0
• Such low k value materials include flourinated silicate glass, polyimides, fluorinated polyimides, hybrid/composites, siloxanes, organic polymers, [alpha] - C:F, Si-O-C, parylenes/fluorinated parylenes, polyterafluoroethylene, nanoporous silca, nanoporous organic, or the like.
• Dielectric layer 102 is formed on substrate layer 100.
• Substrate layer 100 may be, for example, an underlying semiconductor wafer, previously formed dielectric layers, or other semiconductor structures.
• Substrate layer 100 may include, for example, silicon and/or other various semiconductor materials, such as gallium arsenide, or the like depending on the particular application.
• a barrier and/or seed layer 105 may also be deposited on the dielectric layer by various methods, such as chemical vapor deposition (CND), physical vapor deposition (PND), atomic layer deposition (ALD), or the like, such that the barrier layer covers the patterned dielectric layer 102 including the walls of dielectric layer 102 within the recessed areas 102r.
• a barrier layer serves to prevent metal (e.g., copper) from diffusing into the dielectric layer 102 after the subsequent metal layer 106 deposition (Fig. 2B). Any diffusion of copper into the dielectric layer 102 may adversely increase the dielectric constant of the dielectric layer 102.
• Barrier/seed layer 105 can be formed of a suitable conductive material that is resistant to the diffusion of copper, such as titanium, tantalum, tungsten, titanium-nitride, tantalum-nitride, tungsten-nitride, or other suitable material.
• the barrier layer can be omitted. For example, if the dielectric material is sufficiently resistant to the diffusion of the metal layer 106, or if any diffusion of metal layer 106 will not adversely affect the performance of the semiconductor device, the barrier layer may be omitted.
• a seed layer is typically deposited, for example, if metal layer 106 is subsequently electroplated over dielectric layer 102.
• a seed layer is typically a thin layer of copper or other conductive material that metal layer 106 can be electroplated onto.
• a single layer or material of barrier/seed layer 105 may serve as both a barrier layer and a seed layer.
• metal layer 106 is deposited on the surface of the barrier/seed layer 105, or on the dielectric layer 102 if the barrier/seed layer 105 was omitted.
• Metal layer 106 fills the trenches or recessed areas 102r and also covers the non-recessed areas 102n.
• Metal layer 106 may be deposited by PND, CND, ALD, electroplating, electroless plating, or any other convenient method.
• Metal layer 106 is, for example, copper or other suitable conductive material such as aluminum, nickel, chromium, zinc, cadmium, silver, gold, rhodium, palladium, platinum, tin, lead, iron, indium, or the like. As shown in Fig.
• the topology of metal layer 106 may be non-planar with variations in its topology.
• the deposition of metal layer 106 can result in a hump 108 and or concave portion 112 above various features of dielectric layer 102.
• a hump 108 can form above a narrow and high-density trench region
• a concave portion 112 can form above a wide low-density trench region of dielectric layer 102.
• the effects can be especially prevalent in the case of electroplating metal layer 106 over dielectric layer 102 because of the plating chemistry.
• hump 108 and concave portion 112 are illustrative only and that other non-planar topology features of metal layer 106 are possible as described below with respect to Figs. 4A and 4B.
• metal layer 106 is planarized to smooth or reduce features of the topology.
• CMP chemical mechanical polishing
• CMP metal layer 106 reduces the topology, i.e., hump 108, recess 112, and other non-planar topology features of the surface of metal layer 106 to smooth metal layer 106 prior to electropolishing metal layer 106.
• the CMP process is performed to polish metal layer 106 to a first height "a" above the underlying substrate 100, where "a" is greater than a height "b,” equal to the height of dielectric layer 102.
• the CMP process stops short of removing metal layer 106 from the non-recessed areas 102n of dielectric layer 102 and possibly coming in contact with dielectric layer 102. Rather, the CMP process polishes metal layer 106 to planarize and reduce variations in the topology of metal layer 106.
• references to planar and planarizing, specifically in reference to metal layer 106, are not intended to require or suggest that the surface of metal layer 106 be absolutely planar; rather, it is intended to convey that the surface of metal layer 106 is made more smooth or planar. Essentially, planarizing the surface of metal layer 106 reduces the variations in the topology of metal layer 106 prior to electropolishing.
• the CMP process of this exemplary method can be optimized for planarization efficiency, with less emphasis placed on preserving dielectric layer 102 and the underlying structures because the polishing pad of the CMP apparatus (Fig. 5) does not directly contact the underlying structure, such as the dielectric layer 102.
• the stiffness or hardness of a polishing pad may be adjusted to preserve underlying dielectric layer 102.
• a stiff pad with a diamond tip embedded therein or the like can be used in the CMP portion of this example of the method.
• slurry free or abrasive-free polishing processes can be used to reduce scratches in metal layer 106.
• the pressure of the polishing pad can be a factor in controlling and preventing damage to the patterned dielectric layer 102, and the interconnect structure, particularly for integration schemes with copper and low k dielectric films.
• the pressure of the polishing pad ranges from 0.1 pound-force per square inch (PSI) to 10 PSI, for example 5 PSI.
• PSI pound-force per square inch
• the thickness of metal layer 106 removed during the CMP process depends, at least in part, on the topography of the metal layer 106 formed over dielectric layer 102 and the planarization efficiency of the CMP process employed. Typically, the removal thickness is greater than or equal to the difference between a high and low point of the metal layer topology.
• metal layer 106 may be planarized in place of, or with, the exemplary CMP process described above.
• a sacrificial material may be added over metal layer 106 to planarize the surface above metal layer 106.
• the sacrificial material can be conductive or non-conductive such as spin-on-glass, photo-resist, metal alloy, metal compound, or the like.
• the metal layer 106 may then be planarized, for example, by etching away the sacrificial material and portions of metal layer 106.
• the sacrificial material and metal layer 106 should have the same or similar etch rate such that an etching process removes the sacrificial layer and metal layer 106 at similar rates. Etching the planarized metal layer 106 and the sacrificial layer at similar rates to remove the sacrificial layer and portions of metal layer 106 will result in a planarized metal layer 106.
• An example of the process is depicted in Fig. 4A and described below.
• the etching process can be a dry etching process or a wet etching process.
• a dry etching process includes plasma etching, chemical vapor etching, and the like.
• Plasma etching sources may include high-density plasma sources such as a helicon plasma source, inductive coupled plasma source (ICP), and the like.
• the etching gas may include a halogen group such as chlorine based gases.
• PLASMA ETCHING PROCESS Plasma power 500 to 1500 W, preferably 800 W
• Gas pressure 10 to 50 mTorr, preferably 20 mTorr
• Wafer temperature 300 to 500 °C, preferably 400 °C
• Etching gases Chlorine (Cl 2 )
• Plasma power 500 to 1500 W, preferably 800 W
• Gas pressure 10 to 50 mTorr, preferably 20 mTorr
• Step 2 Wafer temperature: 20 to 100 °C, preferably 50 °C Etching gases: Chlorine (Cl 2 ) After Step 1 the top portion of copper and copper compound will be converted to copper chloride (CuCl x ). Step 2:
• the concentration of HC1 may be in the range of 1 to 6 percent by weight, preferably 3 percent.
• a planarization technique similar to those used in the flat- panel display industry to anneal the amorphous Si (a-Si) to poly-Si on glass may be employed to reflow copper after plating metal layer 106 by using a laser to mollify metal layer 106 resulting in a planarized surface.
• Another alternative method includes a high frequency and short pulse laser that can be beamed from a direction parallel to the substrate 100 surface to remove higher portions of the topology of metal layer 106 by evaporation. The short pulse of the laser is used to protect bulk copper and surrounding dielectrics from the effects of high temperatures generated by the laser, i.e., reduce thermobudget.
• the laser can be a solid state laser such as a ruby laser, Nd-glass laser, Nd:YAG (yttrium aluminum garnet, Y Al 5 O 12 ) laser, gas laser, such as a He-Ne laser, CO 2 laser, HF laser, or the like.
• the laser beam can be scanned over the entire surface of substrate 100 to planarize metal layer 106.
• a non-contact type surface topography sensor can be used as an end-point detector in such a process. Exemplary conditions for this planarization process are detailed in the following table:
• metal layer 106 is electropolished. Specifically, metal layer 106 is electropolished from the non-recessed areas 102n of dielectric layer 102 such that metal layer 106 is isolated within recessed areas 102r, or trenches, to form interconnection lines. Metal layer 106 can be polished to the same height as the non-recessed areas. Alternatively, metal layer 106 can be polished to a height below the non-recessed areas. Metal layer 106 can be electropolished by an electropolishing apparatus (Fig. 6) that directs a stream of electrolyte fluid (not shown) to metal layer 106.
• the electrolyte fluid is, for example, any convenient electropolishing fluid, such as phosphoric acid, orthophosphoric acid (H 3 PO 4 ), or the like.
• barrier/seed layer 105 is removed from the exposed regions of non-recessed areas 102n of dielectric layer 102. If layer 105 is, or includes, a seed layer, the electropolishing process that polishes metal layer 106 may remove it, for example. If layer 105 is, or includes, a barrier layer, plasma dry etching, wet etching, or the like may remove it, for example. Additionally, if the metal layer 106 was electropolished to a height less than the non-recessed areas, the non- recessed areas can also be etched at this time to planarize the surface.
• Table IV provides an exemplary range of parameters that can be employed in a plasma dry etch process to remove the barrier layer:
• PROCESS Plasma Power 500 to 2000 W
• Fig. 3 is a flow chart illustrating an exemplary damascene process 300 including a planarizing process and an electroplating process.
• a wafer having recessed and non-recessed areas is provided in block 302.
• a patterned dielectric layer provided on the wafer may define the recessed and non-recessed areas.
• the patterned dielectric layer may be formed on underlying semiconductor structures, including other previously formed dielectric layers, a wafer, or the like. Further, the wafer may be divided up into individual dice that include recessed and non- recessed areas that will be separated at a later state of the processing into individual semiconductor devices.
• a metal layer is then deposited in block 304, such that the metal layer fills the recessed areas within the dielectric layer as well as covers the non-recessed areas of the dielectric layer.
• the metal layer is then planarized in block 306.
• the metal layer undergoes a CMP process to planarize and smooth the topography of the metal layer.
• the planarized metal layer is then electropolished in block 308 to expose the non-recessed areas of the dielectric layer and isolate the metal layer within the recessed areas to form metal interconnection lines.
• a barrier/seed layer can be optionally added prior to the deposition of the metal layer in block 304, in which case, after non-recessed areas are exposed, the barrier/seed layer is etched from the dielectric layer.
• each block in Fig. 3 can include many processes not explicitly described herein, such as masking and etching the wafer to form the recessed areas, or cleansing the metal layer before and/or after planarizing the surface.
• the exemplary damascene process 300 is applicable to both single and dual inlaid applications.
• Figs. 4A and 4B illustrate additional exemplary topologies of metal layer 106 that may be planarized and then electropolished to form interconnection structures.
• metal layer 106 has a topology that roughly corresponds to the shape of the underlying dielectric layer 102. Such a topology could be created, for example, by sputtering metal layer 106 over dielectric layer 102.
• Metal layer 106 is then planarized, for example, by adding a sacrificial material 107 and then etching back the sacrificial material 107 and a portion of metal layer 106 such that metal layer 106 is planarized to dotted line "P."
• sacrificial material 107 can be a metal, metal composites with solvent, such as copper with a solvent, spin-on glass, photo-resist, or the like.
• Sacrificial material 107 can be any material that has a similar etching rate as the underlying metal layer 106, and the etching process can be a conventional dry or wet etch with no selectivity between sacrificial material 107 and metal layer 106.
• metal layer 106 is then electropolished as described above with regard to Fig. 2D.
• Fig. 4B illustrates another exemplary metal layer 106 having an irregular surface topology.
• the irregular surface topology of metal layer 106 may be due to any number of causes ranging from the deposition method to the underlying structure.
• Metal layer 106 is polished similar to Fig. 4A by first planarizing the surface to line "P," by CMP polishing, adding a sacrificial material and etching back, momentarily heating metal layer 106 with a laser or the like. Metal layer 106 is then electropolished. It should be recognized from Figs. 4A and 4B that numerous metal layer topologies can be planarized and electropolished by this method without undue damage to the underlying dielectric layer 102.
• CMP apparatus 400 may be used to planarize metal layer 106.
• An exemplary CMP process proceeds by pressing and rotating the surface of a wafer against a wetted polishing surface. The process is controlled through the chemical, pressure, and temperature conditions of CMP apparatus 400.
• Exemplary CMP apparatus 400 includes a rotatable polishing platen 411 and a polishing pad 412 mounted on polishing platen 411.
• CMP apparatus 400 also includes a rotatable wafer carrier 413 that positions and applies a force to a wafer 401 in the direction indicated by a ⁇ ow 414.
• a chemical slurry is supplied to CMP apparatus 400 through nozzle 417 and dispensed onto the polishing pad 412.
• the chemical slurry is, for example, supplied from a temperature-controlled reservoir (not shown) through nozzle 417. Further, the chemical slurry contains a polishing agent, such as alumina, silica, or the like that is used as an abrasive agent along with other selected chemicals to polish the surface of wafer 401.
• a polishing agent such as alumina, silica, or the like that is used as an abrasive agent along with other selected chemicals to polish the surface of wafer 401.
• the primary parameters that affect the polishing rate are the down pressure 414 on the wafer 401 against polishing pad 412, the rotational speeds of the polishing platen 411 and wafer carrier 413, the composition and temperature of the chemical slurry, and the composition of polishing pad 412. Adjustments of these parameters permit control of the polishing rate and the planarization efficiency of CMP apparatus 400.
• CMP apparatus 400 and the process described with reference to Fig. 5, are for illustrative purposes only. It should be recognized that other CMP apparatus configurations and set-ups may be employed. For example, rotatable polishing platen 411 and polishing pad 412 can be replaced with a belt that moves polishing pad 412 with respect to wafer carrier 413. Also, as will be recognized, the movement of wafer 401 with respect to polishing pad 412 can be achieved in numerous manners. Therefore, the CMP apparatus 400 depicted in Fig. 5 is not intended to be limiting of the CMP apparatus or method that may be used.
• Fig. 6 illustrates an exemplary cross-sectional view of an electropolishing apparatus 500 that can be used to electropolish metal layer 506 formed on semiconductor wafer 501.
• Semiconductor wafer 501 may further include, for example, substrate layer 100, dielectric layer 102, and barrier/seed layer 105 (Figs 2A through 2D). Further, the topology of metal layer 506 will have been planarized prior to the electropolishing, for example, by CMP apparatus 400 (Fig. 5).
• Electrolyte fluid 520 includes any convenient electropolishing fluid, such as phosphoric acid, orthophosphoric acid (H 3 PO 4 ), or the like.
• the electrolyte fluid is orthophosphoric acid having a concentration between about 60 percent by weight and about 85 percent by weight.
• electrolyte fluid 106 can include, for example, glycol at 10 to 40 percent (against weight of the acid). It should be recognized, however, that the concentration and composition of the electrolyte fluid can vary depending on the particular application.
• a power supply 550 supplies opposing charges to an electrode 530 (the cathode) positioned in nozzle 540 and an electrode (the anode) coupled to metal layer 506.
• Power supply 550 can, for example, operate at a constant current or constant voltage mode. With power supply 550 configured to positively charge the electrolyte fluid 520 relative to metal layer 506, metal ions of metal layer 506 are removed from the surface. In this manner the stream of electrolyte fluid 520 electropolishes the portion of metal layer 506 in contact with the stream of electrolyte fluid 520.
• wafer 501 is rotated and translated along axis X to position the entire surface of metal layer 506 in the stream of electrolyte fluid 520 and uniformly electropolish the surface.
• the electrolyte fluid 520 can make a spiral path along the surface of metal layer 506 by rotating wafer 501 while simultaneously translating wafer 501 in the X direction.
• wafer 501 can be held stationary while nozzle 540 is moved to apply the stream of electrolyte 520 to desired portions of metal layer 506.
• both wafer 501 and nozzle 540 can move to apply the stream of electrolyte 520 to desired portions of metal layer 506. Exemplary descriptions of electropolishing methods and apparatus may be found in U.S. Patent Application No.
• wafer 501 including metal layer 506, may be partially or fully immersed within a bath of electrolyte fluid.

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