AU2002336360A1 - Forming a semiconductor structure using a combination of planarizing methods and electropolishing - Google Patents

Forming a semiconductor structure using a combination of planarizing methods and electropolishing

Info

Publication number
AU2002336360A1
AU2002336360A1 AU2002336360A AU2002336360A AU2002336360A1 AU 2002336360 A1 AU2002336360 A1 AU 2002336360A1 AU 2002336360 A AU2002336360 A AU 2002336360A AU 2002336360 A AU2002336360 A AU 2002336360A AU 2002336360 A1 AU2002336360 A1 AU 2002336360A1
Authority
AU
Australia
Prior art keywords
electropolishing
combination
forming
semiconductor structure
planarizing methods
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
AU2002336360A
Other languages
English (en)
Inventor
Ru Kao Chang
Hui Wang
Xiang Yu Yao
Peihaur Yih
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
ACM Research Inc
Original Assignee
ACM Research Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by ACM Research Inc filed Critical ACM Research Inc
Publication of AU2002336360A1 publication Critical patent/AU2002336360A1/en
Abandoned legal-status Critical Current

Links

Classifications

    • C—CHEMISTRY; METALLURGY
    • C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
    • C25F—PROCESSES FOR THE ELECTROLYTIC REMOVAL OF MATERIALS FROM OBJECTS; APPARATUS THEREFOR
    • C25F3/00—Electrolytic etching or polishing
    • C25F3/16—Polishing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B23—MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
    • B23H—WORKING OF METAL BY THE ACTION OF A HIGH CONCENTRATION OF ELECTRIC CURRENT ON A WORKPIECE USING AN ELECTRODE WHICH TAKES THE PLACE OF A TOOL; SUCH WORKING COMBINED WITH OTHER FORMS OF WORKING OF METAL
    • B23H5/00—Combined machining
    • B23H5/06—Electrochemical machining combined with mechanical working, e.g. grinding or honing
    • B23H5/08—Electrolytic grinding
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B24—GRINDING; POLISHING
    • B24B—MACHINES, DEVICES, OR PROCESSES FOR GRINDING OR POLISHING; DRESSING OR CONDITIONING OF ABRADING SURFACES; FEEDING OF GRINDING, POLISHING, OR LAPPING AGENTS
    • B24B37/00—Lapping machines or devices; Accessories
    • B24B37/04—Lapping machines or devices; Accessories designed for working plane surfaces
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/32115—Planarisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/32115—Planarisation
    • H01L21/3212—Planarisation by chemical mechanical polishing [CMP]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
    • H01L21/32134—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by liquid etching only
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
    • H01L21/32135—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only
    • H01L21/32136—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/7684—Smoothing; Planarisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Mechanical Engineering (AREA)
  • Electrochemistry (AREA)
  • General Chemical & Material Sciences (AREA)
  • Organic Chemistry (AREA)
  • Metallurgy (AREA)
  • Materials Engineering (AREA)
  • Plasma & Fusion (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Electrodes Of Semiconductors (AREA)
AU2002336360A 2001-08-17 2002-08-15 Forming a semiconductor structure using a combination of planarizing methods and electropolishing Abandoned AU2002336360A1 (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US31308601P 2001-08-17 2001-08-17
US60/313,086 2001-08-17
PCT/US2002/026167 WO2003017330A2 (en) 2001-08-17 2002-08-15 Forming a semiconductor structure using a combination of planarizing methods and electropolishing

Publications (1)

Publication Number Publication Date
AU2002336360A1 true AU2002336360A1 (en) 2003-03-03

Family

ID=23214320

Family Applications (1)

Application Number Title Priority Date Filing Date
AU2002336360A Abandoned AU2002336360A1 (en) 2001-08-17 2002-08-15 Forming a semiconductor structure using a combination of planarizing methods and electropolishing

Country Status (8)

Country Link
EP (1) EP1423868A2 (ko)
JP (1) JP2005500687A (ko)
KR (1) KR100899060B1 (ko)
CN (1) CN100419963C (ko)
AU (1) AU2002336360A1 (ko)
CA (1) CA2456225A1 (ko)
TW (1) TW569330B (ko)
WO (1) WO2003017330A2 (ko)

Families Citing this family (18)

* Cited by examiner, † Cited by third party
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US6939796B2 (en) * 2003-03-14 2005-09-06 Lam Research Corporation System, method and apparatus for improved global dual-damascene planarization
US6821899B2 (en) * 2003-03-14 2004-11-23 Lam Research Corporation System, method and apparatus for improved local dual-damascene planarization
US7078344B2 (en) * 2003-03-14 2006-07-18 Lam Research Corporation Stress free etch processing in combination with a dynamic liquid meniscus
TW200629392A (en) * 2004-12-22 2006-08-16 Ebara Corp Flattening method and flattening apparatus
WO2010020092A1 (en) 2008-08-20 2010-02-25 Acm Research (Shanghai) Inc. Barrier layer removal method and apparatus
CN101882595B (zh) * 2009-05-08 2014-07-09 盛美半导体设备（上海）有限公司 阻挡层的去除方法和装置
CN103692293B (zh) * 2012-09-27 2018-01-16 盛美半导体设备（上海）有限公司 无应力抛光装置及抛光方法
US8828875B1 (en) 2013-03-08 2014-09-09 Taiwan Semiconductor Manufacturing Company, Ltd. Method and apparatus for improving CMP planarity
CN104097118A (zh) * 2013-04-02 2014-10-15 盛美半导体设备（上海）有限公司 无应力抛光集成装置
CN105870051B (zh) * 2015-01-20 2019-01-11 中芯国际集成电路制造(上海)有限公司 半导体结构的制作方法
WO2016127424A1 (en) * 2015-02-15 2016-08-18 Acm Research (Shanghai) Inc. Method for optimizing metal planarization process
US10074721B2 (en) * 2016-09-22 2018-09-11 Infineon Technologies Ag Method of fabricating a semiconductor wafer that includes producing a planarised surface having both a mesa surface and an insulating layer surface
CN106672892A (zh) * 2016-12-21 2017-05-17 中国电子科技集团公司第五十五研究所 减小三维堆叠中牺牲层在化学机械抛光中凹陷变形的方法
CN108231599B (zh) * 2016-12-22 2021-10-08 联华电子股份有限公司 改善晶片表面平坦均匀性的方法
WO2020138976A1 (ko) * 2018-12-26 2020-07-02 한양대학교에리카산학협력단 반도체 소자의 제조 방법
KR102499041B1 (ko) 2019-01-10 2023-02-14 삼성전자주식회사 반도체 소자 형성 방법
CN111312595A (zh) * 2020-03-03 2020-06-19 合肥晶合集成电路有限公司 金属互连层的制作方法
CN113173552B (zh) * 2021-04-09 2023-06-23 深圳清华大学研究院 具有导电性能的大尺度超滑元件及其加工工艺、大尺度超滑系统

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3557868B2 (ja) * 1997-01-14 2004-08-25 セイコーエプソン株式会社 装飾品の表面処理方法、装飾品および電子機器
US6121152A (en) * 1998-06-11 2000-09-19 Integrated Process Equipment Corporation Method and apparatus for planarization of metallized semiconductor wafers using a bipolar electrode assembly
US6232231B1 (en) * 1998-08-31 2001-05-15 Cypress Semiconductor Corporation Planarized semiconductor interconnect topography and method for polishing a metal layer to form interconnect
US6149830A (en) * 1998-09-17 2000-11-21 Siemens Aktiengesellschaft Composition and method for reducing dishing in patterned metal during CMP process
US6056864A (en) 1998-10-13 2000-05-02 Advanced Micro Devices, Inc. Electropolishing copper film to enhance CMP throughput
US6315883B1 (en) * 1998-10-26 2001-11-13 Novellus Systems, Inc. Electroplanarization of large and small damascene features using diffusion barriers and electropolishing
KR100283108B1 (ko) * 1998-12-28 2001-04-02 김영환 반도체소자의 구리배선 형성방법
JP2001044195A (ja) * 1999-07-28 2001-02-16 Mitsubishi Electric Corp 半導体装置およびその製造方法
KR100297736B1 (ko) * 1999-08-13 2001-11-01 윤종용 트렌치 소자분리방법

Also Published As

Publication number Publication date
CA2456225A1 (en) 2003-02-27
CN1543668A (zh) 2004-11-03
JP2005500687A (ja) 2005-01-06
CN100419963C (zh) 2008-09-17
WO2003017330A2 (en) 2003-02-27
KR20040030147A (ko) 2004-04-08
KR100899060B1 (ko) 2009-05-25
EP1423868A2 (en) 2004-06-02
TW569330B (en) 2004-01-01
WO2003017330A3 (en) 2003-07-24

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Legal Events

Date Code Title Description
MK6 Application lapsed section 142(2)(f)/reg. 8.3(3) - pct applic. not entering national phase