TW200629392A - Flattening method and flattening apparatus - Google Patents

Flattening method and flattening apparatus

Info

Publication number
TW200629392A
TW200629392A TW094145477A TW94145477A TW200629392A TW 200629392 A TW200629392 A TW 200629392A TW 094145477 A TW094145477 A TW 094145477A TW 94145477 A TW94145477 A TW 94145477A TW 200629392 A TW200629392 A TW 200629392A
Authority
TW
Taiwan
Prior art keywords
flattening
metal film
processing
surface irregularities
initial
Prior art date
Application number
TW094145477A
Other languages
Chinese (zh)
Inventor
Yasushi Tohma
Takayuki Saitoh
Tsukuru Suzuki
Akira Kodera
Yutaka Wada
Itsuki Kobata
Original Assignee
Ebara Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ebara Corp filed Critical Ebara Corp
Publication of TW200629392A publication Critical patent/TW200629392A/en

Links

Classifications

    • C—CHEMISTRY; METALLURGY
    • C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
    • C25F—PROCESSES FOR THE ELECTROLYTIC REMOVAL OF MATERIALS FROM OBJECTS; APPARATUS THEREFOR
    • C25F3/00—Electrolytic etching or polishing
    • C25F3/02—Etching
    • C—CHEMISTRY; METALLURGY
    • C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
    • C25F—PROCESSES FOR THE ELECTROLYTIC REMOVAL OF MATERIALS FROM OBJECTS; APPARATUS THEREFOR
    • C25F7/00—Constructional parts, or assemblies thereof, of cells for electrolytic removal of material from objects; Servicing or operating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/32115—Planarisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/32115—Planarisation
    • H01L21/3212—Planarisation by chemical mechanical polishing [CMP]
    • H01L21/32125—Planarisation by chemical mechanical polishing [CMP] by simultaneously passing an electrical current, i.e. electrochemical mechanical polishing, e.g. ECMP
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/7684—Smoothing; Planarisation

Landscapes

  • Engineering & Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Electrochemistry (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Materials Engineering (AREA)
  • Metallurgy (AREA)
  • Organic Chemistry (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Mechanical Treatment Of Semiconductor (AREA)
  • Weting (AREA)
  • Manufacturing Of Printed Wiring (AREA)

Abstract

A flattening method can flatly process a surface of a metal film as an interconnect material over the entire film surface at a sufficiently high processing rate even when the metal film has initial surface irregularities. The flattening method for processing and flattening a surface of a metal film formed on a workpiece and having initial surface irregularities, including: coating only recessed portions of the initial surface irregularities of the metal film with a solid or pasty coating material; and processing the surface of the metal film by electrolytic processing using no abrasive.
TW094145477A 2004-12-22 2005-12-21 Flattening method and flattening apparatus TW200629392A (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2004371672 2004-12-22
JP2004371619 2004-12-22

Publications (1)

Publication Number Publication Date
TW200629392A true TW200629392A (en) 2006-08-16

Family

ID=36601870

Family Applications (1)

Application Number Title Priority Date Filing Date
TW094145477A TW200629392A (en) 2004-12-22 2005-12-21 Flattening method and flattening apparatus

Country Status (4)

Country Link
US (1) US20080121529A1 (en)
JP (1) JP2008524434A (en)
TW (1) TW200629392A (en)
WO (1) WO2006068283A1 (en)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5701736B2 (en) * 2011-12-20 2015-04-15 株式会社東芝 Flattening method and flattening apparatus
KR101531953B1 (en) * 2014-11-26 2015-06-29 (주)프론틱스 Portable Apparatus for Surface Inspection and Eletrolytic Polishing
US9633847B2 (en) * 2015-04-10 2017-04-25 Tokyo Electron Limited Using sub-resolution openings to aid in image reversal, directed self-assembly, and selective deposition
CN110804757B (en) * 2019-11-27 2024-02-20 镇江耐丝新型材料有限公司 Copper particle leveling tool used in copper plating tank

Family Cites Families (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5493152A (en) * 1993-11-09 1996-02-20 Vlsi Technology, Inc. Conductive via structure for integrated circuits and method for making same
JP4513145B2 (en) * 1999-09-07 2010-07-28 ソニー株式会社 Semiconductor device manufacturing method and polishing method
US6756307B1 (en) * 1999-10-05 2004-06-29 Novellus Systems, Inc. Apparatus for electrically planarizing semiconductor wafers
JP2001338926A (en) * 2000-05-29 2001-12-07 Sony Corp Method of manufacturing semiconductor device
JP2002093761A (en) * 2000-09-19 2002-03-29 Sony Corp Polishing method, polishing system, plating method and plating system
US7638030B2 (en) * 2001-06-18 2009-12-29 Ebara Corporation Electrolytic processing apparatus and electrolytic processing method
EP1423868A2 (en) * 2001-08-17 2004-06-02 ACM Research, Inc. Forming a semiconductor structure using a combination of planarizing methods and electropolishing
US20040253809A1 (en) * 2001-08-18 2004-12-16 Yao Xiang Yu Forming a semiconductor structure using a combination of planarizing methods and electropolishing
US20030146019A1 (en) * 2001-11-22 2003-08-07 Hiroyuki Hirai Board and ink used for forming conductive pattern, and method using thereof
CN100507092C (en) * 2002-03-25 2009-07-01 株式会社荏原制作所 Electrolytic processing apparatus and electrolytic processing method
JP2004111940A (en) * 2002-08-26 2004-04-08 Tokyo Seimitsu Co Ltd Polishing pad, polishing apparatus and polishing method using the same
WO2004034452A1 (en) * 2002-10-08 2004-04-22 Ebara Corporation Electrolytic processing apparatus
JP2004134601A (en) * 2002-10-11 2004-04-30 Tokyo Electron Ltd Wiring forming method
JP2004327561A (en) * 2003-04-22 2004-11-18 Ebara Corp Substrate processing method and device thereof
US7566391B2 (en) * 2004-09-01 2009-07-28 Micron Technology, Inc. Methods and systems for removing materials from microfeature workpieces with organic and/or non-aqueous electrolytic media

Also Published As

Publication number Publication date
JP2008524434A (en) 2008-07-10
US20080121529A1 (en) 2008-05-29
WO2006068283A1 (en) 2006-06-29

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