WO2007130452A1 - Removing barnier layer using an electron polishing process - Google Patents

Removing barnier layer using an electron polishing process Download PDF

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Publication number
WO2007130452A1
WO2007130452A1 PCT/US2007/010628 US2007010628W WO2007130452A1 WO 2007130452 A1 WO2007130452 A1 WO 2007130452A1 US 2007010628 W US2007010628 W US 2007010628W WO 2007130452 A1 WO2007130452 A1 WO 2007130452A1
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WIPO (PCT)
Prior art keywords
dielectric layer
layer
recessed area
electro
wafer
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Application number
PCT/US2007/010628
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French (fr)
Inventor
Hul Wang
Jian Wang
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Acm Research, Inc.
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Publication of WO2007130452A1 publication Critical patent/WO2007130452A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02041—Cleaning
    • H01L21/02057—Cleaning during device manufacture
    • H01L21/02068—Cleaning during device manufacture during, before or after processing of conductive layers, e.g. polysilicon or amorphous silicon layers
    • H01L21/02074—Cleaning during device manufacture during, before or after processing of conductive layers, e.g. polysilicon or amorphous silicon layers the processing being a planarization of conductive layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/32115—Planarisation
    • H01L21/3212—Planarisation by chemical mechanical polishing [CMP]
    • H01L21/32125—Planarisation by chemical mechanical polishing [CMP] by simultaneously passing an electrical current, i.e. electrochemical mechanical polishing, e.g. ECMP
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76819—Smoothing of the dielectric
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76835—Combinations of two or more different dielectric layers having a low dielectric constant
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/7684—Smoothing; Planarisation

Definitions

  • the present application generally relates to electro-polishing, and, more particularly, to removing a barrier layer using an electro-polishing process.
  • transistor devices are manufactured or fabricated on semiconductor wafers using a number of different processing steps to create transistor and interconnection elements.
  • conductive (e.g., metal) trenches, vias, and the like are formed in dielectric materials as part of the semiconductor device. The trenches and vias couple electrical signals and power between transistors, interna! circuit of the semiconductor devices, and circuits external to the semiconductor device.
  • the semiconductor wafer may undergo, for example, masking, etching, and deposition processes to form the desired electronic circuitry of the semiconductor devices.
  • multiple masking and etching steps can be performed to form a pattern of recessed areas in a dielectric layer on a semiconductor wafer that serve as trenches and vias for the interconnections.
  • a deposition process may then be performed to deposit a metal layer over the semiconductor wafer thereby depositing metal both in the trenches and vias and also on the non-recessed areas of the semiconductor wafer.
  • the metal deposited on the non-recessed areas of the semiconductor wafer is removed.
  • CMP chemical mechanical polishing
  • a wafer assembly is positioned on a CMP pad located on a platen or web.
  • the wafer assembly includes a substrate having one or more layers and/or features, such as interconnection elements formed in a dielectric layer.
  • a force is then applied to press the wafer assembly against the CMP pad.
  • the CMP pad and the substrate assembly are moved against and relative to one another while applying the force to polish and planarize the surface of the wafer.
  • a polishing solution often referred to as polishing slurry, is dispensed on the CMP pad to facilitate the polishing.
  • the polishing slurry typically contains an abrasive and is chemically reactive to selectively remove from the wafer the unwanted material, for example, a metal layer, more rapidly than other materials, for example, a dielectric material.
  • CMP methods can have several deleterious effects on the underlying semiconductor structure because of the relatively strong mechanical forces involved.
  • the mechanical properties of the conductive materials for example copper and the low k films used in typical damascene processes.
  • the Young Modulus of a low k dielectric film may be greater than 10 orders of magnitude lower than that of copper. Consequently, the relatively strong mechanical force applied on the dielectric films and copper in a CMP process, among other things, can cause stress related defects on the semiconductor structure that include delamination, dishing, erosion, film lifting, scratching, or the like.
  • a metal layer may be removed or etched from a wafer using an electro-polishing process.
  • an electro-polishing process the portion of the wafer to be polished is immersed within an electrolyte fluid solution and an electric charge is then applied to the wafer. These conditions result in copper being removed or polished from the wafer.
  • Barrier layers such as Tantalum, Tantalum nitride, Titanium, and Titanium nitride, cannot be electrically polished by phosphoric and sulfuric acid based electrolyte.
  • barrier layers are typically removed by plasma etch or chemical mechanical polishing (CMP).
  • plasma etching adds additional process step, and CMP damages low k dielectrics under the barrier layer.
  • a first dielectric layer is formed on a semiconductor wafer.
  • the first dielectric layer is resistant to being etched by hydrogen fluoride acid.
  • a second dielectric layer is formed above the first dielectric layer on the semiconductor wafer.
  • the second dielectric layer is susceptible to being etched by hydrogen fluoride acid.
  • the second dielectric layer is formed with a recessed area and a non-recessed area. The recessed area extends into the first dielectric layer.
  • a barrier layer is formed to cover the recessed area and the non-recessed area.
  • the metal layer is formed to fill the recessed area and cover the non-recessed area.
  • the metal layer and the barrier layer are electro-polished to expose the non-recessed area using an electrolyte containing hydrogen fluoride acid.
  • FIGs. IA-IC depict the result of an exemplary electro-polishing process
  • FIGs. 2A-2J depict the result of another exemplary electro-polishing process
  • FJGs. 3A-3I depict the result of another exemplary electro-polishing process
  • FIGs. 4A-4I depict the result of another exemplary electro-polishing process
  • FIGs. 5A-5J depict the result of another exemplary electro-polishing process
  • FIGs. 6 A-6J depict the result of another exemplary electro-pol ishing process
  • FIGs. 7 A-7I depict the result of another exemplary electro-pol ishing process.
  • FIGs. 8 A-8F arc block diagrams of exemplary electro-polishing tools.
  • FIGs. IA to 1C show the detail of the electro-polishing process using a nozzle.
  • the process is preferably performed from center of wafer 1114 to edge of wafer 1 114 with certain over-polishing amount as shown in FIGs. IA to 1C.
  • the electro-polishing current 1116 will easily flow through barrier layer 1112 and then to adjacent Cu film 11 10 and then to edge of wafer as shown in FlG. 1C.
  • barrier layer surrounding copper trench 1120 is being removed by the electro-polishing process, copper and barrier metal in structure 1120 lose the electrical path. Therefore, the electro-polishing process on structure 1120 automatically stops as shown in FIG. 1C.
  • Hydrogen fluoride (HF) acid (49% wt): 10 ml, range between 4 to 40 ml; Phosphoric acid H3PO4 (85% wt): 200 ml, range between 0 to 300 ml; Sulfuric acid H3SO4 (98% wt): 60 ml, range between 0 to 80 ml; Ethylene Glycol: 100 ml, range between 0 to 200 ml; and Glycerin: 50 ml, range between 0 to 100 ml.
  • HF Hydrogen fluoride
  • HF hydrogen fluoride
  • HF acid can be combined with other salt, such as A1C13, ZnC12, MgC12, CrO3, (NH4)HPO4, (NH4)2SO4, NH4F, NH4NO3, and acid, such as HNO3, HCl, HC1O4, and surfactant, such as Benzotriazole (C6H5N3).
  • salt such as A1C13, ZnC12, MgC12, CrO3, (NH4)HPO4, (NH4)2SO4, NH4F, NH4NO3, and acid, such as HNO3, HCl, HC1O4, and surfactant, such as Benzotriazole (C6H5N3).
  • HF acid resistant dielectric materials 1 114 such as Polyimide, fluorinated polyimides, polyimide nanofoams, parylene N, Poly(arylene ethers), Poly(arylenes), polynaphthalene family, aromatic hydrocarbon (SiLK), amorphous carbon film, Teflon-AF, Teflon microemulsion, and the like.
  • silicon oxide based dielectrics are used, then those silicon oxide based dielectrics are preferably covered by another layer of dielectrics with highly HF resistance or blocking performance to form hybrid structures (to be described below with reference to FlGs. 3A to 31).
  • FIGs. 2A to 2 I Another exemplary embodiment to remove barrier is shown in FIGs. 2A to 2 I. The process steps are listed as follows:
  • Step I Deposit the first dielectric layer 2006 on an existing dielectric layer 2012 formed in the previous metal layer as shown in FIG. 2A.
  • Such existing dielectric layer 2012 is made of silicon carbide (SiC), silicon carbide nitride (SiCN) or other dielectric materials with highly HF resistance or HF blocking performance.
  • Deposition method can be chemical vapor deposition (CVD) or spin on dielectric method.
  • Dielectric layer 2006 includes Polyimides, fluorinated polyimides, polyimide nanofoams, parylene N, Poly(arylene ethers), Poly(arylenes), polynaphthalene family, aromatic hydrocarbon (SiLK), amorphous carbon film, Teflon-AF, Teflon microemulsion or other low k dielectrics, or ultra low k dielectrics with high HF acid resistance.
  • Step 2 Deposit the second dielectric layer 2001 above the first dielectric layer 2006 as shown in FIG. 2A.
  • the second dielectric layer 2001 can be silicon oxide, silicon oxide based dielectrics, fluorinated silica, carbon doped silica, and nonporous silica.
  • the second dielectrics can be any dielectric material, which is susceptible to being etched by HF acid.
  • Step3 Etch via 2010 and trench 2009 by plasma as shown in FIG. 2B.
  • barrier layer 2004 is made of Tantalum, Tantalum nitride, Titanium, Titanium nitride, Tungsten, Tungsten nitride, Ruthenium, Ruthenium nitride, Zirconium, Niobium, Molybdenum, Technetium, Rhodium, Palladium, Hafnium, Rhenium, Osmium, and Iridium.
  • Step 5 Plate Cu layer 2002 to fill via and trench as shown in FIG.2D.
  • the plated Cu layer can be further planarized by chemical mechanical polishing (CMP) as disclosed in PCT Patent Application No. PCT/US02/26167 and U.S. Patent Application Serial No. 10/486,982, which are incorporated here by reference in their entireties for all purposes, or can be formed by the flat plating using dummy structure as disclosed in PCT Patent Application No. PCT/US03/11417 and U.S. Patent Application No. 10/510,656, which are incorporated hereby reference in their entireties, or can be electro-polished with contacting pad nozzle disclosed in US Provisional Application Serial No. 60/738,250, which is incorporated herein by reference in its entirety.
  • CMP chemical mechanical polishing
  • Step 6 Remove Cu layer using the electro-polishing process described above with reference to FIGs. 1 A-IC and the apparatus to be described below with reference to FIGs. 8A-8F.
  • FIG. 2E shows the cross section of a Cu interconnect structure just as the Cu layer 2002 is being removed from barrier layer 2005 by using the electro-polishing process.
  • the Cu film in the trench will start to recess, and barrier layer will be removed away as shown in FIG. 2F.
  • the electro-polishing current will stop due to the absence of a conducting path.
  • the barrier residual 2015 may remain on the surface of the second dielectric layer 2001 as shown in FIG. 2F. It is recommended to use constant voltage to perform the above electro-polishing process.
  • the second dielectric layer 2001 is made of silicon oxide, silicon oxide based dielectrics, fluorinated silica, carbon doped silica, and nonporous silica, which is susceptible to being etched away by HF acid. Therefore, the second dielectric layer is etched away by HF acid in the electrolyte as shown in FIG. 2G. As the etching process continues, eventually the barrier residual 2015 will be removed due to undercut etching of dielectrics 2021 underneath as shown in FIGs. 2G and 2H. [0034] After the electro-polishing, the wafer will be transferred to a cleaning cell for removing all chemicals.
  • the additional HF based chemical can be further injected on the wafer surface to etch away barrier residual in case of some barrier residuals are not fully removed in the electro-polishing cell.
  • the etching rate of Tantalum is around 1.5nm/min.
  • HF concentration is in the range of 1% wt to 10% wt.
  • Citric acid (C6H8O7) 0.5% wt can be also added in the cleaning process to remove Copper oxide. Citric acid concentration is in the range of 0.1 %wt to 1% wt. Then the wafer is further cleaned by pure DI water.
  • Step 7 Deposit SiC or SiCN layer 2008 above Cu 2002 and dielectric layer 2006 as shown in FIG. 21.
  • Step 8 Repeat step 1 to step 7 to form another layer of interconnect layer as shown in FIG. 2J.
  • FIGs. 3A to 3 I Another exemplary embodiment to remove the barrier is shown in FIGs. 3A to 3 I. The process steps are listed as follows:
  • Step 1 Deposit the first dielectric layer 3052, and deposit the second dielectric layer (etching stop ⁇ layer) 3050 as shown in FIG. 3A.
  • Deposition method can be chemical vapor deposition (CVD) or spin on dielectric method.
  • the first dielectric layer 3052 includes silicon dioxide, fluorosilicate glass (FSG), HSSQ, diamond-like carbon, carbon-doped SiO2, MSSQ, and nonporous silica.
  • the second dielectric layer 3050 is primarily used to stop the etching process between via and trench during plasma etching.
  • the second function of the second dielectric layer 3050 is to block the HF or Fluorine atom/ion diffused through the third dielectric layer 3006 (to be described below) from reaching the first dielectric layer 3052 during later electro-polishing process, which will be described in detail below with reference to FIG. 3G. It is clear that HF or Fluorine ion will destroy the first dielectric layer 3052 if it penetrates the second dielectric layer 3050.
  • the second dielectric layer 3050 includes silicone carbide (SiC), and Silicon carbide nitride SiCN, or other dielectric materials with high HF acid resistance and blocking performance. In other words, neither HF nor Fluorine atom/ion should penetrate through the second dielectrics being selected.
  • Step 2 Deposit the third dielectric layer 3006 above the second dielectric layer 3050 as shown in FIG. 3A.
  • Deposition method can be chemical vapor deposition (CVD) or spin on dielectric method.
  • the third dielectric layer 3006 include Polyimides, fluorinated polyimides, polyimide nanofoams, parylene N, Poly(arylene ethers), Poly(arylenes), polynaphthalene family, aromatic hydrocarbon (SiLK), amorphous carbon film, Teflon-AF, Teflon microemulsion or other low k dielectrics, or ultra low k dielectrics with high HF acid resistance.
  • Step 3 Deposit the fourth dielectric layer (or sacrificial layer) 3001 above the third dielectric layer 3006 as shown in FIG. 3A.
  • the fourth dielectric layer 3001 can be silicon oxide, silicon oxide based dielectrics, fluorinated silica, carbon doped silica, and nonporous silica.
  • the fourth dielectric layer 3001 should be selected to be able to be etched away by HF acid.
  • Step 4 Deposit additional mask layers for fabricating dual damascene structure. The details of the lithography steps are well known in state of art, and will not be described here.
  • Step5 Etch via 3010 and trench 3009 by plasma, and strip the photo resist as shown in FlG. 3B.
  • Step 6 Deposit barrier layer 3004 and Cu seed layer 3003 as shown in FIG. 3C.
  • barrier layer 3004 is made of single or combination of metal layers such Tantalum, Tantalum Nitride, Titanium, Titanium Nitride, Tungsten, Tungsten nitride, Ruthenium, Zirconium, Niobium, Molybdenum, Technetium, Rhodium, Palladium, Hafnium, Rhenium, Osmium, and Indium.
  • Step 7 Plate Cu layer 3002 to fill via and trench as shown in FIG. 3D.
  • the plated Cu layer can be further planarized by chemical mechanical polishing (CMP) as disclosed in PCT Patent Application No. PCT/US02/26167 and U.S. Patent Application Serial No. 10/486,982, which are incorporated here by reference in their entireties for all purposes, or can be formed by the flat plating using dummy structure as disclosed in PCT Patent Application No. PCT/US03/11417 and U.S. Patent Application No. 10/510,656, which are incorporated hereby reference in their entireties, or can be electro-polished with contacting pad nozzle disclosed in US Provisional Application Serial No. 60/738,250, which is incorporated herein by reference in its entirety.
  • CMP chemical mechanical polishing
  • Step 8 Remove Cu layer using the electro-polishing process described above with reference to FIGs. IA-I C and the apparatus to be described below with reference to FIGs. 8A-8F.
  • FIG. 3E shows the cross section of a Cu interconnect structure just as the Cu layer 3002 is being removed from barrier layer 3005 by using the electro-polishing process.
  • the Cu film in the trench will start to recess, and barrier layer will be removed away as shown in FlG. 3F.
  • the electro-polishing current will stop due to the absence of a conducting path.
  • the barrier residual 3015 may remain on the surface of the dielectric layer 3001 as shown in FIG. 3F due to the same reason. It is recommended to use constant voltage to perform the above electro-polishing process.
  • the fourth dielectric layer 3001 is made of silicon oxide, silicon oxide based dielectrics, fluorinated silica, carbon doped silica, and nonporous silica, which i susceptible to being etched away by HF acid. Therefore, the fourth dielectric layer is etched away by HF acid in the electrolyte as shown in FIG. 3G. As the etching process continues, eventually the barrier residual 3015 will be removed due to undercut etching of dielectrics 3021 underneath as shown in FIGs. 3G and 3H.
  • the wafer will be transferred to a cleaning cell for removing all chemicals.
  • the additional HF based chemical can be further injected on the wafer surface to etch away barrier residual in case of some barrier residuals are not fully removed in the electro-polishing cell.
  • the etching rate of Tantalum is around 1.5nm/min.
  • HF concentration is in the range of 1% wt to 10% wt.
  • Citric acid (C6H8O7) 0.5% wt can be also added in the cleaning process to remove Copper oxide. Citric acid concentration is in the range of 0.1 %wt to 1% wt. Then the wafer is further cleaned by pure DI water.
  • Step 9 Deposit SiC or SiCN layer 3008 above Cu 3002 and dielectric layer 3006 as shown in FIG. 31.
  • Step 10 Repeat step 1 to step 9 to form another layer of interconnect layer (not shown here).
  • Step 1 Deposit the first dielectric layer 4052, deposit the second dielectric layer (etching stop layer) 4050, and deposit the third dielectric layer 4006 as shown in FIG. 4A.
  • Deposition method can be chemical vapor deposition (CVD) or spin on dielectric method.
  • the first and the third dielectric layers include Polyimides, fluorinated polyimides, polyimide nanofoams, parylene N, Poly(arylene ethers), Poly(arylenes), polynaphthalene family, aromatic hydrocarbon (SiLK), amorphous carbon film, Teflon-AF, Teflon microemulsion or other low k dielectrics, or ultra low k dielectrics with high HF acid resistance.
  • the second dielectric layer 4050 is primarily used for the clean etch stop between via and trench during plasma etching. The second function of the second dielectric layer is to block the HF or Fluorine atom/ion diffused through the third dielectric layer 4006 during later electro-polishing process, which will be described in detail below with reference to FIG.
  • the second dielectric material 4050 include silicone carbide (SiC), silicon carbide nitride (SiCN), or other dielectric materials with high HF acid resistance and blocking performance. In other words, neither HF nor Fluorine atom/ion should penetrate through the second dielectrics being selected.
  • Step 2 Deposit the fourth dielectric layer 4001 above the third dielectric layer 4006 as shown in FIG. 4A.
  • the fourth dielectric layer 4001 can be silicon oxide, silicon oxide based dielectrics, fluorinated silica, carbon doped silica, and nonporous silica.
  • the fourth dielectric layer 4001 should be selected to be susceptible to being etched by HF acid.
  • Step 3 Deposit additional mask layers for fabricating dual damascene structure. The details of the lithographic steps are well known in state of art, and will not be described here.
  • Step4 Etch via 4010 and trench 4009 by plasma as shown in FIG. 4B.
  • barrier layer 4004 is made of Tantalum, Tantalum Nitride, Titanium, Titanium Nitride, Tungsten, Tungsten Nitride, Ruthenium, Zirconium, Niobium, Molybdenum, Technetium, Rhodium, Palladium, Hafnium, Rhenium, Osmium, and Indium.
  • Step 6 Plate Cu layer 4002 to fill via and trench as shown in FIG. 4D.
  • the plated Cu layer can be further planarized by chemical mechanical polishing (CMP) as disclosed in PCT Patent Application No. PCT/US02/26167 and U.S. Patent Application Serial No. 10/486,982, which are incorporated here by reference in their entireties for all purposes, or can be formed by the flat plating using dummy structure as disclosed in PCT Patent Application No. PCT/US03/11417 and U.S. Patent Application No. 10/510,656, which are incorporated hereby reference in their entireties, or can be electro-polished with contacting pad nozzle disclosed in US Provisional Application Serial No. 60/738,250, which is incorporated herein by reference in its entirety.
  • CMP chemical mechanical polishing
  • Step 7 Remove Cu layer using the electro-polishing process described above with reference to FIGs. 1 A-IC and the apparatus to be described below with reference to FIGs. 8A-8F.
  • FIG. 4E shows the cross section of a Cu interconnect structure just as the Cu layer 4002 is being removed from barrier layer 4005 by using the electro-polishing process.
  • the Cu film in the trench will start to recess, and barrier layer will be removed away as shown in FIG. 4F.
  • the electro-polishing current will stop due to the absence of a conducting path.
  • the barrier residual 4015 may remain on the surface of the second dielectric layer 4001 as shown in FIG. 4F. It is recommended to use constant voltage to perform the above electro-polishing process.
  • the fourth dielectric layer 4001 is made of silicon oxide, silicon oxide based dielectrics, fluorinated silica, carbon doped silica, and nonporous silica, which is susceptible to being etched away by HF acid. Therefore, the fourth dielectric layer is etched away by HF acid in the electrolyte as shown in FIG. 4G, As the etching process continues, eventually the barrier residual 4015 will be removed due to undercut etching of dielectrics 4021 underneath as shown in FIGs. 4G and 4H.
  • the wafer will be transferred to a cleaning cell for removing all chemicals.
  • the additional HF based chemical can be further injected on the wafer surface to etch away barrier residual in case of some barrier residuals are not fully removed in the electro-polishing cell.
  • the etching rate of Tantalum is around 1.5nm/min.
  • HF concentration is in the range of 1% wt to 10% wt.
  • Citric acid (C6H8O7) 0.5% wt can be also added in the cleaning process to remove Copper oxide. Citric acid concentration is in the range of 0.1%wt to 1% wt. Then the wafer is further cleaned by pure DI water.
  • Step 8 Deposit SiC or SiCN layer 4008 above Cu 4002 and dielectric layer 4006 as shown in FIG. 41.
  • Step 9 Repeat step 1 to step 8 to form another layer of interconnect layer (not shown here).
  • FIGs. 5A to 5 J Another exemplary embodiment to remove the barrier layer is shown in FIGs. 5A to 5 J. The process steps are listed as follows:
  • Step 1 Deposit the first dielectric layer 5006 on an existing dielectric layer 5012 formed in the previous metal layer, and deposit the second dielectric layer 5007 as shown in FIG. 5A.
  • Such existing dielectric layer 5012 is made of silicon carbide (SiC), silicon carbide nitride (SiCN) or other dielectric materials with highly HF resistance or HF blocking performance.
  • Deposition method can be chemical vapor deposition (CVD) or spin on dielectric method.
  • the first dieletric layer 5006 includes Polyimides, fluorinated polyimides, polyimide nanofoams, parylene N, Poly(arylene ethers), Poly(arylenes), polynaphthalene family, aromatic hydrocarbon (SiLK), amorphous carbon film, Teflon-AF, Teflon microemulsion, silicon oxide, fluorine doped silicon oxide, organo silicate materials such as Aurora, Black Diamond, and Coral, Spin-on-MSQ/HSQ, or other low k dielectrics, or ultra low k dielectrics.
  • the second dielectric layer 5007 is primarily used for preventing electrolyte from attacking the first layer dielectric 5006.
  • the second dielectric material 5007 includes silicone carbide (SiC), silicon carbide nitride (SiCN), aluminum oxide (A12O3) or other dielectric materials with high HF acid resistance and blocking performance. In other words, the neither HF nor Fluorine atom/ion should penetrate through the second dielectrics being selected.
  • Step 2 Deposit the third dielectric layer 5001 with thickness of H above the second dielectric layer 5007 as shown in FIG. 5 A.
  • the third dielectric layer 5001 can be silicon oxide, silicon oxide based dielectrics, fluorinated silica, carbon doped silica, and nonporous silica.
  • the third dielectric layer 5001 should be selected to be susceptible to being etched by HF acid.
  • Step 3 Spin on photo resist, and the details of the lithography steps are well known in state of art, and will not be described here.
  • Step4 Etch via 5010 and trench 5009 by plasma as shown in FIG. 5B.
  • barrier layer 5004 deposits barrier layer 5004 and Cu seed layer 5003 as shown in FIG. 5C.
  • barrier layer 5004 is made of Tantalum, Tantalum Nitride, Titanium, Titanium Nitride, Tungsten, Tungsten Nitride, Ruthenium, Zirconium, Niobium, Molybdenum, Technetium, Rhodium, Palladium, Hafnium, Rhenium, Osmium, and Indium.
  • Step 6 Plate Cu layer 5002 to fill via and trench as shown in FIG. 5D.
  • the plated Cu layer can be further planarized by chemical mechanical polishing (CMP) as disclosed in PCT Patent Application No. PCT/US02/26167 and U.S. Patent Application Serial No. 10/486,982, which are incorporated here by reference in their entireties for all purposes, or can be formed by the flat plating using dummy structure as disclosed in PCT Patent Application No. PCT/US03/11417 and U.S. Patent Application No. 10/510,656, which are incorporated hereby reference in their entireties, or can be electro-polished with contacting pad nozzle disclosed in US Provisional Application Serial No. 60/738,250, which is incorporated herein by reference in its entirety.
  • CMP chemical mechanical polishing
  • Step 7 Remove Cu layer using the electro-polishing process described above with reference to FIGs. IA-I C and the apparatus to be described below with reference to FIGs. 8A-8F.
  • FIG. 5E shows the cross section of a Cu interconnect structure just as the Cu layer 5002 is being removed from barrier layer 5005 by using the electro-polishing process.
  • the Cu film in the trench will start to recess, and barrier layer will be removed awayi ⁇ BfSr ⁇ fi S jn FIG. 5F.
  • the electro-polishing process will stop due to the absence of a current conducting path.
  • both Cu inside the trench 5002 and barrier layer between Cu trench and dielectrics will be isolated from the electro-polishing process, or the polishing process will self terminate.
  • the barrier residual 5015 may remain on the surface of the third dielectric layer 5001 as shown in FIG. 5F. It is recommended to use constant voltage to perform the above electro-polishing process.
  • the third dielectric layer 5001 is made of silicon oxide, silicon oxide based dielectrics, fluorinated silica, carbon doped silica, and nonporous silica, which is susceptible to being etched away by HF acid. Therefore, the fourth dielectric layer is etched away by HF acid in the electrolyte as shown in FIG. 5G. As the etching process continues, eventually the barrier residual 5015 will be removed due to undercut etching of dielectrics 5021 underneath as shown in FIGs. 5G and 5H.
  • the second dielectric layer 5007 is made of silicone carbide (SiC), silicon carbide nitride (SiCN), aluminum oxide (A12O3) or other dielectric materials with high HF acid resistance and blocking performance. Therefore the first dielectric layer 5006 underneath the second dielectric layer is protected from being attacked by the electrolyte mainly HF. Thickness of the second dielectric layer is in the range of 5 nm to 100 nm, depending on semiconductor manufacture node.
  • the Cu trench recess D as shown in FIG. 5F should be controlled to be equal to thickness H of the third dielectric layer 5001.
  • the Cu recess D can be controlled by the removal rate ratio of barrier layer to Cu metal.
  • HF concentration in electrolyte determines the removal rate ratio of barrier layer to Cu metal layer. For example, within 5% wt HF concentration, the removal rate ratio of barrier layer (Ta and or TaN) to Cu metal layer is almost proportional to HF concentration.
  • the process should be performed as follows:
  • the HF concentration should be determined to make sure minimum Cu recess and at the same time all Cu residual being removed before the barrier layer being removed.
  • the minimum Cu recess can be in the range of 2 to 10 times of thickness of barrier layer 5004;
  • the thickness of the third dielectric layer is equal to the minimum of Cu trench recess.
  • the thickness of barrier layer is 7 nm.
  • the Cu recess will be around 30 nm if 5% wt HF concentration is .used in a phosphoric/Sulfuric acid/Ethylene Glycol/Glycerin based electrolyte. Therefore the thickness of third dielectric layer 5001 should be designed around 30 nm.
  • the thickness of barrier layer is 7 nm.
  • the Cu recess will be around 60 nm if 2.5% wt HF concentration is used in a phosphoric/Sulfuric acid/Ethylene Glycol/Glycerin based electrolyte. Therefore the thickness of third dielectric layer 5001 should be designed around 60 nm.
  • the wafer will be transferred to a cleaning cell for removing all chemicals.
  • the additional HF based chemical can be further injected on the wafer surface to etch away barrier residual in case of some barrier residuals are not fully removed in the electro-polishing cell.
  • the etching rate of Tantalum is around 1.5nm/min.
  • HF concentration is in the range of 1% wt to 10% wt.
  • Citric acid (C6H8O7) 0.5% wt can be also added in the cleaning process to remove Copper oxide. Citric acid concentration is in the range of 0.1%wt to 1% wt. Then the wafer is further cleaned by pure DI water.
  • Step 8 Deposit SiC or SiCN layer 5008 above Cu 5002 and the second dielectric layer 5007 as shown in FIG. 51.
  • Step 9 Repeat step 1 to step 8 to form another layer of interconnect layer as shown in FIG. 5J.
  • FIGs. 6A to 61 Another exemplary embodiment to remove the barrier layer is shown in FIGs. 6A to 61. The process steps are listed as follows:
  • Step 1 Deposit the first dielectric layer 6052, and deposit the second dielectric layer 6006, and deposit the third dielectric layer 6007 as shown in FIG. 6A.
  • Deposition method can be chemical vapor deposition (CVD) or spin on dielectric method.
  • the first dielectric layer 6052 and the second dielectric layer 6006 include Polyimides, fluorinated polyimides, polyimide nanofoams, parylene N, Poly(arylene ethers), Poly(arylenes), polynaphthalene family, aromatic hydrocarbon (SiLK.), amorphous carbon film, Teflon-AF, Teflon microemulsion, silicon oxide, fluorine doped silicon oxide, organo silicate materials such as Aurora, Black Diamond, and Coral, Spin-on-MSQ/HSQ, or other low k dielectrics, or ultra low k dielectrics.
  • the third dielectric layer 6007 is primarily used for preventing electrolyte from attacking the second dielectric layer 6006.
  • the third dielectric material 6007 includes silicone carbide (SiC), silicon carbide nitride (SiCN), aluminum oxide (A12O3) or other dielectric materials with high HF acid resistance and blocking performance. In other words, neither HF nor Fluorine atom/ion should penetrate through the second dielectrics being selected.
  • Step 2 Deposit the fourth dielectric layer 6001 with thickness of H above the third dielectric layer 6007 as shown in FIG. 6A.
  • the fourth dielectric layer 6001 can be silicon oxide, silicon oxide based dielectrics, fluorinated silica, carbon doped silica, and nonporous silica.
  • the fourth dielectric layer 6001 should be selected to be able to be etched by HF acid.
  • Step 3 Spin on photo resist, and the details of the lithography steps are well known in state of art, and will not be described here.
  • Step4 Etch via 6010 and trench 6009 by plasma as shown in FIG. 6B.
  • barrier layer 6004 is made of Tantalum, Tantalum Nitride, Titanium, Titanium Nitride, Tungsten, Tungsten Nitride, Ruthenium, Zirconium, Niobium, Molybdenum, Technetium, Rhodium, Palladium, Hafnium, Rhenium, Osmium, and Iridium.
  • Step 6 Plate Cu layer 6002 to fill via and trench as shown in FIG. 6D.
  • the plated Cu layer can be further planarized by chemical mechanical polishing (CMP) as disclosed in PCT Patent Application No. PCT/US02/26167 and U.S. Patent Application Serial No. 10/486,982, which are incorporated here by reference in their entireties for all purposes, or can be formed by the flat plating using dummy structure as disclosed in PCT Patent Application No. PCT/US03/1 1417 and U.S. Patent Application No. 10/510,656, which are incorporated hereby reference in their entireties, or can be electro-polished with contacting pad nozzle disclosed in US Provisional Application Serial No. 60/738,250, which is incorporated herein by reference in its entirety.
  • CMP chemical mechanical polishing
  • Step 7 Remove Cu layer using the electro-polishing process described above with reference to FIGs. 1 A-IC and the apparatus to be described below with reference to FIGs. 8A-8F.
  • FIG. 6E shows the cross section of a Cu interconnect structure just as the Cu layer 6002 is being removed from barrier layer 6004 by using the electro-polishing process.
  • the Cu film in the trench will start to recess, and barrier layer will be removed away as shown in FIG. 6F.
  • the electro-polishing process will stop due to the absence of a current conducting path.
  • both Cu inside the trench 6002 and barrier layer between Cu trench 6002 and dielectrics will be isolated from the electro-polishing process, or the polishing process will self-terminate.
  • the barrier residual 6015 may remain on the surface of the fourth dielectric layer 6001 as shown in FIG. 6F. It is recommended to use constant voltage to perform the above electro-polishing process.
  • the fourth dielectric layer 6001 is made of silicon oxide, silicon oxide based dielectrics, fluorinated silica, carbon doped silica, and nonporous silica, which can be etched away by HF acid. Therefore, the fourth dielectric layer is etched away by HF acid in the electrolyte as shown in FIG. 6G. As the etching process continues, eventually the barrier residual 6015 will be removed due to undercut etching of dielectrics 6021 underneath as shown in FIGs. 6G and 6H.
  • the third dielectric layer 6007 is made of silicone carbide (SiC), silicon carbide nitride (SiCN), aluminum oxide (AI2O3) or other dielectric materials with high HF acid resistance and blocking performance.
  • Thickness of the third dielectric layer 6007 is in the range of 5 nm to 100 nm, depending on semiconductor manufacture node.
  • the Cu trench recess D as shown in FIG. 6F should be controlled to be equal to thickness H of the fourth dielectric layer 6001.
  • the Cu recess D can be controlled by the removal rate ratio of barrier layer to Cu metal. More particularly, HF concentration in electrolyte determines the removal rate ratio of barrier layer to Cu metal layer. For example, within 5% wt HF concentration, the removal rate ratio of barrier layer (Ta and or TaN) to Cu metal layer is almost proportional to HF concentration. Thus, the process should be performed as follows:
  • the HF concentration should be determined to make sure minimum Cu recess and at the same time all Cu residual being removed before the barrier layer being removed.
  • the minimum Cu recess can be in the range of 2 to 10 times of thickness of barrier layer 6004;
  • the thickness of the fourth dielectric layer is equal to the minimum of Cu trench recess.
  • the thickness of barrier layer is 7 nm.
  • the Cu recess will be around 30 nm if 5% wt HF concentration is used in a phosphoric/Sulfuric acid/Ethylene Glycol/Glycerin based electrolyte. Therefore the thickness of fourth dielectric layer 6001 should be designed around 30 nm.
  • the thickness of barrier layer is 7 nm.
  • the Cu recess will be around 60 nm if 2.5% wt HF concentration is used in a phosphoric/Sulfuric acid/Ethylene Glycol/Glycerin based electrolyte. Therefore the thickness of fourth dielectric layer 6001 should be designed around 60 nm.
  • HF concentration range should be in the range of 0.5% wt to 5% wt.
  • the wafer will be transferred to a cleaning cell for removing all chemicals.
  • the additional HF based chemical can be further injected on the wafer surface to etch away barrier residual in case of some barrier residuals are not fully removed in the electro-polishing cell.
  • the etching rate of Tantalum is around 1.5nm/min.
  • HF concentration is in the range of 1% wt to 10% wt.
  • Citric acid (C6H8O7) 0.5% wt can be also added in the cleaning process to remove Copper oxide. Citric acid concentration is in the range of 0.1 %wt to 1% wt. Then the wafer is further cleaned by pure Dl water.
  • Step 8 Deposit SiC or SiCN layer 6008 above Cu 6002 and the third dielectric layer 6007 as shown in FIG. 6J.
  • Step 9 Repeat step 1 to step 8 to form another layer of interconnect layer (not shown here).
  • FIGs. 7A to 71 Another exemplary embodiment to remove the barrier layer is shown in FIGs. 7A to 71. The process steps are listed as follows:
  • Step 1 Deposit the first dielectric layer 7052, deposit the second dielectric layer 7050, deposit the third dielectric layer 7006, and deposit the fourth dielectric layer 7007 as shown in FlG. 7A.
  • Deposition method can be chemical vapor deposition (CVD) or spin on dielectric method.
  • the first dielectric layer 7052 includes silicon dioxide, fluorosilicate glass (FSG), HSSQ, diamond-like carbon, carbon-doped SiO2, MSSQ, and nonporous silica.
  • the second dielectric layer 7050 is primarily used for the etch stop between via and trench during plasma etching.
  • the second function of the second dielectric layer 7050 is to block the HF or Fluorine atom/ion diffused through the third dielectric layer 7006 (to be described below) from reaching the first dielectric layer 7052 during later electro-polishing process, which will be described in detail below with reference to FIG. 7G. It is clear that HF or Fluorine ion will destroy the first dielectric layer 7052 if they penetrate the second dielectric layer 7050.
  • the second dielectric layer 7050 includes silicone carbide (SiC), Silicon carbide nitride (SiCN), or other dielectric materials with high HF acid resistance and blocking performance. In other words, neither HF nor Fluorine atom/ion should penetrate through the second dielectrics being selected.
  • the third dielectric layer 7006 include Polyimides, fluorinated polyimides, polyimide nanofoams, parylene N, Poly(arylene ethers), Poly(arylenes), polynaphthalene family, aromatic hydrocarbon (SiLK), amorphous carbon film, Teflon- AF, Teflon microemulsion, or other low k dielectrics, or ultra low k dielectrics.
  • the fourth dielectric layer 7007 is primarily used for preventing electrolyte from attacking the third dielectric layer 7006.
  • the fourth dielectric material 7007 includes silicone carbide (SiC), silicon carbide nitride (SiCN), aluminum oxide (A12O3) or other dielectric materials with high HF acid resistance and blocking performance. In other words, neither HF nor Fluorine atom/ion should penetrate through the fourth dielectrics being selected.
  • Step 2 Deposit the fifth dielectric layer 7001 with thickness of H above the fourth dielectric layer 7007 as shown in FIG. 7A.
  • the fifth dielectric layer 7001 can be silicon oxide, silicon oxide based dielectrics, fluorinated silica, carbon doped silica, and nonporous silica.
  • the fifth dielectric layer 7001 should be selected to be susceptible to being etched by HF acid.
  • Step 3 Spin on photo resist, and the details of the lithography steps are well known in state of art, and will not be described here.
  • Step4 Etch via 7010 and trench 7009 by plasma as shown in FIG. 7B.
  • Step 5 Deposit barrier layer 7004 and Cu seed layer 7003 as shown in FIG. 1C.
  • barrier layer 7004 is made of Tantalum, Tantalum Nitride, Titanium, Titanium Nitride, Tungsten, Tungsten Nitride, Ruthenium, Zirconium, Niobium, Molybdenum, Technetium, Rhodium, Palladium, Hafnium, Rhenium, Osmium, and Iridium.
  • Step 7 Plate Cu layer 7002 to fill via and trench as shown in FIG. 7D.
  • the plated Cu layer can be further planarized by chemical mechanical polishing (CMP) as disclosed in PCT Patent Application No. PCT/US02/26167 and U.S. Patent Application Serial No. 10/486,982, which are incorporated here by reference in their entireties for all purposes, or can be formed by the flat plating using dummy structure as disclosed in PCT Patent Application No. PCT/US03/11417 and U.S. Patent Application No. 10/510,656, which are incorporated hereby reference in their entireties, or can be electro-polished with contacting pad nozzle disclosed in US Provisional Application Serial No. 60/738,250, which is incorporated herein by reference in its entirety.
  • CMP chemical mechanical polishing
  • Step 7 Remove Cu layer using the electro-polishing process described above with reference to FIGs. IA-I C and the apparatus to be described below with reference to FIGs. 8A-8F.
  • FIG. 7E shows the cross section of a Cu interconnect structure just as the Cu layer 7002 is being removed from barrier layer 7004 by using the electro-polishing process.
  • the Cu film in the trench will start to recess, and barrier layer will be removed away as shown in FIG. 7F.
  • the electro-polishing process will stop due to the absence of a current conducting path.
  • both Cu inside the trench 7002 and barrier layer between Cu trench 7002 and dielectrics will be isolated from the electro-polishing process, or the polishing process will self-terminate.
  • the barrier residual 7015 may remain on the surface of the fourth dielectric layer 7001 as shown in FIG. 7F. It is recommended to use constant voltage to perform the above electro-polishing process.
  • the fifth dielectric layer 7001 is made of silicon oxide, silicon oxide based dielectrics, fluorinated silica, carbon doped silica, and nonporous silica, which can be etched away by HF acid. Therefore, the fifth dielectric layer is etched away by HF acid in the electrolyte as shown in FIG. 7G. As the etching process continues, eventually the barrier residual 7015 will be removed due to undercut etching of dielectrics 7021 underneath as shown in FIGs. 7G and 7H.
  • the fourth dielectric layer 7007 is made of silicone carbide (SiC), silicon carbide nitride (SiCN), aluminum oxide (A12O3) or other dielectric materials with high HF acid resistance and blocking performance.
  • Thickness of the fourth dielectric layer 7007 is in the range of 5 nm to 100 ⁇ m, depending on semiconductor manufacture node.
  • the Cu trench recess D as shown in FlG. 7F should be controlled to be equal to thickness H of the third dielectric layer 7001.
  • the Cu recess D can be controlled by the removal rate ratio of barrier layer to Cu metal. More particularly, HF concentration in electrolyte determines the removal rate ratio of barrier layer to Cu metal layer. For example within 5% wt HF concentration, the removal rate ratio of barrier layer (Ta and or TaN) to Cu metal layer is almost proportional to HF concentration. Thus, the process should be performed as follows: a.
  • the HF concentration should be determined to make sure minimum Cu recess and at the same time all Cu residual being removed before the barrier layer being removed.
  • the minimum Cu recess can be in the range of 2 to 10 times of thickness of barrier layer 7004;
  • the thickness of the fifth dielectric layer is equal to the minimum of Cu trench recess.
  • the thickness of barrier layer is 7 nm.
  • the Cu recess will be around 30 nm if 5% wt HF concentration is used in a phosphoric/Sulfuric acid/Ethylene Glycol/Glycerin based electrolyte. Therefore the thickness of fifth dielectric layer 7001 should be designed around 30 nm.
  • the thickness of barrier layer is 7 nm.
  • the Cu recess will be around 60 nm if 2.5% wt HF concentration is used in a phosphoric/Sulfuric acid/Ethylene Glycol/Glycerin based electrolyte. Therefore the thickness of fifth dielectric layer 7001 should be designed around 60 nm.
  • the wafer will be transferred to a cleaning cell for removing all chemicals.
  • the additional HF based chemical can be further injected on the wafer surface to etch away barrier residual in case of some barrier residuals are not fully removed in the electro-polishing cell.
  • the etching rate of Tantalum is around 1.5nm/mi ⁇ .
  • HF concentration is in the range of 1% wt to 10% wt.
  • Citric acid (C6H8O7) 0.5% wt can be also added in the cleaning process to remove Copper oxide. Citric acid concentration is in the range of 0. l%wt to 1% wt. Then the wafer is further cleaned by pure DI water.
  • Step 8 Deposit SiC or SiCN layer 7008 above Cu 7002 and the fourth dielectric layer 7007 as shown in FIG. 71.
  • Step 9 Repeat step 1 to step 8 to form another layer of interconnect layer (not shown here).
  • FIGs. 8A to 8F show an exemplary embodiment of wafer electro-polishing tool with movable nozzle and/or movable chuck.
  • chuck 8020 moves laterally so electrolyte column 8034 can selectively polish any portion of metal layer 8013 as shown in FIGs. 8B and 8 C.
  • nozzle 8032 can move laterally as shown in FIGs. 8E and 8F.
  • the lateral speed and the polishing current are two of major parameters used to control polishing rate profile across the surface of wafer 8014. In general, the polishing rate is proportional to polishing current in certain current region, and is reverse proportional to relative speed of chuck 8020 to nozzle 8032.
  • the electro-polishing tool can include a power supply 8030.
  • the electro-polishing tool can include a control system 8036 connected to the chuck 8020 and the nozzle 8032.
  • Control system 8036 can be configured to apply the stream of electrolyte using the nozzle to the metal layer from the center of the wafer to the edge of the wafer to electro-polish the metal layer and the barrier layer to expose the non-recessed area.
  • FIGs. 8B to 8F can also include the control system 8036 depicted in FIG. 8A.

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Abstract

To electro-polish a metal layer on a semiconductor wafer, a first dielectric layer is formed on a semiconductor wafer The first dielectric layer is resistant to being etched by hydrogen fluoride acid. A second dielectric layer is formed above the first dielectric layer on the semiconductor wafer. The second dielectric layer is susceptible to being etched by hydrogen fluoride acid The second dielectric layer is formed with a recessed area and a non-recessed area The recessed area extends into the first dielectric layer. A barrier layer is formed to cover the recessed area and the non-recessed area The metal layer is formed to fill the recessed area and cover the non-recessed area The metal layer and the barrier layer are electro-polished to expose the non-recessed area using an electrolyte containing hydrogen fluoride acid

Description

REMOVING BARRIER LAYER USING AN ELETRO-POLISHING PROCESS
CROSS-REFERENCE TO RELATED APPLICATIONS
[0001] The present application claims the benefit of U.S. Provisional Application No. 60/797,105, filed May 2, 2006, which is incorporated herein by reference in its entirety for all purposes.
BACKGROUND
1. Field
[0002] The present application generally relates to electro-polishing, and, more particularly, to removing a barrier layer using an electro-polishing process.
2. Related Art
[0003] Semiconductor devices are manufactured or fabricated on semiconductor wafers using a number of different processing steps to create transistor and interconnection elements. To electrically connect transistor terminals associated with the semiconductor wafer, conductive (e.g., metal) trenches, vias, and the like are formed in dielectric materials as part of the semiconductor device. The trenches and vias couple electrical signals and power between transistors, interna! circuit of the semiconductor devices, and circuits external to the semiconductor device.
[0004] In forming the interconnection elements the semiconductor wafer may undergo, for example, masking, etching, and deposition processes to form the desired electronic circuitry of the semiconductor devices. In particular, multiple masking and etching steps can be performed to form a pattern of recessed areas in a dielectric layer on a semiconductor wafer that serve as trenches and vias for the interconnections. A deposition process may then be performed to deposit a metal layer over the semiconductor wafer thereby depositing metal both in the trenches and vias and also on the non-recessed areas of the semiconductor wafer. To isolate the interconnections, such as patterned trenches and vias, the metal deposited on the non-recessed areas of the semiconductor wafer is removed.
[0005] Conventional methods of removing the metal film deposited on the non-recessed areas of the dielectric layer on the semiconductor wafer include, for example, chemical mechanical polishing (CMP). CMP methods are widely used in the semiconductor industry to polish and planarize the metal layer within the trenches and vias with the non-recessed areas of the dielectric layer to form interconnection lines.
[0006] In a CMP process, a wafer assembly is positioned on a CMP pad located on a platen or web. The wafer assembly includes a substrate having one or more layers and/or features, such as interconnection elements formed in a dielectric layer. A force is then applied to press the wafer assembly against the CMP pad. The CMP pad and the substrate assembly are moved against and relative to one another while applying the force to polish and planarize the surface of the wafer. A polishing solution, often referred to as polishing slurry, is dispensed on the CMP pad to facilitate the polishing. The polishing slurry typically contains an abrasive and is chemically reactive to selectively remove from the wafer the unwanted material, for example, a metal layer, more rapidly than other materials, for example, a dielectric material.
[0007] CMP methods, however, can have several deleterious effects on the underlying semiconductor structure because of the relatively strong mechanical forces involved. For example, as interconnection geometries move to 0.13 microns and below, there can exist a large difference between the mechanical properties of the conductive materials, for example copper and the low k films used in typical damascene processes. For instance, the Young Modulus of a low k dielectric film may be greater than 10 orders of magnitude lower than that of copper. Consequently, the relatively strong mechanical force applied on the dielectric films and copper in a CMP process, among other things, can cause stress related defects on the semiconductor structure that include delamination, dishing, erosion, film lifting, scratching, or the like.
[0008] New processing techniques are therefore desired. For example a metal layer may be removed or etched from a wafer using an electro-polishing process. In genera], in an electro-polishing process the portion of the wafer to be polished is immersed within an electrolyte fluid solution and an electric charge is then applied to the wafer. These conditions result in copper being removed or polished from the wafer.
[0009] Barrier layers, such as Tantalum, Tantalum nitride, Titanium, and Titanium nitride, cannot be electrically polished by phosphoric and sulfuric acid based electrolyte. Thus, barrier layers are typically removed by plasma etch or chemical mechanical polishing (CMP). However, plasma etching adds additional process step, and CMP damages low k dielectrics under the barrier layer.
SUMMARY
[0010] In one exemplary embodiment, a first dielectric layer is formed on a semiconductor wafer. The first dielectric layer is resistant to being etched by hydrogen fluoride acid. A second dielectric layer is formed above the first dielectric layer on the semiconductor wafer. The second dielectric layer is susceptible to being etched by hydrogen fluoride acid. The second dielectric layer is formed with a recessed area and a non-recessed area. The recessed area extends into the first dielectric layer. A barrier layer is formed to cover the recessed area and the non-recessed area. The metal layer is formed to fill the recessed area and cover the non-recessed area. The metal layer and the barrier layer are electro-polished to expose the non-recessed area using an electrolyte containing hydrogen fluoride acid.
BRIEF DESCRIPTION OF THE DRAWINGS
[0011] FIGs. IA-IC depict the result of an exemplary electro-polishing process;
[0012] FIGs. 2A-2J depict the result of another exemplary electro-polishing process;
[0013] FJGs. 3A-3I depict the result of another exemplary electro-polishing process;
[0014] FIGs. 4A-4I depict the result of another exemplary electro-polishing process;
[0015] FIGs. 5A-5J depict the result of another exemplary electro-polishing process; [0016] FIGs. 6 A-6J depict the result of another exemplary electro-pol ishing process;
[0017] FIGs. 7 A-7I depict the result of another exemplary electro-pol ishing process; and
[0018] FIGs. 8 A-8F arc block diagrams of exemplary electro-polishing tools.
DETAILED DESCRIPTION
[0019] In one exemplary embodiment, FIGs. IA to 1C show the detail of the electro-polishing process using a nozzle. In order to fully remove barrier layer 1112, the process is preferably performed from center of wafer 1114 to edge of wafer 1 114 with certain over-polishing amount as shown in FIGs. IA to 1C. In this way, the electro-polishing current 1116 will easily flow through barrier layer 1112 and then to adjacent Cu film 11 10 and then to edge of wafer as shown in FlG. 1C. As barrier layer surrounding copper trench 1120 is being removed by the electro-polishing process, copper and barrier metal in structure 1120 lose the electrical path. Therefore, the electro-polishing process on structure 1120 automatically stops as shown in FIG. 1C.
[0020] The electrolytes for removing barrier and copper simultaneously are listed as follows:
Hydrogen fluoride (HF) acid (49% wt): 10 ml, range between 4 to 40 ml; Phosphoric acid H3PO4 (85% wt): 200 ml, range between 0 to 300 ml; Sulfuric acid H3SO4 (98% wt): 60 ml, range between 0 to 80 ml; Ethylene Glycol: 100 ml, range between 0 to 200 ml; and Glycerin: 50 ml, range between 0 to 100 ml.
[0021] In the electrolyte above, hydrogen fluoride (HF) acid is used to remove metal oxide, such as Tantalum oxide and Titanium oxide, formed during the electro-polishing process.
[0022] It should be motioned that HF acid can be combined with other salt, such as A1C13, ZnC12, MgC12, CrO3, (NH4)HPO4, (NH4)2SO4, NH4F, NH4NO3, and acid, such as HNO3, HCl, HC1O4, and surfactant, such as Benzotriazole (C6H5N3).
[0023] Hydrogen fluoride acid attacks silicon oxide or silicon oxide based dielectrics very aggressively. Therefore, it is preferable to use HF acid resistant dielectric materials 1 114, such as Polyimide, fluorinated polyimides, polyimide nanofoams, parylene N, Poly(arylene ethers), Poly(arylenes), polynaphthalene family, aromatic hydrocarbon (SiLK), amorphous carbon film, Teflon-AF, Teflon microemulsion, and the like.
[0024] If silicon oxide based dielectrics are used, then those silicon oxide based dielectrics are preferably covered by another layer of dielectrics with highly HF resistance or blocking performance to form hybrid structures (to be described below with reference to FlGs. 3A to 31).
[0025] Another exemplary embodiment to remove barrier is shown in FIGs. 2A to 2 I. The process steps are listed as follows:
[0026] Step I : Deposit the first dielectric layer 2006 on an existing dielectric layer 2012 formed in the previous metal layer as shown in FIG. 2A. Such existing dielectric layer 2012 is made of silicon carbide (SiC), silicon carbide nitride (SiCN) or other dielectric materials with highly HF resistance or HF blocking performance. Deposition method can be chemical vapor deposition (CVD) or spin on dielectric method. Dielectric layer 2006 includes Polyimides, fluorinated polyimides, polyimide nanofoams, parylene N, Poly(arylene ethers), Poly(arylenes), polynaphthalene family, aromatic hydrocarbon (SiLK), amorphous carbon film, Teflon-AF, Teflon microemulsion or other low k dielectrics, or ultra low k dielectrics with high HF acid resistance.
[0027] Step 2: Deposit the second dielectric layer 2001 above the first dielectric layer 2006 as shown in FIG. 2A. The second dielectric layer 2001 can be silicon oxide, silicon oxide based dielectrics, fluorinated silica, carbon doped silica, and nonporous silica. The second dielectrics can be any dielectric material, which is susceptible to being etched by HF acid.
[00281 Step3: Etch via 2010 and trench 2009 by plasma as shown in FIG. 2B.
[0029] Step 4: Deposit barrier layer 2004 and Cu seed layer 2003 as shown in FIG. 2C. Usually, barrier layer 2004 is made of Tantalum, Tantalum nitride, Titanium, Titanium nitride, Tungsten, Tungsten nitride, Ruthenium, Ruthenium nitride, Zirconium, Niobium, Molybdenum, Technetium, Rhodium, Palladium, Hafnium, Rhenium, Osmium, and Iridium.
[0030] Step 5: Plate Cu layer 2002 to fill via and trench as shown in FIG.2D. The plated Cu layer can be further planarized by chemical mechanical polishing (CMP) as disclosed in PCT Patent Application No. PCT/US02/26167 and U.S. Patent Application Serial No. 10/486,982, which are incorporated here by reference in their entireties for all purposes, or can be formed by the flat plating using dummy structure as disclosed in PCT Patent Application No. PCT/US03/11417 and U.S. Patent Application No. 10/510,656, which are incorporated hereby reference in their entireties, or can be electro-polished with contacting pad nozzle disclosed in US Provisional Application Serial No. 60/738,250, which is incorporated herein by reference in its entirety.
[0031] Step 6: Remove Cu layer using the electro-polishing process described above with reference to FIGs. 1 A-IC and the apparatus to be described below with reference to FIGs. 8A-8F.
[0032] FIG. 2E shows the cross section of a Cu interconnect structure just as the Cu layer 2002 is being removed from barrier layer 2005 by using the electro-polishing process. As the electro-polishing process continues, the Cu film in the trench will start to recess, and barrier layer will be removed away as shown in FIG. 2F. As the barrier layer is being removed, the electro-polishing current will stop due to the absence of a conducting path. Thus, the Cu inside the trench and barrier layer between Cu trench and dielectrics will be isolated from the electro-polishing process, or the polishing process will self-terminate. On the other hand, the barrier residual 2015 may remain on the surface of the second dielectric layer 2001 as shown in FIG. 2F. It is recommended to use constant voltage to perform the above electro-polishing process.
[0033] As described above, the second dielectric layer 2001 is made of silicon oxide, silicon oxide based dielectrics, fluorinated silica, carbon doped silica, and nonporous silica, which is susceptible to being etched away by HF acid. Therefore, the second dielectric layer is etched away by HF acid in the electrolyte as shown in FIG. 2G. As the etching process continues, eventually the barrier residual 2015 will be removed due to undercut etching of dielectrics 2021 underneath as shown in FIGs. 2G and 2H. [0034] After the electro-polishing, the wafer will be transferred to a cleaning cell for removing all chemicals. The additional HF based chemical can be further injected on the wafer surface to etch away barrier residual in case of some barrier residuals are not fully removed in the electro-polishing cell. For example, for 5% (weight) HF concentration, the etching rate of Tantalum is around 1.5nm/min. HF concentration is in the range of 1% wt to 10% wt. Citric acid (C6H8O7) 0.5% wt can be also added in the cleaning process to remove Copper oxide. Citric acid concentration is in the range of 0.1 %wt to 1% wt. Then the wafer is further cleaned by pure DI water.
[0035] Step 7: Deposit SiC or SiCN layer 2008 above Cu 2002 and dielectric layer 2006 as shown in FIG. 21.
[0036] Step 8: Repeat step 1 to step 7 to form another layer of interconnect layer as shown in FIG. 2J.
[0037] Another exemplary embodiment to remove the barrier is shown in FIGs. 3A to 3 I. The process steps are listed as follows:
[0038] Step 1 : Deposit the first dielectric layer 3052, and deposit the second dielectric layer (etching stop ■ layer) 3050 as shown in FIG. 3A. Deposition method can be chemical vapor deposition (CVD) or spin on dielectric method. The first dielectric layer 3052 includes silicon dioxide, fluorosilicate glass (FSG), HSSQ, diamond-like carbon, carbon-doped SiO2, MSSQ, and nonporous silica. The second dielectric layer 3050 is primarily used to stop the etching process between via and trench during plasma etching. The second function of the second dielectric layer 3050 is to block the HF or Fluorine atom/ion diffused through the third dielectric layer 3006 (to be described below) from reaching the first dielectric layer 3052 during later electro-polishing process, which will be described in detail below with reference to FIG. 3G. It is clear that HF or Fluorine ion will destroy the first dielectric layer 3052 if it penetrates the second dielectric layer 3050. The second dielectric layer 3050 includes silicone carbide (SiC), and Silicon carbide nitride SiCN, or other dielectric materials with high HF acid resistance and blocking performance. In other words, neither HF nor Fluorine atom/ion should penetrate through the second dielectrics being selected.
[0039] Step 2: Deposit the third dielectric layer 3006 above the second dielectric layer 3050 as shown in FIG. 3A. Deposition method can be chemical vapor deposition (CVD) or spin on dielectric method. The third dielectric layer 3006 include Polyimides, fluorinated polyimides, polyimide nanofoams, parylene N, Poly(arylene ethers), Poly(arylenes), polynaphthalene family, aromatic hydrocarbon (SiLK), amorphous carbon film, Teflon-AF, Teflon microemulsion or other low k dielectrics, or ultra low k dielectrics with high HF acid resistance.
[0040] Step 3: Deposit the fourth dielectric layer (or sacrificial layer) 3001 above the third dielectric layer 3006 as shown in FIG. 3A. The fourth dielectric layer 3001 can be silicon oxide, silicon oxide based dielectrics, fluorinated silica, carbon doped silica, and nonporous silica. The fourth dielectric layer 3001 should be selected to be able to be etched away by HF acid.
[0041] Step 4: Deposit additional mask layers for fabricating dual damascene structure. The details of the lithography steps are well known in state of art, and will not be described here.
[0042] Step5: Etch via 3010 and trench 3009 by plasma, and strip the photo resist as shown in FlG. 3B. [0043] Step 6: Deposit barrier layer 3004 and Cu seed layer 3003 as shown in FIG. 3C. Usually, barrier layer 3004 is made of single or combination of metal layers such Tantalum, Tantalum Nitride, Titanium, Titanium Nitride, Tungsten, Tungsten nitride, Ruthenium, Zirconium, Niobium, Molybdenum, Technetium, Rhodium, Palladium, Hafnium, Rhenium, Osmium, and Indium.
[0044] Step 7: Plate Cu layer 3002 to fill via and trench as shown in FIG. 3D. The plated Cu layer can be further planarized by chemical mechanical polishing (CMP) as disclosed in PCT Patent Application No. PCT/US02/26167 and U.S. Patent Application Serial No. 10/486,982, which are incorporated here by reference in their entireties for all purposes, or can be formed by the flat plating using dummy structure as disclosed in PCT Patent Application No. PCT/US03/11417 and U.S. Patent Application No. 10/510,656, which are incorporated hereby reference in their entireties, or can be electro-polished with contacting pad nozzle disclosed in US Provisional Application Serial No. 60/738,250, which is incorporated herein by reference in its entirety.
[0045] Step 8: Remove Cu layer using the electro-polishing process described above with reference to FIGs. IA-I C and the apparatus to be described below with reference to FIGs. 8A-8F.
[0046] FIG. 3E shows the cross section of a Cu interconnect structure just as the Cu layer 3002 is being removed from barrier layer 3005 by using the electro-polishing process. As the electro-polishing process continues, the Cu film in the trench will start to recess, and barrier layer will be removed away as shown in FlG. 3F. As barrier layer is being removed, the electro-polishing current will stop due to the absence of a conducting path. Thus, the Cu inside the trench and barrier layer between Cu trench and dielectrics will be isolated from the electro-polishing process, or the polishing process will self-terminate. On the other hand, the barrier residual 3015 may remain on the surface of the dielectric layer 3001 as shown in FIG. 3F due to the same reason. It is recommended to use constant voltage to perform the above electro-polishing process.
[0047] As described before, the fourth dielectric layer 3001 is made of silicon oxide, silicon oxide based dielectrics, fluorinated silica, carbon doped silica, and nonporous silica, which i susceptible to being etched away by HF acid. Therefore, the fourth dielectric layer is etched away by HF acid in the electrolyte as shown in FIG. 3G. As the etching process continues, eventually the barrier residual 3015 will be removed due to undercut etching of dielectrics 3021 underneath as shown in FIGs. 3G and 3H.
[0048] After the electro-polishing, the wafer will be transferred to a cleaning cell for removing all chemicals. The additional HF based chemical can be further injected on the wafer surface to etch away barrier residual in case of some barrier residuals are not fully removed in the electro-polishing cell. For example, for 5% (weight) HF concentration, the etching rate of Tantalum is around 1.5nm/min. HF concentration is in the range of 1% wt to 10% wt. Citric acid (C6H8O7) 0.5% wt can be also added in the cleaning process to remove Copper oxide. Citric acid concentration is in the range of 0.1 %wt to 1% wt. Then the wafer is further cleaned by pure DI water.
[0049] Step 9: Deposit SiC or SiCN layer 3008 above Cu 3002 and dielectric layer 3006 as shown in FIG. 31.
[0050] Step 10: Repeat step 1 to step 9 to form another layer of interconnect layer (not shown here).
[0051] Another exemplary embodiment to remove the barrier layer is shown in FIGs. 4A to 4 I. The process steps are listed as follows: 10052] Step 1 : Deposit the first dielectric layer 4052, deposit the second dielectric layer (etching stop layer) 4050, and deposit the third dielectric layer 4006 as shown in FIG. 4A. Deposition method can be chemical vapor deposition (CVD) or spin on dielectric method. The first and the third dielectric layers include Polyimides, fluorinated polyimides, polyimide nanofoams, parylene N, Poly(arylene ethers), Poly(arylenes), polynaphthalene family, aromatic hydrocarbon (SiLK), amorphous carbon film, Teflon-AF, Teflon microemulsion or other low k dielectrics, or ultra low k dielectrics with high HF acid resistance. The second dielectric layer 4050 is primarily used for the clean etch stop between via and trench during plasma etching. The second function of the second dielectric layer is to block the HF or Fluorine atom/ion diffused through the third dielectric layer 4006 during later electro-polishing process, which will be described in detail below with reference to FIG. 4G. The second dielectric material 4050 include silicone carbide (SiC), silicon carbide nitride (SiCN), or other dielectric materials with high HF acid resistance and blocking performance. In other words, neither HF nor Fluorine atom/ion should penetrate through the second dielectrics being selected.
[0053] Step 2: Deposit the fourth dielectric layer 4001 above the third dielectric layer 4006 as shown in FIG. 4A. The fourth dielectric layer 4001 can be silicon oxide, silicon oxide based dielectrics, fluorinated silica, carbon doped silica, and nonporous silica. The fourth dielectric layer 4001 should be selected to be susceptible to being etched by HF acid.
[0054] Step 3: Deposit additional mask layers for fabricating dual damascene structure. The details of the lithographic steps are well known in state of art, and will not be described here.
[0055] Step4: Etch via 4010 and trench 4009 by plasma as shown in FIG. 4B.
[0056] Step 5: Deposit barrier layer 4004 and Cu seed layer 4003 as shown in FIG. 4C. Usually, barrier layer 4004 is made of Tantalum, Tantalum Nitride, Titanium, Titanium Nitride, Tungsten, Tungsten Nitride, Ruthenium, Zirconium, Niobium, Molybdenum, Technetium, Rhodium, Palladium, Hafnium, Rhenium, Osmium, and Indium.
[0057] Step 6: Plate Cu layer 4002 to fill via and trench as shown in FIG. 4D. The plated Cu layer can be further planarized by chemical mechanical polishing (CMP) as disclosed in PCT Patent Application No. PCT/US02/26167 and U.S. Patent Application Serial No. 10/486,982, which are incorporated here by reference in their entireties for all purposes, or can be formed by the flat plating using dummy structure as disclosed in PCT Patent Application No. PCT/US03/11417 and U.S. Patent Application No. 10/510,656, which are incorporated hereby reference in their entireties, or can be electro-polished with contacting pad nozzle disclosed in US Provisional Application Serial No. 60/738,250, which is incorporated herein by reference in its entirety.
[0058] Step 7: Remove Cu layer using the electro-polishing process described above with reference to FIGs. 1 A-IC and the apparatus to be described below with reference to FIGs. 8A-8F.
[0059] FIG. 4E shows the cross section of a Cu interconnect structure just as the Cu layer 4002 is being removed from barrier layer 4005 by using the electro-polishing process. As the electro-polishing process continues, the Cu film in the trench will start to recess, and barrier layer will be removed away as shown in FIG. 4F. As the barrier layer is being removed, the electro-polishing current will stop due to the absence of a conducting path. Thus, the Cu inside the trench and barrier layer between Cu trench and dielectrics will be isolated from the electro-polishing process, or the polishing process will self terminate. On the other hand, the barrier residual 4015 may remain on the surface of the second dielectric layer 4001 as shown in FIG. 4F. It is recommended to use constant voltage to perform the above electro-polishing process.
[0060] As described before, the fourth dielectric layer 4001 is made of silicon oxide, silicon oxide based dielectrics, fluorinated silica, carbon doped silica, and nonporous silica, which is susceptible to being etched away by HF acid. Therefore, the fourth dielectric layer is etched away by HF acid in the electrolyte as shown in FIG. 4G, As the etching process continues, eventually the barrier residual 4015 will be removed due to undercut etching of dielectrics 4021 underneath as shown in FIGs. 4G and 4H.
[0061] After the electro-polishing, the wafer will be transferred to a cleaning cell for removing all chemicals. The additional HF based chemical can be further injected on the wafer surface to etch away barrier residual in case of some barrier residuals are not fully removed in the electro-polishing cell. For example, for 5% (weight) HF concentration, the etching rate of Tantalum is around 1.5nm/min. HF concentration is in the range of 1% wt to 10% wt. Citric acid (C6H8O7) 0.5% wt can be also added in the cleaning process to remove Copper oxide. Citric acid concentration is in the range of 0.1%wt to 1% wt. Then the wafer is further cleaned by pure DI water.
[0062] Step 8: Deposit SiC or SiCN layer 4008 above Cu 4002 and dielectric layer 4006 as shown in FIG. 41.
[0063] Step 9: Repeat step 1 to step 8 to form another layer of interconnect layer (not shown here).
[0064] Another exemplary embodiment to remove the barrier layer is shown in FIGs. 5A to 5 J. The process steps are listed as follows:
[0065] Step 1 : Deposit the first dielectric layer 5006 on an existing dielectric layer 5012 formed in the previous metal layer, and deposit the second dielectric layer 5007 as shown in FIG. 5A. Such existing dielectric layer 5012 is made of silicon carbide (SiC), silicon carbide nitride (SiCN) or other dielectric materials with highly HF resistance or HF blocking performance. Deposition method can be chemical vapor deposition (CVD) or spin on dielectric method. The first dieletric layer 5006 includes Polyimides, fluorinated polyimides, polyimide nanofoams, parylene N, Poly(arylene ethers), Poly(arylenes), polynaphthalene family, aromatic hydrocarbon (SiLK), amorphous carbon film, Teflon-AF, Teflon microemulsion, silicon oxide, fluorine doped silicon oxide, organo silicate materials such as Aurora, Black Diamond, and Coral, Spin-on-MSQ/HSQ, or other low k dielectrics, or ultra low k dielectrics. The second dielectric layer 5007 is primarily used for preventing electrolyte from attacking the first layer dielectric 5006. The second dielectric material 5007 includes silicone carbide (SiC), silicon carbide nitride (SiCN), aluminum oxide (A12O3) or other dielectric materials with high HF acid resistance and blocking performance. In other words, the neither HF nor Fluorine atom/ion should penetrate through the second dielectrics being selected.
[0066] Step 2: Deposit the third dielectric layer 5001 with thickness of H above the second dielectric layer 5007 as shown in FIG. 5 A. The third dielectric layer 5001 can be silicon oxide, silicon oxide based dielectrics, fluorinated silica, carbon doped silica, and nonporous silica. The third dielectric layer 5001 should be selected to be susceptible to being etched by HF acid. [0067] Step 3: Spin on photo resist, and the details of the lithography steps are well known in state of art, and will not be described here.
[0068] Step4: Etch via 5010 and trench 5009 by plasma as shown in FIG. 5B.
[0069] Step 5: Deposit barrier layer 5004 and Cu seed layer 5003 as shown in FIG. 5C. Usually, barrier layer 5004 is made of Tantalum, Tantalum Nitride, Titanium, Titanium Nitride, Tungsten, Tungsten Nitride, Ruthenium, Zirconium, Niobium, Molybdenum, Technetium, Rhodium, Palladium, Hafnium, Rhenium, Osmium, and Indium.
[0070] Step 6: Plate Cu layer 5002 to fill via and trench as shown in FIG. 5D. The plated Cu layer can be further planarized by chemical mechanical polishing (CMP) as disclosed in PCT Patent Application No. PCT/US02/26167 and U.S. Patent Application Serial No. 10/486,982, which are incorporated here by reference in their entireties for all purposes, or can be formed by the flat plating using dummy structure as disclosed in PCT Patent Application No. PCT/US03/11417 and U.S. Patent Application No. 10/510,656, which are incorporated hereby reference in their entireties, or can be electro-polished with contacting pad nozzle disclosed in US Provisional Application Serial No. 60/738,250, which is incorporated herein by reference in its entirety.
[0071] Step 7: Remove Cu layer using the electro-polishing process described above with reference to FIGs. IA-I C and the apparatus to be described below with reference to FIGs. 8A-8F.
[0072] FIG. 5E shows the cross section of a Cu interconnect structure just as the Cu layer 5002 is being removed from barrier layer 5005 by using the electro-polishing process. As the electro- continues, the Cu film in the trench will start to recess, and barrier layer will be removed awayiδ BfSrøfiSjn FIG. 5F. As barrier layer is being removed, the electro-polishing process will stop due to the absence of a current conducting path. Thus, both Cu inside the trench 5002 and barrier layer between Cu trench and dielectrics will be isolated from the electro-polishing process, or the polishing process will self terminate. On the other hand, the barrier residual 5015 may remain on the surface of the third dielectric layer 5001 as shown in FIG. 5F. It is recommended to use constant voltage to perform the above electro-polishing process.
[0073] As described before, the third dielectric layer 5001 is made of silicon oxide, silicon oxide based dielectrics, fluorinated silica, carbon doped silica, and nonporous silica, which is susceptible to being etched away by HF acid. Therefore, the fourth dielectric layer is etched away by HF acid in the electrolyte as shown in FIG. 5G. As the etching process continues, eventually the barrier residual 5015 will be removed due to undercut etching of dielectrics 5021 underneath as shown in FIGs. 5G and 5H. The second dielectric layer 5007 is made of silicone carbide (SiC), silicon carbide nitride (SiCN), aluminum oxide (A12O3) or other dielectric materials with high HF acid resistance and blocking performance. Therefore the first dielectric layer 5006 underneath the second dielectric layer is protected from being attacked by the electrolyte mainly HF. Thickness of the second dielectric layer is in the range of 5 nm to 100 nm, depending on semiconductor manufacture node.
[0074] It is important to obtain a flat surface as shown in FIG. 5H in order to give better performance for the following lithograph process. Therefore, the Cu trench recess D as shown in FIG. 5F should be controlled to be equal to thickness H of the third dielectric layer 5001. The Cu recess D can be controlled by the removal rate ratio of barrier layer to Cu metal. In more particularly, HF concentration in electrolyte determines the removal rate ratio of barrier layer to Cu metal layer. For example, within 5% wt HF concentration, the removal rate ratio of barrier layer (Ta and or TaN) to Cu metal layer is almost proportional to HF concentration. Thus, the process should be performed as follows:
a. Based on barrier layer thickness for each manufacture node, the HF concentration should be determined to make sure minimum Cu recess and at the same time all Cu residual being removed before the barrier layer being removed. The minimum Cu recess can be in the range of 2 to 10 times of thickness of barrier layer 5004; and
b. Based on the measured minimum recess of Cu trench, then design the thickness of the third dielectric layer to be equal to the minimum of Cu trench recess.
[0075] For example, for 65 nm manufacture node, the thickness of barrier layer is 7 nm. The Cu recess will be around 30 nm if 5% wt HF concentration is .used in a phosphoric/Sulfuric acid/Ethylene Glycol/Glycerin based electrolyte. Therefore the thickness of third dielectric layer 5001 should be designed around 30 nm.
[0076] As another example: for 65 nm manufacture node, the thickness of barrier layer is 7 nm. The Cu recess will be around 60 nm if 2.5% wt HF concentration is used in a phosphoric/Sulfuric acid/Ethylene Glycol/Glycerin based electrolyte. Therefore the thickness of third dielectric layer 5001 should be designed around 60 nm.
[0077] After the electro-polishing, the wafer will be transferred to a cleaning cell for removing all chemicals. The additional HF based chemical can be further injected on the wafer surface to etch away barrier residual in case of some barrier residuals are not fully removed in the electro-polishing cell. For example, for 5% (weight) HF concentration, the etching rate of Tantalum is around 1.5nm/min. HF concentration is in the range of 1% wt to 10% wt. Citric acid (C6H8O7) 0.5% wt can be also added in the cleaning process to remove Copper oxide. Citric acid concentration is in the range of 0.1%wt to 1% wt. Then the wafer is further cleaned by pure DI water.
[0078] Step 8: Deposit SiC or SiCN layer 5008 above Cu 5002 and the second dielectric layer 5007 as shown in FIG. 51.
[0079] Step 9: Repeat step 1 to step 8 to form another layer of interconnect layer as shown in FIG. 5J.
[0080] Another exemplary embodiment to remove the barrier layer is shown in FIGs. 6A to 61. The process steps are listed as follows:
[0081] Step 1 : Deposit the first dielectric layer 6052, and deposit the second dielectric layer 6006, and deposit the third dielectric layer 6007 as shown in FIG. 6A. Deposition method can be chemical vapor deposition (CVD) or spin on dielectric method. The first dielectric layer 6052 and the second dielectric layer 6006 include Polyimides, fluorinated polyimides, polyimide nanofoams, parylene N, Poly(arylene ethers), Poly(arylenes), polynaphthalene family, aromatic hydrocarbon (SiLK.), amorphous carbon film, Teflon-AF, Teflon microemulsion, silicon oxide, fluorine doped silicon oxide, organo silicate materials such as Aurora, Black Diamond, and Coral, Spin-on-MSQ/HSQ, or other low k dielectrics, or ultra low k dielectrics. The third dielectric layer 6007 is primarily used for preventing electrolyte from attacking the second dielectric layer 6006. The third dielectric material 6007 includes silicone carbide (SiC), silicon carbide nitride (SiCN), aluminum oxide (A12O3) or other dielectric materials with high HF acid resistance and blocking performance. In other words, neither HF nor Fluorine atom/ion should penetrate through the second dielectrics being selected.
[0082] Step 2: Deposit the fourth dielectric layer 6001 with thickness of H above the third dielectric layer 6007 as shown in FIG. 6A. The fourth dielectric layer 6001 can be silicon oxide, silicon oxide based dielectrics, fluorinated silica, carbon doped silica, and nonporous silica. The fourth dielectric layer 6001 should be selected to be able to be etched by HF acid.
[0083] Step 3: Spin on photo resist, and the details of the lithography steps are well known in state of art, and will not be described here.
[0084] Step4: Etch via 6010 and trench 6009 by plasma as shown in FIG. 6B.
[0085] Step 5: Deposit barrier layer 6004 and Cu seed layer 6003 as shown in FIG. 6C. Usually, barrier layer 6004 is made of Tantalum, Tantalum Nitride, Titanium, Titanium Nitride, Tungsten, Tungsten Nitride, Ruthenium, Zirconium, Niobium, Molybdenum, Technetium, Rhodium, Palladium, Hafnium, Rhenium, Osmium, and Iridium.
[0086] Step 6: Plate Cu layer 6002 to fill via and trench as shown in FIG. 6D. The plated Cu layer can be further planarized by chemical mechanical polishing (CMP) as disclosed in PCT Patent Application No. PCT/US02/26167 and U.S. Patent Application Serial No. 10/486,982, which are incorporated here by reference in their entireties for all purposes, or can be formed by the flat plating using dummy structure as disclosed in PCT Patent Application No. PCT/US03/1 1417 and U.S. Patent Application No. 10/510,656, which are incorporated hereby reference in their entireties, or can be electro-polished with contacting pad nozzle disclosed in US Provisional Application Serial No. 60/738,250, which is incorporated herein by reference in its entirety.
[0087] Step 7: Remove Cu layer using the electro-polishing process described above with reference to FIGs. 1 A-IC and the apparatus to be described below with reference to FIGs. 8A-8F.
[0088] FIG. 6E shows the cross section of a Cu interconnect structure just as the Cu layer 6002 is being removed from barrier layer 6004 by using the electro-polishing process. As the electro-polishing process continues, the Cu film in the trench will start to recess, and barrier layer will be removed away as shown in FIG. 6F. As the barrier layer is being removed, the electro-polishing process will stop due to the absence of a current conducting path. Thus, both Cu inside the trench 6002 and barrier layer between Cu trench 6002 and dielectrics will be isolated from the electro-polishing process, or the polishing process will self-terminate. On the other hand, the barrier residual 6015 may remain on the surface of the fourth dielectric layer 6001 as shown in FIG. 6F. It is recommended to use constant voltage to perform the above electro-polishing process.
[0089] As described before, the fourth dielectric layer 6001 is made of silicon oxide, silicon oxide based dielectrics, fluorinated silica, carbon doped silica, and nonporous silica, which can be etched away by HF acid. Therefore, the fourth dielectric layer is etched away by HF acid in the electrolyte as shown in FIG. 6G. As the etching process continues, eventually the barrier residual 6015 will be removed due to undercut etching of dielectrics 6021 underneath as shown in FIGs. 6G and 6H. The third dielectric layer 6007 is made of silicone carbide (SiC), silicon carbide nitride (SiCN), aluminum oxide (AI2O3) or other dielectric materials with high HF acid resistance and blocking performance. Therefore the second dielectric layer 6006 underneath the third dielectric layer 6007 is protected from being attacked by the electrolyte mainly HF. Thickness of the third dielectric layer 6007 is in the range of 5 nm to 100 nm, depending on semiconductor manufacture node.
[0090] It is important to obtain a flat surface as shown in FIG. 6H in order to give better performance for the following lithograph process. Therefore the Cu trench recess D as shown in FIG. 6F should be controlled to be equal to thickness H of the fourth dielectric layer 6001. The Cu recess D can be controlled by the removal rate ratio of barrier layer to Cu metal. More particularly, HF concentration in electrolyte determines the removal rate ratio of barrier layer to Cu metal layer. For example, within 5% wt HF concentration, the removal rate ratio of barrier layer (Ta and or TaN) to Cu metal layer is almost proportional to HF concentration. Thus, the process should be performed as follows:
a. Based on barrier layer thickness for each manufacture node, the HF concentration should be determined to make sure minimum Cu recess and at the same time all Cu residual being removed before the barrier layer being removed. The minimum Cu recess can be in the range of 2 to 10 times of thickness of barrier layer 6004; and
b. Based on the measured minimum recess of Cu trench, then design the thickness of the fourth dielectric layer to be equal to the minimum of Cu trench recess.
[0091] For example, for 65 nm manufacture node, the thickness of barrier layer is 7 nm. The Cu recess will be around 30 nm if 5% wt HF concentration is used in a phosphoric/Sulfuric acid/Ethylene Glycol/Glycerin based electrolyte. Therefore the thickness of fourth dielectric layer 6001 should be designed around 30 nm.
[0092] As another example: for 65 nm manufacture node, the thickness of barrier layer is 7 nm. The Cu recess will be around 60 nm if 2.5% wt HF concentration is used in a phosphoric/Sulfuric acid/Ethylene Glycol/Glycerin based electrolyte. Therefore the thickness of fourth dielectric layer 6001 should be designed around 60 nm.
[0093] Higher concentration of HF will reduce the Cu recess. However, higher HF concentration will cause dip or micro trench 6100 at side of Cu line 6002 during electro-polishing process as shown in FIG. 61. In the same way, the barrier layer at sidewall of Cu line can be removed fast by using high HF concentration as shown in FIG. 61. Thus, the end point effect and corner loss or dip should be balanced by adjusting HF concentration. The HF concentration range should be in the range of 0.5% wt to 5% wt.
[0094] After the electro-polishing, the wafer will be transferred to a cleaning cell for removing all chemicals. The additional HF based chemical can be further injected on the wafer surface to etch away barrier residual in case of some barrier residuals are not fully removed in the electro-polishing cell. For example, for 5% (weight) HF concentration, the etching rate of Tantalum is around 1.5nm/min. HF concentration is in the range of 1% wt to 10% wt. Citric acid (C6H8O7) 0.5% wt can be also added in the cleaning process to remove Copper oxide. Citric acid concentration is in the range of 0.1 %wt to 1% wt. Then the wafer is further cleaned by pure Dl water.
[0095] Step 8: Deposit SiC or SiCN layer 6008 above Cu 6002 and the third dielectric layer 6007 as shown in FIG. 6J.
[0096] Step 9: Repeat step 1 to step 8 to form another layer of interconnect layer (not shown here).
[0097] Another exemplary embodiment to remove the barrier layer is shown in FIGs. 7A to 71. The process steps are listed as follows:
[0098] Step 1 : Deposit the first dielectric layer 7052, deposit the second dielectric layer 7050, deposit the third dielectric layer 7006, and deposit the fourth dielectric layer 7007 as shown in FlG. 7A. Deposition method can be chemical vapor deposition (CVD) or spin on dielectric method. The first dielectric layer 7052 includes silicon dioxide, fluorosilicate glass (FSG), HSSQ, diamond-like carbon, carbon-doped SiO2, MSSQ, and nonporous silica. The second dielectric layer 7050 is primarily used for the etch stop between via and trench during plasma etching. The second function of the second dielectric layer 7050 is to block the HF or Fluorine atom/ion diffused through the third dielectric layer 7006 (to be described below) from reaching the first dielectric layer 7052 during later electro-polishing process, which will be described in detail below with reference to FIG. 7G. It is clear that HF or Fluorine ion will destroy the first dielectric layer 7052 if they penetrate the second dielectric layer 7050. The second dielectric layer 7050 includes silicone carbide (SiC), Silicon carbide nitride (SiCN), or other dielectric materials with high HF acid resistance and blocking performance. In other words, neither HF nor Fluorine atom/ion should penetrate through the second dielectrics being selected.
[0099] The third dielectric layer 7006 include Polyimides, fluorinated polyimides, polyimide nanofoams, parylene N, Poly(arylene ethers), Poly(arylenes), polynaphthalene family, aromatic hydrocarbon (SiLK), amorphous carbon film, Teflon- AF, Teflon microemulsion, or other low k dielectrics, or ultra low k dielectrics. The fourth dielectric layer 7007 is primarily used for preventing electrolyte from attacking the third dielectric layer 7006. The fourth dielectric material 7007 includes silicone carbide (SiC), silicon carbide nitride (SiCN), aluminum oxide (A12O3) or other dielectric materials with high HF acid resistance and blocking performance. In other words, neither HF nor Fluorine atom/ion should penetrate through the fourth dielectrics being selected.
[00100] Step 2: Deposit the fifth dielectric layer 7001 with thickness of H above the fourth dielectric layer 7007 as shown in FIG. 7A. The fifth dielectric layer 7001 can be silicon oxide, silicon oxide based dielectrics, fluorinated silica, carbon doped silica, and nonporous silica. The fifth dielectric layer 7001 should be selected to be susceptible to being etched by HF acid.
[00101] Step 3: Spin on photo resist, and the details of the lithography steps are well known in state of art, and will not be described here.
[00102] Step4: Etch via 7010 and trench 7009 by plasma as shown in FIG. 7B. [00103] Step 5: Deposit barrier layer 7004 and Cu seed layer 7003 as shown in FIG. 1C. Usually, barrier layer 7004 is made of Tantalum, Tantalum Nitride, Titanium, Titanium Nitride, Tungsten, Tungsten Nitride, Ruthenium, Zirconium, Niobium, Molybdenum, Technetium, Rhodium, Palladium, Hafnium, Rhenium, Osmium, and Iridium.
[001041 Step 7: Plate Cu layer 7002 to fill via and trench as shown in FIG. 7D. The plated Cu layer can be further planarized by chemical mechanical polishing (CMP) as disclosed in PCT Patent Application No. PCT/US02/26167 and U.S. Patent Application Serial No. 10/486,982, which are incorporated here by reference in their entireties for all purposes, or can be formed by the flat plating using dummy structure as disclosed in PCT Patent Application No. PCT/US03/11417 and U.S. Patent Application No. 10/510,656, which are incorporated hereby reference in their entireties, or can be electro-polished with contacting pad nozzle disclosed in US Provisional Application Serial No. 60/738,250, which is incorporated herein by reference in its entirety.
[00105] Step 7: Remove Cu layer using the electro-polishing process described above with reference to FIGs. IA-I C and the apparatus to be described below with reference to FIGs. 8A-8F.
[00106] FIG. 7E shows the cross section of a Cu interconnect structure just as the Cu layer 7002 is being removed from barrier layer 7004 by using the electro-polishing process. As the electro-polishing process continues, the Cu film in the trench will start to recess, and barrier layer will be removed away as shown in FIG. 7F. As barrier layer is being removed, the electro-polishing process will stop due to the absence of a current conducting path. Thus, both Cu inside the trench 7002 and barrier layer between Cu trench 7002 and dielectrics will be isolated from the electro-polishing process, or the polishing process will self-terminate. On the other hand, the barrier residual 7015 may remain on the surface of the fourth dielectric layer 7001 as shown in FIG. 7F. It is recommended to use constant voltage to perform the above electro-polishing process.
[00107] As described before, the fifth dielectric layer 7001 is made of silicon oxide, silicon oxide based dielectrics, fluorinated silica, carbon doped silica, and nonporous silica, which can be etched away by HF acid. Therefore, the fifth dielectric layer is etched away by HF acid in the electrolyte as shown in FIG. 7G. As the etching process continues, eventually the barrier residual 7015 will be removed due to undercut etching of dielectrics 7021 underneath as shown in FIGs. 7G and 7H. The fourth dielectric layer 7007 is made of silicone carbide (SiC), silicon carbide nitride (SiCN), aluminum oxide (A12O3) or other dielectric materials with high HF acid resistance and blocking performance. Therefore the third dielectric layer 7006 underneath the fourth dielectric layer 7007 is protected from being attacked by the electrolyte mainly HF. Thickness of the fourth dielectric layer 7007 is in the range of 5 nm to 100 πm, depending on semiconductor manufacture node.
[00108] It is important to obtain a flat surface as shown in FIG. 7H in order to give better performance for the following lithograph process. Therefore the Cu trench recess D as shown in FlG. 7F should be controlled to be equal to thickness H of the third dielectric layer 7001. The Cu recess D can be controlled by the removal rate ratio of barrier layer to Cu metal. More particularly, HF concentration in electrolyte determines the removal rate ratio of barrier layer to Cu metal layer. For example within 5% wt HF concentration, the removal rate ratio of barrier layer (Ta and or TaN) to Cu metal layer is almost proportional to HF concentration. Thus, the process should be performed as follows: a. Based on barrier layer thickness for each manufacture node, the HF concentration should be determined to make sure minimum Cu recess and at the same time all Cu residual being removed before the barrier layer being removed. The minimum Cu recess can be in the range of 2 to 10 times of thickness of barrier layer 7004;
b. Based on the measured minimum recess of Cu trench, then design the thickness of the fifth dielectric layer to be equal to the minimum of Cu trench recess.
1001091 For example, for 65 nm manufacture node, the thickness of barrier layer is 7 nm. The Cu recess will be around 30 nm if 5% wt HF concentration is used in a phosphoric/Sulfuric acid/Ethylene Glycol/Glycerin based electrolyte. Therefore the thickness of fifth dielectric layer 7001 should be designed around 30 nm.
[00110] As another example: for 65 nm manufacture node, the thickness of barrier layer is 7 nm. The Cu recess will be around 60 nm if 2.5% wt HF concentration is used in a phosphoric/Sulfuric acid/Ethylene Glycol/Glycerin based electrolyte. Therefore the thickness of fifth dielectric layer 7001 should be designed around 60 nm.
[00111] After the electro-polishing, the wafer will be transferred to a cleaning cell for removing all chemicals. The additional HF based chemical can be further injected on the wafer surface to etch away barrier residual in case of some barrier residuals are not fully removed in the electro-polishing cell. For example, for 5% (weight) HF concentration, the etching rate of Tantalum is around 1.5nm/miπ. HF concentration is in the range of 1% wt to 10% wt. Citric acid (C6H8O7) 0.5% wt can be also added in the cleaning process to remove Copper oxide. Citric acid concentration is in the range of 0. l%wt to 1% wt. Then the wafer is further cleaned by pure DI water.
[00112] Step 8: Deposit SiC or SiCN layer 7008 above Cu 7002 and the fourth dielectric layer 7007 as shown in FIG. 71.
[00113] Step 9: Repeat step 1 to step 8 to form another layer of interconnect layer (not shown here).
[00114] FIGs. 8A to 8F show an exemplary embodiment of wafer electro-polishing tool with movable nozzle and/or movable chuck. During the polishing process, as wafer 8014 is rotated around its center axis, chuck 8020 moves laterally so electrolyte column 8034 can selectively polish any portion of metal layer 8013 as shown in FIGs. 8B and 8 C. Moreover, instead of moving chuck 8020 laterally, nozzle 8032 can move laterally as shown in FIGs. 8E and 8F. The lateral speed and the polishing current are two of major parameters used to control polishing rate profile across the surface of wafer 8014. In general, the polishing rate is proportional to polishing current in certain current region, and is reverse proportional to relative speed of chuck 8020 to nozzle 8032.
[00115] As depicted in FIGs. 8A to 8F, the electro-polishing tool can include a power supply 8030. As also depicted in FIG. 8A, the electro-polishing tool can include a control system 8036 connected to the chuck 8020 and the nozzle 8032. Control system 8036 can be configured to apply the stream of electrolyte using the nozzle to the metal layer from the center of the wafer to the edge of the wafer to electro-polish the metal layer and the barrier layer to expose the non-recessed area. It should be recognized that the various embodiments of the electro-polishing tool depicted in FIGs. 8B to 8F can also include the control system 8036 depicted in FIG. 8A. [00116] Although the present invention has been described with respect to certain embodiments, examples, and applications, it will be apparent to those skilled in the art that various modifications and changes may be made without departing from the invention. For example, HF acid can be combined with other slat and acid to form electrolyte to reach the same purpose.

Claims

CLAIMS What is claimed is:
1. A method of electro-polishing a metal layer on a semiconductor wafer comprising: forming a first dielectric layer on the semiconductor wafer, wherein the first dielectric layer is resistant to being etched by hydrogen fluoride acid; forming a second dielectric layer above the first dielectric layer on the semiconductor wafer, wherein the second dielectric layer is susceptible to being etched by hydrogen fluoride acid, wherein the second dielectric layer is formed with a recessed area and a non-recessed area, and wherein the recessed area extends into the first dielectric layer; forming a barrier layer to cover the recessed area and the non-recessed area; forming a metal layer to fill the recessed area and cover the non-recessed area; and electro-polishing the metal layer and the barrier layer to expose the non-recessed area using an electrolyte containing hydrogen fluoride acid.
2. The method of claim 1, wherein the second dielectric layer is set to be the same as an amount of recess expected in the metal layer within the recessed area after electro-polishing.
3. The method of claim 1, wherein the first dielectric layer includes silicon carbide (SiC) or silicon carbide nitride (SiCN).
4. The method of claim 1, wherein the first dielectric layer includes polyimides, fluorinated polyimides, poiyimide nanofoams, parylene N, ρoly(arylene ethers), poly(arylenes), polynaphthalene family, aromatic hydrocarbon (SiLK), amorphous carbon film, Teflon-AF, or Teflon microemulsion.
5. The method of claim 1, wherein the second dielectric layer includes silicon oxide, silicon oxide based dielectrics, fluorinated silica, carbon doped silica, or nonporous silica.
6. The method of claim 1, wherein the hydrogen fluoride acid concentration in the electrolyte is in the range of 0.5% wt to 5% wt.
7. The method of claim 1, wherein the electrolyte includes phosphoric acid (H3PO4), sulfuric acid (H3SO4), ethylene glycol, or glycerin.
8. The method of claim 1, wherein the barrier layer includes Tantalum, Tantalum nitride, Titanium, Titanium nitride, Tungsten, Tungsten nitride, Ruthenium, Ruthenium nitride, Zirconium, Niobium, Molybdenum, Technetium, Rhodium, Palladium, Hafnium, Rhenium, Osmium, or Iridium.
9. The method of claim 1, further comprising: cleaning the electro-polished wafer with hydrogen fluoride at a concentration range of l%wt to 10% wt.
10. The method of claim 1, further comprising: cleaning electro-polished wafer with citric acid at a concentration range of 0.1 %wt to 1% wt.
11. The method of claim 1, further comprising: prior to electro- polish ing the metal layer, planarizing the metal layer to a flat topography using a chemical mechanical planarization process.
12. The method of claim 1, further comprising: rotating the wafer; and while rotating the wafer, applying the electrolyte to the wafer from the center of the wafer to the edge of the wafer.
13. The method of claim 1, further comprising: forming a third dielectric layer below the first dielectric layer, wherein the third dielectric layer is resistant to being etched by hydrogen fluoride acid; and forming a fourth dielectric layer below the third dielectric layer, wherein the fourth dielectric layer is resistant to being etched by hydrogen fluoride acid, wherein the recessed area extends into the third and fourth dielectric layers.
14. The method of claim 13, wherein the third dielectric layer includes silicon carbide (SiC) or silicon carbide nitride (SiCN).
15. The method of claim 13, wherein the fourth dielectric layer includes Polyimides, fluorinated polyimides, polyimide nanofoams, parylene N, Poly(arylene ethers), Poly(arylenes), polynaphthalene family, aromatic hydrocarbon (SiLK), amorphous carbon film, Teflon-AF, Teflon microemulsion, silicon oxide, silicon oxide based dielectrics, fluorinated silica, carbon doped silica, or nonporous silica.
16. The method of claim 13, further comprising: forming a fifth dielectric layer below the fourth dielectric layer, wherein the fifth dielectric layer is susceptible to being etched by hydrogen fluoride acid, and wherein the recessed area extends into the fifth dielectric layer.
17. The method of claim 16, wherein the fifth dielectric layer includes silicon oxide, silicon oxide based dielectrics, fluorinated silica, carbon doped silica, or nonporous silica.
18. The method of claim 1, further comprising: forming a third dielectric layer below the first dielectric layer, wherein the third dielectric layer is resistant to being etched by hydrogen fluoride acid, wherein the recessed area extends into the third dielectric layer.
19. ' The method of claim 18, wherein the third dielectric layer includes a silicon carbide (SiC) or silicon carbide nitride (SiCN).
20. The method of claim 18, wherein the third dielectric layer includes polyimides, fluorinated polyimides, polyimide nanofoams, parylene N, poly(arylene ethers), poly(arylenes), polynaphthalene family, aromatic hydrocarbon (SiLK), amorphous carbon film, Teflon-AF, or Teflon microemulsion.
21. The method of claim 1 , further comprising: forming a third dielectric layer below the first dielectric layer, wherein the third dielectric layer is resistant to being etched by hydrogen fluoride acid; and forming a fourth dielectric layer below the third dielectric layer, wherein the fourth dielectric layer is susceptible to being etched by hydrogen fluoride acid, wherein the recessed area extends into the third and fourth dielectric layers.
22. The method of claim 21, wherein the third dielectric layer includes Polyimides, fluorinated polyimides, polyimide nanofoams, parylene N, Poly(arylene ethers), Poly(arylenes), polynaphthalene family, aromatic hydrocarbon (SiLK), amorphous carbon film, Teflon-AF, or Teflon microemulsion.
23. The method of claim 21, wherein the fourth dielectric layer includes silicon oxide, silicon oxide based dielectrics, fluorinated silica, carbon doped silica, or nonporous silica.
24. A system to electro-polishing a metal layer on a semiconductor wafer, the system comprising: a chuck configured to rotate the wafer; a nozzle configured to apply a stream of electrolyte to the metal layer, wherein the electrolyte includes hydrogen fluoride acid, wherein the metal layer is on top of a barrier layer, which is formed on top of a second dielectric layer, which is formed on top of a first dielectric layer, wherein the first dielectric layer is resistant to being etched by the hydrogen fluoride acid, wherein the second dielectric layer is susceptible to being etched by hydrogen fluoride acid, wherein the second dielectric layer is formed with a recessed area and a non-recessed area, wherein the recessed area extends into the dielectric first dielectric layer, wherein the barrier layer covers the recessed area and the non-recessed area, and the metal layer fills the recessed area and covers the non- recessed area; and a control system connected to the chuck and the nozzle, wherein the control system is configured to apply the stream of electrolyte using the nozzle to the metal layer from the center of the wafer to the edge of the wafer to electro-polish the metal layer and the barrier layer to expose the non-recessed area.
PCT/US2007/010628 2006-05-02 2007-05-02 Removing barnier layer using an electron polishing process WO2007130452A1 (en)

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