Classifications

• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
  • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
  • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
  • H01L29/70—Bipolar devices
  • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
  • H01L29/73—Bipolar junction transistors
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
  • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
  • H01L29/66007—Multistep manufacturing processes
  • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
  • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
  • H01L29/66234—Bipolar junction transistors [BJT]
  • H01L29/66272—Silicon vertical transistors
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
  • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
  • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
  • H01L21/22—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities
  • H01L21/225—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities using diffusion into or out of a solid from or into a solid phase, e.g. a doped oxide layer
  • H01L21/2251—Diffusion into or out of group IV semiconductors
  • H01L21/2254—Diffusion into or out of group IV semiconductors from or through or into an applied layer, e.g. photoresist, nitrides
  • H01L21/2257—Diffusion into or out of group IV semiconductors from or through or into an applied layer, e.g. photoresist, nitrides the applied layer being silicon or silicide or SIPOS, e.g. polysilicon, porous silicon

Definitions

• the present invention relates to the production of semiconductor components and in particular to the production of bipolar transistors with polysilicon emitters, which have a reduced emitter resistance.
• One embodiment of a bipolar transistor with a polysilicon emitter has a highly doped polysilicon layer which lies above the base and which serves both as a diffusion source for the formation of a flat (emitter / base) semiconductor junction and as a device for contacting the flat emitter region , According to the conventional
• Process steps for producing the base region and the emitter window openings are carried out with either undoped or doped polysilicon, into which an exact amount of arsenic atoms is subsequently implanted if the polysilicon is undoped. Then damage is healed by heat treatment (tempering) and the emitter / base semiconductor junction is formed.
• one of the critical process steps in the manufacture of bipolar transistors with polysilicon emitters is the treatment of the wafer just before the application of the poly Silicon.
• the many different treatments known in the prior art can be roughly divided into two categories.
• the first treatment concerns an intentional or unintentional growth of a thin oxide layer (0.2 to 2 nm).
• the second treatment concerns the growth of a thin thermal nitride layer (approximately 1.0 to 1.5 nm).
• "Interface” treatment is important because it has a strong impact on the electrical characteristics of bipolar transistors with polysilicon emitters.
• polysilicon has the following decisive advantage for the operating properties of the transistor that the interface between the polysilicon layer and the single crystal silicon substrate serves as a diffusion barrier for minority carriers which are injected from the base, as a result of which the current gain and the cutoff frequency of the transistor are significantly increased ,
• a disadvantage of polysilicon is the specific resistance, which is orders of magnitude higher than that of metals.
• the resulting relatively high emitter resistance particularly affects the high frequency properties of the bipolar transistor.
• attempts have been made to use the thinnest possible polysilicon layer.
• there is also a certain minimum thickness of mostly required well over 100 nm since a contact hole etching for the contact pads on this polysilicon layer must stop in order to increase the process reliability in the manufacture of the bipolar transistors. guarantee.
• the problem with the emitter resistance is increased in modern bipolar transistors with very narrow emitter windows, since in this case the polysilicon used can completely fill the emitter window, and the height of the polysilicon layer above the active emitter thus increases further.
• an amorphous silicon can also be used, which in turn can crystallize out at later tempering.
• Suicides are metal / silicon compounds that are used in silicon technology as temperature-stable, low-resistance conductor tracks and contacts.
• the silicide layers are typically 0.1 to 0.2 ⁇ m thick. However, the silicide layer formed in this way is generally relatively irregular, and it is also not possible in practice to fill the emitter window with this layer.
• the layer thickness of the polysilicon was kept as low as possible and the doping thereof was kept as high as possible.
• Polysilicon was avoided where possible, but this was easier with older technologies due to the larger emitter dimensions. If a very narrow gap remains after the deposition of the polysilicon on the emitter, depending on the technology, an increased outlay in the contact hole etching was necessary, since this gap continues during the deposition. rer layers with an undesirable material, e.g. B. can be filled with a nitride barrier.
• the object of the present invention is to provide an improved method for producing a bipolar transistor with a polysilicon emitter, the emitter resistance of which is significantly reduced in order to improve the electrical properties of the bipolar transistor.
• This object is achieved by a method for producing a bipolar transistor with a polysilicon emitter according to claim 1.
• a collector region of a first conductivity type and a base region of a second conductivity type are first generated.
• at least one layer of an insulating material is applied, the at least one layer being structured so that at least a portion of the base region is exposed.
• a layer is produced from a polycrystalline semiconductor material of the first conductivity type that is heavily doped with doping atoms, so that essentially the exposed section is covered.
• the present invention is based on the finding that the specific resistance of the emitter connection can be reduced by the formation of an emitter double layer in the production of a bipolar transistor with a polysilicon emitter and the electrical characteristics of the component can thus be significantly improved.
• the emitter of the bipolar transistor is deposited in two stages.
• the first layer consists of a conventional, highly doped polysilicon material.
• the polysilicon layer now only serves as a source for the doping material and for producing a polysilicon single crystal interface between the polysilicon layer and the single crystal semiconductor material of the substrate.
• the polysilicon layer used can thus be selected to be considerably thinner than previously.
• the second applied layer is a layer made of a highly conductive material, by means of which the lead resistance to the emitter of the bipolar transistor is kept low.
• This highly conductive layer also serves as a stop layer for the contact hole etching to be carried out for the different contact connection areas. This layer can completely fill the emitter window without significantly impairing, ie increasing, the emitter resistance.
• This second highly conductive layer has to withstand the high temperatures of the emitter annealing (the temperature treatment) of typically about 1000 ° C or higher and should also be used for manufacturing reasons in the various manufacturing processes, such as e.g. in dry etching processes, have similar properties to the silicon material used.
• the first, lower layer consists of a polysilicon material, which acts as a dopant source for the active transistor region
• the second, upper layer consists of a highly conductive material, which acts as an etching stop for the contact hole etching of the contact pads and also for vertical current transport between the Contact pads and the polysilicon emitter is used.
• FIG. 2 shows the state of the production process of a bipolar transistor with a polysilicon emitter with a narrow emitter window after the structuring of the emitter double layer, after the annealing and the contacting.
• a single-crystalline silicon body is preferably used, which serves as substrate 10 for the bipolar transistor.
• a first region 12 of a first conductivity type is formed in the substrate 10, this region 12 being referred to below as the collector region.
• a further region 14 of a second conductivity type is formed in the substrate 10, which region is referred to hereinafter as the base region 14.
• the first conductivity type denotes a so-called n-type doping
• the second conductivity type denotes a so-called p-type doping
• Doping in a semiconductor material is referred to as n-type if the majority charge carriers therein are electrons
• doping in a semiconductor material is referred to as p-type if the majority charge carriers are holes therein.
• the conductivity types of the doping can also be selected in reverse.
• the base region 14 is adjacent to the collector region 12, at least a portion of the base region 14 being formed between the surface 15 of the substrate 10 and the collector region 12.
• this layer 17 serves as a p-doped base connection region for the base region 14.
• a dielectric (insulating) material wherein the dielectric layers are structured such that at least a portion of the base region 14 is exposed.
• a layer 18 of a polycrystalline semi-material, preferably polysilicon is applied so that this polysilicon layer 18 essentially covers the exposed portion of the base region 14.
• the polysilicon layer 18 Since undoped polysilicon layers are very high-resistance (about 10 4 ⁇ cm), in the present case, the polysilicon layer 18, since this has an electrically conductive function in the transistor, with dopants, for. B. boron, phosphorus or arsenic, to achieve the respective doping type, the desired doping level and thus the desired electrical conductivity of the polysilicon layer.
• dopants for. B. boron, phosphorus or arsenic
• the doping of the polysilicon layer 18 is generally achieved during the polysilicon deposition by adding suitable materials.
• the polysilicon layer 18 has the first conductivity type (n type).
• a highly doped polysilicon material is preferably already applied, since a further, second layer 20 made of a highly conductive material is applied directly to the existing polysilicon layer 18 in order to form a so-called emitter double layer with the polysilicon layer 18.
• the second layer 20 made of a highly conductive material is usually a silicide layer.
• Suicides are metal / silicon compounds that are used in silicon technology as temperature-stable, low-resistance materials. These silicide layers are typically 0.1 to 0.2 ⁇ m thick, with a thickness of 0.1 to 0.2 ⁇ m meaning the deposited thickness on flat surfaces. The thickness or height of the silicide layer in the emitter window can therefore be well above 0.2 ⁇ m, for example 0.5 ⁇ m. Suicides like MoSi 2 or WSi 2 are most commonly used.
• FIG. 2 To explain the further steps of the method according to the invention for producing a bipolar transistor with poly Silicon emitter is now referred to FIG. 2.
• the present semiconductor structure is now subjected to a temperature treatment (tempering), so that at least some of the dopants from the highly doped polysilicon layer 18 diffuse into the single-crystalline body, ie into the substrate 10.
• the active emitter region 22 is formed in the substrate, that is to say in particular adjacent to the base region 14.
• At least some of the doping atoms of the first conductivity type of the highly doped polysilicon layer 18 thus enter the substrate in order to produce an active emitter region 22 of the first conductivity type adjacent to the base region 14 in the substrate 10.
• the active emitter region 22 extends from the interface 15 between the polysilicon layer 18 and the substrate 10 into the semiconductor material of the substrate 10.
• a temperature treatment, or annealing is understood in silicon technology to be the treatment of silicon at elevated temperatures in an inert atmosphere, e.g. B. nitrogen, argon, hydrogen, forming gas. No new layers grow and no material is removed, but the existing layers and the silicon substrate itself undergo decisive changes.
• the dopants of the first or second conductivity type of the different, differently doped polysilicon layers 17, 18 thereby get into the adjacent semiconductor material of the semiconductor substrate 10.
• the emitter double layer consisting of the polysilicon layer 18 and the highly conductive second layer 20 is patterned in order to produce an emitter connection region of the bipolar transistor.
• the structuring is usually carried out by dry etching of the respective layers.
• the process control is simplified if the upper, highly conductive silicide layer 20 has essentially the same or comparable processing properties, for example etching properties, as the polysilicon layer 18.
• the exposed sections on the semiconductor structure now present are now usually filled with a final insulation material 28. Furthermore, so-called contact holes are etched in order to provide the contact connection 24 for the emitter connection region and the contact connections 26 for the base connection region 17.
• the silicide layer 20 serves as an etching stop for the contact hole etching.
• the specific resistance of the emitter connection region can be significantly reduced, as a result of which the electrical characteristics of a bipolar transistor can be significantly improved.
• the reduction in the emitter resistance achieved by the deposited emitter double layer has a positive effect on the cut-off frequency and generally also on the voltage and power amplification in a circuit.
• the advantageous concept according to the invention for producing a bipolar transistor with a polysilicon emitter thus consists, in summary, of carrying out the deposition of the emitter connection region in two stages.
• the first layer 18 consists of the usual highly doped polysilicon material.
• the second layer 20 is a layer made of a highly conductive material, which keeps the lead resistance low and serves as a stop layer for the contact hole etching. It can fill the emitter window without significantly increasing the emitter resistance. In the preferred process control, this second layer 20 must withstand the high temperatures of the emitter tempering, which are typically around 1000 ° C. or higher, and can have properties comparable to those of the silicon material in order to simplify the process control in dry etching processes.
• a two-layer emitter deposition is therefore carried out according to the invention, the lower layer made of polysilicon as a dopant source for the active transistor region and the upper, highly conductive layer as an etching stop for the contact hole etching and for the vertical current transport between the contact hole and Polysilicon emitter is effective.
• the present invention can also be applied to different transistor architectures, in particular with an epitaxially grown base region.
• transistor architectures in which the base area and sometimes also part of the collector area are grown epitaxially on the substrate. With these architectures Ren, which may be used more and more in the future, the emitter double layer according to the invention can also be used advantageously.

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• Engineering & Computer Science (AREA)
• Microelectronics & Electronic Packaging (AREA)
• Power Engineering (AREA)
• Physics & Mathematics (AREA)
• Ceramic Engineering (AREA)
• Condensed Matter Physics & Semiconductors (AREA)
• General Physics & Mathematics (AREA)
• Computer Hardware Design (AREA)
• Manufacturing & Machinery (AREA)
• Bipolar Transistors (AREA)

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• 2001
  • 2001-07-13 DE DE10134089A patent/DE10134089A1/de not_active Withdrawn
• 2002
  • 2002-07-10 EP EP02753085A patent/EP1407484A2/de not_active Withdrawn
  • 2002-07-10 CN CNB028141016A patent/CN100362636C/zh not_active Expired - Fee Related
  • 2002-07-10 WO PCT/EP2002/008234 patent/WO2003007361A2/de active Application Filing
  • 2002-07-10 KR KR10-2004-7000535A patent/KR20040013146A/ko not_active Application Discontinuation
  • 2002-07-12 TW TW091115532A patent/TW554488B/zh not_active IP Right Cessation
• 2004
  • 2004-01-13 US US10/757,360 patent/US7060583B2/en not_active Expired - Lifetime

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