EP1317777A1 - Cellule de memoire a semi-conducteur pourvue d'un condensateur en tranchee et d'un transistor de selection, et son procede de production - Google Patents

Cellule de memoire a semi-conducteur pourvue d'un condensateur en tranchee et d'un transistor de selection, et son procede de production

Info

Publication number
EP1317777A1
EP1317777A1 EP01962672A EP01962672A EP1317777A1 EP 1317777 A1 EP1317777 A1 EP 1317777A1 EP 01962672 A EP01962672 A EP 01962672A EP 01962672 A EP01962672 A EP 01962672A EP 1317777 A1 EP1317777 A1 EP 1317777A1
Authority
EP
European Patent Office
Prior art keywords
trench
semiconductor memory
diffusion barrier
conductive
selection transistor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP01962672A
Other languages
German (de)
English (en)
Inventor
Wolfram Karcher
Dietmar Temmler
Martin Schrems
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Infineon Technologies AG
Original Assignee
Infineon Technologies AG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Infineon Technologies AG filed Critical Infineon Technologies AG
Publication of EP1317777A1 publication Critical patent/EP1317777A1/fr
Withdrawn legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/03—Making the capacitor or connections thereto
    • H10B12/038—Making the capacitor or connections thereto the capacitor being in a trench in the substrate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/37—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells the capacitor being at least partially in a trench in the substrate
    • H10B12/373—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells the capacitor being at least partially in a trench in the substrate the capacitor extending under or around the transistor

Definitions

  • the present invention relates to a semiconductor memory cell with a trench capacitor and a selection transistor and a method for their production.
  • Integrated circuits (ICs) or chips use capacitors for the purpose of charge storage, e.g. a dynamic random access memory (DRAM).
  • DRAM dynamic random access memory
  • the state of charge in the capacitor represents a data bit.
  • a DRAM chip contains a matrix of memory cells, which are arranged in the form of rows and columns and are driven by word lines and bit lines. The reading out of data from the memory cells or the writing of data into the memory cells is accomplished by activating suitable word lines and bit lines.
  • a DRAM memory cell usually contains a transistor connected to a capacitor.
  • the transistor contains two diffusion regions which are separated from one another by a channel which is controlled by a gate. Depending on the direction of the current flow, one diffusion region is referred to as a drain and the other as a source.
  • the drain region is connected to the bit line, the source region to the trench capacitor and the gate to the word line.
  • the transistor By applying appropriate voltages to the gate, the transistor is controlled so that current flow between the drain and source regions through the channel is turned on and off.
  • DRAM dynamic RAM
  • a problem with the known DRAM variants is the generation of a sufficiently large capacitance in the trench capacitor. This problem will be exacerbated in the future by the progressive miniaturization of semiconductor components.
  • the continuous increase in the integration density means that the area available per memory cell and thus the capacitance of the trench capacitor continues to decrease. Too little capacitance in the trench capacitor can adversely affect the functionality and usability of the storage device, since too little charge is stored in the trench capacitor.
  • sense amplifiers require a sufficient signal level for reliable reading out of the information located in the memory cell.
  • the ratio of the storage capacity of the trench capacitor to the bit line capacitance is crucial when determining the signal level. If the storage capacity of the trench capacitor is too small, this ratio may be too small to generate a sufficient signal in the sense amplifier.
  • a low storage capacity also requires a higher refresh frequency, since the amount of charge stored in the trench capacitor is limited by its capacity and additionally decreases due to leakage currents. If the amount of charge in the storage capacitor falls below a minimum, it is no longer possible to read out the information stored in it with the connected sense amplifiers, the information is lost and reading errors occur. ⁇
  • the outdiffusion of the dopant typically extends over distances between 50 and 150 nanometers (nm). It must be ensured here that the dopant does not diffuse into the channel of the selection transistor, where it can lead to increased leakage currents through the transistor, which render the memory cell in question unusable. This means that a memory cell that is theoretically possible without out-diffusion must be enlarged by the size of the out-diffusion.
  • the task is solved by a semiconductor memory cell with:
  • a selection transistor which is designed as a planar transistor above the trench capacitor; a capacitor dielectric, which is arranged in the trench;
  • a source doping region of the selection transistor which is arranged in the epitaxial layer.
  • the arrangement according to the invention initially arranges a diffusion barrier on the conductive trench filling.
  • the purpose of the diffusion barrier is to prevent dopant in the conductive trench filling from diffusing out, which could damage the selection transistor. What is new is that the diffusion barrier is horizontal. To the space used by the memory cell as possible
  • the inner hole in the cover layer ensures that electrical contact can be established between the conductive trench filling and the source doping region of the selection transistor arranged in the epitaxial layer.
  • a conductive contact is arranged in the inner hole.
  • the conductive contact is designed such that it contacts the conductive trench filling and fills the inner hole of the dielectric layer.
  • the conductive trench filling comprises tungsten, tungsten nitride, titanium nitride, arsenic or phosphorus-doped poly- or amorphous silicon.
  • Another advantageous embodiment of the invention provides that the conductive contact connects the conductive trench filling to the source doping region of the selection transistor. This arrangement makes a conductive contact between the trench capacitor and the selection transistor.
  • the cross-sectional area of the inner hole in the dielectric layer is smaller than the cross-sectional area of the trench.
  • Source doping region additionally has the advantage that the leakage current between the channel and the source doping region is reduced.
  • the insulating cover layer is designed as a lateral edge web.
  • the formation of the insulating cover layer as a lateral edge web comprises for example, that the insulating cover layer is produced using a spacer technique. For this purpose, an insulating layer is deposited conformally on the surface and etched back, the insulating cover layer being formed as a lateral edge web in the trench.
  • the insulating cover layer has an upper edge, and the diffusion barrier is arranged completely below the upper edge.
  • the advantage of this arrangement is an inexpensive manufacture.
  • Another advantage is that if crystal dislocations form at the interface, they cannot slide out of the contact area due to the dielectric annular layer.
  • a further embodiment of the arrangement according to the invention provides that the cover layer has an upper edge and the conductive contact is arranged above the upper edge.
  • the advantage of this arrangement is a larger contact area and thus a reduced resistance, especially if a thin dielectric barrier such as e.g. 1 nm thick silicon nitride is used.
  • the diffusion barrier is arranged on the conductive contact.
  • the object is achieved by a method for producing a semiconductor memory cell with: forming a trench capacitor in a trench which has an upper region and a lower region and is filled with a conductive trench filling; Forming a diffusion barrier on the conductive trench fill; - Epitaxial overgrowth of the diffusion barrier with an epitaxial layer; - Subsequently forming a selection transistor as a planar transistor above the trench capacitor, a source doping region of the selection transistor being formed in the epitaxial layer.
  • One embodiment of the method according to the invention provides that after an epitaxial overgrowth of the diffusion barrier, a reflow process is carried out at a higher temperature than the epitaxial overgrowth.
  • a reflow process is that the epitaxially grown silicon can planarize a surface due to the elevated temperature, for example through a flow effect, and growth defects can be cured.
  • Another advantageous embodiment of the method according to the invention provides that the reflow process is carried out with the addition of hydrogen.
  • the advantage of this process step is that improved planarization and a further reduction in growth defects are achieved.
  • Figure 1 shows a trench capacitor with a selection transistor
  • Figure 2 shows another embodiment of a trench capacitor with a selection transistor
  • FIG. 3 shows a further example of a trench capacitor with a selection transistor, the trench capacitor being connected to the selection transistor with a conductive contact;
  • FIGS. 4 to 8 show a manufacturing method for forming the memory cell shown in FIG. 3;
  • FIGS. 9 to 11 show a production method for forming the memory cell shown in FIG. 2.
  • a memory cell 1 according to the invention is shown in FIG.
  • the memory cell 1 is formed in a substrate 2.
  • the substrate 2 is usually silicon, which can be lightly p- or n-doped (10 15 - 10 17 dopant atoms per cubic centimeter).
  • the memory cell 1 comprises a trench capacitor 3 and a selection transistor 4.
  • the trench capacitor 3 is formed in a trench 5, the lower region of the trench 5 being surrounded by a buried plate 6.
  • the buried plate 6 is a conductive layer that can be formed, for example, by introducing dopant into the substrate 2.
  • the buried plate is doped much more strongly with up to 10 21 dopants / cm 3 .
  • the buried plate 6 is electrically contacted by a buried trough 7, which is also a doped layer, which has the same dopant type as the buried plate 6.
  • An insulation collar 9 is arranged in an upper region of the trench 5.
  • the insulation collar 9 is usually formed from silicon oxide, silicon nitride or a silicon oxynitride.
  • a dielectric layer 8 is formed in the trench 5, the layer 8 being buried in the lower region of the trench
  • the dielectric layer 8 is formed, for example, from a silicon oxynitride. Optionally, it can also be a layer stack made of silicon oxide, silicon nitride and silicon oxynitride.
  • the dielectric layer 8 has the task of the buried plate 6 against a conductive trench filling 10, which in the Trench 5 is arranged to isolate.
  • the buried plate 6 represents an outer capacitor electrode, the conductive trench filling 10 an inner capacitor electrode and the dielectric layer 8 the capacitor dielectric.
  • the selection transistor 4 comprises a source region 12, a drain region 13 and a gate 14, on which a word line 15 is arranged.
  • the source region 12 is connected to a bit line 17 with a bit line contact 16.
  • Bit line 17 is isolated from word line 15 by means of intermediate insulation 18.
  • the drain region 13 lies above the trench 5, the drain region 13 being connected to the conductive trench filling 10 by means of a diffusion barrier 19.
  • the conductive trench filling 10 is usually designed as highly doped and thus low-resistance silicon.
  • a diffusion barrier 19 is arranged between the conductive trench filling 10 and the drain doping region 13.
  • the diffusion barrier 19 is arranged planar on the conductive trench filling 10. The diffusion barrier 19 extends from the dielectric layer 8 to the isolation trench 11.
  • FIG. 2 shows a further exemplary embodiment of a memory cell 1 according to the invention.
  • an insulating cover layer 20 with an inner hole 21 is arranged on the conductive trench filling 10.
  • the diffusion barrier 19 is arranged in the inner hole 21.
  • the insulating cover layer 20 is formed from silicon oxide or silicon nitride or a silicon oxynitride.
  • the diffusion barrier 19 contacts the conductive trench filling 10 with the drain doping region 13. Since part of the cross-sectional area of the trench 5 is covered by the insulating cover layer 20 and only the region of the inner hole 21 and the diffusion barrier 19 are contacted by the drain region 13, the drain region 13 and so that the selection transistor 4 are made significantly smaller. This has the advantage that a larger proportion of the substrate surface can be used by the trench capacitor 3, and thus the capacitance of the trench capacitor 3 can be increased.
  • FIG. 3 A further exemplary embodiment of a memory cell 1 according to the invention is illustrated with reference to FIG. 3.
  • the difference from FIG. 2 is that a conductive contact 22 is formed in the inner hole 21, which is arranged in the insulating cover layer 20.
  • the conductive contact 22 is in turn covered with a diffusion barrier 19, so that the diffusion of dopant out of the conductive trench filling 10 through the diffusion barrier 19 is prevented.
  • the conductive contact 22 is formed in such a way that it projects beyond an upper edge 27 of the insulating cover layer 20 and thus projects into the drain doping region 13. This ensures low-resistance contact between the conductive trench filling 10 and the drain region 13.
  • FIG. 4 A method for producing the memory cell 1 shown in FIG. 3 is described with reference to FIGS. 4 to 8.
  • a substrate 2 which is, for example, a p-doped silicon substrate, is provided.
  • a mask 23 is arranged on the substrate 2 and is used to etch the trench 5.
  • the insulation collar 9 is then formed in the upper region of the trench 5 using the usual methods.
  • the buried plate 6 is formed in the lower region of the trench 5 by introducing dopant into the trench 5. Since the substrate 2 is weakly p-doped, a high n-doping is chosen as the doping of the buried plate 6.
  • the buried trough 7 can, for example, be ⁇ C * to t ⁇ > 1
  • CD ⁇ ⁇ CD tr P- 1 P rr SP ⁇ ⁇ i P 3 ⁇ tr ⁇ - N ⁇ P tr ⁇ - -3 ⁇ - X rr ⁇ - li ü ti 3 P ro ⁇ -_ Pi Pi P ⁇ P Pi ⁇ CD ⁇ LQ ti ⁇ - ⁇ - CD ⁇ - rr 03 rt P -3
  • P CD ⁇ P tr P CD 01 P ⁇ ⁇ P ⁇ - o ⁇ ⁇ ⁇ CQ rr o tr cn H ⁇ - r rt LQ opens to P- P
  • Layer or a diffusion barrier 19 are formed on the conductive contact 22.
  • the insulation collar 9 and the insulating cover layer 20 are etched back. This can be done, for example, with a time-controlled wet etching of boron hydrofluoric acid or a reactive ion etching with CF 4 .
  • a selective silicon epitaxial layer is formed in the trench 5 above the insulation collar 9 on the exposed substrate 2.
  • the interface surface to the substrate 2 can then be cleaned of a natural oxide at 900 ° C. with the addition of hydrogen with a pressure of 20 torr.
  • a selective epitaxy is initiated at 800-1000 ° C. with the addition of silane and hydrogen for an undoped silicon layer, or with the addition of silane, hydrogen and arsine or phosphine for an in situ doping of the grown epitaxial layer.
  • the process elements consisting of undoped epitaxy, doped epitaxy and reflow process can also be repeated several times in succession in corresponding sequences be carried out.
  • the surface of the grown epitaxial layer is planarized by one or more reflow processes carried out during the selective epitaxy, which are carried out with the addition of hydrogen at 900-1100 ° C., and any growth defects in the epitaxial layer are eliminated.
  • this novel process has the advantage that the defect density or the growth defects in the in situ hydrogen reflow process at a temperature which is higher than the growth temperature Epitaxial layer can be reduced.
  • the specified reflow process can be performed during an epi ⁇ - tt F > F 1 c ⁇ ono cn O cn
  • F- P P- P Hi ⁇ - PP ⁇ - P ⁇ - tr ⁇ ⁇ - ⁇ - X F- ⁇ F 1 P ⁇ ⁇ P • d F- 3 Hl ⁇ VD P c ⁇
  • CD P- P CQ tr ⁇ - ⁇ - P- F- P -3 ⁇ tr P ⁇ P P CQ ⁇ - X ro P P- to P ro CD ⁇ - F- rt N p rr ⁇ to ⁇ P P P ⁇ . p. rt F- P P
  • Substrate 2 planarized. This is achieved, for example, with an RIE sinking process or with a reflow process.
  • the epitaxial growth of the epitaxial layer 24 can also be improved in this exemplary embodiment by one or more reflow processes carried out in the meantime, as a result of which growth defects in the epitaxial layer are reduced.

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Semiconductor Memories (AREA)

Abstract

La présente invention concerne une cellule de mémoire à semi-conducteur (1) qui est formée dans un substrat (2) et comprend un condensateur en tranchée (3) et un transistor de sélection (4). Le condensateur en tranchée (3) comprend un diélectrique de condensateur (8) et un matériau de remplissage de tranchée (10) conducteur. Sur le matériau de remplissage de tranchée (10) conducteur est disposée une barrière de diffusion (19) sur laquelle est formée une couche épitaxiale (24). Le transistor de sélection (4) est placé, en tant que transistor planaire, au-dessus du condensateur en tranchée (3), une zone de dopage de drain (13) du transistor de sélection (4) se trouvant dans la couche épitaxiale (24).
EP01962672A 2000-09-15 2001-08-24 Cellule de memoire a semi-conducteur pourvue d'un condensateur en tranchee et d'un transistor de selection, et son procede de production Withdrawn EP1317777A1 (fr)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
DE10045694 2000-09-15
DE10045694A DE10045694A1 (de) 2000-09-15 2000-09-15 Halbleiterspeicherzelle mit Grabenkondensator und Auswahltransistor und Verfahren zu ihrer Herstellung
PCT/DE2001/003235 WO2002023636A1 (fr) 2000-09-15 2001-08-24 Cellule de memoire a semi-conducteur pourvue d'un condensateur en tranchee et d'un transistor de selection, et son procede de production

Publications (1)

Publication Number Publication Date
EP1317777A1 true EP1317777A1 (fr) 2003-06-11

Family

ID=7656334

Family Applications (1)

Application Number Title Priority Date Filing Date
EP01962672A Withdrawn EP1317777A1 (fr) 2000-09-15 2001-08-24 Cellule de memoire a semi-conducteur pourvue d'un condensateur en tranchee et d'un transistor de selection, et son procede de production

Country Status (7)

Country Link
US (1) US7049647B2 (fr)
EP (1) EP1317777A1 (fr)
JP (1) JP2004509469A (fr)
KR (1) KR100523881B1 (fr)
DE (1) DE10045694A1 (fr)
TW (1) TW518751B (fr)
WO (1) WO2002023636A1 (fr)

Families Citing this family (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE10111499C1 (de) * 2001-03-09 2002-07-11 Infineon Technologies Ag Speicherzelle mit einem Graben und Verfahren zu ihrer Herstellung
KR100631092B1 (ko) 2001-03-09 2006-10-02 인피니언 테크놀로지스 아게 반도체 메모리 셀 및 그 제조 방법
DE10113187C1 (de) 2001-03-19 2002-08-29 Infineon Technologies Ag Verfahren zur Herstellung eines Grabenkondensators einer Speicherzelle eines Halbleiterspeichers
DE10128211C1 (de) * 2001-06-11 2002-07-11 Infineon Technologies Ag Speicher mit einer Speicherzelle, umfassend einen Auswahltransistor und einen Speicherkondensator sowie Verfahren zu seiner Herstellung
DE10153110B4 (de) 2001-10-22 2006-11-30 Infineon Technologies Ag Speicherzelle
US20050090053A1 (en) * 2002-01-21 2005-04-28 Infineon Technologies Ag Memory chip with low-temperature layers in the trench capacitor
DE10202139B4 (de) 2002-01-21 2006-07-13 Infineon Technologies Ag Speicherzelle mit einem dünnen Isolationskragen und Speicherbaustein
DE10208774B4 (de) * 2002-02-28 2005-09-15 Infineon Technologies Ag Verfahren zur Herstellung einer Speicherzelle
US6887768B1 (en) * 2003-05-15 2005-05-03 Lovoltech, Inc. Method and structure for composite trench fill
JP3927179B2 (ja) * 2004-01-06 2007-06-06 株式会社東芝 半導体記憶装置およびその製造方法
US7410864B2 (en) * 2004-04-23 2008-08-12 Infineon Technologies Ag Trench and a trench capacitor and method for forming the same
DE102004040046B4 (de) * 2004-08-18 2008-04-30 Qimonda Ag Herstellungsverfahren für einen Grabenkondensator mit einem Isolationskragen, der über einen vergrabenen Kontakt einseitig mit einem Substrat elektrisch verbunden ist, insbesondere für eine Halbleiterspeicherzelle, und entsprechender Grabenkondensator
TWI278069B (en) * 2005-08-23 2007-04-01 Nanya Technology Corp Method of fabricating a trench capacitor having increased capacitance
US20080160735A1 (en) * 2006-12-28 2008-07-03 Qimonda Ag Forming Polysilicon Regions
US8293625B2 (en) * 2011-01-19 2012-10-23 International Business Machines Corporation Structure and method for hard mask removal on an SOI substrate without using CMP process
US10741638B2 (en) * 2018-08-08 2020-08-11 Infineon Technologies Austria Ag Oxygen inserted Si-layers for reduced substrate dopant outdiffusion in power devices
CN113270407B (zh) * 2021-05-18 2023-03-24 复旦大学 动态随机存取存储器及其制备工艺

Family Cites Families (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4649625A (en) * 1985-10-21 1987-03-17 International Business Machines Corporation Dynamic memory device having a single-crystal transistor on a trench capacitor structure and a fabrication method therefor
US4988637A (en) * 1990-06-29 1991-01-29 International Business Machines Corp. Method for fabricating a mesa transistor-trench capacitor memory cell structure
US5214603A (en) * 1991-08-05 1993-05-25 International Business Machines Corporation Folded bitline, ultra-high density dynamic random access memory having access transistors stacked above trench storage capacitors
EP0535541B1 (fr) * 1991-10-02 1996-03-13 Siemens Aktiengesellschaft Procédé de fabrication d'une structure de fossés dans un substrat
TW241392B (fr) * 1993-04-22 1995-02-21 Ibm
US5641694A (en) * 1994-12-22 1997-06-24 International Business Machines Corporation Method of fabricating vertical epitaxial SOI transistor
US6207494B1 (en) * 1994-12-29 2001-03-27 Infineon Technologies Corporation Isolation collar nitride liner for DRAM process improvement
US5998821A (en) * 1997-05-21 1999-12-07 Kabushiki Kaisha Toshiba Dynamic ram structure having a trench capacitor
US5867420A (en) * 1997-06-11 1999-02-02 Siemens Aktiengesellschaft Reducing oxidation stress in the fabrication of devices
US6008104A (en) * 1998-04-06 1999-12-28 Siemens Aktiengesellschaft Method of fabricating a trench capacitor with a deposited isolation collar
US6194736B1 (en) * 1998-12-17 2001-02-27 International Business Machines Corporation Quantum conductive recrystallization barrier layers
US6297086B1 (en) * 1999-03-11 2001-10-02 International Business Machines Corporation Application of excimer laser anneal to DRAM processing
DE19911149C1 (de) * 1999-03-12 2000-05-18 Siemens Ag Integrierte Schaltungsanordnung, die eine in einem Substrat vergrabene leitende Struktur umfaßt, die mit einem Gebiet des Substrats elektrisch verbunden ist, und Verfahren zu deren Herstellung
DE19941148B4 (de) * 1999-08-30 2006-08-10 Infineon Technologies Ag Speicher mit Grabenkondensator und Auswahltransistor und Verfahren zu seiner Herstellung
US6360758B1 (en) * 1999-09-10 2002-03-26 Metso Paper, Inc. Cleaning device in paper machines, board machines or other similar machines for cleaning a fabric, such as wire or felt
DE19946719A1 (de) * 1999-09-29 2001-04-19 Infineon Technologies Ag Grabenkondensator und Verfahren zu seiner Herstellung

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See references of WO0223636A1 *

Also Published As

Publication number Publication date
KR100523881B1 (ko) 2005-10-26
US7049647B2 (en) 2006-05-23
JP2004509469A (ja) 2004-03-25
TW518751B (en) 2003-01-21
WO2002023636A1 (fr) 2002-03-21
KR20030038742A (ko) 2003-05-16
DE10045694A1 (de) 2002-04-04
US20030168690A1 (en) 2003-09-11

Similar Documents

Publication Publication Date Title
WO2002023636A1 (fr) Cellule de memoire a semi-conducteur pourvue d'un condensateur en tranchee et d'un transistor de selection, et son procede de production
DE10362018B4 (de) Anordnung und Verfahren zur Herstellung von vertikalen Transistorzellen und transistorgesteuerten Speicherzellen
DE19930748C2 (de) Verfahren zur Herstellung von EEPROM- und DRAM-Grabenspeicherzellbereichen auf einem Chip
DE19941148B4 (de) Speicher mit Grabenkondensator und Auswahltransistor und Verfahren zu seiner Herstellung
DE10143283C1 (de) Verfahren zur Herstellung eines Grabenkondensators für einen Halbleiterspeicher
EP0875937A2 (fr) Réseau de cellules DRAM et son procédé de fabrication
DE10046945A1 (de) Verfahren zum Herstellen einer nichtflüchtigen Halbleiterspeichervorrichtung und nichtflüchtige Halbleiterspeichervorrichtung
DE10228717B4 (de) Verfahren zum Isolieren aktiver Bereiche von Halbleiterspeicherelementen und zum Isolieren von Elementgebieten eines Halbleiterwafers
EP0917203A2 (fr) Structure de type gain-cell pour DRAM et son procédé de manufacture
EP0945901A1 (fr) Réseau de cellules DRAM à transistor vertical et son procédé de fabrication
EP1125328B1 (fr) Procede de production d'un ensemble de cellules de memoire ram dynamique
DE19845004C2 (de) DRAM-Zellenanordnung und Verfahren zu deren Herstellung
EP1116270A1 (fr) Ensemble circuit integre comportant des transistors verticaux, et son procede de production
DE10328594B4 (de) Halbleiterbauelement mit einer vergrabenen Brücke und Verfahren zur Herstellung eines Halbleiterbauelements mit einer vergrabenen Brücke
EP1129482B1 (fr) Procédé de production d'une configuration de cellules DRAM
EP0992068A1 (fr) Groupement de cellules de memoire ram statique et son procede de production
WO2000033382A1 (fr) Circuit integre et son procede de fabrication
DE102004063025B4 (de) Speicherbauelement und Verfahren zur Herstellung desselben
DE102004006028B4 (de) Verfahren zum Herstellen von Grabenkondensatoren
DE4407532A1 (de) Halbleiter-Speicherzelle und Verfahren zum Bilden derselben
DE10030696B4 (de) Integrierte Schaltungsanordnung mit zumindest einem vergrabenen Schaltungselement und einer Isolationsschicht sowie Verfahren zu deren Herstellung
DE10128211C1 (de) Speicher mit einer Speicherzelle, umfassend einen Auswahltransistor und einen Speicherkondensator sowie Verfahren zu seiner Herstellung
DE10111760A1 (de) Verfahren zur Herstellung einer Speicherzelle eines Halbleiterspeichers
EP0887862A2 (fr) DRAM à cellules à mémoire de type gain
DE19941147A1 (de) Epitaxieschicht und Verfahren zu ihrer Herstellung

Legal Events

Date Code Title Description
PUAI Public reference made under article 153(3) epc to a published international application that has entered the european phase

Free format text: ORIGINAL CODE: 0009012

17P Request for examination filed

Effective date: 20030317

AK Designated contracting states

Designated state(s): AT BE CH CY DE DK ES FI FR GB GR IE IT LI LU MC NL PT SE TR

RBV Designated contracting states (corrected)

Designated state(s): AT BE CH CY DE FR GB IE IT LI

17Q First examination report despatched

Effective date: 20060920

STAA Information on the status of an ep patent application or granted ep patent

Free format text: STATUS: THE APPLICATION IS DEEMED TO BE WITHDRAWN

18D Application deemed to be withdrawn

Effective date: 20090303