EP1242885A2 - Application continue et decompression de configuration d'essai a un circuit en cours d'essai - Google Patents

Application continue et decompression de configuration d'essai a un circuit en cours d'essai

Info

Publication number
EP1242885A2
EP1242885A2 EP00991744A EP00991744A EP1242885A2 EP 1242885 A2 EP1242885 A2 EP 1242885A2 EP 00991744 A EP00991744 A EP 00991744A EP 00991744 A EP00991744 A EP 00991744A EP 1242885 A2 EP1242885 A2 EP 1242885A2
Authority
EP
European Patent Office
Prior art keywords
test pattern
bits
test
circuit
decompressed
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
EP00991744A
Other languages
German (de)
English (en)
Other versions
EP1242885B1 (fr
EP1242885A4 (fr
Inventor
Janusz Rajski
Jerzy Tyszer
Mark Kassab
Nilanjan Mukherjee
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mentor Graphics Corp
Original Assignee
Mentor Graphics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US09/620,021 external-priority patent/US7493540B1/en
Application filed by Mentor Graphics Corp filed Critical Mentor Graphics Corp
Priority to EP09170518.6A priority Critical patent/EP2128763B1/fr
Publication of EP1242885A2 publication Critical patent/EP1242885A2/fr
Publication of EP1242885A4 publication Critical patent/EP1242885A4/fr
Application granted granted Critical
Publication of EP1242885B1 publication Critical patent/EP1242885B1/fr
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3183—Generation of test inputs, e.g. test vectors, patterns or sequences
    • G01R31/318335—Test pattern compression or decompression
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/31813—Test pattern generators
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
    • G01R31/318544—Scanning methods, algorithms and patterns
    • G01R31/318547—Data generators or compressors

Definitions

  • a tester cannot fill the LFSR with a seed concurrently with the LFSR generating a test pattern from the seed.
  • Each of these acts must be done at mutually exclusive times. This makes the operation of the tester very inefficient, i.e., when the seed is serially loaded to the LFSR the scan chains do not operate; and when the loading of the scan chains takes place, the tester cannot transfer a seed to the LFSR.
  • MP-LFSRs polynomial LFSRs
  • Fig. 11 illustrates the use of parallel-to-serial conversion for applying a compressed test pattern to the decompressor.
  • Fig. 12 is a block diagram of a tester according to the invention for testing digital circuits with scan chains.
  • Fig.6 ...identified in Fig.6.
  • the expressions for each scan chain in Fig.7 are listed in the order in which the information is shifted into the chain, i.e., the topmost expression represents the data shifted in first.
  • the decompressor 36 in Fig.6 is to generate a test pattern based on the following partially specified test cube in Table 2 (the contents of the eight scan chains are shown here horizontally, with the leftmost column representing the information that is shifted first into the scan chains): xxxxxxxx scan chain 0 xxxxxxxx scan chain 1 xxxxl lxx scan chain 2 xxOxxxlx scan chain 3 xxxxOxxl scan chain 4 xxOxOxxx scan chain 5 xxlxlxxx scan chain 6 xxxxxxxx scan chain 7

Landscapes

  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Tests Of Electronic Circuits (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

La présente invention concerne un procédé permettant d'appliquer des configurations d'essai destinées à balayer des chaînes dans un circuit en cours d'essai. Ce procédé consiste à prendre une configuration d'essai compressée de bits, à décompresser cette configuration d'essai compressée en une configuration d'essai décompressée de bits lorsque cette configuration d'essai compressée est fournie, et à appliquer cette configuration d'essai décompressée de façon à balayer des chaînes du circuit en cours de test. Ces étapes sont réalisées de façon synchronisée aux mêmes vitesses d'horloge ou à des vitesses différentes, en fonction de la manière dont les bits décompressés seront générés. Un circuit qui réalise cette décompression comprend un décompresseur tel qu'une machine d'états-finis linéaire adaptée pour recevoir des bits de configuration d'essai décompressés. Ce décompresseur décompresse la configuration d'essai en une configuration d'essai décompressée de bits lorsque la configuration d'essai compressée est reçue. Le circuit comprend aussi des chaînes de balayage destinées à essayer une logique de circuit, ces chaînes de balayage étant couplées au décompresseur et adaptées pour recevoir la configuration d'essai décompressée.
EP00991744A 1999-11-23 2000-11-15 Application continue et decompression de configuration d'essai a un circuit en cours d'essai Expired - Lifetime EP1242885B1 (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
EP09170518.6A EP2128763B1 (fr) 1999-11-23 2000-11-15 Application continue et décompression de configuration d'essai a un circuit en cours d'essai

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
US620021 1996-03-21
US16713199P 1999-11-23 1999-11-23
US167131P 1999-11-23
US09/620,021 US7493540B1 (en) 1999-11-23 2000-07-20 Continuous application and decompression of test patterns to a circuit-under-test
PCT/US2000/042211 WO2001039254A2 (fr) 1999-11-23 2000-11-15 Application continue et decompression de configuration d'essai a un circuit en cours d'essai

Related Child Applications (1)

Application Number Title Priority Date Filing Date
EP09170518.6A Division EP2128763B1 (fr) 1999-11-23 2000-11-15 Application continue et décompression de configuration d'essai a un circuit en cours d'essai

Publications (3)

Publication Number Publication Date
EP1242885A2 true EP1242885A2 (fr) 2002-09-25
EP1242885A4 EP1242885A4 (fr) 2005-01-19
EP1242885B1 EP1242885B1 (fr) 2009-10-07

Family

ID=26862887

Family Applications (1)

Application Number Title Priority Date Filing Date
EP00991744A Expired - Lifetime EP1242885B1 (fr) 1999-11-23 2000-11-15 Application continue et decompression de configuration d'essai a un circuit en cours d'essai

Country Status (4)

Country Link
US (2) US7478296B2 (fr)
EP (1) EP1242885B1 (fr)
JP (2) JP3845016B2 (fr)
WO (1) WO2001039254A2 (fr)

Cited By (1)

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US9664739B2 (en) 1999-11-23 2017-05-30 Mentor Graphics Corporation Continuous application and decompression of test patterns and selective compaction of test responses

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US8533547B2 (en) 1999-11-23 2013-09-10 Mentor Graphics Corporation Continuous application and decompression of test patterns and selective compaction of test responses
US6557129B1 (en) 1999-11-23 2003-04-29 Janusz Rajski Method and apparatus for selectively compacting test responses
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US9134370B2 (en) 1999-11-23 2015-09-15 Mentor Graphics Corporation Continuous application and decompression of test patterns and selective compaction of test responses
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US20030120988A1 (en) 2003-06-26
US7877656B2 (en) 2011-01-25
JP2003526778A (ja) 2003-09-09
US20090183041A1 (en) 2009-07-16
JP4684829B2 (ja) 2011-05-18
EP1242885A4 (fr) 2005-01-19
JP2006078493A (ja) 2006-03-23
US7478296B2 (en) 2009-01-13
JP3845016B2 (ja) 2006-11-15
WO2001039254A2 (fr) 2001-05-31
WO2001039254A3 (fr) 2001-12-13

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