WO2024076370A1 - Technologie de balayage d'observation à autotest intégré et logique multiphase - Google Patents

Technologie de balayage d'observation à autotest intégré et logique multiphase Download PDF

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Publication number
WO2024076370A1
WO2024076370A1 PCT/US2022/077755 US2022077755W WO2024076370A1 WO 2024076370 A1 WO2024076370 A1 WO 2024076370A1 US 2022077755 W US2022077755 W US 2022077755W WO 2024076370 A1 WO2024076370 A1 WO 2024076370A1
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WIPO (PCT)
Prior art keywords
scan
observation
signal
test
circuit
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PCT/US2022/077755
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English (en)
Inventor
Nilanjan Mukherjee
Yingdi LIU
Jedrzej Solecki
Janusz Rajski
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Siemens Industry Software Inc.
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Priority to PCT/US2022/077755 priority Critical patent/WO2024076370A1/fr
Publication of WO2024076370A1 publication Critical patent/WO2024076370A1/fr

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    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
    • G01R31/318541—Scan latches or cell details
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
    • G01R31/318555—Control logic
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
    • G01R31/318558—Addressing or selecting of subparts of the device under test
    • G01R31/318563—Multiple simultaneous testing of subparts

Definitions

  • the presently disclosed technology relates to the field of circuit testing. Various implementations of the disclosed technology may be particularly useful for improving test coverage and reducing test application time.
  • a circuit comprising: scan chains comprising scan cells, the scan cells configured to operate in a shift mode or a capture mode based on a scan enable signal, parallel outputs of the scan cells being coupled to functional circuitry of the circuit; one or more observation scan chains comprising observation scan cells, the observation scan cells configured to operate in a shift mode, a capture mode, or a shiftobservation mode based on the scan enable signal and an observation scan enable signal, outputs of the observation scan cells being uncoupled to functional circuitry of the circuit; and a test controller comprising circuitry configured to generate the scan enable signal and the observation scan enable signal for testing the circuit, the testing comprising a scan-capture phase and an observation scan phase, both the scan cells and the observation scan cells operating in the shift mode and the capture mode alternately during the scancapture phase, and the scan cells operating in the shift mode and the observation scan cells operating in the shift-observation mode during the observation scan phase.
  • a number of test patterns for the observation scan-capture phase may be smaller than or equal to a number of test patterns for the scan phase.
  • the circuit may further comprise a pseudorandom pattern generator configured to generate test patterns to be shifted into the scan chains and the one or more observation scan chains; and a test compactor to compact test responses shifted out from the scan chains and the one or more observation scan chains.
  • Each of the observation scan cells may comprise: a state element; and selection and combination circuitry, the selection and combination circuitry comprising: combination circuitry configured to combine a signal from a serial input port of the each of the observation scan cells with a signal from a parallel input port of the each of the observation scan cells to generate an observation scan signal, and selection circuitry configured to select an input signal for the state element from the signal from the serial input port, the signal from the parallel input port, and the observation scan signal based on the scan enable signal and the observation scan enable signal.
  • the combination circuitry may comprise an XOR gate.
  • the state element may be a flip-flop.
  • the selection circuitry comprises a 2-to-l multiplexer and two AND gates.
  • the selection and combination circuitry may further comprise: another combination circuitry configured to combine the signal from the parallel input port with an output signal of the state element to generate a capture-accumulation signal, wherein the selection circuitry is configured to select the input signal for the state element from the signal from the serial input port, the signal from the parallel input port, the observation scan signal, and the capture-accumulation signal based on the scan enable signal and the observation scan enable signal.
  • non-transitory computer-readable media storing computer-executable instructions for causing one or more processors to perform a method, the method comprising: creating the above circuit in a circuit design.
  • a method comprising: testing a circuit, wherein the circuit comprises scan chains and one or more observation scan chains, the scan chains comprising scan cells, the one or more observation scan chains comprising observation scan cells, and wherein the testing comprises a scan-capture phase and an observation scan phase, both the scan cells and the observation scan cells operating in a shift mode and a capture mode alternately during the scan-capture phase, and the scan cells operating in the shift mode and the observation scan cells operating in a shift-observation mode during the observation scan phase.
  • Figure 1 illustrates an example test architecture that may be implemented according to various embodiments of the disclosed technology.
  • Figure 2 illustrates an example of a conventional scan cell.
  • Figure 3 illustrates an example of an observation scan cell that may be implemented according to various embodiments of the disclosed technology.
  • Figure 4 illustrates a table summarizing the four operational modes in which the observation scan cell in Fig. 3 may operate and the associated settings for the two control signals.
  • Figure 5 illustrates how X bits captured by regular scan cells can corrupt observation scan cells using an observation scan system.
  • Figure 6 illustrates a multi-phase observation scan scheme that can be employed to reduce the impact of X bits according to various embodiments of the disclosed technology.
  • Figure 7A illustrates a table showing characteristics of four industrial designs along with X state injections and the resulted corruptions of observation scan chains under a singlephase observation scan scheme.
  • Figure 7B illustrates a table showing test pattern counts needed for 90% test coverage under various test schemes and/or conditions for the four industrial designs shown in Fig. 7A.
  • Figure 8 illustrates an example of a block diagram of an observation scan cell that may be implemented according to various embodiments of the disclosed technology.
  • Figure 9 illustrates another example of a block diagram of an observation scan cell that may be implemented according to various embodiments of the disclosed technology.
  • Figure 10 illustrates a programmable computer system with which various embodiments of the disclosed technology may be employed.
  • design is intended to encompass data describing an entire integrated circuit device. This term also is intended to encompass a smaller group of data describing one or more components of an entire device such as a portion of an integrated circuit device nevertheless.
  • Testing typically includes applying a set of test stimuli (test patterns) to the circuit-under- test and then analyzing responses generated by the circuit-under-test.
  • Functional testing attempts to validate that the circuit-under-test operates according to its functional specification while structural testing tries to ascertain that the circuit-under-test has been assembled correctly from some low-level building blocks as specified in a structural netlist and that these low-level building blocks and their wiring connections have been manufactured without defect.
  • structural testing it is assumed that if functional verification has shown the correctness of the netlist and structural testing has confirmed the correct assembly of the structural circuit elements, then the circuit should function correctly.
  • Structural testing has been widely adopted at least in part because it enables the test (test pattern) generation to focus on testing a limited number of relatively simple circuit elements rather than having to deal with an exponentially exploding multiplicity of functional states and state transitions.
  • test pattern design for test or design for testability (DFT).
  • Scan testing is the most common DFT method. In a basic scan testing scheme, all or most of internal sequential state elements (latches, flip-flops, et al.) in a circuit design are made controllable and observable via a serial interface. These functional state elements are usually replaced with dual-purpose state elements called scan cells.
  • Scan cells are connected together to form scan chains - serial shift registers for shifting in test patterns and shifting out test responses.
  • a scan cell can operate as originally intended for functional purposes (functional/mission mode) and as a unit in a scan chain for scan (scan mode).
  • a widely used type of scan cell include an edge-trigged flip-flop with two-way multiplexer for the data input. The two-way multiplexer is typically controlled by a single control signal called scan enable, which selects the input signal for a scan cell from either a scan signal input port or a system signal input port.
  • the scan signal input port is typically connected to an output of another scan cell while the system signal input port is connected to the functional logic.
  • Scan cells can serve as both a control point and an observation point.
  • Control points can be used to set certain logic values at some locations of the circuit-under-test, exciting a fault and propagating the incorrect value to an observation point.
  • Scan testing allows the test equipment to access gates deeply embedded through the primary inputs/outputs and/or some physical test points and can remove the need for complicated state transition sequences when trying to control or observe what is happening at some internal circuit element.
  • Test patterns for scan testing are typically generated through an automatic test pattern generation (ATPG) process.
  • ATPG usually focuses on a set of faults derived from a gatelevel fault model.
  • a defect is an imperfection caused in a device during the manufacturing process.
  • a fault model is a description of how a defect alters design behavior.
  • a defect is a flaw or physical imperfection that may lead to a fault.
  • ATPG comprises two phases: fault activation and fault propagation.
  • Fault activation establishes a signal value at the fault site opposite that produced by the fault.
  • Fault propagation propagates the fault effect forward by sensitizing a path from a fault site to a scan cell or a primary output.
  • a fault at a site is said to be detected by a test pattern if a test response value captured by a scan cell or a primary output is different than the expected value.
  • the objective of ATPG is to find a test pattern that, when applied to the circuit, enables testers to distinguish between the correct circuit behavior and the faulty circuit behavior caused by one or more particular faults. Effectiveness of ATPG is measured by the fault coverage achieved for the fault model and the number of generated vectors (test pattern counts), which should be directly proportional to test application time.
  • the fault coverage is defined as a ratio of the number of detected faults vs. the total number of faults.
  • the most popular fault model used in practice is the single stuck-at fault model.
  • the stuck-at fault model is a logical fault model because no delay information is associated with the fault definition.
  • Delay faults cause errors in the functioning of a circuit based on its timing. They are caused by the finite rise and fall time periods of the signals in the gates, as well as, the propagation delay of interconnects between the gates. Transition faults are used for their simplicity in modeling spot defects that affect delays at inputs or outputs of gates. Under scan-based tests, the transition faults are associated with an extra delay that is large enough to cause the delay of any path through the fault site to exceed the clock period.
  • PF A Physical failure analysis
  • the process usually includes etching away certain layers and then imaging the silicon surface by scanning electronic microscopy or focused ion beam systems. This PFA process is laborious and time consuming.
  • diagnosis is often employed to narrow down possible locations of the defect(s) based on analyzing the fail log (fail file, failure file).
  • the fail log typically contains information about when (e.g., tester cycle), where (e.g., at what tester channel), and how (e.g., at what logic value) the test failed and which test patterns generate expected test responses.
  • the layout information of the circuit design may also be employed to further reduce the number of defect suspects.
  • Test application in chip manufacturing test is normally performed by automatic test equipment (ATE) (a type of testers). Scan-based tests consume significant amounts of storage and test time on ATE. The data volume increases with the number of logic gates on the chip and the same holds for the number of scan cells. Yet, practical considerations and ATE specifications often limit both the number of pins available for scan in/out and the maximum scan frequency. It is highly desirable to reduce the amount of test data that need to be loaded onto ATE and ultimately to the circuit under test. Fortunately, test patterns are compressible mainly because only 1% to 5% of test pattern bits are typically specified bits (care bits) while the rest are unspecified bits (don't-care bits). Unspecified bits can take on any values with no impact on the fault coverage. Test compression may also take advantage of the fact that test cubes tend to be highly correlated. A test cube is a deterministic test pattern in which the don't-care bits are not filled by ATPG. The correlation exists because faults are structurally related in the circuit.
  • test compression can reduce not only the amount of data stored on the tester but also the test time for a given test data bandwidth.
  • the embedded deterministic test is one example of test compression techniques.
  • the EDT-based compression is composed of two complementary parts: hardware that is embedded on chip, and deterministic ATPG software that generates compressed patterns that utilize the embedded hardware.
  • the EDT hardware features a continuous-flow decompressor.
  • the EDT compression of test cubes is performed by treating the external test data as Boolean variables.
  • Scan cells are conceptually filled with symbolic expressions that are linear functions of input variables injected into the decompressor. In the case of a decompressor comprising a ring generator and an associated phase shifter, a set of linear equations corresponding to scan cells whose values are specified may be used.
  • a compressed pattern can be determined by solving the system of equations.
  • Logic built-in self-test is a DFT technique that permits a circuit to test itself using embedded test logic without the need of an external tester.
  • Classical Logic BIST applications include detecting infant mortality defects during burn-in test, enabling the use of low-cost and/or low-speed testers that only provide power and clock signals, and in-system self-testing to improve the reliability of the system in aerospace/defense, automotive, telecommunications and healthcare industries.
  • a typical logic BIST system includes a test pattern generator for automatically generating test patterns, a test response analyzer (compactor) for compacting test responses into a signature and a logic BIST controller for coordinating the BIST operation and for providing a pass/fail indication.
  • a pseudo-pattern pattern generator (PRPG), a commonly used test pattern generator, can be constructed from a linear feedback shift register (LFSR) or a cellular automaton. To increase the fault coverage, a weighted LFSR may be employed. Another approach is to combine random test patterns with deterministic patterns in some fashion as the BIST logic can be used to handle compressed test patterns that are generated deterministically and stored on chip.
  • PRPG a commonly used test pattern generator
  • LFSR linear feedback shift register
  • a weighted LFSR may be employed.
  • Another approach is to combine random test patterns with deterministic patterns in some fashion as the BIST logic can be used to handle compressed test patterns that are generated deterministically and stored on chip.
  • Fig. 1 illustrates an example test architecture 100 that may be implemented according to various embodiments of the disclosed technology.
  • the test architecture 100 comprises scan chains 110, one or more observation scan chains 150, and a test controller 160.
  • the scan chains 110 can be formed by conventional scan cells.
  • the conventional scan cells can be configured to operate in either a shift mode or a capture mode based on a scan enable signal generated by the test controller 160.
  • Fig. 2 illustrates an example of a conventional scan cell 200.
  • the scan cell 200 comprises a state element 210 and a two- way multiplexer 220.
  • the state element 210 can be implemented using an edge-trigged flip-flop.
  • the two-way multiplexer 220 selects a signal from either a serial input port 230 of the scan cell 200 or a parallel input port 240 of the scan cell 200 as the data input signal for the state element 210.
  • the selection is based on a scan enable signal supplied from a scan enable port 250 of the scan cell 200.
  • the serial input port 230 can be coupled to an output of another scan cell in the same scan chain as the scan cell 200 (e.g., one of the scan chains 110 in Fig. 1) while the parallel input port 240 can be coupled to functional circuitry 270.
  • the scan cell 200 When the scan enable signal 250 selects the serial input port 230 as the data input signal for the state element 210, the scan cell 200 operates in the shift mode; and when the scan enable signal 250 selects the parallel input port 240 as the data input signal for the state element 210, the scan cell 200 operates in the capture mode.
  • the scan cell 200 fans out into two outputs: a serial output 260 which can be coupled to the serial input port of the next scan cell in the scan chain and a parallel output 280 which can be coupled to the functional circuitry 270. In this setup, the data bit stored in the state element 110 is being applied to the functional circuitry 270 continuously even in the shift mode.
  • the one or more observation scan chains 150 can be formed by observation scan cells.
  • the observation scan cells can be configured to operate in a shift mode, a capture mode, or a shift-observation mode based on the scan enable signal used by the scan chains 120 and another control signal referred to as an observation scan enable signal.
  • the observation scan enable signal can also be generated by the test controller 160.
  • the test controller 160 may use a counter to facilitate the generation of the observation scan enable signal based on the scan enable signal.
  • Fig. 3 illustrates an example of an observation scan cell 300 that may be implemented according to various embodiments of the disclosed technology.
  • the observation scan cell 300 comprises a state element 310 and selection and combination circuitry 320.
  • the state element 310 can be implemented using an edge-trigged flip-flop.
  • the selection and combination circuitry 320 comprises combination circuitry 321 and selection circuitry 325.
  • the combination circuitry 321 is configured to combine a signal “5” from a serial input port 330 of the observation scan cell 300 with a signal “ ⁇ 7” from a parallel input port 340 of the observation scan cell 300 to generate a signal “s+d”.
  • the serial input port 330 can be coupled to an output of another scan cell in the same scan chain as the scan cell 300 (e.g., one of the one or more observation scan chains 150 in Fig. 1) while the parallel input port 340 can be coupled to functional circuitry 390.
  • the selection and combination circuitry 320 may further comprise another combination circuitry 323, which is configured to combine the signal “ ” from the parallel input port 340 with a signal “ ?” from an output 370 of the state element 310 to generate a signal “d+Q” .
  • the selection circuitry 325 is configured to select an input signal for the state element 310 from the signal “5”, the signal ’, and the signal “s+ ” if the selection and combination circuitry 320 does not have the combination circuitry 323. If the combination circuitry 323 is present, the signal “s+Q” may also be the fourth signal that can be selected by the selection circuitry 325.
  • the selection is based on two control signals: a scan enable signal from a scan enable port 360 of the observation scan cell 300 and an observation scan enable signal from an observation scan enable port of the observation scan cell 300. It should be noted that while the selection circuitry 325 is shown to receive signals from the combination circuitry 321 and the combination circuitry 323, some part of the selection circuitry 325 may output a signal to either or both of them. One such example will be discussed later.
  • the observation scan cell 300 can operate in one of the above-mentioned three modes (the shift mode, the capture mode, and the shiftobservation mode) if the selection and combination circuitry 320 does not have the combination circuitry 323. Otherwise, the observation scan cell 300 may operate additionally in a capture-accumulation mode.
  • Fig. 4 illustrates a table summarizing the four operational modes in which the observation scan cell 300 may operate and the associated settings for the two control signals.
  • the observation scan enable signal is inactivated, for example, the observation scan cell 300 operates like the scan cell 200 in Fig. 2, performing either a shifting operation or a capturing operation during a test based on the scan enable signal.
  • the data bit stored in the observation scan cell 300 is not applied to functional circuitry 390 in either of the two operations. This is because the observation scan cell 300 does not have the same parallel output to inject the stored bit as the scan cell 200 in Fig. 2.
  • the observation scan enable signal is activated, the observation scan cell 300 can capture test response per shift clock cycle (shift-observation) or capture a test response bit and combine it with the stored bit (capture-accumulation) based on the scan enable signal. Again, the stored bit does not affect the functional circuitry 390.
  • the test architecture 100 can also comprise a pseudo random pattern generator (PRPG) 130 and a test response compactor 140.
  • PRPG pseudo random pattern generator
  • the pseudo random pattern generator 130 is configured to generator test patterns for testing the circuit and its outputs are coupled to serial inputs of the scan chains 110 and the one or more observation scan chains 150.
  • the test response compactor 140 is configured to compact test responses and its inputs of are coupled to serial outputs of the scan chains 110 and the one or more observation scan chains 150.
  • the pseudo random pattern generator 130 can be constructed from a linear feedback shift register (LFSR) or a cellular automaton. Ring generators are a type of linear finite state machines, which can be derived by altering the canonical forms (external feedback, internal feedback) of linear feedback shift registers while maintaining their transition functions.
  • the pseudo random pattern generator 130 can comprise a ring generator and a phase shifter.
  • the phase shifter may comprise XOR gates and can expand the limited outputs of the ring generator to drive a large number of the scan chains 150 and the one or more observation scan chains 150.
  • the test decompressor used by the embedded deterministic test (EDT) can also be implemented using a ring generator and a phase shifter.
  • the pseudo random pattern generator 130 may be configured as a test decompressor during a deterministic test right after the chip is fabricated and then reconfigured to be a pseudo random pattern generator for an in- system test after the chip is installed in a system such as an automobile.
  • the test response compactor 140 can comprise temporal test response compacting circuitry such as a multiple-input signature register (MISR).
  • the test response compactor 140 can further comprise spatial test response compacting circuitry such as one or more XOR gate networks.
  • the test response compactor 140 can still further comprise X- masking circuitry configured to mask X bits in the test responses.
  • the test architecture 100 can be employed to shorten test application time by configuring the one or more observation scan chains 150 to operate in the shift-observation mode test while the scan chains 110 is performing a conventional shift operation.
  • the changing content of scan cells in the scan chains 110 becomes stimuli feeding the circuit every clock cycle, and the observation scan cells in the one or more observation scan chains 150 capture and accumulate test responses every clock cycle.
  • the test architecture 100 can also preserve benefits of the conventional test-per-shift approach by allowing the scan chains 110 to capture test responses after the shift operation loads a test pattern.
  • test point locations such as the observation points coupled to the one or more observation scan chains 150 may be determined by searching for internal lines that have low observability, but are preferable propagation paths for a significant number of faults.
  • control points coupled to the scan chains 110 may be selected by also considering whether they can improve fault propagation towards test-per-clock-driven observation points, and thus increase their detection probability.
  • X states occur in circuit designs due to non-scan flip-flops, uninitialized memory elements, floating buses, bus contentions, internal three-state logic, unwrapped analog modules, false paths, cross-domain paths, or paths with timing closure problems.
  • X states can lead to unknown bits (X bits) in test responses, severely deteriorating test quality.
  • a test response compactor employs a mechanism for masking X bits, which is referred to as X-masking. Not all X bits captured in scan cells are subsequently masked for manufacturing tests.
  • a test compactor can employ X-masking circuitry to mask, based on masking information stored in a register, X bits in the test responses.
  • a simple way for X-masking is to mask any scan chains that capture at least one X bit. This can lead to low fault coverage or high pattern counts because many useful test response bits can be masked as well.
  • the X-masking circuitry may be configured to mask X bits in a per-shift-clock-cycle mode, blocking only certain bits outputted from a scan chain but allowing other bits to be compacted.
  • Fig. 5 uses an observation scan system 500 to illustrate how X bits captured by regular scan cells can corrupt observation scan cells.
  • the observation scan system 500 comprises regular scan chains 511-514, an observation scan chain 520, a pseudo random pattern generator 530 configured to generate test patterns, and a multiple-input signature register 540 serving as a test response compactor.
  • these captured X bits are applied to the functional circuitry continuously in the shift mode via the parallel output ports of the scan cells in the scan chains 511, 513 and 514. Therefore, these X bits can cause some X states to be captured by observation scan cells in the observation scan chain 520. Masking the observation scan chain will lose the benefits of the observation scan technology.
  • a multi -phase observation scan scheme can be employed to reduce the impact of X bits according to various embodiments of the disclosed technology.
  • Fig. 6 illustrates an example of such a multi-phase observation scan scheme.
  • the multi-phase observation scan scheme can comprises two phase: a scan-capture phase 610 and an observation scan phase 620.
  • both scan cells in regular scan chains 630 and observation scan cells in observation scan chains 640 operate in the shift mode and the capture mode alternately.
  • a test pattern is shifted into the scan chains 630 in the shift mode, and a test response is captured by the scan cells in the scan chains 630 in the capture mode.
  • the scan chains 630 then switch back to the shift mode, shifting out the captured test response while shifting in the next test pattern.
  • observation scan cells in observation scan chains 640 do not contribute to the application of the test pattern to the circuit because they do not have parallel output ports. Nor do they capture test response in the shift mode. However, the observation scan cells in the observation scan chains 640 can also capture the test response in the capture mode.
  • the scan cells in the regular scan chains 630 operate in the shift mode, and the observation scan cells in the observation scan chains 640 operates in the shift-observation mode.
  • Test stimuli are continuously applied to the circuit by the regular scan chains 630 and corresponding test responses are continuously captured by the observation scan chains 640 in this phase.
  • Timing exception paths are a main source of X states, and thus X states are rarely generated in the shift mode. Even if an observation scan cell captures one, this X bit will not propagate back into the circuit to corrupt other observation scan cells. As such, outputs of most of the observation scan chains 640 do not need to be masked and the observation scan phase 620 can preserve the benefits of the observation scan technology.
  • the number of test patterns for the observation scan-capture phase may be smaller than or equal to a number of test patterns for the scan phase according to some embodiments of the disclosed technology.
  • Fig. 7A illustrates a table showing characteristics of four industrial designs along with X state injections and the resulted corruptions of observation scan chains under a singlephase observation scan scheme.
  • These four industrial designs DI, D2, D3 and D4 have about 1-3 million gates per design and 1254, 1255, 2502, and 528 scan chains, respectively.
  • these scan chains there are 34, 39, 74, and 7 observation scan chains, respectively.
  • the regular scan chains operate in the shift mode and the capture mode alternately while the observation scan chains operate in the shift-observation mode and the capture-accumulation mode alternately.
  • a small number of random Xs are injected into each of the four designs, as shown in the sixth column.
  • Fig. 7B illustrates a table showing test pattern counts needed for 90% test coverage under various test schemes and/or conditions for the four industrial designs shown in Fig. 7A.
  • Column B shows the number of test patterns needed under the condition that neither X states are injected nor observation scan chains are used.
  • Column C shows the number of test patterns needed under the condition that no X states are injected but observation scan chains are used.
  • Column D computes the ratio of Column B vs. Column C, which shows that except for Design 4, using observation scan chains can reduce the pattern count by a factor of greater than 7.
  • Columns E shows test pattern counts under the condition that X states are injected but no observation scan chains are used.
  • Columns F shows test pattern counts under the condition that both X states are injected and observation scan chains are used in a two- phase observation scan scheme.
  • the ratios of Column E vs. Column F and Column B vs. Column F are listed in Columns G and H, respectively.
  • Columns G shows a significant pattern count reduction when the two-phase observation scan scheme is used. This cannot be achieved using a single-phase observation scan scheme. Even compared with the regular LBST run with no X states, a pattern count reduction over 2.5 times can be achieved for designs D1-D3 using the two-phase observation scan scheme. For Design D4, the two-phase observation scan scheme only requires about 15% more patterns comparing to the regular LBIST run without any Xs.
  • Fig. 8 illustrates an example of a block diagram of an observation scan cell 800 that may be implemented according to various embodiments of the disclosed technology.
  • the observation scan cell 800 comprises a state element 810 and selection and combination circuitry 820.
  • the state element 810 can be implemented using a flip-flop.
  • the selection and combination circuitry 820 comprises two logic XOR gates 830 and 840 functioning as the combination circuitry 321 and the combination circuitry 323 shown in Fig. 3, respectively.
  • the XOR gate 930 can generate a first signal by combining a signal from a scan input port (SI) 870 of the observation scan cell 800 with a signal from a functional circuit input port (D) 860 (also referred to as parallel input port) of the observation scan cell 800.
  • the XOR gate 840 can generate a second signal by combining the signal from the functional circuit input port (D) 860 of the observation scan cell 800 with an output signal (Q) 815 of the state element 810.
  • the selection and combination circuitry 820 further comprises a four-to-one multiplexer 850 functioning as the selection circuitry 325 shown in Fig. 3.
  • the four-to-one multiplexer 850 can select, based on two selection input signals Ml (880) and M2 (890) of the observation scan cell 800, an input signal for the state element 810 from four signals: the first signal, the second signal, the signal from the scan input port (SI) 870 of the observation scan cell 800, and the signal from the functional circuit input port (D) 860 of the observation scan cell 800.
  • the selection input signals Ml (880) and M2 (890) can be the scan enable signal and the observation scan enable signal in Fig. 4, respectively.
  • the observation scan cell 800 When the signal from the scan input port (SI) 830 of the observation scan cell 800 is selected, the observation scan cell 800 operates in the conventional shift mode. When the signal from the functional circuit input port (D) 840 of the observation scan cell 800 is selected, the observation scan cell 800 operates in the conventional capture mode or in the circuit functional mode. When the first signal is selected, the observation scan cell 800 accumulates the circuit test responses during the shift mode for regular scan cells, corresponding to the shift-observation mode shown in Fig. 4. When the second signal is selected, the observation scan cell 800 accumulates the circuit test responses during a capture mode for regular scan cells, corresponding to the capture-accumulation mode shown in Fig. 4.
  • Fig. 9 illustrates another example of a block diagram of an observation scan cell 900 that may be implemented according to various embodiments of the disclosed technology.
  • the observation scan cell 900 comprises a state element 910 and selection and combination circuitry 915.
  • the selection and combination circuitry 915 comprises two logic XOR gates 940 and 930 functioning as the combination circuitry 321 and the combination circuitry 323 shown in Fig. 3, respectively.
  • the selection and combination circuitry 915 employs two AND gates 923 and 925 along with a two-to-one multiplexer 920, rather than the single four-to-one multiplexer 850, to perform the selection function.
  • outputs of the AND gates 923 and 925 are the signal from an output port (Q) 990 of the state element 910 and the signal from the functional circuit input port (D) 970, respectively.
  • the XOR gates 940 and 930 thus combine the signal from the functional circuit input port (D) 970 with the signal from the scan input port (SI) 980 and the signal from the output port of the state element 910, respectively.
  • the selection input signal Ml (960) can determine whether the former combined signal or the latter combined signal drives the state element 910, which correspond to the shift-observation mode and the capture-accumulation mode in Fig. 4, respectively.
  • FIG. 10 shows an illustrative example of such a programmable computer (a computing device 1001).
  • the computing device 1001 includes a computing unit 1003 with a processing unit 1005 and a system memory 1007.
  • the processing unit 1005 may be any type of programmable electronic device for executing software instructions, but will conventionally be a microprocessor.
  • the system memory 1007 may include both a readonly memory (ROM) 1009 and a random access memory (RAM) 1011.
  • ROM readonly memory
  • RAM random access memory
  • both the read-only memory (ROM) 1009 and the random access memory (RAM) 1011 may store software instructions for execution by the processing unit 1005.
  • the processing unit 1005 and the system memory 1007 are connected, either directly or indirectly, through a bus 1013 or alternate communication structure, to one or more peripheral devices.
  • the processing unit 1005 or the system memory 1007 may be directly or indirectly connected to one or more additional memory storage devices, such as a “hard” magnetic disk drive 1015, a removable magnetic disk drive 1017, an optical disk drive 1019, or a flash memory card 1021.
  • the processing unit 1005 and the system memory 1007 also may be directly or indirectly connected to one or more input devices 1023 and one or more output devices 1025.
  • the input devices 1023 may include, for example, a keyboard, a pointing device (such as a mouse, touchpad, stylus, trackball, or joystick), a scanner, a camera, and a microphone.
  • the output devices 1025 may include, for example, a monitor display, a printer and speakers.
  • one or more of the peripheral devices 1015-1025 may be internally housed with the computing unit 1003. Alternately, one or more of the peripheral devices 1015-1025 may be external to the housing for the computing unit 1003 and connected to the bus 1013 through, for example, a Universal Serial Bus (USB) connection.
  • USB Universal Serial Bus
  • the computing unit 1003 may be directly or indirectly connected to one or more network interfaces 1027 for communicating with other devices making up a network.
  • the network interface 1027 translates data and control signals from the computing unit 1003 into network messages according to one or more communication protocols, such as the transmission control protocol (TCP) and the Internet protocol (IP).
  • TCP transmission control protocol
  • IP Internet protocol
  • the interface 1027 may employ any suitable connection agent (or combination of agents) for connecting to a network, including, for example, a wireless transceiver, a modem, or an Ethernet connection.
  • TCP transmission control protocol
  • IP Internet protocol
  • connection agent or combination of agents
  • the computer 1001 is illustrated as an example only, and it not intended to be limiting.
  • Various embodiments of the disclosed technology may be implemented using one or more computing devices that include the components of the computer 1001 illustrated in Fig. 10, which include only a subset of the components illustrated in Fig. 10, or which include an alternate combination of components, including components that are not shown in Fig. 10.
  • various embodiments of the disclosed technology may be implemented using a multi-processor computer, a plurality of single and/or multiprocessor computers arranged into a network, or some combination of both.

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  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Tests Of Electronic Circuits (AREA)

Abstract

Un circuit comprend des chaînes de balayage comprenant des cellules de balayage et une ou plusieurs chaînes de balayage d'observation. Les chaînes de balayage comprennent des cellules de balayage. La ou les chaînes de balayage d'observation comprennent des cellules de balayage d'observation. Le test du circuit comprend une phase de capture de balayage et une phase de balayage d'observation. Pendant la phase de capture de balayage, à la fois les cellules de balayage et les cellules de balayage d'observation fonctionnent dans un mode de décalage et dans un mode de capture en alternance. Pendant la phase de balayage d'observation, les cellules de balayage fonctionnent dans le mode de décalage et les cellules de balayage d'observation fonctionnent dans un mode d'observation de décalage.
PCT/US2022/077755 2022-10-07 2022-10-07 Technologie de balayage d'observation à autotest intégré et logique multiphase WO2024076370A1 (fr)

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