EP1218945A1 - Ensemble circuit servant a former un condensateur mos a faible dependance vis-a-vis de la tension et a faible encombrement - Google Patents

Ensemble circuit servant a former un condensateur mos a faible dependance vis-a-vis de la tension et a faible encombrement

Info

Publication number
EP1218945A1
EP1218945A1 EP00978967A EP00978967A EP1218945A1 EP 1218945 A1 EP1218945 A1 EP 1218945A1 EP 00978967 A EP00978967 A EP 00978967A EP 00978967 A EP00978967 A EP 00978967A EP 1218945 A1 EP1218945 A1 EP 1218945A1
Authority
EP
European Patent Office
Prior art keywords
circuit arrangement
mos
transistors
gate
channel
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP00978967A
Other languages
German (de)
English (en)
Inventor
Thomas Tille
Doris Schmitt-Landsiedel
Jens Sauerbrey
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Infineon Technologies AG
Original Assignee
Infineon Technologies AG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from DE19961487A external-priority patent/DE19961487B4/de
Application filed by Infineon Technologies AG filed Critical Infineon Technologies AG
Publication of EP1218945A1 publication Critical patent/EP1218945A1/fr
Withdrawn legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/0805—Capacitors only
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
    • H01L29/92—Capacitors having potential barriers
    • H01L29/94—Metal-insulator-semiconductors, e.g. MOS

Definitions

  • Circuit arrangement for forming a MOS capacitor with low voltage dependence and a small area requirement
  • the invention relates to a circuit arrangement according to the preamble of patent claim 1.
  • MOS circuits metal oxide semiconductor circuits
  • the capacitances are formed by a gate connection, a gate oxide and a substrate.
  • the MOS capacitance has the advantage of a smaller space requirement and sometimes lower manufacturing costs.
  • the disadvantage lies in the voltage dependency of the capacitance curve, which only permits limited use of the MOS capacitance over the entire voltage range.
  • the object on which the invention is based is now to specify a circuit arrangement for forming a MOS capacitor with low voltage dependency, in which the disadvantages mentioned above are avoided and which is particularly space-saving.
  • the invention consists essentially in the fact that transistors are formed in the circuit arrangement for forming a MOS capacitor in the form of so-called short-channel MOS transistors, the channel length of which goes against the channel length that can be minimally implemented in the corresponding technology, which means that in addition to the intrinsic and also extrinsic Capacities can be used to form the MOS capacity.
  • extrinsic capacities is particularly important for compensated MOS capacities that are operated in depletion. This means a considerably reduced area requirement, particularly for compensation circuits operated in depletion.
  • FIG. 2 shows a diagram with the capacitance over the gate-bulk voltage, plotted for a circuit arrangement with short-channel transistors in comparison to a corresponding circuit arrangement with conventional long-channel transistors,
  • FIG. 3 shows a diagram with a minimum capacitance that can be generated as a function of the channel length of the MOS
  • FIG. 4 shows a first circuit arrangement according to the invention for compensating the voltage dependence of MOS capacitances
  • FIG. 5 shows a capacitance-voltage diagram for comparing short and long-channel transistors in the case of the circuit arrangement from FIG. 4,
  • Figure 6 shows a second circuit arrangement according to the invention for compensating the voltage dependence of MOS capacitances
  • FIG. 7 shows a further capacitance-voltage diagram for comparing short and long-channel transistors in the case of the circuit arrangement from FIG. 6.
  • a MOS capacitance consisting of gate connection, gate oxide and substrate has a voltage-dependent capacitance curve in accordance with its operating range, which can be seen, for example, from FIG. 1, curve (a).
  • curve (a) For the listed here te example are source, drain and well connection of a p-channel MOS transistor connected together.
  • the MOS capacitance In accordance with the applied gate bulk voltage VQB, the MOS capacitance is typically very non-linear. If the gate bulk voltage is greater than the ribbon voltage, the CMOS transistor is blocked (accumulation), the MOS capacitance being essentially determined by the thickness of the gate oxide.
  • the MOS capacitance being essentially determined by the thickness of the depletion layer and the thickness of the gate oxide becomes. If the gate-bulk voltage falls below the threshold voltage of the MOS transistor, an inversion layer or a p-channel (inversion) forms below the gate oxide and the MOS capacitance is essentially determined by the thickness of the gate oxide.
  • FIG. 2 shows a diagram with the usable capacitance C over the gate-bulk voltage VQB for a circuit arrangement with short-channel transistors in comparison to a corresponding circuit arrangement with conventional long-channel transistors.
  • Short-channel transistors here are understood to mean MOS transistors with a channel length that goes against the minimum channel length that can be implemented in the corresponding technology and typically have a channel length of less than or equal to approximately 1 ⁇ m for a 0.18 ⁇ m process, for example.
  • extrinsic capacitance components also contribute to the total capacitance, since the gate / source and gate / drain overlap region have a large area-related influence on the formation of the total capacitance in the case of a short channel length.
  • FIG. 2 shows a minimum capacitance C m i n is shown as a function of the channel length L, where a sharp increase in capacity from a channel length of less than or equal to about 1 micron noticeable.
  • the influence of the extrinsic capacitance components increases and the useful capacity in this case is essentially formed by the gate oxide, the deposition layer, but also by the gate / source and gate / drain overlap regions.
  • the capacities resulting from the overlapping areas are each to be subdivided into an almost voltage-independent portion between the gate and HDD area (Heavily Doped Diffusion Area) and a low voltage-dependent portion between the gate and LDD area (Lightly Doped Diffusion Area).
  • the gate / bulk overlap capacities can be neglected due to their small size in relation to the total capacity.
  • the depth of the depletion slump greatly reduced, that is, the operated for the nominal capacity in depletion compensation circuits decisive minimum capacitance C m i n in the depletion slump increases by a multiple of, resulting in a strong increase of the effective usable capacity results per area.
  • FIGS 4 and 6 show a first and second circuit arrangement according to the invention for compensation, in which the drain and source connections D1, S2 and D2, S2 of the respective MOS transistors Tl, T2 are connected to one another and opposite a respective gate Gl, G2 or bulk BLK1, BLK2 are biased such that the MOS transistors each work in the required voltage range exclusively in the depletion range.
  • the MOS transistors T1 and T2 are connected in series, with the gate of one transistor being connected to the gate of the other transistor and the bulk of one transistor being connected to the bulk of the other transistor, and being between the non-connected bulk - or gate connections connections A and B the useful capacity lies.
  • a defined potential at a node 2 between the anti-serial MOS transistors is not decisive for the selection of the operating range, but is recommended to avoid charging, since this can prevent a drift in the working range or a gate breakdown.
  • a high-resistance element R for example a so-called “leader”, is advantageous against fixed potential V3 to prevent gate charging. This has the advantage that there is no abrupt potential equalization of the gate node, which is necessary for special circuitry Applications can be useful.
  • FIG. 5 shows the useful capacitance C for the circuit arrangement according to FIG. 4 as a function of the voltage V ⁇ B at the useful capacitance for short-channel transistors in comparison to long-channel transistors. It is clear here that, with a voltage V ⁇ B equal to 0 zero, at least one useful capacitance which is larger by a factor of 3 is achieved with short-channel transistors.
  • FIG. 6 shows a circuit arrangement according to the invention with two MOS transistors T1 and T2 of the same channel type connected in anti-parallel, in which the widened depletion region of the transistors described above is also used.
  • the bulk terminal of transistor T2 and the gate terminal Gl of transistor T1 are connected to a terminal A of the MOS capacitor.
  • the drain and source connections D1 and S2 of the transistor Tl are connected to a voltage source for a bias voltage VI and the drain and source connections D2 and S2 of the transistor T2 are connected to a voltage source for a bias voltage V2.
  • FIG. 7 shows the capacitance C for the circuit arrangement according to FIG. 6 as a function of the voltage V ⁇ B of the capacitance between terminals A and B in the case of short-channel transistors and in the case of long-channel transistors.
  • V ⁇ B the minimum capacitance C m n i occurs in both cases and is in short-channel - transistors about 4 times as great as in long channel transistors.
  • Such circuit arrangements can be used in all integrated circuits with capacitive elements, such as in switched-capacitor (SC) filters and analog-digital converters, such as sigma-delta converters.
  • SC switched-capacitor
  • analog-digital converters such as sigma-delta converters.

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

L'invention concerne un ensemble circuit comportant des transistors MOS (T1, T2), à canal court, présentant le même type de canal, montés en anti-série ou antiparallèle. Elle concerne en particulier le mode de déplétion exclusif dudit ensemble circuit dans la plage de tension requise. Le recours à des capacités extrinsèques permet d'obtenir une augmentation considérable de la capacité utile (A, B) par rapport aux ensembles circuits classiques comportant des transistors MOS classiques à canal long. Ces circuits permettent d'obtenir une réduction importante de l'encombrement et des coûts.
EP00978967A 1999-09-30 2000-09-29 Ensemble circuit servant a former un condensateur mos a faible dependance vis-a-vis de la tension et a faible encombrement Withdrawn EP1218945A1 (fr)

Applications Claiming Priority (7)

Application Number Priority Date Filing Date Title
DE19946977 1999-09-30
DE19946977 1999-09-30
DE19947116 1999-09-30
DE19947116 1999-09-30
DE19961487 1999-12-20
DE19961487A DE19961487B4 (de) 1999-09-30 1999-12-20 Schaltungsanordnung zur Bildung eines MOS-Kondensators mit geringer Spannungsabhängigkeit und geringem Flächenbedarf
PCT/DE2000/003479 WO2001024277A1 (fr) 1999-09-30 2000-09-29 Ensemble circuit servant a former un condensateur mos a faible dependance vis-a-vis de la tension et a faible encombrement

Publications (1)

Publication Number Publication Date
EP1218945A1 true EP1218945A1 (fr) 2002-07-03

Family

ID=27219302

Family Applications (1)

Application Number Title Priority Date Filing Date
EP00978967A Withdrawn EP1218945A1 (fr) 1999-09-30 2000-09-29 Ensemble circuit servant a former un condensateur mos a faible dependance vis-a-vis de la tension et a faible encombrement

Country Status (3)

Country Link
US (1) US6700149B2 (fr)
EP (1) EP1218945A1 (fr)
WO (1) WO2001024277A1 (fr)

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE10207739A1 (de) * 2002-02-22 2003-09-11 Infineon Technologies Ag Integrierte Halbleiterschaltung mit einer Parallelschaltung gekoppelter Kapazitäten
TWI373925B (en) * 2004-02-10 2012-10-01 Tridev Res L L C Tunable resonant circuit, tunable voltage controlled oscillator circuit, tunable low noise amplifier circuit and method of tuning a resonant circuit
US7508898B2 (en) * 2004-02-10 2009-03-24 Bitwave Semiconductor, Inc. Programmable radio transceiver
US7672645B2 (en) 2006-06-15 2010-03-02 Bitwave Semiconductor, Inc. Programmable transmitter architecture for non-constant and constant envelope modulation
US20080111642A1 (en) * 2006-11-09 2008-05-15 Jose Bohorquez Apparatus and methods for vco linearization
JP5233604B2 (ja) * 2008-11-13 2013-07-10 富士通株式会社 半導体装置
US8143941B2 (en) * 2009-11-12 2012-03-27 Qualcomm, Incorporated Active analog filter having a MOS capacitor device with improved linearity
US10892260B2 (en) 2019-03-06 2021-01-12 Himax Technologies Limited Capacitor
TWI686956B (zh) * 2019-03-21 2020-03-01 奇景光電股份有限公司 電容器
CN111785716B (zh) * 2019-04-03 2023-05-23 奇景光电股份有限公司 电容器

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US4268951A (en) * 1978-11-13 1981-05-26 Rockwell International Corporation Submicron semiconductor devices
NL8003874A (nl) 1980-07-04 1982-02-01 Philips Nv Veldeffektcapaciteit.
US4786828A (en) 1987-05-15 1988-11-22 Hoffman Charles R Bias scheme for achieving voltage independent capacitance
IT1225614B (it) 1988-08-04 1990-11-22 Sgs Thomson Microelectronics Processo per la fabbricazione di dispositivi integrati cmos con lunghezze di gate ridotte e drain leggermente drogato
JPH0582741A (ja) * 1991-09-20 1993-04-02 Fujitsu Ltd Ｍｏｓキヤパシタ
US5576565A (en) * 1993-03-31 1996-11-19 Matsushita Electric Industrial Co., Ltd. MIS capacitor and a semiconductor device utilizing said MIS capacitor
JPH07221599A (ja) * 1994-02-08 1995-08-18 Nippondenso Co Ltd キャパシタ回路及びそれを用いたスイッチトキャパシタフィルタ
DE4447307A1 (de) * 1994-12-31 1996-07-04 Bosch Gmbh Robert Schaltungsanordnung zur Verminderung der Spannungsabhängigkeit einer MOS-Kapazität
US6028473A (en) * 1995-03-09 2000-02-22 Macronix International Co., Ltd. Series capacitor charge pump with dynamic biasing
US5801411A (en) * 1996-01-11 1998-09-01 Dallas Semiconductor Corp. Integrated capacitor with reduced voltage/temperature drift
US5926064A (en) 1998-01-23 1999-07-20 National Semiconductor Corporation Floating MOS capacitor
US6472233B1 (en) * 1999-08-02 2002-10-29 Advanced Micro Devices, Inc. MOSFET test structure for capacitance-voltage measurements

Non-Patent Citations (1)

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Title
See references of WO0124277A1 *

Also Published As

Publication number Publication date
WO2001024277A1 (fr) 2001-04-05
US20020135044A1 (en) 2002-09-26
US6700149B2 (en) 2004-03-02

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