EP1218945A1 - Circuit arrangement for creating a mos capacitor with a lower voltage dependency and a lower surface area requirement - Google Patents

Circuit arrangement for creating a mos capacitor with a lower voltage dependency and a lower surface area requirement

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Publication number
EP1218945A1
EP1218945A1 EP00978967A EP00978967A EP1218945A1 EP 1218945 A1 EP1218945 A1 EP 1218945A1 EP 00978967 A EP00978967 A EP 00978967A EP 00978967 A EP00978967 A EP 00978967A EP 1218945 A1 EP1218945 A1 EP 1218945A1
Authority
EP
European Patent Office
Prior art keywords
circuit arrangement
mos
transistors
gate
channel
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP00978967A
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German (de)
French (fr)
Inventor
Thomas Tille
Doris Schmitt-Landsiedel
Jens Sauerbrey
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Infineon Technologies AG
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Infineon Technologies AG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from DE19961487A external-priority patent/DE19961487B4/en
Application filed by Infineon Technologies AG filed Critical Infineon Technologies AG
Publication of EP1218945A1 publication Critical patent/EP1218945A1/en
Withdrawn legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/0805—Capacitors only
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
    • H01L29/92—Capacitors with potential-jump barrier or surface barrier
    • H01L29/94—Metal-insulator-semiconductors, e.g. MOS

Definitions

  • Circuit arrangement for forming a MOS capacitor with low voltage dependence and a small area requirement
  • the invention relates to a circuit arrangement according to the preamble of patent claim 1.
  • MOS circuits metal oxide semiconductor circuits
  • the capacitances are formed by a gate connection, a gate oxide and a substrate.
  • the MOS capacitance has the advantage of a smaller space requirement and sometimes lower manufacturing costs.
  • the disadvantage lies in the voltage dependency of the capacitance curve, which only permits limited use of the MOS capacitance over the entire voltage range.
  • the object on which the invention is based is now to specify a circuit arrangement for forming a MOS capacitor with low voltage dependency, in which the disadvantages mentioned above are avoided and which is particularly space-saving.
  • the invention consists essentially in the fact that transistors are formed in the circuit arrangement for forming a MOS capacitor in the form of so-called short-channel MOS transistors, the channel length of which goes against the channel length that can be minimally implemented in the corresponding technology, which means that in addition to the intrinsic and also extrinsic Capacities can be used to form the MOS capacity.
  • extrinsic capacities is particularly important for compensated MOS capacities that are operated in depletion. This means a considerably reduced area requirement, particularly for compensation circuits operated in depletion.
  • FIG. 2 shows a diagram with the capacitance over the gate-bulk voltage, plotted for a circuit arrangement with short-channel transistors in comparison to a corresponding circuit arrangement with conventional long-channel transistors,
  • FIG. 3 shows a diagram with a minimum capacitance that can be generated as a function of the channel length of the MOS
  • FIG. 4 shows a first circuit arrangement according to the invention for compensating the voltage dependence of MOS capacitances
  • FIG. 5 shows a capacitance-voltage diagram for comparing short and long-channel transistors in the case of the circuit arrangement from FIG. 4,
  • Figure 6 shows a second circuit arrangement according to the invention for compensating the voltage dependence of MOS capacitances
  • FIG. 7 shows a further capacitance-voltage diagram for comparing short and long-channel transistors in the case of the circuit arrangement from FIG. 6.
  • a MOS capacitance consisting of gate connection, gate oxide and substrate has a voltage-dependent capacitance curve in accordance with its operating range, which can be seen, for example, from FIG. 1, curve (a).
  • curve (a) For the listed here te example are source, drain and well connection of a p-channel MOS transistor connected together.
  • the MOS capacitance In accordance with the applied gate bulk voltage VQB, the MOS capacitance is typically very non-linear. If the gate bulk voltage is greater than the ribbon voltage, the CMOS transistor is blocked (accumulation), the MOS capacitance being essentially determined by the thickness of the gate oxide.
  • the MOS capacitance being essentially determined by the thickness of the depletion layer and the thickness of the gate oxide becomes. If the gate-bulk voltage falls below the threshold voltage of the MOS transistor, an inversion layer or a p-channel (inversion) forms below the gate oxide and the MOS capacitance is essentially determined by the thickness of the gate oxide.
  • FIG. 2 shows a diagram with the usable capacitance C over the gate-bulk voltage VQB for a circuit arrangement with short-channel transistors in comparison to a corresponding circuit arrangement with conventional long-channel transistors.
  • Short-channel transistors here are understood to mean MOS transistors with a channel length that goes against the minimum channel length that can be implemented in the corresponding technology and typically have a channel length of less than or equal to approximately 1 ⁇ m for a 0.18 ⁇ m process, for example.
  • extrinsic capacitance components also contribute to the total capacitance, since the gate / source and gate / drain overlap region have a large area-related influence on the formation of the total capacitance in the case of a short channel length.
  • FIG. 2 shows a minimum capacitance C m i n is shown as a function of the channel length L, where a sharp increase in capacity from a channel length of less than or equal to about 1 micron noticeable.
  • the influence of the extrinsic capacitance components increases and the useful capacity in this case is essentially formed by the gate oxide, the deposition layer, but also by the gate / source and gate / drain overlap regions.
  • the capacities resulting from the overlapping areas are each to be subdivided into an almost voltage-independent portion between the gate and HDD area (Heavily Doped Diffusion Area) and a low voltage-dependent portion between the gate and LDD area (Lightly Doped Diffusion Area).
  • the gate / bulk overlap capacities can be neglected due to their small size in relation to the total capacity.
  • the depth of the depletion slump greatly reduced, that is, the operated for the nominal capacity in depletion compensation circuits decisive minimum capacitance C m i n in the depletion slump increases by a multiple of, resulting in a strong increase of the effective usable capacity results per area.
  • FIGS 4 and 6 show a first and second circuit arrangement according to the invention for compensation, in which the drain and source connections D1, S2 and D2, S2 of the respective MOS transistors Tl, T2 are connected to one another and opposite a respective gate Gl, G2 or bulk BLK1, BLK2 are biased such that the MOS transistors each work in the required voltage range exclusively in the depletion range.
  • the MOS transistors T1 and T2 are connected in series, with the gate of one transistor being connected to the gate of the other transistor and the bulk of one transistor being connected to the bulk of the other transistor, and being between the non-connected bulk - or gate connections connections A and B the useful capacity lies.
  • a defined potential at a node 2 between the anti-serial MOS transistors is not decisive for the selection of the operating range, but is recommended to avoid charging, since this can prevent a drift in the working range or a gate breakdown.
  • a high-resistance element R for example a so-called “leader”, is advantageous against fixed potential V3 to prevent gate charging. This has the advantage that there is no abrupt potential equalization of the gate node, which is necessary for special circuitry Applications can be useful.
  • FIG. 5 shows the useful capacitance C for the circuit arrangement according to FIG. 4 as a function of the voltage V ⁇ B at the useful capacitance for short-channel transistors in comparison to long-channel transistors. It is clear here that, with a voltage V ⁇ B equal to 0 zero, at least one useful capacitance which is larger by a factor of 3 is achieved with short-channel transistors.
  • FIG. 6 shows a circuit arrangement according to the invention with two MOS transistors T1 and T2 of the same channel type connected in anti-parallel, in which the widened depletion region of the transistors described above is also used.
  • the bulk terminal of transistor T2 and the gate terminal Gl of transistor T1 are connected to a terminal A of the MOS capacitor.
  • the drain and source connections D1 and S2 of the transistor Tl are connected to a voltage source for a bias voltage VI and the drain and source connections D2 and S2 of the transistor T2 are connected to a voltage source for a bias voltage V2.
  • FIG. 7 shows the capacitance C for the circuit arrangement according to FIG. 6 as a function of the voltage V ⁇ B of the capacitance between terminals A and B in the case of short-channel transistors and in the case of long-channel transistors.
  • V ⁇ B the minimum capacitance C m n i occurs in both cases and is in short-channel - transistors about 4 times as great as in long channel transistors.
  • Such circuit arrangements can be used in all integrated circuits with capacitive elements, such as in switched-capacitor (SC) filters and analog-digital converters, such as sigma-delta converters.
  • SC switched-capacitor
  • analog-digital converters such as sigma-delta converters.

Abstract

The invention relates to a circuit arrangement, comprising short-channel MOS transistors (T1, T2) of the same channel type which are not connected in series or parallel and in particular, to their exclusive depletion mode in the required voltage area. The circuit arrangement achieves a considerable increase in the effective capacitance (A, B) in relation to circuit arrangements comprising conventional long channel MOS transistors, by the use of extrinsic capacitances. Said circuits reduce both the surface area requirement and costs.

Description

Beschreibungdescription
Schaltungsanordnung zur Bildung eines MOS-Kondensators mit geringer Spannungsabhängigkeit und geringem Flächenbedarf.Circuit arrangement for forming a MOS capacitor with low voltage dependence and a small area requirement.
Die Erfindung betrifft eine Schaltungsanordnung nach dem Oberbegriff des Patentanspruchs 1.The invention relates to a circuit arrangement according to the preamble of patent claim 1.
Es ist bekannt, in MOS-Schaltungen (Metall-Oxid- Semiconductor-Schaltungen) Kapazitäten mit Hilfe von MOS- Transistoren zu realisieren. Die Kapazitäten werden hierbei von einem Gateanschluß, einem Gateoxid und einem Substrat gebildet. Gegenüber Polysilizum/Oxid/Polysilizium-Kapazitäten, Polysilizium/Oxid/Metall-Kapazitäten und Metall/Oxid/Metall - Kapazitäten besitzt die MOS-Kapazität den Vorteil eines geringeren Flächenbedarfs und teilweise geringerer Herstellungskosten. Der Nachteil liegt in der Spannungsabhängigkeit des Kapazitätsverlaufs, was eine Nutzung der MOS-Kapazität über den gesamten Spannungsbereich nur begrenzt zuläßt .It is known to realize capacitances in MOS circuits (metal oxide semiconductor circuits) with the aid of MOS transistors. The capacitances are formed by a gate connection, a gate oxide and a substrate. Compared to polysilicon / oxide / polysilicon capacities, polysilicon / oxide / metal capacities and metal / oxide / metal capacities, the MOS capacitance has the advantage of a smaller space requirement and sometimes lower manufacturing costs. The disadvantage lies in the voltage dependency of the capacitance curve, which only permits limited use of the MOS capacitance over the entire voltage range.
Aus der europäischen Patentanmeldung mit der Veröffentlichungs-Nummer EP 0 720 238 ist eine Schaltungsanordnung bekannt, bei der mit Hilfe von zwei in Reihe geschalteten MOS- Transistoren diese Spannungsabhängigkeit vermindert wird, wo- bei die verwendeten Transistoren jeweils in Akkumulation oder Inversion betrieben werden. Für kleine Betriebsspannungen ist dieses Prinzip jedoch nicht bzw. nur begrenzt einsetzbar. In aktuellen CMOS-Prozessen ist zudem auch die Gate-Kapazität in Akkumulation und Inversion spannungsabhängig.A circuit arrangement is known from the European patent application with the publication number EP 0 720 238, in which this voltage dependency is reduced with the aid of two MOS transistors connected in series, the transistors used being operated in accumulation or inversion. However, this principle cannot be used or can only be used to a limited extent for small operating voltages. In current CMOS processes, the gate capacitance in accumulation and inversion is also voltage-dependent.
Aus dem Digest of Technical Papers zum 1996 Symposium on VLSI Circuits, Seiten 152 und 153, „Novel Design Techniques for High-Linearity MOSFET-Only Switched-Capacitor Circuits", Yos- hizawa, Temes et al . ist eine „Parallelkompensation" von MOS- Transistoren bekannt, bei der lediglich eine Parallelschaltung von zwei in Reihe geschalteten MOS-Transistoren vorhan- den ist, die jeweils wiederum in Akkumulation oder Inversion betrieben werden.From the Digest of Technical Papers for the 1996 Symposium on VLSI Circuits, pages 152 and 153, "Novel Design Techniques for High-Linearity MOSFET-Only Switched-Capacitor Circuits", Yoshizawa, Temes et al. Is a "parallel compensation" from MOS - Transistors known, in which there is only a parallel connection of two MOS transistors connected in series. is that are in turn operated in accumulation or inversion.
Die der Erfindung zugrundeliegende Aufgabe besteht nun darin, eine Schaltungsanordnung zur Bildung eines MOS-Kondensators mit geringer Spannungsabhän igkeit anzugeben, bei der die obengenannten Nachteile vermieden werden und die besonders platzsparend ist.The object on which the invention is based is now to specify a circuit arrangement for forming a MOS capacitor with low voltage dependency, in which the disadvantages mentioned above are avoided and which is particularly space-saving.
Diese Aufgabe wird erfindungsgemäß durch die Merkmale des Patentanspruchs 1 gelöst. Vorteilhafte Ausgestaltungen der Erfindung ergeben sich aus den weiteren Ansprüchen.This object is achieved by the features of claim 1. Advantageous embodiments of the invention result from the further claims.
Die Erfindung besteht im wesentlichen darin, daß Transistoren in der Schaltungsanordnung zur Bildung eines MOS-Kondensators in Form von sogenannten Kurzkanal -MOS-Transistoren, deren Kanallänge gegen die minimal in der entsprechenden Technologie realisierbare Kanallänge geht, ausgebildet sind, wodurch neben den intrinsischen auch extrinsische Kapazitäten zur Bil- düng der MOS-Kapazität genutzt werden. Die Ausnutzung der ex- trinsischen Kapazitäten kommt vor allem bei kompensierten MOS-Kapazitäten zum Tragen, die in Verarmung (Depletion) betrieben werden. Dies bedeutet, insbesondere für in Depletion betriebene Kompensationsschaltungen, einen erheblich redu- zierten Flächenaufwand.The invention consists essentially in the fact that transistors are formed in the circuit arrangement for forming a MOS capacitor in the form of so-called short-channel MOS transistors, the channel length of which goes against the channel length that can be minimally implemented in the corresponding technology, which means that in addition to the intrinsic and also extrinsic Capacities can be used to form the MOS capacity. The use of extrinsic capacities is particularly important for compensated MOS capacities that are operated in depletion. This means a considerably reduced area requirement, particularly for compensation circuits operated in depletion.
Weiterhin gelten die Vorteile gegenüber Polysilizi- um/Oxid/Polysilizium-Kapazitäten, Polysilizium/Oxid/Metall- Kapazitäten und Metall/Oxid/Metall -Kapazitäten in Anbetracht der Fläche bzw. kostenintensiver zusätzlicher Prozeßschichten. Somit lassen sich insbesondere Analogschaltungen für niedrige VersorgungsSpannungen zusammen mit DigitalSchaltungen als „Einchip-Lösung" preisgünstig in einem einzigen Prozeß herstellen.Furthermore, the advantages over polysilicon / oxide / polysilicon capacities, polysilicon / oxide / metal capacities and metal / oxide / metal capacities apply in view of the area or cost-intensive additional process layers. Thus, in particular, analog circuits for low supply voltages can be inexpensively produced in a single process together with digital circuits as a “one-chip solution”.
Die Erfindung wird nachfolgend anhand von Ausführungsbeispielen näher erläutert . Dabei zeigt Figur 1 zum Vergleich einen typischen Kapazitäts-The invention is explained in more detail below on the basis of exemplary embodiments. It shows Figure 1 for comparison a typical capacity
Spannungsverlauf einer bekannten MOS-Kapazität (nach S. M. Sze, „Physics of Semiconductor Devices", se- cond edition, John Wiley and Sons, New York, Chiche- ster, Brisbane, Toronto, p. 371, 1981),Voltage curve of a known MOS capacitance (according to S. M. Sze, "Physics of Semiconductor Devices", second edition, John Wiley and Sons, New York, Chester, Brisbane, Toronto, p. 371, 1981),
Figur 2 ein Diagramm mit der Kapazität über der Gate-Bulk- Spannung, aufgetragen für eine Schaltungsanordnung mit Kurzkanal -Transistoren im Vergleich zu einer entsprechenden Schaltungsanordnung mit üblichen Langkanal-Transistoren,FIG. 2 shows a diagram with the capacitance over the gate-bulk voltage, plotted for a circuit arrangement with short-channel transistors in comparison to a corresponding circuit arrangement with conventional long-channel transistors,
Figur 3 ein Diagramm mit einer jeweils erzeugbaren minimalen Kapazität in Abhängigkeit von der Kanallänge der MOS-FIG. 3 shows a diagram with a minimum capacitance that can be generated as a function of the channel length of the MOS
Transistoren in einer solchen Schaltungsanordnung,Transistors in such a circuit arrangement,
Figur 4 eine erste erfindungsgemäße Schaltungsanordnung zur Kompensation der Spannungsabhängigkeit von MOS- Kapazitäten,FIG. 4 shows a first circuit arrangement according to the invention for compensating the voltage dependence of MOS capacitances,
Figur 5 ein Kapazitäts-Spannungs-Diagramm zum Vergleich von Kurz- und Langkanal -Transistoren im Fall der Schaltungsanordnung von Figur 4 ,FIG. 5 shows a capacitance-voltage diagram for comparing short and long-channel transistors in the case of the circuit arrangement from FIG. 4,
Figur 6 eine zweite erfindungsgemäße Schaltungsanordnung zur Kompensation der Spannungsabhängigkeit von MOS- Kapazitäten undFigure 6 shows a second circuit arrangement according to the invention for compensating the voltage dependence of MOS capacitances and
Figur 7 ein weiteres Kapazitäts-Spannungs-Diagramm zum Vergleich von Kurz- und Langkanal -Transistoren im Fall der Schaltungsanordnung von Figur 6.FIG. 7 shows a further capacitance-voltage diagram for comparing short and long-channel transistors in the case of the circuit arrangement from FIG. 6.
Eine aus Gateanschluß, Gateoxid und Substrat bestehende MOS- Kapazität besitzt entsprechend ihres Betriebsbereiches einen spannungsabhängigen Kapazitätsverlauf, was beispielsweise aus Figur 1, Verlauf (a) ersichtlich ist. Für das hier aufgeführ- te Beispiel sind Source-, Drain- und Wannenanschluß eines p- Kanal-MOS-Transistors zusammengeschaltet. Entsprechend der anliegenden Gate-Bulk-Spannung VQB verhält sich die MOS- Kapazität typischerweise stark nichtlinear. Bei einer Gate- Bulk-Spannung größer als die Flachbandspannung ist der CMOS- Transistor gesperrt (Akkumulation) , wobei die MOS-Kapazität im wesentlichen durch die Dicke des Gateoxids bestimmt wird. Wird die Gate-Bulk-Spannung verringert, so verarmt der Bereich unter dem Gateoxid an beweglichen Ladungsträgern und es bildet sich eine Sperrschicht aus (Depletion) , wobei die MOS- Kapazität im wesentlichen durch die Dicke der Depletion- Schicht und die Dicke des Gateoxids bestimmt wird. Unterschreitet die Gate-Bulk-Spannung die Einsatzspannung des MOS- Transistors, so bildet sich unterhalb des Gateoxids eine In- versionsschicht bzw. ein p-Kanal aus (Inversion) und die MOS- Kapazität wird im wesentlichen durch die Dicke des Gateoxids bestimmt .A MOS capacitance consisting of gate connection, gate oxide and substrate has a voltage-dependent capacitance curve in accordance with its operating range, which can be seen, for example, from FIG. 1, curve (a). For the listed here te example are source, drain and well connection of a p-channel MOS transistor connected together. In accordance with the applied gate bulk voltage VQB, the MOS capacitance is typically very non-linear. If the gate bulk voltage is greater than the ribbon voltage, the CMOS transistor is blocked (accumulation), the MOS capacitance being essentially determined by the thickness of the gate oxide. If the gate bulk voltage is reduced, the region under the gate oxide becomes depleted of movable charge carriers and a barrier layer is formed (depletion), the MOS capacitance being essentially determined by the thickness of the depletion layer and the thickness of the gate oxide becomes. If the gate-bulk voltage falls below the threshold voltage of the MOS transistor, an inversion layer or a p-channel (inversion) forms below the gate oxide and the MOS capacitance is essentially determined by the thickness of the gate oxide.
In Figur 2 ist ein Diagramm mit der erzielbaren Nutzkapazität C über der Gate-Bulk-Spannung VQB für eine Schaltungsanordnung mit Kurzkanal -Transistoren im Vergleich zu einer entsprechenden Schaltungsanordnung mit üblichen Langkanal - Transistoren dargestellt. Unter Kurzkanal -Transistoren werden hier MOS-Transistoren mit einer Kanallänge, die gegen die mi- nimal in der entsprechenden Technologie realisierbare Kanallänge geht, verstanden und weisen typischerweise eine Kanallänge kleiner gleich ca. 1 μm für beispielsweise einen 0,18 μm-Prozeß auf. Bei Kurzkanal -MOS-Transistoren tragen zusätzlich extrinsische Kapazitätsanteile zur Gesamtkapazität bei, da bei kurzer Kanallänge das Gate/Source- und Gate/Drain-Überlappgebiet flächenmäßig stark in die Bildung der Gesamtkapazität eingeht. Ferner wird aus Figur 2 deutlich, daß im Bereich um 0 Volt bei Kurzkanal -Transistoren eine konstantere und größere Nutzkapazität vorliegt als bei einer entsprechenden Schaltungsanordnung mit Langkanal - Transistoren . In Figur 3 ist eine minimale Kapazität Cmin in Abhängigkeit der Kanallänge L dargestellt, wobei ein starker Anstieg der Kapazität ab einer Kanallänge von kleiner gleich ca. 1 μm auffällt. Mit abnehmender Kanallänge wächst der Einfluß der extrinsischen Kapazitätsanteile und die Nutzkapazität wird in diesem Fall im wesentlichen durch das Gateoxid, die Deple- tion-Schicht aber auch durch die Gate/Source- und Gate/Drain- Überlappgebiete gebildet. Die aus den Überlappgebieten resultierenden Kapazitäten sind jeweils in einem nahezu spannungs- unabhängigen Anteil zwischen Gate und HDD-Gebiet (Heavily Do- ped Diffusion Area) und in einen gering spannungsabhängigen Anteil zwischen Gate und LDD-Gebiet (Lightly Doped Diffusion Area) zu unterteilen. Die Gate/Bulk-Überlappkapazitäten können aufgrund ihrer geringen Größe im Verhältnis zur Gesamtka- pazität hingegen vernachlässigt werden. Bei kurzen Kanallängen verringert sich die Tiefe des Depletion-Einbruches stark, das heißt, die für die Nominalkapazität in Depletion betriebener Kompensationsschaltungen ausschlaggebende minimale Kapazität Cmin im Depletion-Einbruch erhöht sich um ein Vielfa- ches, woraus ein starker Zuwachs der effektiven Nutzkapazität pro Fläche resultiert.FIG. 2 shows a diagram with the usable capacitance C over the gate-bulk voltage VQB for a circuit arrangement with short-channel transistors in comparison to a corresponding circuit arrangement with conventional long-channel transistors. Short-channel transistors here are understood to mean MOS transistors with a channel length that goes against the minimum channel length that can be implemented in the corresponding technology and typically have a channel length of less than or equal to approximately 1 μm for a 0.18 μm process, for example. In the case of short-channel MOS transistors, extrinsic capacitance components also contribute to the total capacitance, since the gate / source and gate / drain overlap region have a large area-related influence on the formation of the total capacitance in the case of a short channel length. It is also clear from FIG. 2 that in the region around 0 volts there is a more constant and larger useful capacity in the case of short-channel transistors than in the case of a corresponding circuit arrangement with long-channel transistors. 3 shows a minimum capacitance C m i n is shown as a function of the channel length L, where a sharp increase in capacity from a channel length of less than or equal to about 1 micron noticeable. With decreasing channel length, the influence of the extrinsic capacitance components increases and the useful capacity in this case is essentially formed by the gate oxide, the deposition layer, but also by the gate / source and gate / drain overlap regions. The capacities resulting from the overlapping areas are each to be subdivided into an almost voltage-independent portion between the gate and HDD area (Heavily Doped Diffusion Area) and a low voltage-dependent portion between the gate and LDD area (Lightly Doped Diffusion Area). The gate / bulk overlap capacities, on the other hand, can be neglected due to their small size in relation to the total capacity. For short channel lengths, the depth of the depletion slump greatly reduced, that is, the operated for the nominal capacity in depletion compensation circuits decisive minimum capacitance C m i n in the depletion slump increases by a multiple of, resulting in a strong increase of the effective usable capacity results per area.
In Figur 4 und 6 sind eine erste und zweite erfindungsgemäße Schaltungsanordnung zur Kompensation dargestellt, bei denen die Drain- und Source-Anschlüsse Dl, S2 und D2 , S2 der jeweiligen MOS-Transistoren Tl, T2 miteinander verbunden und gegenüber einem jeweiligen Gate Gl , G2 bzw. Bulk BLK1 , BLK2 so vorgespannt sind, daß die MOS-Transistoren jeweils im geforderten Spannungsbereich ausschließlich im Depletion-Bereich arbeiten.4 and 6 show a first and second circuit arrangement according to the invention for compensation, in which the drain and source connections D1, S2 and D2, S2 of the respective MOS transistors Tl, T2 are connected to one another and opposite a respective gate Gl, G2 or bulk BLK1, BLK2 are biased such that the MOS transistors each work in the required voltage range exclusively in the depletion range.
In Figur 4 sind die MOS-Transistoren Tl und T2 antiseriell geschaltet, wobei jeweils das Gate des einen Transistors mit dem Gate des anderen Transistors bzw. das Bulk des einen Transistors mit dem Bulk des anderen Transistors verbunden ist und wobei zwischen den jeweils nicht verbundenen Bulk- bzw. Gateanschlüsse Anschlüsse A und B die Nutzkapazität liegt. Ein definiertes Potential an einem Knotenpunkt 2 zwischen den antiseriell geschalteten MOS-Transistoren ist für die Wahl des Betriebsbereiches nicht maßgebend, aber zur Vermeidung von Aufladungen empfehlenswert, da hierdurch eine Drift des Arbeitsbereiches bzw. ein Gatedurchbruch vermieden werden kann. Bei einer gategekoppelten Anordnung ist ein hochohmiges Element R, zum Beispiel ein sogenannter „Blee- der" , gegen festes Potential V3 zur Verhinderung von Gateaufladungen von Vorteil. Dies bietet den Vorteil, daß kein ab- rupter Potentialausgleich des Gateknotens erfolgt, was für spezielle schaltungstechnische Anwendungen von Nutzen sein kann.In FIG. 4, the MOS transistors T1 and T2 are connected in series, with the gate of one transistor being connected to the gate of the other transistor and the bulk of one transistor being connected to the bulk of the other transistor, and being between the non-connected bulk - or gate connections connections A and B the useful capacity lies. A defined potential at a node 2 between the anti-serial MOS transistors is not decisive for the selection of the operating range, but is recommended to avoid charging, since this can prevent a drift in the working range or a gate breakdown. In the case of a gate-coupled arrangement, a high-resistance element R, for example a so-called “leader”, is advantageous against fixed potential V3 to prevent gate charging. This has the advantage that there is no abrupt potential equalization of the gate node, which is necessary for special circuitry Applications can be useful.
In Figur 5 ist für die Schaltungsanordnung nach Figur 4 die Nutzkapazität C in Abhängigkeit der Spannung V^B an der Nutzkapazität für Kurzkanal -Transistoren im Vergleich zu Langkanaltransistoren dargestellt. Hierbei wird deutlich, daß, bei einer Spannung V^B gleich 0 Null, mindestens eine um den Faktor 3 größere Nutzkapazität mit Kurzkanal -Transistoren er- zielt wird.FIG. 5 shows the useful capacitance C for the circuit arrangement according to FIG. 4 as a function of the voltage V ^ B at the useful capacitance for short-channel transistors in comparison to long-channel transistors. It is clear here that, with a voltage V ^ B equal to 0 zero, at least one useful capacitance which is larger by a factor of 3 is achieved with short-channel transistors.
In Figur 6 ist eine erfindungsgemäße Schaltungsanordnung mit zwei antiparallel geschalteten MOS-Transistoren Tl und T2 vom gleichen Kanaltyp dargestellt, bei der auch der oben be- schriebene verbreiterte Depletion-Bereich der Transistoren genutzt wird. Der Bulkanschluß des Transistors T2 und der Gateanschluß Gl des Transistors Tl sind mit einem Anschluß A des MOS-Kondensators verbunden. Die Drain- und Source- Anschlüsse Dl und S2 des Transistors Tl sind mit einer Span- nungsquelle für eine Vorspannung VI und die Drain- und Sour- ce-Anschlüsse D2 und S2 des Transistors T2 sind mit einer Spannungsquelle für eine Vorspannung V2 verbunden. Der Bulkanschluß BLK1 des Transistors Tl ist über eine Spannungs- quelle für eine Verschiebespannung V3 und der Gateanschluß G2 des Transistors T2 ist über eine Spannungsquelle für eine Verschiebespannung V4 mit dem anderen Anschluß B der MOS- Kapazität verbunden. In Figur 7 ist für die Schaltungsanordnung nach Figur 6 die Kapazität C in Abhängigkeit von der Spannung V^B der Kapazität zwischen Anschluß A und B im Falle von Kurzkanal- Transistoren und im Falle von Langkanaltransistoren darge- stellt. Bei einer Spannung V^B gleich 0 Volt tritt in beiden Fällen die minimale Kapazität Cmin auf und ist bei Kurzkanal - Transistoren ca. 4 mal so groß wie bei Langkanaltransistoren. Zwischen V^B =FIG. 6 shows a circuit arrangement according to the invention with two MOS transistors T1 and T2 of the same channel type connected in anti-parallel, in which the widened depletion region of the transistors described above is also used. The bulk terminal of transistor T2 and the gate terminal Gl of transistor T1 are connected to a terminal A of the MOS capacitor. The drain and source connections D1 and S2 of the transistor Tl are connected to a voltage source for a bias voltage VI and the drain and source connections D2 and S2 of the transistor T2 are connected to a voltage source for a bias voltage V2. Bulk terminal BLK1 of transistor T1 is connected via a voltage source for a shift voltage V3 and gate terminal G2 of transistor T2 is connected via a voltage source for a shift voltage V4 to the other terminal B of the MOS capacitance. FIG. 7 shows the capacitance C for the circuit arrangement according to FIG. 6 as a function of the voltage V ^ B of the capacitance between terminals A and B in the case of short-channel transistors and in the case of long-channel transistors. At a voltage V ^ B equal to 0 volts, the minimum capacitance C m n i occurs in both cases and is in short-channel - transistors about 4 times as great as in long channel transistors. Between V ^ B =
- 0,4 Volt und V^B = + 0,4 Volt ist dieser Faktor ebenfalls ca . 4 , nimmt jedoch bei betragsmäßig höheren Spannungen ab.- 0.4 volts and V ^ B = + 0.4 volts this factor is also approx. 4, but decreases with higher amounts.
Derartige Schaltungsanordnungen können in allen integrierten Schaltungen mit kapazitiven Elementen eingesetzt werden, wie zum Beispiel in Switched-Capacitor (SC) Filtern und Analog- Digital -Wandlern, wie zum Beispiel Sigma-Delta-Wandlern. Such circuit arrangements can be used in all integrated circuits with capacitive elements, such as in switched-capacitor (SC) filters and analog-digital converters, such as sigma-delta converters.

Claims

Patentansprüche claims
1. Schaltungsanordnung zur Bildung einer MOS-Kapazität mit geringer Spannungsabhängigkeit, bei der zwei MOS-Transistoren (Tl, T2) vorhanden sind, deren jeweiliger Drain- und Source-Anschluß (Dl, Sl und D2 , S2) miteinander verbunden sind, d a d u r c h g e k e n n z e i c h n e t, daß die zwei MOS-Transistoren Kurzkanal -Transistoren sind, wobei deren Kanallänge gegen die minimal in der entsprechenden Technologie realisierbare Kanallänge geht.1. Circuit arrangement for forming a MOS capacitance with low voltage dependency, in which two MOS transistors (Tl, T2) are present, the respective drain and source connections (Dl, Sl and D2, S2) are connected to one another, characterized in that that the two MOS transistors are short-channel transistors, the channel length of which goes against the minimally realizable channel length in the corresponding technology.
2. Schaltungsanordnung nach Anspruch 1, d a d u r c h g e k e n n z e i c h n e t, daß die zwei MOS-Transistoren in Verarmung betriebene Kurzkanal-Transistoren sind.2. Circuit arrangement according to claim 1, d a d u r c h g e k e n n z e i c h n e t that the two MOS transistors are depleted short-channel transistors.
3. Schaltungsanordnung nach Anspruch 1 oder 2, d a d u r c h g e k e n n z e i c h n e t, daß die Kanallänge kleiner oder gleich 1 μm beträgt.3. Circuit arrangement according to claim 1 or 2, d a d u r c h g e k e n n z e i c h n e t that the channel length is less than or equal to 1 micron.
4. Schaltungsanordnung nach einem der Ansprüche 1 bis 3, d a d u r c h g e k e n n z e i c h n e t, daß die zwei MOS-Transistoren (Tl, T2) den gleichen Kanaltyp aufweisen und antiseriell geschaltet sind und deren Depleti - on-Bereiche dadurch verbreitert sind, daß eine Potential - differenz (VI, V2) zwischen miteinander verbundenen jeweiligen Bulk-Anschlüssen (BLK1, BLK2) bzw. miteinander verbundenen jeweiligen Gates (Gl, G2) und den jeweils verbundenen Drain- und Source-Anschlüssen besteht.4. Circuit arrangement according to one of claims 1 to 3, characterized in that the two MOS transistors (Tl, T2) have the same channel type and are connected in series and their depletion - on areas are broadened in that a potential difference (VI , V2) between interconnected respective bulk connections (BLK1, BLK2) or interconnected respective gates (Gl, G2) and the respectively connected drain and source connections.
5. Schaltungsanordnung nach einem der Ansprüche 1 bis 3, d a d u r c h g e k e n n z e i c h n e t, daß die zwei MOS-Transistoren antiparallel geschaltet sind, wobei jeweils ein Bulk-Anschluß (BLK1, BLK2) des einen MOS- Transistors mit dem Gate (G2, Gl) des jeweils anderen Transistors (T2, Tl) über einen jeweiligen Anschluß (A, B) der MOS- Kapazität verbunden ist, und deren Depletion-Bereiche dadurch verbreitert sind, daß eine Potentialdifferenz (VI, V2) zwischen einem jeweiligen Bulk-Anschluß (BLK2, BLKl) bzw. einem Gate (Gl, G2) und den jeweils verbundenen Drain- und Source- Anschlüssen (Dl, Sl und D2 , S2) besteht. 5. Circuit arrangement according to one of claims 1 to 3, characterized in that the two MOS transistors are connected antiparallel, each having a bulk connection (BLK1, BLK2) of a MOS transistor with the gate (G2, Gl) of the other Transistors (T2, Tl) via a respective connection (A, B) of the MOS Capacity is connected, and their depletion areas are broadened in that a potential difference (VI, V2) between a respective bulk connection (BLK2, BLKl) or a gate (Gl, G2) and the respectively connected drain and source Connections (Dl, Sl and D2, S2) exists.
EP00978967A 1999-09-30 2000-09-29 Circuit arrangement for creating a mos capacitor with a lower voltage dependency and a lower surface area requirement Withdrawn EP1218945A1 (en)

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DE19946977 1999-09-30
DE19947116 1999-09-30
DE19947116 1999-09-30
DE19946977 1999-09-30
DE19961487 1999-12-20
DE19961487A DE19961487B4 (en) 1999-09-30 1999-12-20 Circuit arrangement for forming a MOS capacitor with low voltage dependence and low space requirement
PCT/DE2000/003479 WO2001024277A1 (en) 1999-09-30 2000-09-29 Circuit arrangement for creating a mos capacitor with a lower voltage dependency and a lower surface area requirement

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