CN111785716B - Capacitor with a capacitor body - Google Patents

Capacitor with a capacitor body Download PDF

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Publication number
CN111785716B
CN111785716B CN201910264732.4A CN201910264732A CN111785716B CN 111785716 B CN111785716 B CN 111785716B CN 201910264732 A CN201910264732 A CN 201910264732A CN 111785716 B CN111785716 B CN 111785716B
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switch
transistor
terminal
coupled
capacitor
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CN111785716A (en
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陈禀亮
简兆良
汤士逸
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Himax Technologies Ltd
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Himax Technologies Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
    • H01L27/0266—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using field effect transistors as protective elements
    • H01L27/0285—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using field effect transistors as protective elements bias arrangements for gate electrode of field effect transistors, e.g. RC networks, voltage partitioning circuits

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Electronic Switches (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

A capacitor includes a first transistor, a second transistor, and a control circuit. A first terminal of the first transistor is coupled to a first terminal of the capacitor. The first terminal of the second transistor is coupled to the second terminal of the capacitor. In the normal mode, the control circuit turns on the first transistor and the second transistor, the second terminal of the second transistor is coupled to the control terminal of the first transistor via the control circuit, and the control terminal of the second transistor is coupled to the second terminal of the first transistor via the control circuit. In the power saving mode, the control circuit turns off the first transistor and the second transistor.

Description

Capacitor with a capacitor body
Technical Field
The invention relates to a capacitor.
Background
Capacitors are often widely used in integrated circuits. For example, a capacitor coupled between the system voltage rail (system voltage rail) and the ground voltage rail (ground voltage rail) may be used as a decoupling capacitor (decoupling capacitor). The decoupling capacitor has a voltage stabilizing function.
In integrated circuits, some capacitor implementations use transistors, such as Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET). For example, when an N-channel Metal-Oxide-Semiconductor (NMOS) transistor is used as a capacitor, the gate of the NMOS transistor is directly coupled to the system voltage rail, and the drain and source of the NMOS transistor are directly coupled to the ground voltage rail. When a P-channel Metal-Oxide-Semiconductor (PMOS) transistor is used as the capacitor, the drain and source of the PMOS transistor are directly coupled to the system voltage rail, and the gate of the PMOS transistor is directly coupled to the ground voltage rail. In any event, because the gate of the transistor is directly coupled to the power rail (either the system voltage rail or the ground voltage rail), when an electrostatic discharge (electrostatic discharge, ESD) event occurs on the power rail, the ESD current is likely to break down the gate of the transistor and burn the transistor.
Disclosure of Invention
The present invention provides a capacitor to improve electrostatic discharge (electrostatic discharge, ESD) protection and reduce leakage current in power saving modes.
An embodiment of the present invention provides a capacitor. The capacitor includes a first transistor, a second transistor, and a control circuit. The first terminal of the first transistor is coupled to the first terminal of the capacitor. The first terminal of the second transistor is coupled to the second terminal of the capacitor. The control circuit is coupled between the first transistor and the second transistor. In the power saving mode, the control circuit turns off the first transistor and the second transistor. In the normal mode, the control circuit turns on the first transistor and the second transistor, the second terminal of the second transistor is coupled to the control terminal of the first transistor via the control circuit, and the control terminal of the second transistor is coupled to the second terminal of the first transistor via the control circuit.
Based on the above, in the capacitor according to the embodiments of the present invention, the control terminals of the first transistor and the second transistor are not directly coupled to the first terminal and the second terminal of the capacitor, so as to improve the ESD protection capability. When the system enters the power saving mode, the control circuit can turn off the first transistor and the second transistor to reduce the leakage current.
In order to make the above features and advantages of the present invention more comprehensible, embodiments accompanied with figures are described in detail below.
Drawings
Fig. 1 is a schematic diagram of a circuit block (circuit block) of a capacitor according to an embodiment of the invention.
FIG. 2 is a circuit block diagram illustrating the control circuit of FIG. 1 according to one embodiment of the present invention.
FIG. 3 is a circuit block diagram illustrating the control circuit of FIG. 1 according to another embodiment of the present invention.
Fig. 4 is a circuit block diagram illustrating the control circuit shown in fig. 1 according to another embodiment of the present invention.
Fig. 5 is a timing diagram illustrating an operating state of the switch of fig. 4 according to an embodiment of the present invention.
Fig. 6 is a timing diagram illustrating an operational state of the switch of fig. 4 according to another embodiment of the present invention.
FIG. 7 is a circuit block diagram illustrating the control circuit of FIG. 1 according to yet another embodiment of the present invention.
FIG. 8 is a circuit block diagram illustrating the control circuit of FIG. 1 according to a further embodiment of the present invention.
Fig. 9 is a timing diagram illustrating an operating state of the switch of fig. 8 according to an embodiment of the present invention.
Fig. 10 is a timing diagram illustrating an operating state of the switch of fig. 8 according to another embodiment of the present invention.
FIG. 11 is a circuit block diagram illustrating the control circuit of FIG. 1 according to another embodiment of the present invention.
Fig. 12 is a timing diagram illustrating an operating state of the switch of fig. 11 according to an embodiment of the present invention.
Fig. 13 is a timing diagram illustrating an operational state of the switch of fig. 11 according to another embodiment of the present invention.
FIG. 14 is a circuit block diagram illustrating the control circuit of FIG. 1 according to yet another embodiment of the present invention.
Fig. 15 is a timing diagram illustrating an operating state of the switch of fig. 14 according to an embodiment of the present invention.
Fig. 16 is a timing diagram illustrating an operational state of the switch of fig. 14 according to another embodiment of the present invention.
FIG. 17 is a circuit block diagram illustrating the control circuit of FIG. 1 according to a further embodiment of the present invention.
Fig. 18 is a circuit block diagram illustrating the control circuit of fig. 1 according to another embodiment of the present invention.
Fig. 19 is a timing diagram illustrating an operating state of the switch of fig. 18 according to an embodiment of the present invention.
Fig. 20 is a timing diagram illustrating an operational state of the switch of fig. 18 according to another embodiment of the present invention.
[ reference numerals description ]
100: capacitor with a capacitor body
110: control circuit
111. 112: reverse brake
CSP: charge sharing period
NM: normal mode
P1, N1: transistor with a high-speed transistor
PCP: during precharge
PR1, PR2: power supply rail
PSM: power saving mode
PSP: during power saving period
S1, S2: control signal
SLP: sleep signal
SW1, SW2, SW3, SW4, SW5, SW6, SW7, SW8, SW9: switch
VS, VSB: short circuit control signal
Detailed Description
The term "coupled" as used throughout this specification (including the claims) may refer to any direct or indirect connection. For example, if a first device couples (or connects) to a second device, that connection may be through a direct connection, or through an indirect connection via other devices and connections. In addition, wherever possible, the same reference numbers will be used throughout the drawings and the description to refer to the same or like parts. Elements/components/steps in different embodiments that use the same reference numerals or use the same language may be referred to in relation to each other.
Fig. 1 is a schematic diagram of a circuit block (circuit block) of a capacitor 100 according to an embodiment of the invention. In the embodiment shown in fig. 1, a first terminal of the capacitor 100 is coupled to the power rail PR1, and a second terminal of the capacitor 100 is coupled to the power rail PR2. In accordance with design requirements, in some embodiments, power rail PR1 may transmit a system voltage (e.g., system voltage VDD) and power rail PR2 may transmit a reference voltage (e.g., ground voltage VSS). In other embodiments, power rail PR1 may transmit the reference voltage and power rail PR2 may transmit the system voltage.
In no way should the application of the capacitor 100 be limited to the embodiment shown in fig. 1. Any capacitor in an electronic circuit may be implemented with reference to capacitor 100 shown in fig. 1.
The capacitor 100 includes a transistor P1, a transistor N1, and a control circuit 110. When the transistor P1 is one of an N-channel Metal-Oxide-Semiconductor (NMOS) transistor and a P-channel Metal-Oxide-Semiconductor (PMOS) transistor, the transistor N1 is the other of the NMOS transistor and the PMOS transistor. For example, in the embodiment shown in FIG. 1, transistor P1 is a PMOS transistor and transistor N1 is an NMOS transistor. In other embodiments, the transistor P1 may be an NMOS transistor and the transistor N1 may be a PMOS transistor, depending on design requirements.
A first terminal (e.g., source) of the transistor P1 is coupled to a first terminal of the capacitor 100. A first terminal (e.g., source) of the transistor N1 is coupled to a second terminal of the capacitor 100. The control circuit 110 is coupled between the transistor P1 and the transistor N1. In the normal mode, the second terminal (e.g., drain) of the transistor N1 is coupled to the control terminal (e.g., gate) of the transistor P1 via the control circuit 110, and the control terminal (e.g., gate) of the transistor N1 is coupled to the second terminal (e.g., drain) of the transistor P1 via the control circuit 110.
The control circuit 110 is coupled to the control terminal of the transistor P1 and the control terminal of the transistor N1. In the power saving mode, the control circuit 110 turns off the transistor P1 via the control signal S1 and turns off the transistor N1 via the control signal S2. Since the transistor P1 and the transistor N1 are turned off, the leakage current of the capacitor 100 can be effectively reduced.
In the normal mode, the control circuit 110 can turn on (turn on) the transistor P1 and the transistor N1. The present embodiment does not limit the conduction mechanism of the transistor P1 and the transistor N1. For example, in some embodiments, the control circuit 110 may turn on the transistor P1 via the control signal S1 and turn on the transistor N1 via the control signal S2. In other embodiments, the control circuit 110 may not output the control signals S1 and S2 in the normal mode, i.e. the output of the control circuit 110 is floating. When the output of the control circuit 110 is in a floating state, the positive charge at the control terminal of the transistor P1 is drained to the power rail PR2 through the transistor N1, i.e. the voltage at the control terminal of the transistor P1 is pulled down. Therefore, when the output of the control circuit 110 is in the floating state, the transistor P1 and the transistor N1 are turned on.
It should be noted that the gates of transistor P1 and transistor N1 are not directly coupled to the first and second terminals of capacitor 100, so that ESD current is less likely to break through the gates of the transistors (with greater ESD protection capability). When the system enters the power saving mode, the control circuit 110 can turn off the transistor P1 and the transistor N1 to reduce the leakage current.
The blocks of the control circuit 110 may be implemented in hardware (hardware), firmware (firmware), software (software), or a combination of any three according to various design requirements. In hardware, the blocks of the control circuit 110 may be implemented as logic circuits on an integrated circuit (integrated circuit). The relevant functions of the control circuit 110 described above may be implemented as hardware using a hardware description language (hardware description languages, such as Verilog HDL or VHDL) or other suitable programming language. For example, the functions associated with the control circuit 110 described above may be implemented in one or more logic blocks, modules, and/or circuits.
Fig. 2 is a circuit block diagram illustrating the control circuit 110 shown in fig. 1 according to an embodiment of the present invention. In the embodiment shown in fig. 2, the control circuit 110 includes a switch SW1 and a switch SW2. The first terminal of the switch SW1 is coupled to a first voltage. The first voltage may be any voltage sufficient to turn off the transistor P1 according to design requirements. For example, in the embodiment shown in fig. 2, the first voltage may be a system voltage (e.g., system voltage VDD) of the power supply rail PR 1. The second terminal of the switch SW1 is coupled to the control terminal of the transistor P1. The switch SW1 is controlled by the sleep signal SLP. The sleep signal SLP may be a control signal sent by a system controller (not shown). When the sleep signal SLP is at the first logic level (indicating that the system enters the sleep mode or the power saving mode), the switch SW1 is turned on. When the switch SW1 is turned on, the first voltage can turn off the transistor P1. When the sleep signal SLP is at the second logic level (indicating that the system enters the normal mode), the switch SW1 is turned off.
The first terminal of the switch SW2 is coupled to the second voltage. The second voltage may be any voltage sufficient to turn off transistor N1, depending on design requirements. For example, in the embodiment shown in fig. 2, the second voltage may be a reference voltage (e.g., a ground voltage VSS) of the power rail PR2. A second terminal of the switch SW2 is coupled to the control terminal of the transistor N1. The switch SW2 is controlled by the sleep signal SLP. When the sleep signal SLP is at the first logic level (indicating that the system enters the sleep mode or the power saving mode), the switch SW2 is turned on. When the switch SW2 is turned on, the second voltage may turn off the transistor N1. When the sleep signal SLP is at the second logic level (indicating that the system enters the normal mode), the switch SW2 is turned off.
Fig. 3 is a circuit block diagram illustrating the control circuit 110 shown in fig. 1 according to another embodiment of the present invention. In the embodiment shown in fig. 3, the control circuit 110 includes a switch SW1, a switch SW2, an inverse gate 111 and an inverse gate 112. The switch SW1 and the switch SW2 shown in fig. 3 can be analogized with reference to the related descriptions of the switch SW1 and the switch SW2 shown in fig. 2, and thus the description thereof will not be repeated. In the embodiment shown in FIG. 3, the switch SW1 comprises a PMOS transistor and the switch SW2 comprises an NMOS transistor.
The input of the inverse gate 111 is used for receiving the sleep signal SLP. The sleep signal SLP may be a control signal sent by a system controller (not shown). When the sleep signal SLP is at a first logic level (e.g., a high logic level), it indicates that the system enters a sleep mode or a power saving mode. When the sleep signal SLP is at a second logic level (e.g., a low logic level), it indicates that the system enters a normal mode. The output of the inverse gate 111 is coupled to the gate of the PMOS transistor (switch SW 1). The input of the inverse gate 112 is coupled to the output of the inverse gate 111. The output of the inverse gate 112 is coupled to the gate of the NMOS transistor (switch SW 2).
Fig. 4 is a circuit block diagram illustrating the control circuit 110 shown in fig. 1 according to another embodiment of the present invention. In the embodiment shown in fig. 4, the control circuit 110 includes a switch SW1, a switch SW2, and a switch SW3. The switch SW1 and the switch SW2 shown in fig. 4 can be analogized with reference to the related description of fig. 2 or fig. 3, and thus are not described again. The first terminal of the switch SW3 is coupled to the control terminal of the transistor P1. A second terminal of the switch SW3 is coupled to the control terminal of the transistor N1. During charge sharing (charge sharing) in the power saving mode, the switch SW3 is turned on. During the power saving period of the power saving mode after the charge sharing period, the transistor P1 and the transistor N1 are turned off. In the normal mode, the switch SW3 is off.
The implementation of the switch SW3 may be determined according to design requirements. For example, in the embodiment shown in fig. 4, the switch SW3 may include a transmission gate (transmission gate). The first terminal of the transmission gate is coupled to the control terminal of the transistor P1. The second terminal of the transmission gate is coupled to the control terminal of the transistor N1. The control end of the transmission gate is controlled by a short-circuit control signal VS, and the inverting control end of the transmission gate is controlled by a short-circuit control signal VSB, wherein the short-circuit control signal VSB is an inverting signal of the short-circuit control signal VS.
The capacitor 100 with the switch SW3 enhances performance in the power saving mode. If the short control signal VS is high because the switch SW3 shorts the control terminal of the transistor N1 and the control terminal of the transistor P1 together, the loop of the capacitor 100 is weakened (i.e., the voltage level of the control terminal of the transistor N1 is pulled down from the system voltage VDD to VDD/2 and the voltage level of the control terminal of the transistor P1 is pulled up from the ground voltage VSs to VDD/2). If the short circuit control signal VS goes high before the switch SW1 and the switch SW2 are turned on, the control terminals of the transistor N1 and the transistor P1 are rapidly pulled to the ground voltage VSs and the system voltage VDD, respectively, because the switch SW1 and the switch SW2 discharge or charge half power to the control terminals of the transistor N1 and the transistor P1. In some applications, the capacitance of capacitor 100 is very large, and switch SW3 helps to improve the performance of transistor N1 and transistor P1 during the period of disabling capacitor 100.
Fig. 5 is a timing diagram illustrating an operating state of the switch of fig. 4 according to an embodiment of the present invention. The horizontal axis in fig. 5 represents time, and the vertical axis represents signal level. In the normal mode NM, the switch SW1, the switch SW2, and the switch SW3 are off. During the charge sharing period CSP of the power saving mode PSM, the switch SW3 is on. After the end of the charge sharing period CSP, the switch SW3 is turned off. During a power saving period PSP of a power saving mode PSM after the charge sharing period CSP, the switches SW1 and SW2 are turned on (i.e., the transistors P1 and N1 are turned off).
Fig. 6 is a timing diagram illustrating an operational state of the switch of fig. 4 according to another embodiment of the present invention. The horizontal axis in fig. 6 represents time, and the vertical axis represents signal level. In the normal mode NM, the switch SW1, the switch SW2, and the switch SW3 are off. During the charge sharing period CSP of the power saving mode PSM, the switches SW1 and SW2 are off and the switch SW3 is on. During a power save period PSP of the power save mode PSM after the charge share period CSP, the switches SW1 and SW2 are on (i.e., the transistors P1 and N1 are off) and the switch SW3 is off.
Fig. 7 is a circuit block diagram illustrating the control circuit 110 of fig. 1 according to another embodiment of the present invention. In the embodiment shown in fig. 7, the control circuit 110 includes a switch SW1, a switch SW2, and a switch SW3. The switch SW1 and the switch SW2 shown in fig. 7 may refer to the related descriptions of fig. 2 or 3, and the switch SW3 shown in fig. 7 may refer to the related descriptions of fig. 4 to 6, so that the description is omitted. In the embodiment shown in fig. 7, the switch SW3 may comprise a transistor. The first terminal of the transistor is coupled to the control terminal of the transistor P1. The second terminal of the transistor is coupled to the control terminal of the transistor N1. The control terminal of the transistor is controlled by the short-circuit control signal VS.
Fig. 8 is a circuit block diagram illustrating the control circuit 110 of fig. 1 according to a further embodiment of the present invention. In the embodiment shown in fig. 8, the control circuit 110 includes a switch SW1, a switch SW2, a switch SW4, and a switch SW5. The switch SW1 and the switch SW2 shown in fig. 8 can refer to the related descriptions of fig. 2 or fig. 3, and thus are not described again.
The switch SW4 is coupled between the second terminal of the transistor P1 and the control terminal of the transistor N1 (i.e., the first terminal of the switch SW4 is coupled to the second terminal of the transistor P1, and the second terminal of the switch SW4 is coupled to the control terminal of the transistor N1). The switch SW5 is coupled between the control terminal of the transistor P1 and the second terminal of the transistor N1 (i.e., the first terminal of the switch SW5 is coupled to the second terminal of the transistor N1, and the second terminal of the switch SW5 is coupled to the control terminal of the transistor P1). In the normal mode NM, the switch SW4 and the switch SW5 are on, and in the power saving mode PSM, the switch SW4 and the switch SW5 are off.
The switches SW4 and SW5 help to improve the performance of the transistors N1 and P1 during the period when the capacitor 100 is disabled. If the switches SW4 and SW5 are turned off before the switches SW1 and SW2 are turned on, the control terminals of the transistors N1 and P1 are rapidly pulled to the ground voltage VSS and the system voltage VDD, respectively. In other embodiments, one of the switch SW4 and the switch SW5 may be omitted, depending on design requirements.
Fig. 9 is a timing diagram illustrating an operating state of the switch of fig. 8 according to an embodiment of the present invention. The horizontal axis in fig. 9 represents time, and the vertical axis represents signal level. In the normal mode NM, the switch SW1 and the switch SW2 are off, and the switch SW4 and the switch SW5 are on. In the power saving mode PSM, the switch SW4 and the switch SW5 are off. After the switches SW4 and SW5 are turned off, the switches SW1 and SW2 are turned on in the power saving mode PSM.
Fig. 10 is a timing diagram illustrating an operating state of the switch of fig. 8 according to another embodiment of the present invention. The horizontal axis in fig. 10 represents time, and the vertical axis represents signal level. In the normal mode NM, the switch SW1 and the switch SW2 are off, and the switch SW4 and the switch SW5 are on. In the power saving mode PSM, the switches SW1 and SW2 are on (i.e., the transistors P1 and N1 are off), and the switches SW4 and SW5 are off.
Fig. 11 is a circuit block diagram illustrating the control circuit 110 shown in fig. 1 according to another embodiment of the present invention. In the embodiment shown in fig. 11, the control circuit 110 includes a switch SW1, a switch SW2, a switch SW3, a switch SW4, and a switch SW5. The switch SW1 and the switch SW2 shown in fig. 11 can be analogized with reference to the related descriptions of fig. 2 or 3, the switch SW3 shown in fig. 11 can be analogized with reference to the related descriptions of fig. 4 to 7, and the switch SW4 and the switch SW5 shown in fig. 11 can be analogized with reference to the related descriptions of fig. 8 to 10, so that the description is omitted.
Fig. 12 is a timing diagram illustrating an operating state of the switch of fig. 11 according to an embodiment of the present invention. The horizontal axis shown in fig. 12 represents time, and the vertical axis represents signal level. In the normal mode NM, the switch SW1, the switch SW2, and the switch SW3 are off, and the switch SW4 and the switch SW5 are on. In the power saving mode PSM, the switch SW4 and the switch SW5 are off. After the switches SW4 and SW5 are turned off, the switches SW1, SW2 and SW3 may be turned on in the power saving mode PSM. For example, the CSP switch SW1 and the switch SW2 are off and the switch SW3 is on during the charge sharing period of the power saving mode PSM, and the PSP switch SW1 and the switch SW2 are on and the switch SW3 is off during the power saving period of the power saving mode PSM after the charge sharing period CSP.
Fig. 13 is a timing diagram illustrating an operational state of the switch of fig. 11 according to another embodiment of the present invention. The horizontal axis in fig. 13 represents time, and the vertical axis represents signal level. In the normal mode NM, the switch SW1, the switch SW2, and the switch SW3 are off, and the switch SW4 and the switch SW5 are on. After the normal mode NM is ended, the switch SW4 and the switch SW5 are turned off in the power saving mode PSM. During a period in which the switch SW4 and the switch SW5 are turned off, the switch SW3 is turned on in the charge sharing period CSP of the power saving mode PSM, and during a power saving period PSP of the power saving mode PSM subsequent to the charge sharing period CSP, the switch SW1 and the switch SW2 are turned on and the switch SW3 is turned off.
Fig. 14 is a circuit block diagram illustrating the control circuit 110 of fig. 1 according to another embodiment of the present invention. In the embodiment shown in fig. 14, the control circuit 110 includes a switch SW1, a switch SW2, a switch SW3, a switch SW4, a switch SW5, a switch SW6, and a switch SW7. The switch SW1 and the switch SW2 shown in fig. 14 can be analogized with reference to the related descriptions of fig. 2 or 3, the switch SW3 shown in fig. 14 can be analogized with reference to the related descriptions of fig. 4 to 7 and 11 to 13, and the switch SW4 and the switch SW5 shown in fig. 14 can be analogized with reference to the related descriptions of fig. 8 to 13, so that the description is omitted.
In the embodiment shown in fig. 14, the first terminal of the switch SW6 is coupled to a certain voltage (e.g. the ground voltage VSS). A second terminal of the switch SW6 is coupled to the control terminal of the transistor P1. A first terminal of the switch SW7 is coupled to a certain voltage (e.g. the system voltage VDD). A second terminal of the switch SW7 is coupled to the control terminal of the transistor N1. In the normal mode NM, the switch SW6 and the switch SW7 are on. In the power saving mode PSM, the switch SW6 and the switch SW7 are off. The switches SW6 and SW7 are used to precharge the control terminal of the transistor P1 and the control terminal of the transistor N1. When capacitor 100 is enabled (during normal mode NM), switch SW6 and switch SW7 will help capacitor 100 get ready faster. In other embodiments, one of the switches SW6 and SW7 may be omitted, depending on design requirements.
Fig. 15 is a timing diagram illustrating an operating state of the switch of fig. 14 according to an embodiment of the present invention. The horizontal axis in fig. 15 represents time, and the vertical axis represents signal level. In the normal mode NM, the switch SW1, the switch SW2 and the switch SW3 are off, and the switch SW4, the switch SW5, the switch SW6 and the switch SW7 are on. After the normal mode NM is ended, the switches SW4, SW5, SW6 and SW7 are turned off in the power saving mode PSM. In the charge sharing period CSP of the power saving mode PSM, the switch SW3 is on and the switches SW1 and SW2 are off. After the charge sharing period CSP, in the power saving period PSP of the power saving mode PSM, the switch SW1 and the switch SW2 are turned on and the switch SW3 is turned off.
Fig. 16 is a timing diagram illustrating an operational state of the switch of fig. 14 according to another embodiment of the present invention. The horizontal axis in fig. 16 represents time, and the vertical axis represents signal level. The operations of the switches SW1, SW2, SW3, SW4 and SW5 shown in fig. 16 can be analogized with reference to the related description of fig. 15, and thus are not repeated. In the embodiment shown in fig. 16, the switch SW6 and the switch SW7 are turned off in the power saving mode PSM, the switch SW6 and the switch SW7 are turned on in the precharge period PCP of the normal mode NM, and the switch SW6 and the switch SW7 are turned off after the precharge period PCP in the normal mode NM.
Fig. 17 is a circuit block diagram illustrating the control circuit 110 of fig. 1 according to a further embodiment of the present invention. In the embodiment shown in fig. 17, the control circuit 110 includes a switch SW1, a switch SW2, a switch SW3, a switch SW4, a switch SW5, a switch SW6, a switch SW7, a switch SW8, and a switch SW9. The switch SW1 and the switch SW2 shown in fig. 17 can be analogized with reference to the related descriptions of fig. 2 or 3, the switch SW3 shown in fig. 17 can be analogized with reference to the related descriptions of fig. 4 to 7 and 11 to 16, the switch SW4 and the switch SW5 shown in fig. 17 can be analogized with reference to the related descriptions of fig. 8 to 16, and the switch SW6 and the switch SW7 shown in fig. 17 can be analogized with reference to the related descriptions of fig. 14 to 16, so that the description is omitted.
In the embodiment shown in fig. 17, a first terminal of the switch SW8 is configured to be coupled to a certain voltage (e.g., a ground voltage VSS). A second terminal of the switch SW8 is coupled to the second terminal of the transistor N1 and the first terminal of the switch SW5. A first terminal of the switch SW9 is configured to be coupled to a certain voltage (e.g., the system voltage VDD). A second terminal of the switch SW9 is coupled to the second terminal of the transistor P1 and the first terminal of the switch SW 4. In the normal mode NM, the switch SW8 and the switch SW9 are off. In the power saving mode PSM, the switch SW8 and the switch SW9 are on. The control signals of the switch SW8 and the switch SW9 may be inverted signals of the control signals of the switch SW4 and the switch SW5.
Fig. 18 is a circuit block diagram illustrating the control circuit 110 of fig. 1 according to another embodiment of the present invention. In the embodiment shown in fig. 18, the control circuit 110 includes a switch SW1, a switch SW2, a switch SW3, a switch SW4, a switch SW6, and a switch SW7. The switch SW1 and the switch SW2 shown in fig. 18 can be analogized with reference to the related descriptions of fig. 2 or 3, the switch SW3 shown in fig. 18 can be analogized with reference to the related descriptions of fig. 4 to 7 and 11 to 16, the switch SW4 shown in fig. 18 can be analogized with reference to the related descriptions of fig. 8 to 16, and the switch SW7 shown in fig. 18 can be analogized with reference to the related descriptions of fig. 14 to 16, so that the description is omitted.
Fig. 19 is a timing diagram illustrating an operating state of the switch of fig. 18 according to an embodiment of the present invention. The horizontal axis in fig. 19 represents time, and the vertical axis represents signal level. In the normal mode NM, the switches SW1, SW2 and SW3 are off, and the switches SW4, SW6 and SW7 are on. After the normal mode NM is ended, the switches SW4, SW6 and SW7 are turned off in the power saving mode PSM. During the period when the switch SW4 is turned off, the switch SW3 is turned on in the charge sharing period CSP of the power saving mode PSM. After the charge sharing period CSP, during the power saving period PSP of the power saving mode PSM, the switch SW1 and the switch SW2 are turned on and the switch SW3 is turned off.
Fig. 20 is a timing diagram illustrating an operational state of the switch of fig. 18 according to another embodiment of the present invention. The horizontal axis in fig. 20 represents time, and the vertical axis represents signal level. The operations of the switches SW1, SW2, SW3 and SW4 shown in fig. 20 can be analogized with reference to the related description of fig. 19, and thus will not be repeated. In the embodiment shown in fig. 20, the switch SW6 and the switch SW7 are turned off in the power saving mode PSM, the switch SW6 and the switch SW7 are turned on during the precharge period PCP of the normal mode NM, and the switch SW6 and the switch SW7 are turned off after the precharge period PCP in the normal mode NM.
In summary, in the capacitor 100 according to the embodiments of the present invention, the control terminals of the transistor P1 and the transistor N1 are not directly coupled to the first terminal and the second terminal of the capacitor 100, so as to improve the ESD protection capability. When the system enters the power saving mode, the control circuit 110 can turn off the transistor P1 and the transistor N1 to reduce the leakage current.
Although the present invention has been described with reference to the above embodiments, it should be understood that the invention is not limited thereto, but rather is capable of modification in detail without departing from the spirit and scope of the present invention as defined in the appended claims.

Claims (12)

1. A capacitor, comprising:
a first transistor having a first terminal for coupling to a first terminal of the capacitor;
a second transistor having a first terminal for coupling to a second terminal of the capacitor; and
a control circuit coupled between the first transistor and the second transistor, wherein
In a power saving mode, the control circuit turns off the first transistor and the second transistor, and
in a normal mode, the control circuit turns on the first transistor and the second transistor, wherein a second terminal of the second transistor is coupled to a control terminal of the first transistor via the control circuit, and a control terminal of the second transistor is coupled to a second terminal of the first transistor via the control circuit,
wherein the control circuit includes:
a first switch having a first terminal for coupling to a first voltage, wherein a second terminal of the first switch is coupled to the control terminal of the first transistor, and the first voltage turns off the first transistor when the first switch is turned on;
a second switch having a first terminal for coupling to a second voltage, wherein a second terminal of the second switch is coupled to the control terminal of the second transistor, and the second voltage turns off the second transistor when the second switch is turned on;
a third switch having a first terminal for coupling to the second voltage, wherein a second terminal of the third switch is coupled to the control terminal of the first transistor; and
a fourth switch having a first terminal for coupling to the first voltage, wherein a second terminal of the fourth switch is coupled to the control terminal of the second transistor.
2. The capacitor of claim 1 wherein the first end of the capacitor is configured to be coupled to a first power rail and the second end of the capacitor is configured to be coupled to a second power rail.
3. The capacitor of claim 1 wherein when the first transistor is one of an NMOS transistor and a PMOS transistor, the second transistor is the other of the NMOS transistor and the PMOS transistor.
4. The capacitor of claim 1, wherein the first switch and the second switch are controlled by a sleep signal.
5. The capacitor of claim 1 wherein said first switch comprises a PMOS transistor and said second switch comprises an NMOS transistor, said control circuit further comprising:
a first inverse gate having an input end for receiving a sleep signal, wherein an output end of the first inverse gate is coupled to the gate of the PMOS transistor; and
a second inverse gate having an input coupled to the output of the first inverse gate, wherein an output of the second inverse gate is coupled to the gate of the NMOS transistor.
6. The capacitor of claim 1, wherein the third switch and the fourth switch are on in the normal mode and the third switch and the fourth switch are off in the power saving mode.
7. The capacitor of claim 1, wherein the third and fourth switches are off in the power saving mode, the third and fourth switches are on during a precharge period of the normal mode, and the switches and fourth switches are off after the precharge period in the normal mode.
8. The capacitor of claim 1, wherein the control circuit comprises:
a switch having a first terminal for coupling to the control terminal of the first transistor, wherein a second terminal of the switch is coupled to the control terminal of the second transistor, and the switch is on during a charge sharing period in the power saving mode, the first transistor and the second transistor are off during a power saving period of the power saving mode subsequent to the charge sharing period, and the switch is off in the normal mode.
9. The capacitor of claim 1, wherein the control circuit comprises:
the first switch is coupled between the second end of the first transistor and the control end of the second transistor, wherein the first switch is turned on in the normal mode, and the first switch is turned off in the power saving mode.
10. The capacitor of claim 9, wherein the control circuit further comprises:
a second switch having a first terminal for coupling to a first voltage, wherein a second terminal of the second switch is coupled to the second terminal of the first transistor and to a first terminal of the first switch, the second switch being off in the normal mode and the second switch being on in the power saving mode.
11. The capacitor of claim 1, wherein the control circuit comprises:
the first switch is coupled between the control end of the first transistor and the second end of the second transistor, wherein the first switch is turned on in the normal mode, and the first switch is turned off in the power saving mode.
12. The capacitor of claim 11, wherein the control circuit further comprises:
a second switch having a first terminal for coupling to a second voltage, wherein the second terminal of the second switch is coupled to the second terminal of the second transistor and a first terminal of the first switch, the second switch being off in the normal mode and the second switch being on in the power saving mode.
CN201910264732.4A 2019-04-03 2019-04-03 Capacitor with a capacitor body Active CN111785716B (en)

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US6228696B1 (en) * 1998-11-05 2001-05-08 Vantis Corporation Semiconductor-oxide-semiconductor capacitor formed in integrated circuit
WO2001024277A1 (en) * 1999-09-30 2001-04-05 Infineon Technologies Ag Circuit arrangement for creating a mos capacitor with a lower voltage dependency and a lower surface area requirement
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