TWI224426B - Input/output buffer - Google Patents

Abstract

An input/output buffer. An input/output circuit is composed of a first PMOS transistor and a first NMOS transistor, has an I/O port coupled to an I/O pad, and a N-well region. An N-well control circuit controls the voltage level at the N-well region of the first PMOS transistor according to input signals at the I/O pad. A P-gate control circuit receives a second gate control signal and outputs to the gate of the first PMOS transistor. The P-gate control circuit is composed of a transmission gate and a third PMOS transistor. The transmission gate and the third PMOS transistor do not have to follow the design rule for ESD, and the wafer area required for the P-gate control circuit can be decreased because the P-gate control circuit is not directly connected to the I/O pad.

Description

1224426

FIELD OF THE INVENTION The present invention relates to an input / output buffer and a round-in / output buffer, which can reduce the chip area of the prior art, especially the related art. The 1C device that has been integrated ^ + r is driven by a # μ &# lightning pressure. In this 4Mr station, the electrical system voltage of Houji + "Hot", the signal of the voltage level is set to the signal of the satellite = to the ground potential. 'However, the thinner the system voltage is, the lower the two-volt installation of the mid-closed oxide layer becomes. Miao & = special, and may be reduced in the future. A new IC device suitable for 3.3 volts will be compatible with peripheral circuits for 5 volts. For example, ^ Personal H ′ is suitable for a 3.3-volt-like card, and it is often used in conjunction with a peripheral device with an applicable name of 5 groups. Therefore, there will be problems between 3.3 volt ic devices and 5 volt old 1C devices. 'Figure 1 is a schematic diagram showing the circuit structure of a conventional I / O buffer 14 suitable for a 33 volt IC. As shown, the 1/0 buffer 14 is coupled to an input buffer 16 and a bonding pad 20 of an IC device (not shown). The I / O buffer 14 is composed of a first circuit 10, a second circuit 12, a

A PMOS transistor P1 and an NMOS transistor N1 are formed. When the I / O buffer 14 is operated in the input mode, both the PMOS transistor P1 and the NMOS transistor N1 enter a non-conducting state. To do this, the first circuit 10 will output a high voltage level signal, such as 3.'3V, to the gate of the PMOS transistor P1, so that the PMOS transistor is turned off. At the same time, the second circuit 12 will output a low-level signal, such as 0V, to the gate of the NMOS transistor N1, so that N * ii〇s

1224426 V. Description of the invention (2) Transistor cut off. However, if the bonding pad 20 receives an input signal of -5V, the gate voltage of the PMOS transistor pi at this time is 3.3V, the terminal voltage is 5v, and the source 3: 3V. Since the gate voltage (3.3V) of the PMOS transistor pi is lower than its drain voltage (jv), this drain voltage will cause the pMOS transistor to enter the reverse conduction mode. Furthermore, 'Generally speaking, since the PMOS transistor is formed on an N, on the substrate] and its drain / source is p-type, it will form between its drain, source and N-well region 19.一 接面 二 极 体 18。 One junction surface diode 18. And the drain of the pM0s transistor is coupled to the bonding pad 20, and now receives an input signal (5V) higher than the system voltage (3.3V), and its substrate is connected to the system voltage of 3.3V : The junction diode 18 will be forward biased, so that an unnecessary large current will be generated between the external 5V voltage source and the internal 3.3V voltage source. In order to solve the above problems, US Pat. No. 6,011,409 discloses an I / O buffer suitable for 3.3V. Figure 2 is a schematic diagram of another conventional 1/0 buffer 30, which is suitable for receiving an input voltage higher than the system voltage. P-type gate controller 32 is used to transmit a first gate control signal VP to the PM0S transistor p3 of the I / O circuit, and the n-type well area control circuit 34 ′ is used to input according to the input on the I / O bonding pad 36 Voltage, adjust the voltage on the floating well area of pM0s transistor Q3, so that unnecessary large current can be avoided. However, in the I / O buffer 30, since the transistors q5 and ... are directly connected to the I / O bonding pad 36, the transistors Q5 and Q6 need to comply with the design specifications of ESD protection. Therefore, the umbilicus occupies a larger wafer area. SUMMARY OF THE INVENTION In view of this, the primary purpose of the present invention is to avoid 丨 / 〇 buffering

1224426 V. Description of the invention (3) ^ When receiving an input voltage that is still below the system voltage, unnecessary leakage will occur! Ϊ The above purpose, the present invention provides a 1/0 buffer, which can avoid belonging current 'and Can reduce the area occupied by the chip. The π / 〇Γ electric 1 Λ purpose, in the 1/0 buffer of the present invention, the input / output and a first 1M two-first " " " " ir—transistor. The i / g circuit has a pure-to-one terminal, and the f / MOS transistor has a floating N-type well region, and the U-side first transistor has a closed electrode for connection. Put-: 塾: = 巧. Two well zone control circuit, based on I ,. Connect to potential. The _pmc) s transistor is a closed-pole control circuit on the type well. It is pulled by ιν and output to the first PM0S transistor to receive; the gate control signal system is-transmission gate-- The inter-electrode control circuit should not be directly connected to the 1/0 bonding pad, so the first M0S transistor does not need a design gate that conforms to ESD protection. "Reduce the area of the chip occupied by the p-type gate control circuit." When the I / O buffer operates in the input mode, if the signal is 5V (higher than 3.3V system voltage), the N-well area control ^ wheel ^ the potential on the N-well area of a PM0S transistor is adjusted to 5V If the voltage on the first stage is changed from 5V to 0V (less than 33 ¥ system voltage), the wheel-end circuit will control the voltage on the first PM0S transistor-type well area to control the system voltage ( 3.3V). Therefore, the 1/0 buffer can be avoided = integrated to the system current. The required leakage 0697-10221TWF (nl); P2003-010; DEMMIS.ptd Page 8 1224426 V. Description of the invention (4) The above-mentioned objects, features, and advantages of the invention can be more clearly understood. A preferred embodiment is given below in conjunction with the accompanying drawings for detailed description. : Embodiment ^ Figure 3 is a schematic diagram of the I / O buffer 100 of the present invention. The I / O buffer 100 / is capable of receiving an input signal higher than the system voltage vcc. In this embodiment, the system voltage is Taking 3.3V as an example, the input signal is switched between 0V and 5 ¥, but it is not intended to limit the present invention. As shown in Figure 3, the 1 / 〇 buffer 100 includes a p-type gate. The control circuit 120, an N-well area control circuit 13 and a 1/0 circuit 14. The 1/0 buffer 100 is 1 / () through an I / O transmission terminal 132 and an IC device (not shown). The bonding pad 110 is connected, and the I / O buffer 100 is controlled by two gate control signals PG and ng from a core circuit (not shown). In this embodiment, the I / O circuit i 40 includes a pM〇s transistor, two NMOS transistors N1, N2, and has a 1/0 transmission end 132, coupled to the 1 / () bonding pad. PMOS transistor Pi has a floating N-type well area VNW, a The drain is used as the I / O transmission terminal of the I / O circuit 140, and a source is coupled to the system voltage VCC. The NMOS transistor N1 has a gate for receiving the voltage from a core circuit (not shown). A first gate control signal rib, and a source ground. The NMOS transistor N2 has a gate coupling system voltage vcc, and a drain coupled to the I / O bonding pad 11 through an I / O transmission terminal 132, and A source is coupled to the terminal of the long transistor N1. * The P-type gate control circuit 120 is coupled between a second gate control signal PG and the PMOS transistor ^ to receive the second closed-pole control. Signal and pass

I224426

° P-type gate control circuit 丨 2 〇 is composed of one pass' and the transmission gate system includes the gate input gate of the transistor to the PMOS transistor PI and a PMOS transistor N6 and PMOS transistor P5 . In the p-type gate control circuit, the PM0S transistor has a gate-dissipated vtw voltage Λ voltage V ?, a source coupled to the floating N-type well area of the transistor and pr, ^, and pole coupling. Connect the gate of the above PMOS transistor. The PM0S transistor = 5 has-the source side is connected to the second interrogation control signal%, and one pole j is connected to the free pole of the PMOS transistor and the drain of the PM0 transistor. m〇s N: There is an interrogator connected to the system voltage vcc, a source is connected to the second interrogator system No. 4 PG, and a drain is connected to the gate of the PMo transistor. The N-well area control circuit 13 is composed of three PMOS transistors p2 and p4 and one NMOS transistor N3. When the 1/0 buffer is operated in the input mode, the well area control circuit 130 adjusts the potential on the floating n-type well area VNW of the PMOS transistor P1 according to the input voltage on the 1/0 bonding pad 110. ”In the N-well area control circuit 130, the NMOS transistor N3 has a drain connected to the I / O bonding pad 110, a gate coupled to the system voltage VCC, and a gate coupled to the gate of the PMOS transistor P4. The PMOS transistor P2 has a floating N-type well region VNW coupled to the PMOS transistor P1, a gate coupled to the voltage VCC, and a drain coupled to 1 via a 1/0 transmission terminal 132. / 〇 bonding pad 110 〇 PM0S transistor P3, has a gate surface connection system voltage vcc,-, the source through the I / O transmission terminal 132 to I / O junction 塾 11〇, and a very light, To the source of the NMOS transistor N3. The PMOS transistor P4 has a non-pole lightly connected system voltage VCC, a source coupled to the floating N-type well region VNW of the PMOS transistor Pi, and a gate coupled to NM. Source of S transistor and pM0s transistor

0697-1022nW (nl); P2003-010; DEMMIS.ptd Page 10 1224426 V. The drain of invention description (6). In this embodiment, the PMOS transistor p is connected to the substrate forming all the PMOS transistor ps to p6. Zone 1 VNW When the I / O buffer 100 is operating in the input mode, the voltage state is turned off, so _s transistor N1 will be cut off: "Ϊ:? Pole = signal PG will be in a high voltage state, so PM0S transistor ρι is also combined ^ If the input signal at the transmission end 132 is 5V (higher than the system voltage), due to the system voltage (3 3v) on the gate of the PMOS transistor P2, ί Ϊί> and the 5V voltage on the pole (connected to 1 / 〇 bonding pad), so the 5V input signal will be transmitted to the well area control circuit 13, that is, the n-well area control circuit 130 will adjust the potential of the PMOS transistor pi-type well area VNW to 5V. In other words, the PM0S transistor p3 will be turned on, and the 5 ° input voltage will be transmitted to the gates of the PMOS transistors P4 and P5 through the PMOS transistor P3 and the NMOS transistor N3, thereby turning on the pM0s transistor. p4, p5. At this time, the i PMOS transistor P6 is also turned on because its gate voltage (connected to the system voltage VCC) is lower than 5V on its source (connected to the floating n-well region VNW).

In addition, 'if the voltage at the transmission end 132 changes from 5V to 0V (less than 3 · 3ν system voltage)', both the PMOS transistor P2 and P3 will be stopped, and the input voltage of 0V will pass through the NMOS transistor N3, It is transmitted to the gate of the PMOS transistor P4 to turn on the PMOS transistor P4. Then, the system voltage (3.3V) will be connected to the N-well area VNW ', that is, the N-well area control circuit 13 will adjust the potential of the N-well area VNW of the pM0s transistor ρ to the system voltage. (3.3V). Therefore, the I / O buffer 100 of the present invention can receive an input voltage signal higher than the system voltage, and can avoid unnecessary leakage current. Furthermore, in the present invention, since

1224426

The f circuit should not be directly connected to the i / g connection, so it is said that the transistor P6 does not need to meet the design specifications of ESD protection. Because of-, it can save the chip area occupied by the P-type gate control circuit. Figure 4 shows another example 2 of the 1/0 buffer of the present invention. The circuit 200 includes a plurality of PM0s drivers, each driver has a transmission gate and corresponding two PM0s transistors, where pM 〇s transistor 〃, all drains of P5 — 0 ~ P5_N are connected to 1 / 〇 bond pad 11 (^ 再

A PMOS transistor (P4--0 ~ P4_N) has a gate system connected to the system J = CC 'a source is coupled to the floating N-type well region VWN, and a drain is coupled to the sub-PMOS transistor The gate of the crystal. Since these pM0s drivers (and PMOS transistors P4-0 ~ P4-N) are not directly connected to 1/0 bonding pads / armors, the transmission gates and PMOS transistors P4-0 ~ P4-N do not need to comply with ESD protection. Tactics norms. Therefore, when using a complex PM0S driver, ... said = product will be more obvious. Although the present invention has been disclosed in the preferred embodiment as above, it does not limit the present invention. Any person skilled in the art can make changes and decorations without departing from the spirit and scope of the invention. Therefore, The protection of the present invention is defined by the scope of the attached patent application. . Worship

0697-10221TWF (nl); P2003 >010; DEMMIS.ptd

1224426 Brief Description of Drawings Figure 1 shows the circuit structure of a conventional I / O buffer suitable for a 3.3V 1C device. Fig. 2 is a schematic diagram of another conventional I / 0 buffer. Fig. 3 is a schematic diagram of an I / 0 buffer according to the present invention. Figure 4 shows another schematic diagram of the I / 0 buffer of the present invention. Explanation of symbols Conventional technology 10: First circuit; 12: Second circuit; 14, 30: I / O buffer; 16 input buffer 321 ·, 18 junction diode; 19 N-type well area 1 20, 36: Bonding pad; VFW: Floating N-type well area; / TN, TN: I / O control signal; PI, Nl, Q1 to Q6: MOS transistor; 3 2: P-type gate control circuit; 34: N-type well Zone control circuit; VP, Gn: Gate control signal. The present invention 140: I / O circuit; 120: P-type gate control circuit; 130: N well area control circuit;

0697-10221TWF (nl); P2003-010; DEMMIS.ptd Page 13 1224426 The diagram briefly illustrates I 0 0: I / 0 buffer; 132: I / O transmission end; VNW: floating N-type well area; II 0: I / 0 bonding pad; VCC: system voltage; PG, NG, PG [0] ~ PG [n]: gate control signals; ΠΠ ~ N4, Pbu P6, P4_0 ~ P4_N, P5_0 ~ P5 —N: MOS transistor. _

0697-10221TW (η 1); P2003-010; DEMMIS.ptd p. 14

Claims (1)

1224426 VI. Application for patent range Voltage 1 round 2 output buffer (1 / ° buffer), which is made up of-system first-"said; ^ (1/0) circuit, including-first-cut s transistor and-: The above 1 / 〇 circuit has a transmission terminal connected to an I / O. The first circular transistor has a -closed pole for receiving-= gate control signals, and the first PM0S j is the transmission wheel terminal. , And a "well area;, with / and pole as an N well area control circuit, coupled to the potential of the N-type well area of the above-mentioned blue transistor; the connection and the mouth to control the last P The gate-type control circuit uses __ and transmits it to the first PMΟς fa # to receive the first gate control signal. The controller includes a _transistor pole; wherein the p-type closed-pole transistor is: The second _s transistor and-the second blue, L: = "signal, a gate is lightly connected to the above system, and the pole is connected to the first P: the source is on the system = description = body PMOS transistor: = 〇8 transistor, with -source lightly connected to the above-mentioned "type", with P: pole two, the above input voltage exceeds the above system voltage 0697-1022nW (nl); P200.3.0i0; DEMMISi ptd Page 15 1224426 6. When applying for a patent, 'the potential of the n-type well area of the PMOS transistor mentioned above, 敕 the potential of the input voltage. Adjust 2 to The above 3 · The input / round out buffer described in item 2 of the scope of the patent application, the above-mentioned input voltage of the N well area control circuit in the bean is low-to: The potential on the _ well area of the: r transistor, to = The potential of the system voltage. ~ 4. The input / output is slow as described in item 丨 of the patent application scope. The above I / O circuit further includes a third NMOS transistor with a source spot and a drain. The drain of the first NMOS transistor is coupled to the above-mentioned connection, 塾 'and a gate respectively to the above-mentioned system voltage. Σ 5. In the input / output slow bean described in item 4 of the scope of patent application The above N-well area control circuit includes: & @ 八一 第 _os transistor 'N-well area with a source coupled to the first pM0 crystal'-gate lightly connected to the system voltage and coupled to the above joint Pad; and-the fifth PMOS transistor, which has a -gate lightly connected to the above system voltage, a source A pole connected to the junction and a drain; a sixth PMOS transistor having a gate-connected to the fifth pM0s electric body's drain, a source connected to the first pM0s The N region of the transistor; and-the fourth NMOS transistor, which has an interrogator lightly connected to the above-mentioned system voltage, and a source and a drain respectively coupled to the above-mentioned pads and the gate of the sixth PMOS transistor. 6 · —One kind of input / output buffer (I / 〇buffer), including ... 1224426 VI. Application scope: a floating N-type well area; a gate controlling a first NMOS transistor with k 'and a source ground; mask = two-sided s transistor with-open pole light connection —System voltage, one :::: connect: to connect 塾 'and -zhou to connect the above-嶋 and the ===. Second, the system voltage is described, and a? 0s transistor 'has a source coupled to the system voltage, and a drain coupled to the 1/0 bonding pad; a second PMOS transistor, which has A drain is coupled to the I / O to the N-type well, an interval pole is connected to the system voltage, and a source is connected to the port to float a third PM0S transistor with a source coupled to the above 丨 / 0 Access pad,-the gate is coupled to the above system voltage, and-the drain. The source of the NMOS transistor; ^ Second promise: The transistor has a free pole coupled to the drain of the third PMMOS transistor, a drain coupled to the system voltage, and a $ Floating N-type well area; f transfer :: transmission gate, which has a fourth facet transistor and a fifth contact, 'wherein the fourth NMOS transistor has a source control signal-gate control signal A gate-pole is coupled to the above-mentioned system voltage, and ~~ on the if: rs transistor, and the fifth _ electric body has-the source consumes the second gate control signal. 697- 1022nW (nl); P2003-010; DEMMIS.ptd page 17 1224426 6. Application scope of the patent The above-mentioned N-well area control circuit, and a drain coupled to the gate of the first PMOS transistor; and a sixth The PMOS transistor has a gate coupled to the system voltage, a drain coupled to the gate of the first PMOS transistor, and a floating N-type well region whose source is coupled to the first PMOS transistor. The floating N-type well region is electrically connected to the substrate forming the first to sixth PMOS transistors. 0697-10221TW (nl); P2003-010; DEMMIS.ptd p.18