EP1148405B1 - Linearer Regler mit niedriger Überspannung im Übergangszustand - Google Patents

Linearer Regler mit niedriger Überspannung im Übergangszustand Download PDF

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Publication number
EP1148405B1
EP1148405B1 EP01108258A EP01108258A EP1148405B1 EP 1148405 B1 EP1148405 B1 EP 1148405B1 EP 01108258 A EP01108258 A EP 01108258A EP 01108258 A EP01108258 A EP 01108258A EP 1148405 B1 EP1148405 B1 EP 1148405B1
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EP
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Prior art keywords
voltage
regulator
output
transistor
switch
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EP01108258A
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English (en)
French (fr)
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EP1148405A1 (de
Inventor
Nicolas Marty
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STMicroelectronics SA
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STMicroelectronics SA
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    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
    • G05F1/10—Regulating voltage or current
    • G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is dc
    • G05F1/56—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices
    • G05F1/565—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices sensing a condition of the system or its load in addition to means responsive to deviations in the output of the system, e.g. current, voltage, power factor
    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
    • G05F1/10—Regulating voltage or current
    • G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is dc
    • G05F1/56—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices
    • G05F1/575—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices characterised by the feedback circuit

Definitions

  • the present invention relates to linear low voltage drop regulators (LDO).
  • Such controllers are the subject of various applications, particularly in the field of mobile telephones for supplying regulated voltage to radio transceiver circuits from a supply voltage supplied by a rechargeable battery.
  • EP 971 280 discloses a regulator comprising a regulating transistor, a differential amplifier which drives the gate of the regulating transistor, and two MOS transistors connected between the gate of the regulating transistor and the ground, which are turned on when the power is turned on. regulator to assist the output of the differential amplifier in charging the gate capacitance of the regulating transistor.
  • EP 892 332 discloses a regulator having an NMOS output transistor driven by a differential amplifier and proposes to improve the efficiency of the feedback circuit of the regulator by supplying the differential amplifier by means of a variable bias current whose intensity is proportional to the variations of the output voltage of the regulator.
  • FIG. 1 represents a conventional regulator 10 whose output delivers a regulated voltage Vout to a load Z.
  • the load Z represents, for example, various radio circuits present in a mobile telephone.
  • the regulator 10 is powered by a voltage Vbat, delivered here by the battery 1 of the mobile phone, and comprises a differential amplifier 2 whose output drives the gate G of a regulation transistor 3 of the PMOS type.
  • the output stage of the amplifier 2 comprises an internal resistor Rg represented in dotted lines, or gate resistance, which determines the gain of the amplifier 2 and the maximum current that it can output.
  • the transistor 3 receives on its source S the voltage Vbat and its drain D, which is connected to the output of the regulator 10, is connected to the anode of a capacitor Cst for filtering and stabilizing the voltage Vout, arranged in parallel with the load Z.
  • the amplifier 2 receives on its negative input a reference voltage Vref and on its positive input a feedback voltage Vfb (feedback), for example a fraction of the voltage Vout brought back to the input of the amplifier 2 via a voltage divider bridge comprising two resistors R1, R2.
  • the amplifier 2 In an application such as the power supply of the radio circuits of a mobile telephone, it is important that the amplifier 2 has as little power consumption as possible in order to preserve the battery life 1.
  • the Grid resistor Rg of the output stage of the amplifier 2 must be chosen high value, for example 100K ⁇ , in order to limit the maximum current flowing in the output stage to the high state.
  • the regulation transistor 3 must have a low RdsON series resistance in the on state (drain-source resistance) in order to be able to deliver a large current without a drastic drop in voltage across its terminals.
  • transistor 3 has typically a width ratio on high gate length, for example a 2 gate width 10 W 5 micrometers for a length L of 0.6 micrometer grid, which represents a ratio W / L of order of 3 ⁇ 10 5 and a very large transistor width. Because of its size and its high W / L ratio, the transistor 3 also has a high gate capacitance Cg, shown in dotted lines in FIG. 1, of the order of 100 to 200 picofarads.
  • FIGS. 2A, 2B, 2C illustrate an overvoltage phenomenon appearing at the output of the regulator of a mobile telephone when the telephone transmits at regular intervals, for example every 4 milliseconds, data bursts or " GSM burst ".
  • FIG. 2A represents the battery voltage Vbat whose nominal value Vbatnom is here 3.5 v.
  • FIG. 2B represents the gate voltage Vg whose value oscillates in the vicinity of a voltage Vgnom equal to Vbat-Vtp when the regulator is stabilized, ie here 2.8 V if the threshold voltage Vtp of the transistor is 0.7
  • FIG. 2C represents the output voltage Vout whose nominal value Voutnom is here 2.8 V when the regulator is stabilized.
  • the radio circuits of the phone come into service to issue a salvo.
  • the current consumed is very important and the voltage Vbat drops sharply below the nominal value Voutnom (FIG 2A) due to the internal resistance of the battery.
  • Amplifier 2 is unbalanced, voltage Vg goes to 0 (FIG 2B), gate capacitance C g is fully discharged and transistor 3 is on.
  • the regulator 10 thus operates in follower mode, the output voltage Vout being substantially equal to the voltage Vbat (FIG 2C).
  • the burst emission is complete and the consumed current decreases.
  • the battery voltage Vbat rises rapidly (FIG 2A), for example in 1 microsecond, to its nominal value Vbatnom.
  • the output voltage Vout follows the voltage Vbat up to to reach, at a time t3, its nominal value Voutnom.
  • the amplifier 2 releases its output from the low state to the high state and the gate of the transistor 3 is connected to the voltage Vbat via the gate resistor Rg, which should normally be cause the transistor 3 to be blocked immediately.
  • the gate voltage Vg only increases very slowly because of the high value of the gate resistance Rg, which limits the delivered current, and the high value of the grid capacity Cg.
  • the output stage of the amplifier 2 is therefore unable to instantly charge the gate capacitance Cg and block the transistor 3.
  • the latter continues to be on and the voltage Vout continues to monitor the voltage Vbat.
  • a peak of voltage OS can thus be seen at the output of the regulator. This peak voltage can disappear only from a time t4, when the gate voltage Vg crosses the value Vbat-Vtp ensuring the blocking of the transistor 3, and provided that the load Z consumes current.
  • the present invention aims to overcome this disadvantage.
  • an object of the present invention is to eliminate, or at least limit, the transient overvoltage effect at the output of a voltage regulator without it being necessary to modify the structure of the transistor. regulation to decrease its gate capacity.
  • Another object of the present invention is also to eliminate or limit the transient overvoltage effect without it being necessary to increase the maximum current that can be delivered by the output of the regulation amplifier.
  • control means of the switch are arranged to compare the output voltage of the regulator or a voltage proportional to the output voltage with the reference voltage.
  • control means of the switch comprise a comparator whose output delivers a signal for closing the switch, the comparator receiving on one input the reference voltage and on another input the output voltage or a voltage proportional to the output voltage.
  • the comparator has a switching hysteresis chosen so that the switch is reopened when the output voltage becomes lower than a second threshold lower than the first threshold and greater than the nominal value of the output voltage.
  • the regulation transistor is a PMOS transistor and the blocking potential is the supply voltage.
  • the amplifier comprises an output stage having a gate resistance of value that is too great for the current passing through the gate resistor alone can provide rapid blocking of the regulating transistor when the supply voltage increases rapidly.
  • the switch is a PMOS transistor having a drain-source resistance in the on-state that is much lower than the gate resistance of the output stage of the amplifier.
  • the present invention also relates to a mobile phone comprising a battery and radio circuits powered by the battery via a voltage regulator according to the invention.
  • the present invention also provides a method for preventing or limiting the occurrence of an overvoltage at the output of a voltage regulator when the regulator supply voltage is rapidly increasing according to claim 9.
  • the method comprises a step of reopening the switch when the output voltage of the regulator becomes lower than a second threshold between the nominal value of the output voltage and the first threshold.
  • FIG. 3 represents a regulator 20 according to the invention, supplied here by a voltage Vbat supplied by the anode of a battery 1.
  • the regulator 20 comprises, like that of FIG. 1, a differential amplifier 2 whose output controls the gate of FIG. a regulation transistor 3 of PMOS type.
  • the drain D of the transistor 3 is connected at the output of the regulator 20 to a stabilization capacitor Cst arranged in parallel with a load Z.
  • the output voltage Vout is brought back to the positive input of the amplifier 2 by means of a divider bridge comprising two resistors R1, R2.
  • the resistor R2 here consists of two resistors R21, R22 in series.
  • the reference voltage Vref applied to the negative input of the amplifier 2 is for example a so-called band gap voltage having a good stability in temperature function, generated by means of PN junction diodes and current mirrors.
  • the voltage Vref is thus independent of the voltage Vbat, provided, of course, that it is chosen to be lower than the lowest value of the voltage Vbat.
  • the operation of the regulator 20 in steady state is in accordance with the conventional regulator.
  • the regulator 20 comprises an anti-surge switch 4 connected between the anode of the battery 1 and the gate G of the transistor 3.
  • the switch 4 is here a transistor of the PMOS type whose source S receives the voltage Vbat and whose drain D is connected to the gate G of the transistor 3.
  • the ratio W / L length to gate width of the transistor 4 is chosen so that its series resistance RdsON in the on state is rather low, preferably very low. less than the gate resistance Rg of the output stage of the amplifier 2.
  • the gate G of the transistor 4 is driven by a signal Vos delivered by the output of a comparator 5.
  • the comparator 5 is powered by the voltage Vbat and receives on its positive input the voltage Vref and on its input negative a voltage VA.
  • the resistor R21 is small in front of the resistor R22 so that the voltage VA is very close to the voltage Vfb.
  • R 21 x R two
  • R 22 ( 1 - x ) R two with "x" between 0 and 1 and close to 0, x being for example equal to 0.05.
  • the comparator 5 and the anti-overvoltage transistor 4 become active transiently, when the voltage Vbat rises suddenly after falling sharply due to a peak current consumption, for example in the situation exposed to the preamble, that is, ie after the transmission of a data burst by the radio circuit of a mobile phone.
  • a peak current consumption for example in the situation exposed to the preamble, that is, ie after the transmission of a data burst by the radio circuit of a mobile phone.
  • FIGS. 2A, 4A, 4B, 4C which respectively represent the profile of the battery voltage Vbat, the voltage Vg delivered by the amplifier 2 on the gate of the regulation transistor 3, the voltage Vout and control voltage Vos of the surge protector 4.
  • the regulator 20 During the fall of the voltage Vbat, from the time t1, the regulator 20 is unbalanced and goes into follower mode, the output voltage Vout copying the voltage Vbat. During this period, the voltage VA continues to drop and thus remains lower than the voltage Vref, the signal Vos at the output of the comparator remaining at 1 (Vbat).
  • the voltage Vbat rises suddenly and the voltage Vout follows the voltage Vbat.
  • the voltage Vout reaches the control point Voutnom and the amplifier 2 switches its output high.
  • the amplifier is, by design, unable to deliver the current required to immediately load the gate capacitance Cg of the transistor 3.
  • the output voltage Vout therefore continues to rise after the instant t3 and follow the voltage Vbat, the transistor 3 remaining passing.
  • the voltage Vout reaches a threshold value Vout1 such that the voltage VA at the input of the comparator 5 becomes equal to Vref.
  • the output of the comparator 5 switches to 0 (FIG 4C) and the surge transistor 4 turns on. Since the RdsON series resistance in the on state of transistor 4 is low, the gate G of the regulation transistor 3 receives the current required to charge the gate capacitance Cg and the transistor 3 blocks almost instantaneously.
  • the voltage Vout stops rising and goes back down to its nominal value Voutnom (Fig. 4B). According to the invention, the appearance of the voltage peak OS represented in FIG. 2C, characteristic of a conventional regulator, is thus neutralized, by helping the amplifier 2 to block the regulation transistor 3 by means of the transistor 4.
  • the threshold Vout1 tripping transistor 4 can be defined by means of the parameter x mentioned above, which is a function of the resistors R1, R2, R21 and R22.
  • V out ( R 1 + R two ) V AT / ( 1 - x ) R two replacing VA by Vref and Vout by Vout1 in relation (9)
  • V out 1 ( R 1 + R two ) V ref / ( 1 - x ) R two
  • V out 1 V outnom / ( 1 - x ) the term x being small, it comes: ( 12 ) V out 1 ⁇ V outnom + x V outnom is : ( 13 ) V out 1 ⁇ V outnom +
  • the parasitic overvoltage phenomenon is limited in this example to 0.035 V with the present invention, a negligible voltage peak in the eyes the nominal value of the output voltage.
  • the regulator 20 may comprise a direct feedback of the voltage Vout on the input of the amplifier 2.
  • the comparator 5 it is advantageous in practice for the comparator 5 to have a switching hysteresis in order to avoid any instability of the voltage Vout in the vicinity of the threshold Vout1.
  • the output of the comparator 5 goes to 1 when the voltage VA reaches a value Vref 'substantially less than Vref.
  • This value Vref ' corresponds, at the output of the regulator 20, to a voltage Vout2 between Voutnom and Vout1 ( Figures 4B and 4C).
  • FIG. 5 represents, by way of example, a low consumption amplifier structure 2 having a limited output current.
  • the amplifier comprises as input a differential stage represented here in the form of a block 30, receiving the voltage Vref and Vfb.
  • the differential stage 30 is biased by a current generator 31 which limits its consumption.
  • the output of the differential stage 30 drives the gate of a NMOS-type transistor 32, connected between the output node of the amplifier 2 and the ground.
  • the transistor 32 is biased on its drain D by a current generator 33 limiting the consumption of the output stage in the low state.
  • the gate resistor Rg also in amplifier 2 is the gate resistor Rg, connected to the output node of the amplifier and receiving at its other end the voltage Vbat.
  • the transistor 32 pulls the output of the amplifier to ground and the resistor Rg pulls the output to the supply voltage Vbat according to the value of the signal delivered by the differential stage 30.
  • the anti-surge transistor 4 can be modeled as a perfect switch 4-1 in series with a resistor 4-2, which here is the RdsON series resistor of the transistor.
  • a resistor 4-2 which here is the RdsON series resistor of the transistor.
  • an external resistor may optionally be added to the switch 4 to limit the load current of the gate capacitance Cg while maintaining an acceptable blocking time transient.
  • the regulator according to the invention is of course capable of various applications other than that set forth in the preamble, and various alternative embodiments and improvements.
  • the divider bridge formed by the resistors R21, R22 is eliminated and the voltage Vfb is directly applied to an input of the comparator 5.
  • the comparator 5 is a threshold comparator ⁇ . The comparator output does not pass at 0 when the voltage Vfb becomes greater than or equal to Vref + ⁇ .
  • the surge switch according to the invention must receive a potential ensuring the blocking of the control transistor.
  • the teaching set forth in the present application thus applies to the production of a regulator having an NMOS-type control transistor, for the resolution of the inverse problem, namely the discharge of the gate capacitance of the regulation transistor at the blocking of it when the maximum current entering the output stage of the amplifier when it goes to 0 is limited.
  • This potential is, for example, ground with an NMOS control transistor.

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Electromagnetism (AREA)
  • General Physics & Mathematics (AREA)
  • Radar, Positioning & Navigation (AREA)
  • Automation & Control Theory (AREA)
  • Continuous-Control Power Sources That Use Transistors (AREA)

Claims (12)

  1. Spannungsregler (20) mit einem Serien-niederohmigen MOS-Regelungstransistor (3), von dem eine erste Klemme (S) eine Versorgungsspannung (Vbat) empfängt und von dem die andere Klemme (D) an den Ausgang des Reglers angeschlossen ist, und mit einem Verstärker (2), von dem der Ausgang das Gitter (G) des MOS-Regelungstransistors (3) steuert, und dies in Abhängigkeit von der Abweichung zwischen einer Bezugsspannung (Vref) und einer Gegenkopplungsspannung (Vfb), die mit der Ausgangsspannung (Vout) verbunden ist, dadurch gekennzeichnet, dass er Folgendes umfasst:
    - einen Schalter (4), von dem eine erste Klemme (D) an das Gitter des MOS-Regelungstransistors (3) angeschlossen ist und die andere Klemme (S) auf die Versorgungsspannung (Vbat) gebracht wird, die ein Blockierpotential (Vbat) des Regelungstransistors (3) bildet, und
    - Steuermittel (5, R1, R2, R21, R22) des Schalters (4), die den Ausgang des Reglers überwachen, die angeordnet sind, um den Schalter (4) zu schließen, wenn die Ausgangsspannung (Vout) des Reglers größer als ein erster Schwellenwert (Vout1) über dem Nennwert (Voutnom) der Ausgangsspannung ist.
  2. Regler nach Anspruch 1, in dem die Steuermittel (5, R1, R2, R21, R22) des Schalters (4) angeordnet sind, um die Ausgangsspannung des Reglers (Vout) oder eine Spannung (VA) proportional zur Ausgangsspannung mit der Bezugsspannung (Vref) zu vergleichen.
  3. Regler nach Anspruch 2, in dem die Steuermittel des Schalters einen Komparator (5) umfassen, von dem der Ausgang ein Schließsignal (Vos) des Schalters liefert, wobei der Komparator an einem Eingang die Bezugsspannung (Vref) und an einem anderen Eingang die Ausgangsspannung (Vout) oder eine Spannung (VA) proportional zur Ausgangsspannung empfängt.
  4. Regler nach Anspruch 3, in dem der Komparator (5) eine Schalthysterese aufweist, die derart gewählt ist, dass der Schalter (4) wieder offen ist, wenn die Ausgangsspannung (Vout) kleiner als ein zweiter Schwellenwert (Vout2) unter einem ersten Schwellenwert (Vout1) und über dem Nennwert (Voutnom) der Ausgangsspannung wird.
  5. Regler nach einem der Ansprüche 1 bis 4, im dem der Regelungstransistor (3) ein PMOS-Transistor ist und das Blockierpotential die Versorgungsspannung (Vbat) ist.
  6. Regler nach Anspruch 5, in dem der Verstärker (2) eine Ausgangsstufe umfasst, die einen Gitterwiderstand (Rg) aufweist, deren Wert zu hoch ist, damit der Strom, der durch den Gitterwiderstand (Rg) fließt, allein eine schnelle Blockierung des Regelungstransistors (3) gewährleisten kann, wenn die Versorgungsspannung (Vbat) schnell steigt.
  7. Regler nach Anspruch 6, in dem der Schalter (4) ein PMOS-Transistor ist, dessen Drain-Sourcewiderstand (RdsON) im Flussbereich viel niedriger als der Gitterwiderstand (Rg) der Ausgangsstufe des Verstärkers ist.
  8. Mobiltelefon mit einer Batterie (1) und mit Funksprechkreisen, die von der Batterie durch einen Spannungsregler (20) nach einem der Ansprüche 1 bis 7 versorgt werden.
  9. Verfahren, um das Auftreten einer Überspannung am Ausgang eines Spannungsreglers (20) nach einem der Ansprüche 1 bis 7 zu verhindern oder zu begrenzen, wenn die Versorgungsspannung (Vbat) des Reglers schnell steigt, wobei der Regler (20) einen MOS-Regelungstransistor (3) mit hoher Gitterkapazität (Cg) aufweist, von dem das Gitter durch einen Verstärker (2) gesteuert wird, der einen Strom liefert, der allein ungenügend ist, um eine schnelle Blockierung des Regelungstransistors (3) zu gewährleisten, wobei das Verfahren dadurch gekennzeichnet ist, dass es einen Schritt umfasst, der darin besteht, einen Schalter (4) vorzusehen, der zwischen dem Gitter des Regelungstransistors (3) und einem Blockierpotential (Vbat) des Regelungstransistors angeschlossen ist, und einen Schritt, der darin besteht, den Schalter derart zu schließen, wenn die Ausgangsspannung des Reglers größer als ein erster Schwellenwert (Vout1) über dem Nennwert (Voutnom) der Ausgangsspannung wird, dass der Verstärker (2) vorübergehend unterstützt wird, den Regelungstransistor (3) zu blockieren.
  10. Verfahren nach Anspruch 9, das einen Schritt umfasst, der darin besteht, den Schalter (4) wieder zu öffnen, wenn die Ausgangsspannung des Reglers kleiner als ein zweiter Schwellenwert (Vout2) zwischen dem Nennwert (Voutnom) der Ausgangsspannung und dem ersten Schwellenwert (vout1) wird.
  11. Verfahren nach einem der Ansprüche 9 und 10, in dem der Schalter (4) durch einen Komparator (5) gesteuert wird, der am Eingang eine Bezugsspannung (Vref) des Reglers und eine Spannung (VA) proportional zur Ausgangsspannung (Vout) des Reglers empfängt.
  12. Verfahren nach einem der Ansprüche 9 bis 11, im dem der Regelungstransistor (3) ein PMOS-Transistor ist und das Blockierpotential die Versorgungsspannung (Vbat) ist.
EP01108258A 2000-04-12 2001-03-31 Linearer Regler mit niedriger Überspannung im Übergangszustand Expired - Lifetime EP1148405B1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
FR0004673 2000-04-12
FR0004673A FR2807847B1 (fr) 2000-04-12 2000-04-12 Regulateur lineaire a faible surtension en regime transitoire

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EP1148405A1 EP1148405A1 (de) 2001-10-24
EP1148405B1 true EP1148405B1 (de) 2006-06-07

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US (1) US6388433B2 (de)
EP (1) EP1148405B1 (de)
DE (1) DE60120270D1 (de)
FR (1) FR2807847B1 (de)

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EP1148405A1 (de) 2001-10-24
US20010050546A1 (en) 2001-12-13
DE60120270D1 (de) 2006-07-20
FR2807847B1 (fr) 2002-11-22
US6388433B2 (en) 2002-05-14
FR2807847A1 (fr) 2001-10-19

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