EP1231529B1 - Referenzspannungsgeneratoreinrichtung mit hoher Genauigkeit - Google Patents

Referenzspannungsgeneratoreinrichtung mit hoher Genauigkeit Download PDF

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Publication number
EP1231529B1
EP1231529B1 EP02290301A EP02290301A EP1231529B1 EP 1231529 B1 EP1231529 B1 EP 1231529B1 EP 02290301 A EP02290301 A EP 02290301A EP 02290301 A EP02290301 A EP 02290301A EP 1231529 B1 EP1231529 B1 EP 1231529B1
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EP
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Prior art keywords
voltage
circuit
reference voltage
initialization
transistor
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EP02290301A
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English (en)
French (fr)
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EP1231529A1 (de
Inventor
Philippe Messager
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Microchip Technology Nantes
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Atmel Nantes SA
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    • GPHYSICS
    • G05CONTROLLING; REGULATING
    • G05FSYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F1/00Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
    • G05F1/10Regulating voltage or current
    • G05F1/46Regulating voltage or current wherein the variable actually regulated by the final control device is dc
    • G05F1/56Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices
    • G05F1/565Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices sensing a condition of the system or its load in addition to means responsive to deviations in the output of the system, e.g. current, voltage, power factor
    • GPHYSICS
    • G05CONTROLLING; REGULATING
    • G05FSYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F1/00Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
    • G05F1/10Regulating voltage or current
    • G05F1/46Regulating voltage or current wherein the variable actually regulated by the final control device is dc
    • G05F1/56Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices
    • G05F1/575Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices characterised by the feedback circuit

Definitions

  • the present invention relates to a device generating a precise reference voltage, more particularly intended to produce, from an external supply potential capable of varying between a minimum value and a maximum value, a precise reference output voltage. which is stable regardless of the operating temperature of the generator and the value of the external supply potential.
  • Such generating devices are particularly suitable for providing a stable reference potential to an electronic circuit, such as for example an analog-digital converter, so as to make the operation of the latter more stable and more precise, while reducing the consumption of these devices. generators.
  • the invention relates more particularly to those comprising a semiconductor circuit 1, more commonly referred to as a "band-gap" circuit in English language, this type of circuit making it possible to generate a reference voltage, hereinafter referred to as semiconductor circuit 1, and at least one voltage multiplier circuit 2 cascaded with this semiconductor circuit, said voltage multiplier circuit being adapted to supply, from the reference voltage delivered by the semiconductor circuit, the reference output voltage stable.
  • a semiconductor circuit 1 more commonly referred to as a "band-gap" circuit in English language
  • this type of circuit making it possible to generate a reference voltage, hereinafter referred to as semiconductor circuit 1
  • at least one voltage multiplier circuit 2 cascaded with this semiconductor circuit said voltage multiplier circuit being adapted to supply, from the reference voltage delivered by the semiconductor circuit, the reference output voltage stable.
  • FIG. 1a Such a generating device of the prior art is represented in FIG. 1a.
  • semiconductor circuits of this type require, before any use, a pre-adjustment so that the reference potential delivered by the latter is as stable and accurate as possible regardless of any variations in the external supply voltage and temperature.
  • the voltage multiplier circuit 2 comprises a differential amplifier OPA receiving on its negative terminal the voltage reference Vref as a reference voltage and a resistive reaction circuit R ' 1 , R' 2 , R'3 with a decoupling capacitor C 2 comprising a regulation transistor Tr connected between the supply voltage Vcc and the resistive bridge reducing partly the output voltage V OUT , reference voltage deemed accurate, on the positive terminal of the operational amplifier OPA.
  • the gate electrode of the regulation transistor Tr is connected and controlled by the output of the differential amplifier OPA, the junction point between the regulation transistor Tr and the resistive bridge constituting the output terminal delivering the reference voltage deemed accurate.
  • the regulation transistor Tr plays the role of a voltage-controlled resistor and the multiplier circuit 2 makes it possible to slave the output voltage to a value greater than the reference voltage Vref, but less than the value of the supply voltage.
  • Vcc as a function of the relative values of the resistors R ' 1 , R' 2 and R 3 , the resistance value of the regulation transistor Tr being low.
  • the variations of the supply voltage, and the reference voltage Vref are amplified accordingly, which affects the real accuracy of the assembly.
  • these reference generators have a high consumption especially when the external supply potential Vcc is at its maximum value.
  • US-A-6,046,577 discloses a low voltage voltage regulator of waste.
  • the object of the present invention is in particular to remedy these drawbacks by improving the precision and the stability of the precise reference generator devices, independently of their relative adjustment in external supply voltage, respectively in operating temperature, while benefiting from a lesser consumption.
  • the present invention proposes a device generating a precise reference voltage according to claim 1.
  • the initialization circuit comprises a generator circuit of a control pulse of determined duration, this control pulse, applied to the gate electrode of the control transistor controlling the control transistor in the fully conductive state, for the duration initializing. This makes it possible to impose on the output terminal of the generator device of a precise reference voltage a voltage equal to the voltage for setting the supply voltage during the initialization period.
  • the device generating a precise reference voltage comprises a semiconductor circuit 1 of the " band-gap " type which is cascaded with a circuit voltage multiplier 2.
  • the semiconductor circuit 1 is constituted by a "band-gap" type circuit as represented in FIG. 1b generating a reference voltage Vref.
  • FIG. 1b An example of such a semiconductor circuit generating a reference voltage is shown schematically in Figure 1b above when this circuit is powered by a supply voltage Vcc.
  • the latter is made in the form of an integrated circuit. It is widely used in the prior art and provides a relatively stable reference voltage Vref.
  • This circuit is known as a "bandgap reference voltage source", the word bandgap being a word of English origin designating the energy of passage of the electrons from the conduction band to the valence band in the semiconductor driver used. This energy depends, in a known manner, on the temperature. Reference sources of this type use the dependence of certain circuit parameters as a function of this energy and therefore of the temperature, to achieve, by appropriate compensations, an approximately stable reference voltage Vref.
  • the circuit of FIG. 1b essentially comprises two diode-mounted bipolar transistors T 1 , T 2 , three resistors R 1 , R 2 , R 3 , and an operational amplifier OPA.
  • the amplifier OPA which is powered by the external supply voltage Vcc, comprises an inverting input connected to the collector of the bipolar transistor T ' 2 , and a non-inverting input connected to the resistor R 1 which is itself connected to the collector of the bipolar transistor T ' 1 .
  • the resistor R 3 allows the establishment of the circuit during a rise of the external supply voltage Vcc.
  • the reference voltage Vref stable according the temperature and the external supply voltage Vcc, is provided at the output S of the circuit.
  • V ref V b e two + two ⁇ R two R 1 ln ( I two I 1 ) V T
  • V be2 and V T are respectively the emitter base voltage and the threshold voltage of the transistor T ' 2
  • I 1 and I 2 the currents flowing respectively in the resistors R 1 and R 2 , In denoting the natural logarithm.
  • the amplitude value of the reference voltage Vref then obtained at the output is of the order of 1.25V.
  • This semiconductor circuit 1 is subjected, in a manner analogous to the prior art bandgap reference voltage sources, to a prior adjustment.
  • the semiconductor circuit 1 is set so that Vref varies from 2 mV in temperature and 30 mV in voltage.
  • the voltage multiplier circuit 2 comprises a differential amplifier 20 consisting of an operational amplifier OP 1 which is mounted as a voltage multiplier, the voltage multiplier circuit 2 operating as a multiplier and a voltage regulator .
  • This differential amplifier 20 has an input not inverter + which is connected directly to the output S of the semiconductor circuit 1, an output S 1 which delivers a predetermined output voltage V OUT , constituting the desired precise reference voltage.
  • This output S 1 is connected by a galvanic connection 3 to the power supply input IN of the semiconductor circuit 1 generating the reference voltage Vref.
  • a capacitor C 1 smoothes the reference voltage Vref and a capacitor C 3 smoothes the output voltage V OUT .
  • a resistive feedback circuit which comprises a regulation transistor Tr connected between the supply voltage Vcc and a resistive bridge R ' 1 , R' 2 , R ' 3 reducing, in part, the precise reference voltage, output voltage V OUT delivered by the output terminal S 1 , to the non-inverting terminal + of the differential amplifier 20, operational amplifier OPA.
  • the gate electrode of the regulation transistor Tr is connected and controlled by the output of the differential amplifier 20.
  • the junction point between the regulation transistor Tr and the resistive bridge constitutes for the precise reference voltage generating device the terminal output S 1 delivering the precise reference voltage V OUT .
  • the reference voltage Vref constitutes a set value.
  • the regulation transistor Tr plays the role of an adjustable voltage-controlled resistor by the output of the differential amplifier 20.
  • a decoupling capacitor C 2 makes it possible to ensure the stability of the servocontrol by introducing a margin of suitable phase under transient conditions.
  • an initialization circuit 4 is connected to the gate electrode of the regulation transistor Tr.
  • This circuit 4 allows, in a transient state, during initialization, when power is applied to the supply voltage Vcc of the device.
  • precise reference generator, object of the invention to replace the precise reference voltage Vref, not yet established by the semiconductor circuit 1 of the "band-gap" type , this type of circuit having a voltage operating threshold not insignificant power supply, by the voltage of establishment of the supply voltage Vcc.
  • Such a procedure makes it possible, on the one hand, in a transient state, during initialization, to feed the semiconductor circuit 1 from the voltage for setting the supply voltage Vcc, and, because of this, the increasing nature of this supply voltage, to cause, according to a cumulative phenomenon, the corresponding rise in the output voltage V OUT delivered by the output terminal S 1 and therefore that of the supply voltage of the circuit to semi -conductors 1 because of the presence of the link
  • This operating mode allows, on the other hand, in steady state, to deliver on the output terminal S 1 , the precise reference voltage sought, the reference voltage Vref having reached its nominal value, and to supply the semiconductor circuit 1 from the nominal value of the reference voltage Vref.
  • Vref 1.25V
  • R'1 0.955M ⁇
  • R'2 0.16M ⁇
  • the differential amplifier 20 which is thus cascaded with the semiconductor circuit 1 generator of the reference voltage Vref and which, as a result, receives as its reference voltage the reference voltage Vref, makes it possible to deliver a voltage of regulated V OUT output constituting the precise reference voltage sought regardless of the operating temperature and the external supply voltage Vcc.
  • a fine-tuning of the semiconductor circuit 1 may be chosen preferentially, since the voltage regulation as a function of the supply voltage is also provided by the multiplier and voltage regulator circuit 2.
  • the series connection of the semiconductor circuit 1 and the voltage multiplier circuit 2 makes it possible to produce a device generating a precise reference voltage which is particularly suitable for being associated with a load, such as an electronic circuit, of digital or analog type, requiring a very stable voltage reference for a comparison of ADC digital analog conversion for example and a controlled operating stability. This is so, for example, analog converters digital.
  • the advantage of such an assembly resides in fact in the loopback, by the galvanic connection 3, the voltage multiplier circuit 2 on the supply input of the semiconductor circuit 1 generator of the reference voltage Vref which allows advantageously to substantially reduce the adjustment of the voltage accuracy of the latter but to increase the accuracy of the temperature adjustment range. It is possible to obtain a high precision of the reference voltage Vref of the semiconductor circuit 1 and therefore of the output voltage V OUT . Indeed, when the semiconductor circuit 1 generator of the reference voltage Vref and the multiplier circuit 2 have each reached their steady state, in steady state, the regulation transistor Tr is adjusted so that the output voltage V OUT is fed back to the power supply input IN of the semiconductor circuit 1, which is then powered from the stable supply voltage constituted by the precise reference voltage.
  • the initialization circuit 4 may be formed by a generator of a fixed duration control pulse.
  • the control pulse CP applied to the gate electrode of the regulation transistor Tr makes it possible to bring this transistor to the fully conductive state during the initialization period and thus to impose on the terminal output S 1 of the specific voltage generator device object of the invention, and on the supply terminal of the semiconductor circuit 1 generator of the reference voltage Vref, a voltage substantially equal to the voltage setting the supply voltage.
  • the generator 4 may be constituted by a monostable type circuit of adjustable duration from a control voltage VD.
  • the duration of the control pulse CP can be adjusted experimentally for a given circuit group.
  • the generator 4 is of course supplied by the supply voltage Vcc, which is established more rapidly than the reference voltage Vref delivered by the semiconductor circuit 1.
  • the circuit 4 generating a determined duration control pulse is constituted by a bistable type circuit, synchronized to a start time and an end time of the initialization time.
  • the initialization time is defined by the beginning, respectively the end of the establishment of the reference voltage Vref delivered by the semiconductor circuit 1.
  • FIG. 3 A specific embodiment of the preferred embodiment of the initialization circuit 4 is shown in FIG. 3.
  • the same references represent the same elements as in the context of FIG.
  • the synchronized bistable type circuit comprises a first and a second circuit for detecting the simultaneous presence of a reference voltage setting voltage Vref, delivered by the semiconductor circuit 1, respectively of the precise reference voltage V OUT present at the output terminal S 1 .
  • the first and second detection circuits are each formed by an N-MOS transistor T 2 , T 3 connected in cascade via a resistor R ' 4 between the supply voltage Vcc and the ground voltage V GND .
  • the gate of the transistor T 2 is connected at the output S of the semiconductor circuit 1 to detect the presence of the voltage for setting the reference voltage Vref.
  • the gate of the transistor T 3 is connected to a point representative of the output voltage V OUT in order to detect the presence of the voltage for establishing the precise reference voltage.
  • This representative point may, for example, be constituted by the connection point of the resistive bridge, the junction point between R ' 2 and R' 3 for example.
  • a nonlinear switching circuit NL is provided. This circuit is formed by two cascaded inverters INV 1 and INV 2 .
  • the non-linear circuit controls an initialization control transistor TN 4 , which is connected between the gate of the regulation transistor Tr and the reference voltage V GND .
  • the gate electrode of the initialization control transistor is directly connected to the output of the second inverter INV 2 forming the nonlinear circuit NL.
  • the non-linear switching circuit NL receives as input the voltage detected by the first and the second detection circuit T 2 , T 3 , and makes it possible to compare this detected voltage representative of a reference voltage or a reference voltage respectively. accurate less than a threshold value. This threshold value is representative of the initialization time.
  • the non-linear switching circuit NL delivers a first control voltage as long as the detected voltage is greater than the threshold value and a second control voltage otherwise, to the initialisation control transistor T 4 , which delivers in turn switching the control pulse CP to regulation transistor Tr.
  • the device generating a precise voltage according to the present invention operates in the following manner.
  • the semiconductor circuit 1 generator of the reference voltage Vref When powering up, the semiconductor circuit 1 generator of the reference voltage Vref outputs a first potential close to 0V, Vref ⁇ 1V, and the differential amplifier 20 outputs a first near output potential. 0V, V OUT ⁇ 2V, the transistors T 2 and T 3 are then blocked.
  • the input of the inverter INV 1 then receives a voltage equal to V CC which is supplied to the source of the transistor T 3 by R ' 4 .
  • This voltage is transmitted via the two inverters INV 1 and INV 2 constituting the nonlinear switching circuit NL on the gate of the transistor T 4 which turns on.
  • the gate of the regulation transistor Tr is then biased by the drain / source voltage of the transistor 4, which has a low level, the regulation transistor Tr becoming in turn passing.
  • the input of the inverter INV 1 then receives a voltage of zero value which is supplied on the source of the transistor T 3 . This voltage is transmitted via the non-linear switching circuit NL to the gate of transistor T 4 which becomes blocked.
  • the gate of the regulation transistor Tr is then biased by the output voltage V SI1 delivered by the differential amplifier 20, and the regulation transistor Tr then behaves as a resistor which follows the evolution of V SI1 .
  • the output voltage constituting the precise reference voltage is now delivered to the power supply input IN of the semiconductor circuit 1.
  • the semiconductor circuit 1 generator of the reference voltage is intrinsically stable and accurate in voltage, without which it is necessary to make a specific adjustment in voltage, which then makes it possible to choose a precise adjustment in temperature, rather than in tension. Measurements have shown that the voltage accuracy of the semiconductor circuit 1 generator of the reference voltage was of the order of 2mV. Such accuracy and stability are advantageously reflected in the output voltage V OUT output OUT and constituting the precise reference voltage in the sense of the present invention.

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Claims (4)

  1. Generatoreinrichtung einer Präzisionsreferenzspannung (Vout), die eine Halbleiterschaltung (1), die eine zweite Referenzspannung (Vref) generiert, und eine Spannungsvervielfachungsschaltung (2) umfasst, die von einer Versorgungsspannung (Vcc) aus gespeist werden, welche Spannungsvervielfachungsschaltung (2) mindestens einen Differenzial-Vervielfacher (20) umfasst, der an seinem negativen Pol die zweite Referenzspannung (Vref) als Sollspannung aufnimmt, sowie einen resistiven Rückkopplungskreis, der einen Regeltransistor (Tr) umfasst, der zwischen die Versorgungsspannung (Vcc) und eine Widerstandsbrücke aus ohmschen Widerständen (C2, R'1) geschaltet ist, der die Präzisionsreferenzspannung (Vout) teilweise zum positiven Pol des Differenzial-Vervielfachers (20) zurückleitet, wobei die Steuerelektrode des Regeltransistors (Tr) an den Ausgang des Differenzial-Vervielfachers (20) gelegt ist und von diesem gesteuert wird und der Verbindungspunkt zwischen dem Regeltransistor (20) und der Widerstandsbrücke für diese Generatoreinrichtung eine Ausgangsklemme (S1) darstellt, welche die Präzisionsreferenzspannung (Vout) liefert, dadurch gekennzeichnet, dass sie ferner umfasst:
    - eine galvanische Verbindung, die die Ausgangsklemme (S1), die die Präzisionsreferenzspannung (Vout) liefert, an den Speiseeingang (IN) der Halbleiterschaltung (1) legt;
    - eine Initialisierungsschaltung (4), die an die Steuerelektrode des Regeltransistors (Tr) gelegt ist und Mittel zum Unterspannungsetzen der Generatoreinrichtung einer Präzisionsreferenzspannung bei der Initialisierung im Übergangsbetrieb auf Versorgungsspannung (Vcc) umfasst, um die besagte Präzisionsreferenzspannung (Vout) durch die Spannung zu ersetzen, mit der die Versorgungsspannung aufgebaut wird, wobei einerseits bei der Initialisierung im Übergangsbetrieb die Halbleiterschaltung von der Spannung aus gespeist wird, mit der die Versorgungsspannung aufgebaut wird, und andererseits im Dauerbetrieb die Ausgangsklemme (S) der Generatoreinrichtung mit der Präzisionsreferenzspannung (Vout) gespeist wird, um die Halbleiterschaltung (1) von dieser Präzisionsreferenzspannung (Vout) aus zu speisen.
  2. Vorrichtung nach Anspruch 1, dadurch gekennzeichnet, dass die Initialisierungsschaltung (4) eine Schaltung zur Erzeugung eines Steuerimpulses bestimmter Dauer umfasst, wobei der an die Steuerelektrode des Regeltransistors (Tr) angelegte Steuerimpuls den Regeltransistor in einen vollkommen leitenden Zustand während der Dauer der Initialisierung steuert, wodurch an die Ausgangsklemme (S1) der Einrichtung eine Spannung angelegt werden kann, die gleich der Spannung ist, mit der die Versorgungsspannung aufgebaut wird.
  3. Vorrichtung nach Anspruch 2, dadurch gekennzeichnet, dass die Schaltung zum Erzeugen eines Steuerimpulses bestimmter Länge von einer Schaltung der bistabilen Art gebildet wird, der auf den Anfangszeitpunkt und den Beendigungszeitpunkt der Initialisierungszeit abgestimmt wird, die von dem Anfang bzw. Ende des Aufbaus der zweiten Referenzspannung (Vref) bestimmt wird, die von der Halbleiterschaltung (1) geliefert wird.
  4. Vorrichtung nach Anspruch 3, dadurch gekennzeichnet, dass die synchronisierte Schaltung der bistabilen Art umfasst:
    - eine erste und eine zweite Schaltung zur Ermittlung des gleichzeitigen Vorhandenseins einer Spannung zum Aufbau der Referenzspannung bzw. der Präzisionsreferenzspannung (Vout) an der Ausgangsklemme (S1), wobei diese erste und zweite Ermittlungsschaltung in Kaskade geschaltet sind und die Erzeugung einer ermittelten Spannung erlauben, die für die zweite Referenzspannung (Vref) bzw. die Präzisionsreferenzspannung (Vout) steht, die unter einem Schwellenwert liegt, der die Dauer der Initialisierungszeit wiedergibt;
    - eine nicht-lineare Umsteuerungsschaltung, die am Eingang die ermittelte Spannung aufnimmt und einen Vergleich dieser ermittelten Spannung mit dem Schwellenwert erlaubt, welche nicht-lineare Schaltung eine erste Steuerspannung liefert, solange die ermittelte Spannung über dem Schwellenwert liegt, und ansonsten eine zweite Steuerspannung liefert;
    - einen Initialisierungssteuerungstransistor, dessen an den Ausgang der nicht-linearen Schaltung angelegte Steuerelektrode durch die erste bzw. zweite Steuerspannung umgesteuert wird, die von der nicht-linearen Umsteuerungsschaltung geliefert wird, wobei der Initialisierungssteuerungstransistor parallel zwischen die Steuerelektrode des Regeltransistors und die Massespannung der Einrichtung geschaltet ist, wodurch der Initialisierungssteuerungstransistor so gesteuert werden kann, dass er leitend wird, wenn die nicht-lineare Umsteuerungsschaltung die erste Steuerspannung liefert, wobei die Ausgangsklemme der Einrichtung während der Initialisierungszeit die Spannung zum Aufbau der Versorgungsspannung mittels des vollkommen leitend gemachten Regeltransistors liefert, bzw. dass der Initialisierungssteuerungstransistor blockiert wird, wenn die nicht-lineare Umsteuerungsschaltung die zweite Steuerungsspannung liefert, wobei die Ausgangsklemme der Einrichtung die Präzisionsreferenzspannung (Vout) mittels des Regeltransistors liefert, der die Funktion eines Widerstands hat, dessen Spannung durch den Ausgang des Differenzial-Vervielfachers (20) gesteuert wird.
EP02290301A 2001-02-09 2002-02-07 Referenzspannungsgeneratoreinrichtung mit hoher Genauigkeit Expired - Lifetime EP1231529B1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
FR0101821 2001-02-09
FR0101821A FR2820904B1 (fr) 2001-02-09 2001-02-09 Dispositif generateur d'une tension de reference precise

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EP1231529B1 true EP1231529B1 (de) 2006-06-14

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Families Citing this family (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH10260741A (ja) * 1997-03-17 1998-09-29 Oki Electric Ind Co Ltd 定電圧発生回路
DE10226057B3 (de) * 2002-06-12 2004-02-12 Infineon Technologies Ag Integrierte Schaltung mit Spannungsteiler und gepuffertem Kondensator
WO2004034169A1 (ja) * 2002-10-08 2004-04-22 Fujitsu Limited 電圧安定化回路
US6724176B1 (en) * 2002-10-29 2004-04-20 National Semiconductor Corporation Low power, low noise band-gap circuit using second order curvature correction
KR100629258B1 (ko) * 2003-03-20 2006-09-29 삼성전자주식회사 내부 전압 발생회로
FR2853475B1 (fr) * 2003-04-01 2005-07-08 Atmel Nantes Sa Circuit integre delivrant des niveaux logiques a une tension independante de la tension d'alimentation, sans regulateur associe pour la partie puissance, et module de communication correspondant
KR100558477B1 (ko) * 2003-04-28 2006-03-07 삼성전자주식회사 반도체 장치의 내부 전압 발생회로
KR100626367B1 (ko) * 2003-10-02 2006-09-20 삼성전자주식회사 내부전압 발생장치
US7429888B2 (en) * 2004-01-05 2008-09-30 Intersil Americas, Inc. Temperature compensation for floating gate circuits
US8315588B2 (en) * 2004-04-30 2012-11-20 Lsi Corporation Resistive voltage-down regulator for integrated circuit receivers
US7453252B1 (en) * 2004-08-24 2008-11-18 National Semiconductor Corporation Circuit and method for reducing reference voltage drift in bandgap circuits
KR100645048B1 (ko) * 2004-10-20 2006-11-10 삼성전자주식회사 반도체 메모리 장치에 사용되는 전압 레귤레이터
US7221209B2 (en) * 2005-05-12 2007-05-22 Intersil Americas, Inc Precision floating gate reference temperature coefficient compensation circuit and method
TWI353553B (en) * 2007-12-26 2011-12-01 Asustek Comp Inc Cpu core voltage supply
US9111603B1 (en) * 2012-02-29 2015-08-18 Altera Corporation Systems and methods for memory controller reference voltage calibration
CN104615181B (zh) * 2013-11-05 2016-06-22 智原科技股份有限公司 电压调节器装置与相关方法
US9317051B2 (en) * 2014-02-06 2016-04-19 SK Hynix Inc. Internal voltage generation circuits
US9983607B2 (en) 2014-11-04 2018-05-29 Microchip Technology Incorporated Capacitor-less low drop-out (LDO) regulator

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4127783A (en) * 1977-04-25 1978-11-28 Motorola, Inc. Regulated constant current circuit
JPH0519914A (ja) * 1991-07-17 1993-01-29 Sharp Corp 半導体装置の内部降圧回路
US5721485A (en) * 1996-01-04 1998-02-24 Ibm Corporation High performance on-chip voltage regulator designs
US6046577A (en) * 1997-01-02 2000-04-04 Texas Instruments Incorporated Low-dropout voltage regulator incorporating a current efficient transient response boost circuit
EP0971280A1 (de) * 1998-07-07 2000-01-12 Motorola Semiconducteurs S.A. Spannungsregler und Verfahren zur Spannungsregelung
US6225857B1 (en) * 2000-02-08 2001-05-01 Analog Devices, Inc. Non-inverting driver circuit for low-dropout voltage regulator

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US20020136065A1 (en) 2002-09-26
US6650175B2 (en) 2003-11-18
FR2820904A1 (fr) 2002-08-16
FR2820904B1 (fr) 2003-06-13
DE60212217T2 (de) 2007-05-24
DE60212217D1 (de) 2006-07-27
EP1231529A1 (de) 2002-08-14

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