EP1231529A1 - Referenzpannungsgeneratoreinrichtung mit hoher Genauigkeit - Google Patents

Referenzpannungsgeneratoreinrichtung mit hoher Genauigkeit Download PDF

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Publication number
EP1231529A1
EP1231529A1 EP02290301A EP02290301A EP1231529A1 EP 1231529 A1 EP1231529 A1 EP 1231529A1 EP 02290301 A EP02290301 A EP 02290301A EP 02290301 A EP02290301 A EP 02290301A EP 1231529 A1 EP1231529 A1 EP 1231529A1
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EP
European Patent Office
Prior art keywords
voltage
circuit
reference voltage
initialization
transistor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
EP02290301A
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English (en)
French (fr)
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EP1231529B1 (de
Inventor
Philippe Messager
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Microchip Technology Nantes
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Atmel Nantes SA
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Publication date
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Publication of EP1231529A1 publication Critical patent/EP1231529A1/de
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Publication of EP1231529B1 publication Critical patent/EP1231529B1/de
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    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
    • G05F1/10—Regulating voltage or current
    • G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is dc
    • G05F1/56—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices
    • G05F1/565—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices sensing a condition of the system or its load in addition to means responsive to deviations in the output of the system, e.g. current, voltage, power factor
    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
    • G05F1/10—Regulating voltage or current
    • G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is dc
    • G05F1/56—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices
    • G05F1/575—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices characterised by the feedback circuit

Definitions

  • the present invention relates to a device generator of a precise reference voltage, plus particularly intended to produce, from a potential external power supply that may vary between minimum value and maximum value, a voltage of precise reference output which is stable whatever generator operating temperature and value of the external supply potential.
  • Such generating devices are particularly suited to provide a potential for stable reference to an electronic circuit, such as by example an analog-to-digital converter, so that make the operation of the latter more stable and more precise, while reducing the consumption of these generators.
  • the invention relates more particularly to those comprising a semiconductor circuit 1, more commonly referred to as a "band-gap" circuit in English language, this type of circuit making it possible to generate a reference voltage, hereinafter designated semiconductor circuit 1, and at least one voltage multiplier circuit 2 mounted in cascade with this semiconductor circuit, this voltage multiplier circuit being intended to supply, from the reference voltage delivered by the semiconductor circuit, the stable reference output voltage.
  • a semiconductor circuit 1 more commonly referred to as a "band-gap" circuit in English language
  • this type of circuit making it possible to generate a reference voltage, hereinafter designated semiconductor circuit 1
  • at least one voltage multiplier circuit 2 mounted in cascade with this semiconductor circuit, this voltage multiplier circuit being intended to supply, from the reference voltage delivered by the semiconductor circuit, the stable reference output voltage.
  • FIG. 1a Such a generator device of the prior art is shown in FIG. 1a.
  • the voltage multiplier circuit 2 comprises a differential amplifier OPA receiving on its negative terminal the reference voltage Vref as the reference voltage and a resistive reaction circuit R ' 1 , R' 2 , R '3 with a decoupling capacity C 2 comprising a regulating transistor Tr connected between the supply voltage Vcc and the resistive bridge bringing in part the output voltage V OUT , reference voltage deemed to be precise, on the positive terminal of the OPA operational amplifier.
  • the gate electrode of the regulating transistor Tr is connected and controlled by the output of the differential amplifier OPA, the junction point between the regulating transistor Tr and the resistive bridge constituting the output terminal delivering the reference voltage deemed to be precise.
  • the regulating transistor Tr plays the role of a voltage-controlled resistor and the multiplier circuit 2 makes it possible to control the output voltage V OUT to a value greater than the reference voltage Vref, but less than the value of the voltage d 'supply Vcc, as a function of the relative values of the resistors R' 1 , R ' 2 and R 3 , the resistance value of the regulating transistor Tr being low.
  • the variations in the supply voltage, and in the reference voltage Vref are amplified accordingly, which affects the real accuracy of the assembly.
  • the object of the present invention is in particular to remedy these drawbacks by improving accuracy and the stability of the reference generator devices precise, regardless of their relative voltage setting external power supply, respectively at operation, while benefiting from less consumption.
  • the device generating a voltage of precise reference includes a semiconductor circuit generating a reference voltage and a voltage multiplier circuit supplied from a supply voltage.
  • the circuit voltage multiplier includes at least one amplifier differential receiving on its negative terminal this voltage of reference as setpoint voltage and a circuit resistive reaction comprising a regulating transistor connected between the supply voltage and a resistive bridge reducing, in part, the precise reference voltage to the positive terminal of this differential amplifier.
  • the gate electrode of the regulating transistor is connected and controlled by the output of the differential amplifier and the junction point between the regulating transistor and the resistive bridge constitutes, for this generating device, an output terminal delivering the reference voltage precise.
  • the initialization circuit includes a circuit generator of a command pulse of fixed duration, this control pulse, applied to the electrode gate of the regulating transistor controlling this transistor fully conductive state, during initialization time. This allows to impose on the terminal output of the device generating a voltage of reference specifies a voltage equal to the voltage establishing the supply voltage during initialization time.
  • the device generating a precise reference voltage comprises a semiconductor circuit 1, of the " band-gap " type which is connected in cascade with a voltage multiplier circuit 2.
  • the semiconductor circuit 1 is constituted by a "band-gap" type circuit as shown in FIG. 1b generating a reference voltage Vref.
  • FIG. 1b An example of such a semiconductor circuit generating a reference voltage is shown schematically in FIG. 1b above when this circuit is supplied by a supply voltage Vcc.
  • the latter is produced in the form of an integrated circuit. It is widely used in the prior art and provides a relatively stable reference voltage Vref.
  • This circuit is known by the name of "reference voltage source to bandgap", the word bandgap being a word of English origin designating the energy of passage of the electrons from the conduction band to the valence band in the semi- conductor used. This energy depends, in known manner, on the temperature. Reference sources of this type use the dependence of certain circuit parameters as a function of this energy and therefore of the temperature, to achieve, by appropriate compensations, an approximately stable reference voltage Vref.
  • the circuit of FIG. 1b essentially comprises two bipolar transistors T 1 , T 2 mounted as a diode, three resistors R 1 , R 2 , R 3 , and an operational amplifier OPA.
  • the amplifier OPA which is supplied by the external supply voltage Vcc, comprises an inverting input connected to the collector of the bipolar transistor T ' 2 , and a non-inverting input connected to the resistor R 1 which is itself connected to the collector of the bipolar transistor T ' 1 .
  • Resistor R 3 meanwhile, allows the establishment of the circuit during an increase in the external supply voltage Vcc.
  • the reference voltage Vref stable as a function of the temperature and of the external supply voltage Vcc, is supplied at output S of the circuit.
  • the stability of the reference voltage Vref is based in particular on an appropriate choice of the junction surfaces of the two bipolar transistors T ' 1 , T' 2 , and the values of R 1 and R 2 .
  • V be2 and V T are respectively the emitter base voltage and the threshold voltage of transistor T ' 2 , and I 1 and I 2 the currents flowing respectively in resistors R 1 and R 2 , In denoting the natural logarithm.
  • the amplitude value of the reference voltage Vref then obtained at the output is of the order of 1.25V.
  • This semiconductor circuit 1 is subjected, in a manner analogous to the band-gap reference voltage sources of the prior art, to a prior adjustment.
  • the semiconductor circuit 1 is adjusted so that Vref varies from 2 mV in temperature and 30 mV in voltage.
  • the voltage multiplier circuit 2 comprises a differential amplifier 20, constituted by an operational amplifier OP 1 which is mounted as a voltage multiplier, the voltage multiplier circuit 2 operating as a multiplier and as a voltage regulator .
  • This differential amplifier 20 has a non-inverting input + which is connected directly to the output S of the semiconductor circuit 1, an output S 1 which delivers a predetermined output voltage V OUT , constituting the precise reference voltage sought.
  • This output S 1 is connected by a galvanic link 3 to the power supply input IN of the semiconductor circuit 1 generating the reference voltage Vref.
  • the semiconductor circuit 1 is, in steady state, supplied by the precise reference voltage, as will be described in more detail in the description.
  • a capacitor C 1 makes it possible to smooth the reference voltage Vref and a capacitor C 3 makes it possible to smooth the output voltage V OUT .
  • a resistive feedback circuit which includes a regulating transistor Tr connected between the supply voltage Vcc and a resistive bridge R ' 1 , R' 2 , R ' 3 bringing, in part, the precise reference voltage, output voltage V OUT delivered by the output terminal S 1 , on the non-inverting terminal + of the differential amplifier 20, operational amplifier OPA.
  • the gate electrode of the regulation transistor Tr is connected and controlled by the output of the differential amplifier 20.
  • the junction point between the regulation transistor Tr and the resistive bridge constitutes for the reference voltage generator device the terminal output S 1 delivering the precise reference voltage V OUT .
  • the reference voltage Vref constitutes a set value.
  • the regulating transistor Tr plays the role of an adjustable resistor controlled in voltage by the output of the differential amplifier 20.
  • a decoupling capacity C 2 makes it possible to ensure the stability of the servo by introducing a margin phase suitable for transient conditions.
  • an initialization circuit 4 is connected to the gate electrode of the regulating transistor Tr.
  • This circuit 4 allows in transient mode, upon initialization, when powering up at the supply voltage Vcc of the device precise reference generator, object of the invention, to replace the precise reference voltage Vref, not yet established by the semiconductor circuit 1 of the "band-gap" type , this type of circuit having a voltage operating threshold non-negligible supply voltage, by the establishment voltage of the supply voltage Vcc.
  • Such an operating mode makes it possible, on the one hand, in transient mode, on initialization, to supply the semiconductor circuit 1 from the establishment voltage of the supply voltage Vcc, and, as a result of the increasing nature of this supply voltage, to cause, according to a cumulative phenomenon, the correlative rise of the output voltage V OUT delivered by the output terminal S 1 and therefore that of the supply voltage of the semi circuit -conductors 1 due to the presence of the galvanic link 3.
  • This operating mode makes it possible, on the other hand, in steady state, to deliver on the output terminal S 1 , the precise reference voltage sought, the reference voltage Vref having reached its nominal value, and supplying the semiconductor circuit 1 from the nominal value of the reference voltage Vref.
  • Vref 1.25V
  • R'1 0.955M ⁇
  • R'2 0.16M ⁇
  • the differential amplifier 20 which is thus connected in cascade with the semiconductor circuit 1 generating the reference voltage Vref and which, therefore, receives as reference voltage the reference voltage Vref, makes it possible to deliver a voltage of regulated output V OUT constituting the precise reference voltage sought whatever the operating temperature and the external supply voltage Vcc. It will be understood in particular that a fine temperature adjustment of the semiconductor circuit 1 can be chosen preferentially, since the voltage regulation as a function of the supply voltage is moreover ensured by the voltage multiplier and regulator circuit 2.
  • the series connection of the semiconductor circuit 1 and of the voltage multiplier circuit 2 allows a device generating a precise reference voltage which is particularly suitable for being associated with a load, such as an electronic circuit, of digital type or analog, requiring a very stable voltage reference for an ADC analog-to-digital conversion comparison for example and controlled operating stability. he this is so, for example, analog converters digital.
  • the initialization circuit 4 can be formed by a generator of a control pulse of determined duration.
  • the control pulse CP applied to the gate electrode of the regulation transistor Tr makes it possible to bring this transistor to the fully conductive state during the initialization period and thus to impose on the terminal output S 1 of the precise voltage generator device which is the subject of the invention, and on the supply terminal of the semiconductor circuit 1 generator of the reference voltage Vref, a voltage substantially equal to the establishment voltage of the supply voltage.
  • the generator 4 can be constituted by a type circuit monostable with adjustable duration from a voltage of VD command.
  • the setting of the pulse duration of CP command can be carried out experimentally for a group of given circuits.
  • the generator 4 is of course supplied by the supply voltage Vcc, which is established faster than the reference voltage Vref delivered by the semiconductor circuit 1.
  • circuit 4 generating a duration control pulse determined is constituted by a bistable type circuit, synchronized to a start time and an end time of the initialization time.
  • the duration is defined by the start, respectively the end of establishment of the reference voltage Vref delivered by the semiconductor circuit 1.
  • FIG. 3 A specific embodiment of the preferred embodiment of the initialization circuit 4 is shown in FIG. 3.
  • the same references represent the same elements as in the context of FIG. 2.
  • the synchronized bistable type circuit comprises a first and a second circuit for detecting the simultaneous presence of a voltage for establishing the reference voltage Vref, delivered by the semiconductor circuit 1, respectively of the precise reference voltage V OUT present on the output terminal S 1 .
  • the first and second detection circuits are each formed by an N-MOS transistor T 2 , T 3 connected in cascade via a resistor R ' 4 between the supply voltage Vcc and the ground voltage V GND .
  • the gate of the transistor T 2 first detection circuit, is connected to the output S of the semiconductor circuit 1 to detect the presence of the establishment voltage of the reference voltage Vref.
  • the gate of transistor T 3 is connected to a point representative of the output voltage V OUT to detect the presence of the voltage for establishing the precise reference voltage.
  • This representative point may, for example, be constituted by the connection point of the resistive bridge, the junction point between R ' 2 and R' 3 for example.
  • a non-linear switching circuit NL is provided. This circuit is formed by two cascaded inverters INV 1 and INV 2 .
  • the non-linear circuit controls an initialization control transistor TN 4 , which is connected between the gate of the regulation transistor Tr and the reference voltage V GND .
  • the gate electrode of the initialization control transistor is directly connected to the output of the second inverter INV 2 forming the non-linear circuit NL.
  • the non-linear switching circuit NL receives as input the voltage detected by the first and second detection circuits T 2 , T 3 , and makes it possible to compare this detected voltage representative of a reference voltage, respectively of a reference voltage accurate below a threshold value. This threshold value is representative of the initialization time.
  • the non-linear switching circuit NL delivers a first control voltage as long as the detected voltage is greater than the threshold value and a second control voltage otherwise, to the initialization control transistor T 4 , which delivers in switching the control pulse CP to the regulating transistor Tr.
  • the device generating a precise voltage according to the present invention operates in the following manner.
  • the semiconductor circuit 1 generator of the reference voltage Vref delivers at output a first potential close to 0V, Vref ⁇ 1V, and the differential amplifier 20 delivers at output a first output potential close from 0V, V OUT ⁇ 2V, the transistors T 2 and T 3 are then blocked.
  • the input of the inverter INV 1 then receives a voltage of value equal to V cc which is supplied on the source of the transistor T 3 by R ' 4 . This voltage is transmitted via the two inverters INV 1 and INV 2 constituting the non-linear switching circuit NL on the gate of the transistor T 4 which turns on.
  • the input of the inverter INV 1 then receives a voltage of zero value which is supplied on the source of the transistor T 3 . This voltage is transmitted via the non-linear switching circuit NL on the gate of transistor T 4 which becomes blocked.
  • the gate of the regulation transistor Tr is then biased by the output voltage V SI1 delivered by the differential amplifier 20, and the regulation transistor Tr then behaves like a resistor which follows the evolution of V SI1 .
  • the output voltage constituting the precise reference voltage is now supplied to the power supply input IN of the semiconductor circuit 1.
  • the semiconductor circuit 1 generating the reference voltage is intrinsically stable and precise in voltage, without it is necessary to make a specific voltage adjustment, which then makes it possible to choose a precise temperature adjustment, rather than voltage. Measurements have shown that the voltage accuracy of the semiconductor circuit 1 generating the reference voltage was of the order of 2mV. Such precision and stability are advantageously passed on to the output voltage V OUT delivered at output OUT and constituting the precise reference voltage within the meaning of the present invention.

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Electromagnetism (AREA)
  • General Physics & Mathematics (AREA)
  • Radar, Positioning & Navigation (AREA)
  • Automation & Control Theory (AREA)
  • Control Of Electrical Variables (AREA)
EP02290301A 2001-02-09 2002-02-07 Referenzspannungsgeneratoreinrichtung mit hoher Genauigkeit Expired - Lifetime EP1231529B1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
FR0101821A FR2820904B1 (fr) 2001-02-09 2001-02-09 Dispositif generateur d'une tension de reference precise
FR0101821 2001-02-09

Publications (2)

Publication Number Publication Date
EP1231529A1 true EP1231529A1 (de) 2002-08-14
EP1231529B1 EP1231529B1 (de) 2006-06-14

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EP02290301A Expired - Lifetime EP1231529B1 (de) 2001-02-09 2002-02-07 Referenzspannungsgeneratoreinrichtung mit hoher Genauigkeit

Country Status (4)

Country Link
US (1) US6650175B2 (de)
EP (1) EP1231529B1 (de)
DE (1) DE60212217T2 (de)
FR (1) FR2820904B1 (de)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2016073340A1 (en) * 2014-11-04 2016-05-12 Microchip Technology Incorporated Capacitor-less low drop-out (ldo) regulator

Families Citing this family (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH10260741A (ja) * 1997-03-17 1998-09-29 Oki Electric Ind Co Ltd 定電圧発生回路
DE10226057B3 (de) * 2002-06-12 2004-02-12 Infineon Technologies Ag Integrierte Schaltung mit Spannungsteiler und gepuffertem Kondensator
JP4167225B2 (ja) * 2002-10-08 2008-10-15 富士通株式会社 電圧安定化回路及び制御方法
US6724176B1 (en) * 2002-10-29 2004-04-20 National Semiconductor Corporation Low power, low noise band-gap circuit using second order curvature correction
KR100629258B1 (ko) * 2003-03-20 2006-09-29 삼성전자주식회사 내부 전압 발생회로
FR2853475B1 (fr) * 2003-04-01 2005-07-08 Atmel Nantes Sa Circuit integre delivrant des niveaux logiques a une tension independante de la tension d'alimentation, sans regulateur associe pour la partie puissance, et module de communication correspondant
KR100558477B1 (ko) * 2003-04-28 2006-03-07 삼성전자주식회사 반도체 장치의 내부 전압 발생회로
KR100626367B1 (ko) * 2003-10-02 2006-09-20 삼성전자주식회사 내부전압 발생장치
US7429888B2 (en) * 2004-01-05 2008-09-30 Intersil Americas, Inc. Temperature compensation for floating gate circuits
US8315588B2 (en) * 2004-04-30 2012-11-20 Lsi Corporation Resistive voltage-down regulator for integrated circuit receivers
US7453252B1 (en) * 2004-08-24 2008-11-18 National Semiconductor Corporation Circuit and method for reducing reference voltage drift in bandgap circuits
KR100645048B1 (ko) * 2004-10-20 2006-11-10 삼성전자주식회사 반도체 메모리 장치에 사용되는 전압 레귤레이터
US7221209B2 (en) * 2005-05-12 2007-05-22 Intersil Americas, Inc Precision floating gate reference temperature coefficient compensation circuit and method
TWI353553B (en) * 2007-12-26 2011-12-01 Asustek Comp Inc Cpu core voltage supply
US9111603B1 (en) * 2012-02-29 2015-08-18 Altera Corporation Systems and methods for memory controller reference voltage calibration
CN104615181B (zh) * 2013-11-05 2016-06-22 智原科技股份有限公司 电压调节器装置与相关方法
US9317051B2 (en) * 2014-02-06 2016-04-19 SK Hynix Inc. Internal voltage generation circuits

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0971280A1 (de) * 1998-07-07 2000-01-12 Motorola Semiconducteurs S.A. Spannungsregler und Verfahren zur Spannungsregelung
US6046577A (en) * 1997-01-02 2000-04-04 Texas Instruments Incorporated Low-dropout voltage regulator incorporating a current efficient transient response boost circuit

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4127783A (en) * 1977-04-25 1978-11-28 Motorola, Inc. Regulated constant current circuit
JPH0519914A (ja) * 1991-07-17 1993-01-29 Sharp Corp 半導体装置の内部降圧回路
US5721485A (en) * 1996-01-04 1998-02-24 Ibm Corporation High performance on-chip voltage regulator designs
US6225857B1 (en) * 2000-02-08 2001-05-01 Analog Devices, Inc. Non-inverting driver circuit for low-dropout voltage regulator

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6046577A (en) * 1997-01-02 2000-04-04 Texas Instruments Incorporated Low-dropout voltage regulator incorporating a current efficient transient response boost circuit
EP0971280A1 (de) * 1998-07-07 2000-01-12 Motorola Semiconducteurs S.A. Spannungsregler und Verfahren zur Spannungsregelung

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2016073340A1 (en) * 2014-11-04 2016-05-12 Microchip Technology Incorporated Capacitor-less low drop-out (ldo) regulator
US9983607B2 (en) 2014-11-04 2018-05-29 Microchip Technology Incorporated Capacitor-less low drop-out (LDO) regulator
US10761552B2 (en) 2014-11-04 2020-09-01 Microchip Technology Incorporated Capacitor-less low drop-out (LDO) regulator, integrated circuit, and method

Also Published As

Publication number Publication date
US6650175B2 (en) 2003-11-18
US20020136065A1 (en) 2002-09-26
FR2820904B1 (fr) 2003-06-13
DE60212217D1 (de) 2006-07-27
FR2820904A1 (fr) 2002-08-16
EP1231529B1 (de) 2006-06-14
DE60212217T2 (de) 2007-05-24

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