EP1062651B1 - Verfahren zur datenanzeige auf einer matrixanzeige mit alternierender abtastsequenz in benachbarten spaltengruppen - Google Patents

Verfahren zur datenanzeige auf einer matrixanzeige mit alternierender abtastsequenz in benachbarten spaltengruppen Download PDF

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Publication number
EP1062651B1
EP1062651B1 EP99907671A EP99907671A EP1062651B1 EP 1062651 B1 EP1062651 B1 EP 1062651B1 EP 99907671 A EP99907671 A EP 99907671A EP 99907671 A EP99907671 A EP 99907671A EP 1062651 B1 EP1062651 B1 EP 1062651B1
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EP
European Patent Office
Prior art keywords
columns
lines
block
data
line
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Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
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EP99907671A
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English (en)
French (fr)
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EP1062651A1 (de
Inventor
Thierry Kretz
Bruno Mourey
Hugues Lebrun
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Thales Avionics LCD SA
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Thales Avionics LCD SA
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Publication of EP1062651A1 publication Critical patent/EP1062651A1/de
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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0243—Details of the generation of driving signals
    • G09G2310/0245—Clearing or presetting the whole screen independently of waveforms, e.g. on power-on
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0283—Arrangement of drivers for different directions of scanning
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0297—Special arrangements with multiplexing or demultiplexing of display data in the drivers for data electrodes, in a pre-processing circuitry delivering display data to said drivers or in the matrix panel, e.g. multiplexing plural data signals to one D/A converter or demultiplexing the D/A converter output to multiple columns
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0209—Crosstalk reduction, i.e. to reduce direct or indirect influences of signals directed to a certain pixel of the displayed image on other pixels of said image, inclusive of influences affecting pixels in different frames or fields or sub-images which constitute a same image, e.g. left and right images of a stereoscopic display
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters

Definitions

  • the present invention relates to a method for displaying data on a matrix display, more particularly a matrix display constituted by N data lines and M selection lines at the intersections of which are located image points or pixels, in which the N lines of data are grouped in P blocks of N 'lines of data each.
  • liquid crystal screens used in direct vision or projection. These screens are, in general, composed of a first substrate comprising selection lines, referenced below lines, and data lines, referenced below columns, at the intersections of which the image points are located and of a second substrate comprising a counter electrode, the liquid crystals being inserted between the two substrates.
  • the image points consist in particular of pixel electrodes connected through switching circuits, such as transistors, to the selection lines and to the data lines.
  • the selection lines and the data lines are respectively connected to peripheral control circuits generally called "drivers" (in English).
  • the line drivers scan the lines one after the other and close the switching circuits, that is to say pass the transistors of each line.
  • the column drivers apply information to each line of data, namely, charge the electrodes of the selected pixels and modify the optical properties of the liquid crystal included between these electrodes and the counter-electrode, thus allowing the formation of images on the screen.
  • each column is connected by its own connection line to the screen column drivers.
  • the principle of multiplexing is used between the outputs of the driver-columns and the columns of the screen so as to reduce the number of tracks at the input of the cell.
  • each block consists of transistors 3, one of the electrodes of which is connected to a column and the other electrode of which is connected to the same electrode of the other transistors of the block, all of these electrodes being connected to a video input referenced DB1 for the first block, DB2 for the second block, DBP for the last block.
  • the gates of the transistors 3 each receive a demultiplexing signal DW1, DW2, DW3 ... DW9.
  • Each block has the same structure.
  • FIG. 2 The timing diagrams of the voltages recorded on the successive columns of the same block 1 receiving a video signal DB1 to DBP are shown in FIG. 2. It was assumed for the plotting of these timing diagrams, that the DC and AC voltage errors introduced by the column - line - column coupling (referenced 2 in FIGURE 1), the origin of which was described in French patent n ° 96 00259 filed on January 11, 1996, are perfectly corrected by the compensation circuit presented in this same patent .
  • Each chronogram represents a time-line of a given column (1 to 9) of a block connected for example to DB1.
  • the decomposition of the signals can be done as follows: 1. Preload of all columns of the matrix 4 ⁇ s 2. Stabilization of the preload 0,5 ⁇ s 3. Sampling of the video on the 9 columns of the DB block 9 x 2 ⁇ s 4. Equalization between column and pixel 7,5 ⁇ s 5. Deselection of the line 2 .mu.s.
  • the object of the present invention is to propose a method for displaying data on a matrix display which overcomes this drawback.
  • the scanning of 1 at N 'then from N' to 1, every other selection line is made.
  • scanning from 1 to N 'then from N' to 1 is performed on 4 successive selection lines, the scanning being carried out in a first direction during 2 successive selection lines and in a second direction during the 2 other following selection lines.
  • the process according to the present invention mainly applies to a matrix display of the type of that shown in FIGURE 1.
  • This display consists of N rows of data or columns and M rows of selection in intersections of which the image points or pixels are not represented.
  • the N columns are grouped into P blocks 1 of N ′ columns each.
  • P blocks 1 of N ′ columns each For example, in FIGURE 1, a block of 9 columns is shown.
  • the column control circuit will include 80 blocks of 9 adjacent columns and will operate with frequency approximately 500 kHz sampling rate.
  • each block 1 receives in parallel one of the P or 80 data signals which is demultiplexed by signals DW1 to DW9 on the N 'or 9 columns of a block.
  • each block 1 is successively scanned from line C1 to C9 in applying sampling pulses DW1 to DW9, and one obtains on each column C1 to C9, signals as shown in FIGURE 2. Then for the next line L2, each block is scanned starting from column C9 to the column C1 by applying sampling pulses from DW9 to DW1 from so as to reduce the DC error as explained in the introduction with reference to FIGURE 2.
  • the inversion of the scanning is carried out by reversing the arrival of the sampling pulses each two lines among four lines according to the following table: line frame 1 frame 2 frame 3 1 DW 1 to 9 DW 1 to 9 DW 1 to 9 2 DW 1 to 9 DW 1 to 9 DW 1 to 9 3 DW 9 to 1 DW 9 to 1 DW 9 to 1 4 DW 9 to 1 DW 9 to 1 DW 9 to 1 5 DW 1 to 9 DW 1 to 9 DW 1 to 9 6 DW 1 to 9 DW 1 to 9 DW 1 to 9 DW 1 to 9 DW 1 to 9
  • the present invention also relates to a circuit making it possible to set up this process.
  • This circuit consists of at least one logic circuit programmable associated with a line counter determining the reversal of the direction of scanning.
  • the signal referenced Preset at the output of the line counter 11 controlled by the CL line clock is sent respectively on a modulo N '15 counter and on a DW 16 counter.
  • the modulo N' counter 15 is controlled by the data clock CD and operates in such a way that:
  • the DW 16 counter is controlled by the DW clock CDW and works as follows:
  • This information at the output of the DW counter is sent on a circuit level 17 and returned to the modulo counter N '15.

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  • Engineering & Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)
  • Liquid Crystal Display Device Control (AREA)

Claims (4)

  1. Verfahren zur Wiedergabe von Daten auf einem Matrixwiedergabeschirm aus N Datenleitungen und M Auswahlleitungen, bei deren Schnittpunkten die Bildpunkte oder Pixel liegen, wobei die N Datenleitungen in P Blöcke mit je N' Datenleitungen umgruppiert sind (N = P × N'), jeder Block parallel eines der P Datensignale empfängt, das auf den N' Leitungen des Blocks demultiplexiert wird,
    dadurch gekennzeichnet, daß
    abwechselnd entsprechend den Auswahlleitungen die Abtastung der N' Datenleitungen eines Blocks entweder mit 1 bis N' oder mit N' bis 1 erfolgt.
  2. Verfahren nach Anspruch 1, dadurch gekennzeichnet, daß die Abtastung mit 1 bis N' und dann mit N' bis 1 in jeder zweiten Auswahlleitung erfolgt.
  3. Verfahren nach Anspruch 1, dadurch gekennzeichnet, daß die Abtastung mit 1 bis N' und dann mit N' bis 1 auf vier aufeinanderfolgenden Auswahlleitungen erfolgt, daß die Abtastung in einer ersten Richtung während zwei aufeinanderfolgenden Auswahlleitungen und in einer zweiten Richtung während der anderen beiden folgenden Auswahlleitungen erfolgt.
  4. Schaltung zur Durchführung des Verfahrens nach einem der Ansprüche 1 bis 3, dadurch gekennzeichnet, daß sie wenigstens eine programmierbare logische Schaltung mit einem Leitungszähler enthält, der die Umkehr der Abtastrichtung bestimmt.
EP99907671A 1998-03-10 1999-03-09 Verfahren zur datenanzeige auf einer matrixanzeige mit alternierender abtastsequenz in benachbarten spaltengruppen Expired - Lifetime EP1062651B1 (de)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
FR9802919A FR2776107A1 (fr) 1998-03-10 1998-03-10 Procede d'affichage de donnees sur un afficheur matriciel
FR9802919 1998-03-10
PCT/FR1999/000524 WO1999046753A1 (fr) 1998-03-10 1999-03-09 Procede d'affichage de donnees sur afficheur matriciel avec ordre de balayage alterne en groupes adjacents de colonnes

Publications (2)

Publication Number Publication Date
EP1062651A1 EP1062651A1 (de) 2000-12-27
EP1062651B1 true EP1062651B1 (de) 2002-07-03

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ID=9523867

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Application Number Title Priority Date Filing Date
EP99907671A Expired - Lifetime EP1062651B1 (de) 1998-03-10 1999-03-09 Verfahren zur datenanzeige auf einer matrixanzeige mit alternierender abtastsequenz in benachbarten spaltengruppen

Country Status (7)

Country Link
US (1) US6924785B1 (de)
EP (1) EP1062651B1 (de)
JP (1) JP4727038B2 (de)
KR (1) KR100587433B1 (de)
DE (1) DE69902015T2 (de)
FR (1) FR2776107A1 (de)
WO (1) WO1999046753A1 (de)

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JP2004037498A (ja) * 2002-06-28 2004-02-05 Seiko Epson Corp 電気光学装置の駆動回路、電気光学装置、電子機器及び電気光学装置の駆動方法
JP2004145300A (ja) * 2002-10-03 2004-05-20 Seiko Epson Corp 電子回路、電子回路の駆動方法、電子装置、電気光学装置、電気光学装置の駆動方法及び電子機器
JP2006072385A (ja) * 2002-10-03 2006-03-16 Seiko Epson Corp 電子装置及び電子機器
FR2873227B1 (fr) * 2004-07-13 2006-09-15 Thales Sa Afficheur matriciel
FR2889763B1 (fr) * 2005-08-12 2007-09-21 Thales Sa Afficheur matriciel a affichage sequentiel des couleurs et procede d'adressage
US8184974B2 (en) 2006-09-11 2012-05-22 Lumexis Corporation Fiber-to-the-seat (FTTS) fiber distribution system
FR2913818B1 (fr) * 2007-03-16 2009-04-17 Thales Sa Matrice active d'un ecran electroluminescent organique
TWI334126B (en) * 2007-07-17 2010-12-01 Au Optronics Corp Voltage adjusting circuit, method, and display apparatus having the same
FR2934919B1 (fr) * 2008-08-08 2012-08-17 Thales Sa Registre a decalage a transistors a effet de champ.
CN102576356B (zh) 2009-08-06 2016-04-27 路美克斯公司 串联联网光纤到座位的机内娱乐系统
US8424045B2 (en) 2009-08-14 2013-04-16 Lumexis Corporation Video display unit docking assembly for fiber-to-the-screen inflight entertainment system
US8416698B2 (en) 2009-08-20 2013-04-09 Lumexis Corporation Serial networking fiber optic inflight entertainment system network configuration

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Also Published As

Publication number Publication date
EP1062651A1 (de) 2000-12-27
FR2776107A1 (fr) 1999-09-17
WO1999046753A1 (fr) 1999-09-16
DE69902015T2 (de) 2003-03-06
JP2002507007A (ja) 2002-03-05
DE69902015D1 (de) 2002-08-08
US6924785B1 (en) 2005-08-02
JP4727038B2 (ja) 2011-07-20
KR20010041675A (ko) 2001-05-25
KR100587433B1 (ko) 2006-06-09

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