EP0992066A1 - Circuit a semi-conducteur et procede de fabrication dudit circuit - Google Patents

Circuit a semi-conducteur et procede de fabrication dudit circuit

Info

Publication number
EP0992066A1
EP0992066A1 EP98941230A EP98941230A EP0992066A1 EP 0992066 A1 EP0992066 A1 EP 0992066A1 EP 98941230 A EP98941230 A EP 98941230A EP 98941230 A EP98941230 A EP 98941230A EP 0992066 A1 EP0992066 A1 EP 0992066A1
Authority
EP
European Patent Office
Prior art keywords
semiconductor
semiconductor substrate
poly
circuit device
contacting
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
EP98941230A
Other languages
German (de)
English (en)
Inventor
Sven Kanitz
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Qimonda AG
Original Assignee
Infineon Technologies AG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Infineon Technologies AG filed Critical Infineon Technologies AG
Publication of EP0992066A1 publication Critical patent/EP0992066A1/fr
Ceased legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/525—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections
    • H01L23/5252—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections comprising anti-fuses, i.e. connections having their state changed from non-conductive to conductive
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/525—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections
    • H01L23/5256—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections comprising fuses, i.e. connections having their state changed from conductive to non-conductive
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Definitions

  • the invention relates to a monolithically integrated semiconductor circuit device with a semiconductor substrate, in which or on which a plurality of circuit elements are formed, which are arranged one below the other and optionally with other elements, in particular at the edge of the semiconductor substrate
  • Contact points are electrically connected by means of conductor track patterns, which are provided in several contact levels, starting with a first contact level closest to the main surface of the semiconductor substrate, up to a last contact level.
  • the invention further relates to a method for producing such a monolithically integrated semiconductor circuit device.
  • fuse structures are used in integrated circuits in order to cut (“fuse”) or create new (“anti-fuse”) electrically conductive connections by means of laser radiation after the actual manufacturing process.
  • PLA programmable logic arrays
  • the logic operations are programmed using fuses.
  • fuses prevent unauthorized persons from accessing test modes of the circuit.
  • fuses are used to activate redundant circuit parts, in particular memory cells, and to switch off faulty ones.
  • DRAM dynamic random access memories
  • the invention is based on the object of specifying a monolithically integrated semiconductor circuit device and a method for its production, in which a risk-free and error-free activation of the fuses can be ensured even with more than two metallization levels.
  • the object is achieved by a method according to claim 1 and a semiconductor circuit device according to claim 5.
  • a fuse device consisting of separable connecting bridges (fuses) or connectable line interruptions (antifuses) is formed at least in regions from the conductor track pattern of the penultimate contacting level.
  • the monolithically integrated semiconductor circuit device has at least one completely formed semiconductor memory device with the associated control circuits and monolithically integrated on the same semiconductor substrate has a complete digital logic component, and the safety device is associated with the redundancy activation of defective memory cells or memory cell groups of the semiconductor memory device.
  • the semiconductor memory device is in particular a dynamic random access memory (DRAM) with a memory capacity of at least 1 megabit, in particular at least 4 megabits.
  • DRAM dynamic random access memory
  • at least three contacting levels are provided, the first contacting level being a polysilicon conductor pattern and the second, third , and optionally further contact level each has a conductor track pattern made of metal.
  • Figure 1 is a schematic plan view of the fuse window with the fuse paths to be cut in a monolithically integrated semiconductor circuit device
  • FIG. 2 shows a schematic cross section through the semiconductor circuit device along the section line II-II according to FIG. 1.
  • FIGS. 1 and 2 show, in a highly simplified manner, a monolithically integrated semiconductor circuit device 1 with a semiconductor substrate 2 made of single-crystal silicon, in which or on which a plurality of circuit elements such as logic gates, transistors, memory cells and the like are formed, which are interconnected and optionally with one another
  • Other contact points in particular arranged on the edge of the semiconductor substrate 2, are electrically connected by means of conductor track patterns 4, 5, 6, 10 which provided in several contacting levels, in the illustrated embodiment in the four contacting levels poly-Si, Ml, M2, M3 starting with the first contacting level poly-Si closest to the main surface 3 of the semiconductor substrate 2, up to the last, only schematically indicated contacting level M3 are.
  • the exemplary embodiment shown is a monolithically integrated semiconductor circuit device with a DRAM memory device with a memory capacity of 1.5 megabits, and a digital logic component in FIG.
  • a DRAM memory component and a logic component are thus combined in the semiconductor circuit device according to the invention.
  • Four contacting levels are provided:
  • a conductor track pattern made of polysilicon tracks is formed, which is used, for example, for contacting gate connections of the MOS components which are formed in or on the substrate 2.
  • the conductor pattern 5 of the second contacting level M1 made of metal, in particular aluminum or tungsten
  • the conductor pattern 6 of the penultimate contacting level M2 again made of metal, in particular aluminum or tungsten, make contact via tungsten plugs 9 (“plugs”) on polysilicon, and the like
  • Conductor pattern 10 of the last contacting level (M3) which make contact via further tungsten plugs 11.
  • the separable connecting bridges (fuses) 8 of the securing device are laid in the penultimate contacting level, here the metallization level M2, in order to influence the fluctuations in layer thickness of the underlying layer Reduce layers and ultimately increase the reliability of redundancy activation Production reduced by reducing the etching time during the production of the fuse window 7.
  • the fuse tracks 8 made from the material of the metallization level M2 (for example Al or AlSiCu) (only two such fuse tracks are indicated in FIG. 1, in reality there are substantially more fuse tracks arranged parallel to one another within the fuse window 7) provided) by the energy of a pulsed laser (for example neodymium YAG laser) locally, ie melted in a typical width of 2 to about 5 ⁇ and interrupted in this way.
  • a pulsed laser for example neodymium YAG laser
  • the invention is not limited to four-layer contacting levels with metallizations Ml, M2, M3 as shown.
  • More complex logic devices typically require more than two levels of metallization, i.e. M3, M4 and more;
  • the decisive factor here is that, in accordance with the principle of the invention, the fuse tracks 8 to be cut are always laid in the penultimate contact level, that is to say, for example, in the

Abstract

Circuit (1) intégré monolithique à semi-conducteur qui comporte un substrat (2) semi-conducteur sur lequel sont formés plusieurs éléments de circuit qui sont connectés électriquement entre eux et le cas échéant avec d'autres points de contact, placés en particulier au bord du substrat (2) semi-conducteur au moyen de motifs de pistes conductrices (4, 5, 6), lesdits motifs étant constitués de plusieurs plans de contact (Poly-Si, M1, M2, M3), commençant par un premier plan (Poly-Si) qui est le plus proche de la surface principale (3) du substrat semi-conducteur (2), et allant jusqu'à un dernier plan de contact (M3). A partir du motif de pistes conductrices (6) de l'avant-dernier plan de contact (M2) est formé au moins localement un dispositif coupe-circuit constitué d'étriers de jonction amovibles (fusibles) ou d'interruptions de circuit pouvant être reliées (antifusibles). La présente invention concerne en outre un procédé de fabrication dudit circuit (1).
EP98941230A 1997-06-24 1998-06-24 Circuit a semi-conducteur et procede de fabrication dudit circuit Ceased EP0992066A1 (fr)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
DE19726881 1997-06-24
DE19726881A DE19726881A1 (de) 1997-06-24 1997-06-24 Halbleiterschaltungsvorrichtung und Verfahren zur Herstellung
PCT/DE1998/001741 WO1998059370A1 (fr) 1997-06-24 1998-06-24 Circuit a semi-conducteur et procede de fabrication dudit circuit

Publications (1)

Publication Number Publication Date
EP0992066A1 true EP0992066A1 (fr) 2000-04-12

Family

ID=7833551

Family Applications (1)

Application Number Title Priority Date Filing Date
EP98941230A Ceased EP0992066A1 (fr) 1997-06-24 1998-06-24 Circuit a semi-conducteur et procede de fabrication dudit circuit

Country Status (4)

Country Link
US (1) US6310396B1 (fr)
EP (1) EP0992066A1 (fr)
DE (1) DE19726881A1 (fr)
WO (1) WO1998059370A1 (fr)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6909152B2 (en) * 2002-11-14 2005-06-21 Infineon Technologies, Ag High density DRAM with reduced peripheral device area and method of manufacture

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6218732A (ja) 1985-07-15 1987-01-27 インタ−ナショナル　ビジネス　マシ−ンズ　コ−ポレ−ション 集積回路とその個性化方法
JP2859288B2 (ja) * 1989-03-20 1999-02-17 株式会社日立製作所 半導体集積回路装置及びその製造方法
US5025300A (en) * 1989-06-30 1991-06-18 At&T Bell Laboratories Integrated circuits having improved fusible links
EP0469252B1 (fr) * 1990-06-19 1998-01-21 Texas Instruments Incorporated Décodeur à trajet de laser pour schéma de redondance de DRAM
US5132571A (en) * 1990-08-01 1992-07-21 Actel Corporation Programmable interconnect architecture having interconnects disposed above function modules
US5314840A (en) * 1992-12-18 1994-05-24 International Business Machines Corporation Method for forming an antifuse element with electrical or optical programming
US5618750A (en) * 1995-04-13 1997-04-08 Texas Instruments Incorporated Method of making fuse with non-corrosive termination of corrosive fuse material
US5759876A (en) * 1995-11-01 1998-06-02 United Technologies Corporation Method of making an antifuse structure using a metal cap layer

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See references of WO9859370A1 *

Also Published As

Publication number Publication date
US6310396B1 (en) 2001-10-30
WO1998059370A1 (fr) 1998-12-30
DE19726881A1 (de) 1999-01-07

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