Classifications

• • H—ELECTRICITY
  • H04—ELECTRIC COMMUNICATION TECHNIQUE
  • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
  • H04L27/00—Modulated-carrier systems
  • H04L27/26—Systems using multi-frequency codes
• • H—ELECTRICITY
  • H04—ELECTRIC COMMUNICATION TECHNIQUE
  • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
  • H04L1/00—Arrangements for detecting or preventing errors in the information received
  • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
  • H04L1/0056—Systems characterized by the type of code used
  • H04L1/0057—Block codes
• • H—ELECTRICITY
  • H04—ELECTRIC COMMUNICATION TECHNIQUE
  • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
  • H04L1/00—Arrangements for detecting or preventing errors in the information received
  • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
  • H04L1/0045—Arrangements at the receiver end
  • H04L1/0054—Maximum-likelihood or sequential decoding, e.g. Viterbi, Fano, ZJ algorithms
• • H—ELECTRICITY
  • H04—ELECTRIC COMMUNICATION TECHNIQUE
  • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
  • H04L1/00—Arrangements for detecting or preventing errors in the information received
  • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
  • H04L1/0056—Systems characterized by the type of code used
  • H04L1/0071—Use of interleaving
• • H—ELECTRICITY
  • H04—ELECTRIC COMMUNICATION TECHNIQUE
  • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
  • H04L25/00—Baseband systems
  • H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
  • H04L25/0202—Channel estimation
  • H04L25/0212—Channel estimation of impulse response
  • H04L25/0214—Channel estimation of impulse response of a single coefficient
• • H—ELECTRICITY
  • H04—ELECTRIC COMMUNICATION TECHNIQUE
  • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
  • H04L25/00—Baseband systems
  • H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
  • H04L25/0202—Channel estimation
  • H04L25/0224—Channel estimation using sounding signals
  • H04L25/0228—Channel estimation using sounding signals with direct estimation from sounding signals
  • H04L25/023—Channel estimation using sounding signals with direct estimation from sounding signals with extension to other symbols
  • H04L25/0232—Channel estimation using sounding signals with direct estimation from sounding signals with extension to other symbols by interpolation between sounding signals
• • H—ELECTRICITY
  • H04—ELECTRIC COMMUNICATION TECHNIQUE
  • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
  • H04L27/00—Modulated-carrier systems
  • H04L27/26—Systems using multi-frequency codes
  • H04L27/2601—Multicarrier modulation systems
  • H04L27/2647—Arrangements specific to the receiver only
• • H—ELECTRICITY
  • H04—ELECTRIC COMMUNICATION TECHNIQUE
  • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
  • H04L27/00—Modulated-carrier systems
  • H04L27/26—Systems using multi-frequency codes
  • H04L27/2601—Multicarrier modulation systems
  • H04L27/2647—Arrangements specific to the receiver only
  • H04L27/2649—Demodulators
  • H04L27/26524—Fast Fourier transform [FFT] or discrete Fourier transform [DFT] demodulators in combination with other circuits for demodulation
• • H—ELECTRICITY
  • H04—ELECTRIC COMMUNICATION TECHNIQUE
  • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
  • H04L27/00—Modulated-carrier systems
  • H04L27/26—Systems using multi-frequency codes
  • H04L27/2601—Multicarrier modulation systems
  • H04L27/2647—Arrangements specific to the receiver only
  • H04L27/2655—Synchronisation arrangements
  • H04L27/2657—Carrier synchronisation
• • H—ELECTRICITY
  • H04—ELECTRIC COMMUNICATION TECHNIQUE
  • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
  • H04L27/00—Modulated-carrier systems
  • H04L27/26—Systems using multi-frequency codes
  • H04L27/2601—Multicarrier modulation systems
  • H04L27/2647—Arrangements specific to the receiver only
  • H04L27/2655—Synchronisation arrangements
  • H04L27/2662—Symbol synchronisation
• • H—ELECTRICITY
  • H04—ELECTRIC COMMUNICATION TECHNIQUE
  • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
  • H04L27/00—Modulated-carrier systems
  • H04L27/26—Systems using multi-frequency codes
  • H04L27/2601—Multicarrier modulation systems
  • H04L27/2647—Arrangements specific to the receiver only
  • H04L27/2655—Synchronisation arrangements
  • H04L27/2662—Symbol synchronisation
  • H04L27/2665—Fine synchronisation, e.g. by positioning the FFT window
• • H—ELECTRICITY
  • H04—ELECTRIC COMMUNICATION TECHNIQUE
  • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
  • H04L1/00—Arrangements for detecting or preventing errors in the information received
  • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
  • H04L1/0056—Systems characterized by the type of code used
  • H04L1/0064—Concatenated codes
  • H04L1/0065—Serial concatenated codes

Definitions

• This invention relates to receivers of electromagnetic signals employing multicar ⁇ er modulation More particularly this invention relates to a digital receiver which is implemented on a single VLSI chip for receiving transmissions employing orthogonal frequency division multiplexing, and which is suitable for the reception of digital video broadcasts
• Coded orthogonal frequency division multiplexing (“COFDM”) has been proposed for digital audio and digital video broadcasting, both of which require efficient use of limited bandwidth, and a method of transmission which is reliable in the face of several effects
• COFDM Coded orthogonal frequency division multiplexing
• the impulse response of a typical channel can be modeled as the sum of a plurality of Dirac pulses having different delays
• Each pulse is subject to a multiplication factor, in which the amplitude generally follows a Rayleigh law
• Such a pulse train can extend over several microseconds, making unencoded transmission at high bit rates unreliable
• other major difficulties in digital terrestrial transmissions at high data rates include multipath propagation, and adjacent channel interference, where the nearby frequencies have highly correlated signal
• n 0
• guard interval so chosen is large enough to absorb any intersymbol interference, and is established by preceding each symbol by a replication of a portion of itself.
• the replication is typically a cyclic extension of the terminal portion of the symbol.
• a data symbol 4 has an active interval 6 which contains all the data transmitted in the symbol.
• the terminal portion 8 of the active interval 6 is repeated at the beginning of the symbol as the guard interval 10.
• the COFDM signal is represented by the solid line 12. It is possible to cyclically repeat the initial portion of the active interval 6 at the end of the symbol.
• a serial data stream 14 is converted to a series of parallel streams 16 in a serial-to-parallel converter 18.
• Each of the parallel streams 16 is grouped into x bits each to form a complex number, where x determines the signal constellation of its associated parallel stream.
• pilot carriers are inserted via a signal mapper 22 for use in synchronization and channel estimation in the receiver.
• the pilot carriers are typically of two types. Continual pilot carriers are transmitted in the same location in each symbol, with the same phase and amplitude. In the receiver, these are utilized for phase noise cancellation, automatic frequency control, and time/sampling synchronization.
• Scattered pilot carriers are distributed throughout the symbol, and their location typically changes from symbol to symbol. They are primarily useful in channel estimation.
• the complex numbers are modulated at baseband by the inverse fast fourier transform ("IFFT") in block 24.
• IFFT inverse fast fourier transform
• a guard interval is then inserted at block 26.
• the discrete symbols are then converted to analog, typically low-pass filtered, and then upconverted to radiofrequency in block 28.
• the signal is then transmitted through a channel 30 and received in a receiver 32.
• the receiver applies an inverse of the transmission process to obtain the transmitted information.
• an FFT is applied to demodulate the signal.
• Quadrature amplitude modulation Various levels of quadrature amplitude modulation (“QAM”) are supported, as are different inner code rates, in order to balance bit rate against ruggedness.
• the system is intended to accommodate a transport layer according to the Moving Picture Experts Group ("MPEG”), and is directly compatible with M P E G - 2 c o d e d TV s i g n a l s ( I S O / I E C 1 38 1 8 ) .
• MPEG Moving Picture Experts Group
• M P E G - 2 c o d e d TV s i g n a l s ( I S O / I E C 1 38 1 8 ) In the noted European Telecommunications Standard data carriers in a COFDM frame can be either quadrature phase shift keyed ("QPSK”), 16-QAM, 64-QAM, non- uniform 16-QAM, or non-uniform 64-QAM using Gray mapping.
• QPSK quadrat
• phase disturbances are of two types. First, noisy components which disturb neighbor carriers in a multicarrier system are called the “foreign noise contribution" ("FNC"). Second, a noisy component which disturbs its own carrier is referred to as the "own noise contribution”.
• FNC foreign noise contribution
• the position of ideal constellation samples are indicated by "x" symbols 34.
• the effect of foreign noise contribution is stochastic, resulting in Gaussianlike noise.
• Samples perturbed in this manner are indicated on Fig. 5 as circles 36.
• the effects of the own noise contribution is a common rotation of all constellation points, indicated as a displacement between each "x" symbol 34 and its associated circle 36. This is referred to as the "common phase error", which notably changes from symbol to symbol, and must therefore be recalculated each symbol period T s .
• the common phase error may also be interpreted as a mean phase deviation during the symbol period T s .
• the invention provides a digital receiverfor multicar ⁇ ersignals that are transmitted by orthogonal frequency division multiplexing
• the multicarrier signal carries a stream of data symbols having an active interval, and a guard interval in which the guard interval is a replication of a portion of the active interval
• an analog to digital converter is coupled to a front end amplifier
• An l/Q demodulator is provided for recovering in phase and quadrature components from data sampled by the analog to digital converter, and an automatic gam control circuit is coupled to the analog to digital converter
• a low pass filter circuit accepting I and Q data from the l/Q demodulator, the I and Q data are decimated and provided to a resampling circuit
• An interpolator in the resampling circuit accepts the decimated I and Q data at a first rate and outputs resampled I and Q data at a second rate
• An FFT window synchronization circuit is coupled to the resampling circuit for locating a boundary of the guard interval
• the FFT window synchronization circuit has a first delay element accepting currently arriving resampled I and Q data, and outputting delayed resampled I and Q data
• a subtracter produces a signal representative of the difference between the currently arriving resampled I and Q data and the delayed resampled I and Q data
• the subtracter output signal is converted to a signal having a unipolar magnitude, which is preferably the absolute value of the signal provided by the subtracter
• a second delay element stores the output signal of the first circuit, and a third delay element receives the delayed output of the second delay element
• a statistical relationship is calculated between data stored in the second delay element and data stored in the third delay element
• the output of the FFT window synchronization circuit is representative of the statistical relationship Preferably the statistical relationship is the F ratio.
• the FFT processor is capable of operation in a 2K mode and in an 8K mode.
• the FFT processor has an address generatorfor the memory of each stage, which accepts a signal representing the order dependency of a currently required multiplicand, and generates an address of the memory wherein the currently required multiplicand is stored.
• each multiplicand is stored in the lookup table in order of its respective order dependency for multiplication by the complex coefficient multiplier, so that the order dependencies of the multiplicands define an incrementation sequence.
• the address generator has an accumulator for storing a previous address that was generated thereby, a circuit for calculating an incrementation value of the currently required multiplicand responsive to the incrementation sequence, and an adder for adding the incrementation value to the previous address.
• multiplicands are stored in row order, wherein in a first row a first incrementation sequence is 0, in a second row a second incrementation sequence is 1 , in a third row first and second break points B1 , B2 of a third incrementation sequence are respectively determined by the relationships
• the receiver provides channel estimation and correction circuitry.
• Pilot location circuitry receives a transformed digital signal representing a frame from the FFT processor, and identifies the position of pilot carriers therein.
• the pilot carriers are spaced apart in a carrier spectrum of the transformed digital signal at intervals K and have predetermined magnitudes.
• the pilot location circuitry has a first circuit for computing an order of carriers in the transformed digital signal, positions of said carriers being calculated modulo K.
• a correlation circuit is provided for correlating K sets of accumulated magnitude values with the predetermined magnitudes In the correlation a first member having a position calculated modulo K in of each of the K sets is uniquely offset from a start position of the frame
• the pilot location circuitry also has a bit reversal circuit for reversing the bit order of the transformed digital signal
• amplitudes are used to represent the magnitudes of the carriers
• the magnitudes of the carriers and the predetermined magnitudes are absolute values
• the correlation circuitry also has a peak tracking circuit for determining the spacing between a first peak and a second peak of the K sets of accumulated magnitudes, wherein the first peak is the maximum magnitude, and the second peak is the second highest magnitude
• the channel estimation and correction circuitry also has an interpolating filter for estimating the channel response between the pilot carriers, and a multiplication circuit for multiplying data carriers output by the FFT processor with a correction coefficient produced by the interpolating filter
• the channel estimation and correction circuitry also has a phase extraction circuit accepting a data stream of phase-uncorrected I and Q data from the FFT processor, and producing a signal representative of the phase angle of the uncorrected data
• the phase extraction circuit includes an accumulator for the phase angles of succeeding phase-uncorrected I and Q data
• the channel estimation and correction circuitry includes an automatic frequency control circuit coupled to the phase extraction circuit, in which a memory stores the accumulated common phase error of a first symbol carried in the phase-uncorrected I and Q data
• An accumulator is coupled to the memory and accumulates differences between the common phase error of a plurality of pilot carriers in a second symbol and the common phase error of corresponding pilot carriers in the first symbol
• the output of the accumulator is filtered, and coupled to the l/Q demodulator
• the coupled output of the accumulator of the automatic frequency control circuit is enabled in the l/Q demodulator only during reception of a guard interval therein
• the channel estimation and correction circuitry also has an automatic sampling rate control circuit coupled to the phase extraction circuit, in which a memory stores the individual accumulated phase errors of pilot carriers in a first symbol carried in the phase-uncorrected I and Q data
• An accumulator is coupled to the memory and accumulates differences between the phase errors of individual pilot carriers in a second symbol and phase errors of corresponding pilot carriers in the first symbol to define a plurality of accumulated intersymbol carrier phase error differentials.
• a phase slope is defined by a difference between a first accumulated intersymbol carrier phase differential and a second accumulated intersymbol carrier phase differential.
• the output of the accumulator is filtered and coupled to the l/Q demodulator.
• the sampling rate control circuit stores a plurality of accumulated intersymbol carrier phase error differentials and computes a line of best fit therebetween.
• the coupled output signal of the accumulator of the automatic sampling rate control circuit is enabled in the resampling circuit only during reception of a guard interval therein.
• a common memory for storing output of the phase extraction circuit is coupled to the automatic frequency control circuit and to the automatic sampling rate control circuit.
• phase extraction circuit also has a pipelined circuit for iteratively computing the arctangent of an angle of rotation according to the series
• x is a ratio of the phase-uncorrected I and Q data.
• the pipelined circuit includes a constant coefficient multiplier, and a multiplexerfor selecting one of a plurality of constant coefficients of the series. An output of the multiplexer is connected to an input of the constant coefficient multiplier.
• the pipelined circuit has a multiplier, a first memory for storing the quantity x 2 , wherein the first memory is coupled to a first input of the multiplier, and has a second memory for holding an output of the multiplier.
• a feedback connection is provided between the second memory and a second input of the multiplier.
• the pipelined circuit also has a third memory for storing the value of the series. Under direction of a control circuit coupled to the third memory, the pipeline circuit computes N terms of the series, and also computes N+1 terms of the series.
• An averaging circuit is also coupled to the third memory and computes the average of N terms and N+1 terms of the series.
• Data transmitted in a pilot carrier of the multicarrier signal is BCH encoded according to a code generator polynomial h(x).
• a demodulator operative on the BCH encoded data is provided, which includes an iterative pipelined BCH decoding circuit.
• the BCH decoding circuit is circuit coupled to the demodulator It forms a Galois Field of the polynomial, and calculates a plurality of syndromes therewith
• the BCH decoding circuit includes a plurality of storage registers, each storing a respective one of the syndromes, and a plurality of feedback shift registers, each accepting data from a respective one of the storage registers
• the BCH decoding circuit has a plurality of Galois field multipliers Each of the multipliers is connected in a feedback loop across a respective one of the feedback shift registers and multiplies the output of its associated feedback shift register by an alpha value of the Galois Field An output Galois field multiplier multiplies the outputs of two of the feedback shift registers
• a logical network forms an
• the output Galois field multiplier has a first register initially storing a first multiplicand A, a constant coefficient multiplier connected to the first register for multiplication by a value ⁇ An output of the constant coefficient multiplier is connected to the first register to define a first feedback loop, whereby in a kth cycle of clocked operation the first register contains a Galois field product A ⁇ k A second register is provided for storing a second multiplicand B An AND gate is connected to the second register and to the output of the constant coefficient multiplier An adder has a first input connected to an output of the AND gate An accumulator is connected to a second input of the adder, and the Galois field product AB is output by the adder
• the invention provides a method for the estimation of a frequency response of a channel It is performed by receiving from a channel an analog multicarrier signal that has a plurality of data carriers and scattered pilot carriers The scattered pilot carriers are spaced apart at an interval N and are transmitted at a power that differs from the transmitted power of the data carriers
• the analog multicarrier signal is converted to a digital representationthereof
• a Fou ⁇ ertransform is performed on the digital representation of the multicarrier signal to generate a transformed digital signal
• the bit order of the transformed digital signal is reversed to generate a bit-order reversed signal
• Magnitudes of the carriers in the bit-order reversed signal are cyclically accumulated in N accumulators, amd the accumulated magnitudes are correlated with the power of the scattered pilot carriers Responsive to the correlation, a synchronizing signal is generated that identifies a carrier position of the multicarrier signal, preferably an active carrier.
• the step of accumulating magnitudes is performed by adding absolute values of a real component of the bit-order reversed signal to respective absolute values of imaginary components thereof to generate sums, and respectively storing the sums in the N accumulators.
• the step of correlating the accumulated magnitudes also is performed by identifying a first accumulator having the highest of the N values stored therein, which represents a first carrier position, and by identifying a second accumulator which has the second highest of the N values stored therein, which represents a second carrier position. The interval between the first carrier position and the second carrier position is then determined.
• the position of a carrier of a first symbol in the bit-order reversed signal is compared with a position of a corresponding carrier of a second symbol therein.
• interpolation is performed between pilot carriers to determine correction factors for respective intermediate data carriers disposed therebetween, and respectively adjusting magnitudes of the intermediate data carriers according to the correction factors.
• a mean phase difference is determined between corresponding pilot carriers of successive symbols of the transformed digital signal.
• a first control signal representing the mean phase difference is provided to control the frequency of reception of the multicarrier signal. The first control signal is enabled only during reception of a guard interval.
• a line of best fit is determined for the inter-symbol phase differences of multiple carriers to define a phase slope.
• Fig. 1 illustrates the spectrum of a COFDM subchannel
• Fig. 2 shows a frequency spectrum for multiple carriers in a COFDM signal
• Fig. 3 is a diagram of a signal according to COFDM and shows a data symbol format
• Fig. 4 is a block diagram illustrating an FFT based COFDM system
• Fig. 5 illustrates certain perturbations in a COFDM signal constellation
• Fig. 6 is a flow diagram of a method of timing synchronization according to a preferred embodiment of the invention
• Fig 7 is a plot of an F ratio test performed on several data symbols for coarse timing synchronization
• Fig 8 is a plot of an incomplete beta function for different degrees of freedom
• Fig 9 is a plot helpful in understanding a test of statistical significance according to the invention.
• Fig 10 is an electrical schematic of a synchronization circuit according to an alternate embodiment of the invention.
• Fig 11 is an electrical schematic of a synchronization circuit according to another alternate embodiment of the invention
• Fig 12 is a block diagram of a single-chip embodiment of a digital receiver in accordance with the invention
• Fig 13 is a block diagram illustrating the front end of the digital receiver shown in Fig 12 in further detail
• Fig 14 is a block diagram illustrating the FFT circuitry, channel estimation and correction circuitry of the digital receiver shown in Fig 12,
• Fig 15 is a block diagram illustrating another portion of the digital receiver shown in Fig 12,
• Fig 16 is a more detailed block diagram of the channel estimation and correction circuitry shown in Fig 14, Fig 17 is a schematic of the automatic gam control circuitry of the digital receiver shown in Fig 12,
• Fig 18 is a schematic of the l/Q demodulator of the digital receiver shown in Fig 12,
• Fig 19 illustrates in greater detail a low pass filter shown in Fig 13, Fig 20 shows the response of the low pass filter shown in Fig 19,
• Fig 21 shows the resampling circuitry of the digital receiver shown in Fig 12,
• Fig 22 illustrates a portion of an interpolator in the resampling circuitry of Fig 21 .
• Fig 23 is a more detailed block diagram of the FFT window circuitry shown in Fig 14, Fig 24 is a schematic of a butterfly unit in the FFT calculation circuitry shown in
• Figs 25 and 26 are schematics of butterfly units in accordance with the prior art
• Fig 27 is a schematic of a radix 2 2 + 2 FFT processor in accordance with the invention
• Fig 28 is 32 point flow graph of the FFT processor shown in Fig 27,
• Fig 29 is a schematic of a configurable 2K 8K radix 2 2 +2 single path, delay feedback pipelined FFT processor in accordance with the invention
• Fig 30 is a detailed schematic of a complex multiplier used in the circuitry shown in Fig 29,
• Fig 31 is a detailed schematic of an alternateembodimentof a complex multipliers used in the circuitry shown in Fig 29,
• Fig 32 is another diagram illustrating the organization of the twiddle factors for each of the multipliers in the circuitry shown in Fig 29,
• Fig 33 illustratesthe organization of the twiddle factors for each of the multipliers in the circuitry shown in Fig 29,
• Fig 34 is a schematic of address generator used in the circuitry shown in Fig 29, Fig 35 is a schematic of a generalization of the address generator shown in Fig
• Fig 36 is a flow chart illustrating the process of pilot location conducted by the channel estimation and correction circuitry shown in Fig 16,
• Fig 37 is a flow chart of an embodiment of the pilot localization procedure according to the invention.
• Fig 38 is a more detailed block diagram of the tps sequence block of the circuitry shown in Fig 14,
• Fig 39 is a schematic of a BCH decoder used in the tps processing circuitry shown Fig 40 is a more detailed schematic of a Galois field multiplier shown in Fig 39,
• Fig 41 is a block diagram genencally illustrating the automatic sampling control and automatic frequency control loops of the digital receiver shown in Fig 12,
• Fig 42 is a more detailed block diagram of the automatic sampling control and automatic frequency control loops shown in Fig 41
• Fig 43 is a more detailed block diagram of the phase extract block of the circuitry shown in Fig 42,
• Fig 44 is a schematic of the circuitry employed to calculate an arctangent in the block diagram shown in Fig 43,
• Fig 45 is a plot of the square error at different values of ⁇ of the Taylor expansion to 32 terms
• Fig 46 is a plot of the square error at different values of ⁇ of the Taylor expansion to 31 terms
• Fig 47 is a plot of the square error at different values of ⁇ of the average of the Taylor expansion to 31 and 32 terms
• Fig 48 is a plot of the phase differences of pilot carriers with a line of best fit shown
• Fig. 49 is a more detailed block diagram an alternate embodiment of the automatic sampling control and automatic frequency control loops shown in Fig. 41 ;
• Fig. 50 illustrates a coded constellation format used in the demapping circuitry of Fig. 15;
• Fig. 51 illustratesthe conversion of l,Q data to binary data value using the format shown in Fig. 50;
• Fig. 52 is a more detailed block diagram of the symbol deinterleaving circuitry shown in Fig. 15;
• Fig. 53 is a more detailed block diagram of the bit deinterleaving circuitry shown in Fig. 15;
• Fig. 54 illustratesthe conversion from a coded constellation format to a 24 bit soft l/Q format by the bit deinterleaving circuitry shown in Fig. 53;
• Fig. 55 is a more detailed block diagram of the microprocessor interface of the receiver shown in Fig. 12;
• Fig. 56 is a more detailed block diagram of the system controller of the receiver shown in Fig. 12; and
• Fig. 57 is a state diagram relating to channel acquisition in the system controller of the receiver shown in Fig. 56. Alignment of The FFT Window
• a statistical method is applied to COFDM signals to find the end of the guard interval 10. This method is explained with reference to the above noted European Telecommunications Standard, but is applicable to many forms of frequency division multiplexing having prefixed or postfixed guard intervals. It allows the receiver 32 to find the end of the guard interval given only the received sampled complex signal ( solid line 12) and the size of the active interval 6 . The method relies on the fact that the guard interval 10 is a copy of the last part of the data symbol 4.
• the guard interval 10 and the last part of the data symbol 4 will differ. If the errors introduced are random then a statistical method can be applied.
• the received complex signal is sampled at a rate which is nearly identical to that used in the transmitter. A difference signal is found for a pair of received samples which are separated by a period of time which is as close as possible to the active interval 6. This period should be equal to the size of the fast fourier transform ("FFT") being applied (i.e. 2048 or 8192 samples).
• FFT fast fourier transform
• samples of the input signal are stored over an interval which includes at least one symbol period T s .
• the dispersion of the difference signal S is calculated over a block of samples.
• the block is moved back in time over a number of samples, n, and the dispersion is recalculated.
• These two blocks are referred to herein as "comparison blocks”.
• the ratio of a current dispersion in a first comparison block to the dispersion in a previous comparison block is found.
• the F ratio significance test is used to find significant differences in the dispersions of the two comparison blocks.
• the F ratio is defined as
• VAR(i) is the variance of a block of values of length N samples.
• F ratio significance test is used in the preferred embodiment, other functions of the two dispersion values which give a signal relating to the change in dispersion could be used. There are many such functions.
• An advantage of the F ratio is that for a random input signal it has a known probability distribution, allowing convenient statistical analysis for purposes of performance analysis and system design. Also the F ratio intrinsically normalizes the signal, making the result independent of the signal level. The method is disclosed with reference to Fig. 6, in which a first member of a sample pair in a current evaluation block is measured at step 38. A delay of one active interval 6 ( Fig. 3) is experienced in step 40.
• step 42 A second member of the sample pair is measured in step 42, and the difference between the first and second member is determined and stored in step 44.
• the end of the current block is tested at decision step 46.
• the size of the evaluation block should not exceed the length of a guard interval, and may be considerably smaller. In the event the end of the current block has not yet been reached, another sample is acquired at step 48, and control returns to step 38.
• step 50 the dispersion of the current block is measured in step 50, and is treated as one of two comparison blocks of data.
• a test is made at decision step 52 to determine if a group of two comparison blocks have been evaluated. If this test is negative, then another block of data is acquired in step 54, after which control returns to step 38. The other block of data need not be contiguous with the block just completed.
• step 52 the F ratio is computed for the group of two comparison blocks at step 56.
• the results obtained in step 56 are submitted to peak detection in step 60. Peak detection optionally includes statistical tests of significance, as is explained hereinbelow.
• H 0 has very low probability it can be rejected, which would correspond to detection of the start or end of the guard interval From the way the COFDM symbol is constructed H 0 is expected to be true for comparison blocks lying entirely within the guard interval or within the active interval, but false when the comparison blocks straddle a boundary at the start or end of the guard interval If comparison blocks of random samples are drawn from the same population then the probability of F is given by
• v 2 T v,F and v 1 and v 2 are the number of degrees of freedom with which the first and second dispersions are estimated
• Equation (12) The formula for dispersion given in Equation (12) would require a multiplier for implementation in silicon.
• the calculation of F is a division in which the (N-1 ) normalisation constants cancel out as long as the two blocks have the same size. Accurate multiplication and division can be expensive in silicon.
• simplifications have been implemented which give less accurate, but still viable, values for F. S, can be assumed to have zero mean so it is not necessary to calculate the mean from the block of samples. This also increases the number of degrees of freedom from (N-1) to N. Instead of calculating variance using the standard sum of squares formula, the dispersion can be estimated by the mean absolute deviation.
• the formula for VAR(i) becomes
• Equation (16) The (1/N) factor divides out in the calculation of F if the two blocks have the same size. But there still remains the division of the two dispersions and the squaring required. These can be tackled using logarithms to the base 2. Substituting from Equation (16) into Equation (11) gives
• the calculation can thus be reduced to require only addition and subtraction arithmetic operations.
• the above described method is employed using either the real or the imaginary parts of the signal instead of the modulus. This embodiment achieves economy in hardware.
• n parameter of equation (11) has been optimized.
• the two blocks straddle more of the transition to the active interval, giving a well-defined increase in the dispersion.
• n>2 has the drawback that several successive points will give significant increases as the later block travels up to the boundary. This small problem is easily overcome by introducing a dead period after detection of the boundary. That is, once a spike has been detected a set of samples equal to the size of the FFT window is accepted before further attempts are made to locate another spike. The dead period has the added benefit of not introducing false spikes.
• the spikes 66, 68 increase, whilst the H 0 noisy F signal remain much the same.
• a third alternateembodimentof the invention is disclosed with reference to Fig 10 which schematically illustrates a timing synchronization circuit 70
• the circuit accepts a complex input signal 72, and includes a circuit module 74 which develops the modulus of its input, which is taken from node 83
• the circuit module 74 insures that the value being subsequently processed is an unsigned number
• the input to the circuit module 74 is a difference signal which is developed by a subtracter 75 which takes as inputs the input signal 72 and a delayed version of the input signal 72 which has been processed through a delay circuit 79, preferably realized as a FIFO 77 of length L, where L is the size of the FFT window
• the circuit module 74 can be modified, and can be any known circuit that removes the sign of the output of the subtracter 75, or sets the sign so that the outputs accumulate
• the signal on line 88 is an index into a lookup table, preferably implemented as a read-only-memory ("ROM"), and shown as ROM 90
• ROM 90 The address of the ROM 90 contains the logarithm to the base 2 of the magnitude of the signal on line 88, which then appears at node 92
• the node 92 is connected to a subtracter 94, and to a delay circuit, shown as FIFO 98, which is used to develop the denommatorof the middle term of equation (17)
• the subtracter 94 produces a signal which is compared against the log 2 of a predetermined threshold value F UM , T in a comparison circuit 106, shown for simplicity as an adder 108 connected to a comparator 110
• the output signal SYNC 112 is asserted when the boundary of a guard interval has been located
• a timing synchronization circuit 1 16 is similar to the timing synchronization circuit 70, except now the delay circuit 79 is realized as the FIFO 77, and another FIFO 100, one of which is selected by a multiplexer 102 Both of the FIFOs 77, 100 provide the same delay, however the capacities of the two are different
• the FIFO 100 provides for storage of samples taken in an interval equal to the size of the FFT window, and is normally selected in a first mode of operation, for example during channel acquisition, when it is necessary to evaluate an entire symbol in order to locate a boundary of a guard interval in the noted European Telecommunications standard, up to 8K of data storage is required, with commensurate resource requirements During subsequent operation, the approximate location of the guard interval boundaries will be known from the history of the previous symbols In a second mode of operation, It is therefore only necessary to evaluate a much smaller interval in order to verify the exact
• a radio frequency signal is received from a channel such as an antenna 128, into a tuner 130 which is conventional, and preferably has first and second intermediate frequency amplifiers
• the output of the second intermediate frequency amplifier (not shown), is conducted on line 132 to an analog to digital converter 134
• the digitized output of the analog to digital converter 134 is provided to block 136 in which l/Q demodulation, FFT, channel estimation and correction, inner and outer deinterleaving, and forward error correction are conducted
• AGC automatic gain control
• l/Q samples at are received by an IQ demodulator 144 from the analog to digital converter 134 (Fig 12) on a bus 146 at a rate of 20 megasamples per second
• An AGC circuit 148 also takes its input from the bus 146
• a frequency rate control loop is implemented using a numerically controlled oscillator 150, which receives frequency error signals on line 152, and frequency error update information on line 154. Frequency and sampling rate control are achieved in the frequency domain, based on the pilot carrier information.
• the frequency error signals which are derived from the pilot carriers, and the frequency error update information will both be disclosed in further detail shortly.
• the I and Q data output from the IQ demodulator 144 are both passed through identical low pass filters 156, decimated to 10 megasamples per second, and provided to a sine interpolator 158.
• Sample rate control is achieved using a numerically controlled oscillator 160 which receives sample rate control information derived from the pilot signals on line 162, and receives sample error update timing information on line 164.
• Fig. 14 acquisition and control of the FFT window are performed in block 166, which receives signals from the sine interpolator 158 (Fig. 13).
• the FFT computations are performed in FFT calculation circuitry 168.
• Channel estimation and correction are performed in channel estimation and correction block 170, and involves localization of the pilot carriers, as will be described below in greater detail.
• the tps information obtained during pilot localization is processed in tps sequence extract block 172.
• Uncorrected pilot carriers are provided by the circuitry of channel estimation and correction block 170 to correction circuitry 174, which develops sampling rate error and frequency error signals that are fed back to the numerically controlled oscillators 150, 160 (Fig. 13).
• corrected I and Q data output from channel estimation and correction block 170 are provided to demapping circuitry 176.
• the current constellation and hierarchical constellation parameters, derived from the tps data, are also input on lines 178, 180.
• the resulting symbols are deinterleaved in symbol deinterleaver 182, utilizing a 1512 x 13 memory store. One bit of each cell in the memory store is used to flag carriers having insufficient signal strength for reliable channel correction.
• Bit deinterleaver 184 then provides deinterleaved I and Q data to a Viterbi Decoder 186, which discards the flagged carriers, so that unreliable carriers do not influence traceback metrics.
• a Forney deinterleaver 188 accepts the output of the Viterbi Decoder 186 and is coupled to a Reed-Solomon decoder 190.
• the forward error correction provided by the Viterbi and Reed-Solomon decoders is relied upon to recover lost data in the case of flagged carriers.
• a mean value is calculated in block 192 for uncorrected carriers with reference to the previous symbol.
• Data carriers whose interpolated channel response falls below some fraction, preferably 0.2, of this mean will be marked with a bad_carrier flag 194.
• the bad_carrier flag 194 is carried through the demapping circuitry 176, symbol deinterleaver 182, and bit deinterleaver 184, to the Viterbi Decoder 186 where it is used to discard data relating to the unreliable carriers
• the parameters used to set the bad_carr ⁇ er flag 194 can be varied by the microprocessor interface 142
• An output interface 196 produces an output which can be an MPEG-2 transport stream
• the symbol deinterleaver 182, and the bit deinterleaver 184 are conventional
• the Viterbi decoder 186, Forney deinterleaver 188, Reed-Solomon decoder 190, and the output interface 196 are conventional They can be the components disclosed in copending Application No 638,273, entitled "An Error Detection and Correction System for a Stream of Encoded Data", filed April 26, 1996, Application No 480,976, entitled “Signal Processing System", filed June 7, 1995, and Application No 481 ,107, entitled "S
• the input and output signals and the register map of the multicarrier digital receiver 126 are described in tables 4, and 5 respectively Automatic Gain Control
• a Sigma-Delta modulator 200 is used to provide a signal which can be used as a gain control to a tuner once it has been low-pass filtered by an external R-C network
• K is a constant (normally K «1 ) which determines the gam in the AGC control loop
• the mean value can be determined from the statistics of Gaussian noise, which is a close approximation to the properties of the COFDM input signal, where the input data is scaled to +/-1
• the control voltage signal 202 is set back to its initial value when the signal resync 204 is set low, indicating a channel change or some other event requiring resynchronization
• the function of the IQ demodulator 144 (Fig 13) is to recover m-phase and quadrature components of the received sampled data It is shown in further detail in Fig 18
• the numerically controlled oscillator 150 generates m-phase and quadrature sinusoids at a rate of (32/7) MHz, which are multiplied with data samples in multipliers 206
• the address generator 208 advances the phase linearly
• the frequency error input 210 increments or decrements the phase advance value
• the samples are multiplied with the sinusoids in the multipliers 206us ⁇ ng 10 bit x 10 bit multiply operations
• the IQ demodulator 144 is operated at 20 MHZ and then retimed to 40MHz in retiming block 212
• the IQ demodulator 144 is operated at 40MHz, in which case the retiming block 212 is omitted
• Sinusoids are generated by the address generator 208 on lines 214, 216
• the phase value is employed as an address into a lookup table ROM 218 Only quarter cycles are stored in the lookup table ROM 218 to save area Full cycles can be generated from the stored quarter cycles by manipulating the data from the ROM 218 and inverting the data in the case of negative cycles
• Two values are read from the lookup table ROM 218 for every input sample - a cosine and a sine, which differ in phase by 90 degrees
• the input and output signals of the IQ demodulator 144 are described in tables 9 and 10 respectively Low Pass Filter
• the purpose of the low pass filters 156 (Fig 13) is to remove aliased frequencies after IQ demodulation - frequencies above the 32/7 MHz second IF are suppressed by 40dB I and Q data are filtered separately
• the output data is decimated to 10 megasamples per second ("Msps") because the filter removes any frequencies above 1/4 of the original 20 Msps sampling rate
• the filter is constructed with approximately 60 taps which are symmetrical about the center allowing the filter structure to be optimized to reduce the number of multipliers 220
• Fig 19 is a block diagram of one of the low pass filters 156, the other being identical Fig 19 shows a representative symmetrical tap 222, and a center tap 224 The required filter response of the low pass filters 156 is shown in Fig 20
• the input and output signals of the low pass filters 156 are described in tables 11 and 12 respectively Resampling
• the purpose of resampling is to reduce the 10 Msps data stream output from the low pass filters 156 down to a rate of (64/7) Msps, which is the nominal sample rate of the terrestrial digital video broadcasting ("DVB-T") modulator at the transmitter.
• Resampling is accomplished in the sine interpolator 158, and the numerically controlled oscillator 160.
• the latter generates a nominal 64/7 MHZ signal.
• the resampling circuitry is shown in further detail in Fig. 21.
• the numerically controlled oscillator 160 generates a valid pulse on line 226 and a signal 228 representing the interpolation distance for each 40MHz clock cycle in which a 64/7MHz sample should be produced.
• the interpolation distance is used to select the appropriate set of interpolating filter coefficients which are stored in coefficient ROMs 230. It should be noted that only the sine interpolatorfor I data is illustrated in Fig. 21.
• the structures for Q data are identical.
• the sine interpolation circuit disclosed in our noted Application No. 08/638,273 is suitable, with appropriate adjustment of the operating frequencies.
• the function of the FFT Window function is to locate the "active interval" of the COFDM symbol, as distinct from the "guard interval". This function is referred to herein for convenience as "FFT Window".
• the active interval contains the time domain representation of the 2048 carriers which will be recovered by the FFT itself.
• the FFT window operates in two modes; Acquisition and Tracking.
• Acquisition mode the entire incoming sample stream is searched for the guard interval/active interval boundary. This is indicated when the F-ratio reaches a peak, as discussed above.
• window timing is triggered and the incoming sample stream is searched again for the next guard interval/active interval boundary.
• the length ofthe guard interval is known and the expected position of the next guard/active boundary can be predicted.
• the FFT window function then switches to tracking mode.
• This embodiment is similar to the fourth alternate embodiment discussed above in respect of the tracking mode.
• tracking mode only a small section of the incoming sample stream around the point where the guard/active boundary is expected to be is searched.
• the position of the active interval drifts slightly in response to IF frequency and sampling rate offsets in the front-end before the FFT is calculated. This drift is tracked and FFT window timing corrected, the corrections being inserted only during the guard interval
• a threshold level set from statistical considerations, is applied to the F-ratio signal (see Fig 7) to detect the negative and positive spikes which occur at the start and end of the guard interval respectively The distance between the spikes is used to estimate the guard interval size Repeated detection of the positive spikes is used to confirm correct synchronization
• the F-ratio signal becomes noisy and the spikes are not always reliably detectable
• peak detection is used to find the spikes in the F-ratios It has been found that a fixed threshold is reliable only at or exceeding about a car ⁇ er- to-noise ("C/N") ratio of 12 dB Peak detection is generally more sensitive and more specific, with generally reliable operation generally at 6 - 7 dB
• C/N car ⁇ er- to-noise
• Peak detection is generally more sensitive and more specific, with generally reliable operation generally at 6 - 7 dB
• the maxima should occur at the end of the guard interval
• the difference in time between the two maxima is checked against the possible guard interval sizes With an allowance for noise, the difference in time indicates the most likely guard interval size and the maxima themselves provide a good indication of the start of the active part of the symbol
• this process is iterated for several symbols to confirm detection, and is expected to improve performance when the C/N ratio is low
• the data stream is passed to accumulators 242, 244, each holding 64 moduli Conversion to logarithms and subtraction of the logarithms is performed in block 246
• the peaks are detected in peak detector block 248
• Averaging of the symbol peaks is performed in block 250 In noisy conditions, the maxima may be due to noise giving possibly inaccurate indications of the guard interval length and the start of the active symbol
• the general strategy to cope with this is to perform a limited number of retries
• the variance estimates are calculated from 64 values only Under noisy conditions, the variance estimates become very noisy and the spikes can become obscured In an optional variation this problem is solved by obtaining more values for the variance estimate, by storing the variance estimate during acquisition for each of the possible T+G max points in the storage block 256
• the variance estimates themselves may be formed by accumulating variances for each point, and then filtering in time over a number of symbols
• a moving average filter or an infinite impulse response (“MR") filter is suitable
• a moving run of symbols, preferably between 16 and 32, are integrated in block 252, which increases the reliability of peak detection under noisy conditions
• the storage block 256 holding the integrated F-ratio values is searched to find the maximum value This is of length T+G max , where G max is the maximum guard interval size, T/4
• the memory for storage block 256 is dynamically allocated, depending on whether acquisition mode or tracking mode is operative Any unused memory is released to other processes Similarly in tracking mode the integrated data stream is
• the discrete Fourier transform (“DFT”) has the well known formula
• N the number of points in the DFT
• x(k) the kth output in the frequency domain
• x(n) the nth input in the time domain
• W is also known as a "twiddle factor"
• N 1000 the DFT imposes a heavy computational burden and becomes impractical
• the continuous Fourier transform when computed according to the well known FFT algorithm, breaks the original N-point sequence into two shorter sequences
• the FFT is implemented using the basic butterfly unit 258 as shown in Fig 24
• the butterfly unit 258 exploits the fact that the powers of W are really just complex additions or subtractions
• a real-time FFT processor realized as the FFT calculation circuitry 168 (Fig 14) is a key component in the implementation of the multicarrier digital receiver 126 (Fig 12)
• Known 8K pipeline FFT chips have been implemented with 1 5M transistors, requiring an area of 100 mm 2 in 0 5 ⁇ technology, based on the architecture of Bi and Jones Even using a memory implementation with 3-trans ⁇ stor digital delay line techniques, over 1 M transistors are needed This has been further reduced with alternative architecture to 0 6M, as reported in the document A New Approach to Pipeline FFT Processor Shousheng He and Mats Torkelson, Teracom Svensk RundRadio DTTV-SA 180, TM 1547 This document proposes a hardware-oriented rad ⁇ x-2 2 algorithm having rad ⁇ x-4 multiplicative complexity
• the requirements of the FFT computation in the present invention require the implementation of a radix 2 2 +2 FFT processor
• the butterfly structure BF2II 262 differs from the butterfly structure BF2I 260 in that it has logic 264 and has a crossover 266 for crossing the real and imaginary inputs to facilitate multiplication by -j
• Fig 27 illustratesthe retimed architecture of a radix 2 2 + 2 FFT processor 268 in accordance with the invention, which is fully pipelined, and comprises a plurality of stages, stage-0 270 through stage-6 272 Except for stage-0 270, the stages each comprise one butterfly structure BF2I 260 and one butterfly structure BF2H 262, and storage RAMS 274, 276 associated therewith stage-0 270 only has a single butterfly structure BF2I 260
• This architecture performs a straight-forward 32-po ⁇ nt FFT stage-6 272 has control logic associated therewith, including demultiplexer 278 and multiplexer 280, allowing stage-6 272 to be bypassed, thus providing a 2K implementation of the FFT Counters 282 configure the butterfly structures BF2I 260 and BF2II 262 to select one of the two possible diagonal computations, during which data is being simultaneously written to and read from the storage RAMS 274, 276 Fig 28 illustrates a 32 point flow graph of the FFT processor
• the FFT processor 284 has 6 complex multipliers, each requiring 3 hardware multipliers 300, a total of 18 hardware multipliers 300 would be required
• Fig 31 in which some ofthe hardware multipliers 300 are replaced by multiplexers 302, 304
• Fig 29 there are a plurality of RAMS 306, 308, 310, 312, 314,
• the lookup table space is multiplied by a power of 4 at each stage.
• the lookup table for multiplier M 3 contains 512 entries. It can be deduced by extrapolation that multiplier M 5 must contain 8192 twiddle factors, and corresponds to the size of the FFT being performed by the FFT processor 284 (Fig. 29).
• Figs. 33 and 32 show the organization of the twiddle factors for each of the multipliers, wherein the terminology M k represents the multiplier associated with the kth stage.
• table 334 relates to multiplier M 0 .
• the notation for the W values (twiddle factors) is shown in box 336.
• the subscript "B" at the bottom right represents a time stamp, that is an order dependency in which the twiddle factors are required by the pipeline.
• the superscript "A” represents the address of the twiddle factor in its lookup table.
• the superscript "N” is the index of the twiddle factor.
• B2 MN (((4B2 Mo + 1)x4 + 1)x4 + 1) ... ⁇ 3 5)
• Break point B3 for line 0 at which the sequence changes from increments of 2,2,2,2 to the pattern 1 ,1 ,2,1 ,1 ,2... can be located by inspecting tables 338, 340, and 330.
• table 338 the break point B3 occurs very late in the line, such that the second sequence only presents its first two elements.
• break point B3 can be expressed as
• Fig 34 schematically illustrates an address generator 342 for the above described address generation scheme, and is specific for the table 340 and multiplier M 2 128 possible input states are accepted in lines ⁇ n_Addr 350, and a multiplexer 352 selects the two most significant bits to decode 1 of 4 values
• the output of the multiplexer 352 relates to the line number of the input state Actually the output is the address increment applicable to the line number of the input state, and is used to control a counter 354 whose incremental address changes according to value on line 356
• the increment for line 3 of table 340 is provided to the multiplexer 352 on line 358, and has a value of zero, as was explained above
• the increment for line 1 of table 340 is provided to the multiplexer 352 on line 360, and has a value of 1
• decoding logic 362 decodes the states for line 2 of table 340 The relationship of the current input state to the two break points of line 2 are tested by comparators 374,
• the break point is actually set one sample earlier than the comparator output to allow for retiming
• the outputs of the comparators 374 376 are selectors for the multiplexers 378, 380 respectively
• Fig 35 is a generalization of address generator 342 (Fig 34), in which the incoming address has a path of B bits Like elements in Figs 34 and 35 are given the same reference numerals
• the structure of address generator 394 is similar to that of the address generator 342, except now the various lines of the input ⁇ n_addr 396 and the output out_addr[B-2 0] 398 are denoted in terms of B
• the multiplexer 352 in Fig 35 is selected by input ⁇ n_addr [B
• Verilog code for the address generator 394 is generic, enabling any power-of- four table to be implemented Channel Estimation and Correction
• channel estimation and correction block 170 (Fig 14) is to estimate the frequency response of the channel based on the received values of the continuous and scattered pilots specified in the ETS 300744 telecommunicationsstandard and generate compensation coefficients which correct for the channel effects and thus reconstruct the transmitted spectrum
• Fig 16 A more detailed block diagram of the channel estimation and correction block 170 is shown in Fig 16
• the channel estimation and correction block 170 needs to locate the pilots before any channel estimation can take place
• the circuitry performs a convolution across the 2048 carriers to locate the positions of the scattered pilots which are always evenly spaced, 12 carriers apart Having found the scattered pilots the continual pilots can be located, once this is done the exact position of the 1705 active carriers within the 2048 outputs of the FFT calculation circuitry 168 (Fig 14) is known
• a timing generator 404 within the block can then be initialized, which then generates reference timing pulses to locate pilots for channel estimation calculation and for use in other functions of the demodulator as well
• Channel estimation is performed by using the evenly spaced scattered pilots, and then interpolating between them to generate the fre ⁇ uency response of the channel
• the received carriers (pilots and data) are complex divided by the interpolated channel response to produced a corrected spectrum
• a complete symbol is held in a buffer 406 This corrects for the bit-reversed order of the data received from the FFT calculation circuitry 168 It should be noted
• pilot search procedure 14 begins with the localization of the scattered and continual pilots, which occurs in pilot locate block 408.
• Scattered pilots which according to the ETS 300 744 telecommunications standard, occur every 12 data samples, offset by 3 samples with respect to the start of the frame in each succeeding frame.
• the power of the pilot carriers is 4/3 the maximum power of any data carrier, a succession of correlations are performed using sets of carriers spaced at intervals of 12.
• One of the 12 possible sets is correlates highly with the boosted pilot carrier power.
• a first embodiment of the pilot search procedure is now disclosed with reference to Figs. 36 and 16. It should be noted that the scattered pilot search procedure is done on the fly, and storage is only required in so far as is necessary to perform the subsequent step of continual piiot location discussed below.
• the signal pilot_lock412 is set low. Then, at step 414 the process awaits the first symbol pulse from the FFT calculation circuitry 168 (Fig. 14) on line 416 indicating the start of the first symbol. The first symbol is received and stored. In one embodiment of the pilot search procedure each point from 0 to 2047 is read in turn, accumulating each value (
• Two well known peak trackers indicate the accumulator with highest value (Peakl ) and the accumulator having the second highest value (Peak2).
• the accumulator having the highest value corresponds to the scattered pilot orientation.
• the second highest value is tracked so that the difference between the highest peak and the second highest peak can be used as a "quality" measure.
• decision step 418 if the two peaks are not far enough apart, a test for completion of a full range frequency sweep is made at decision step 420. If the test fails, failure of the scattered pilot search is reported at step 422. Otherwise, at step 424 the IQ Demodulator LO frequency is incremented by +1/8 carrier spacing by incrementing the magnitude of the control signal freq_sweep 426.
• the peak difference threshold can be altered by the control microprocessor via the microprocessor interface 142 and block 430.
• the scattered pilot peak is in accumulator 0, 3, 6 or 9 the pilot offset is 0 If the scattered pilot peak is in accumulator 1 , 4, 7, or 10 then pilot offset is 1 , etc Then 45 carrier positions expected for continual pilots are read, adding the pilot offset value to the address, and accumulating (
• + jq j) values This procedure is repeated until first 115 continual pilot start positions have been searched From the ETS 300 744 telecommunications standard the number of possible first carrier positions among the active carriers lying in a contiguous block between carrier 0 and carrier 2047 is easily calculated as (2048-1705) / 3 115, as explained below It is thus guaranteed that the active interval begins within the first (2048-1705) carrier positions The carrier corresponding to the peak value stored is the first active carrier in the symbol
• step 434 the timing generator404 is reset to synchronize to the first active carrier and scattered pilot phase
• the signal pilotjock 412 is then set high at step 436, indicating that the pilots have been located successfully, then at step 436 the timing generator 404 is reset to synchronize to the first active carrier and scattered pilot phase
• the scattered pilot search is repeated periodically, and evaluated at decision step 440 This can be done at each symbol, or less frequently, depending upon propagation conditions
• the predicted movement of the scattered pilot correlation peak is reflected by appropriate timing in the timing generator404, and can be used as a test that timing has remained synchronized Failure of the test at decision step 440 is reported at step 442, and the signal pilotjock
• step 444 the assertion of the signal resync 204, generally occurring after a channel change or on power up, the signal pilotjock 412 is set low Then, at step 446 a symbol is accepted for evaluation
• a search for scattered pilots conducted according to any of the procedures explained above, is performed at step 448 Then a search for continual pilots is performed as described above at step 450
• decision step 452 it is determined whether two symbols have been processed If the test fails, control returns to step 446 and another symbol is processed If the test succeeds at step 454 another test is made for consistency in the positions of the scattered and continual pilots in the two symbols If the test at step 454 fails, then the procedure beginning with decision step 420 is performed in the same manner as previously described with reference to Fig 36 If the test at step 454 succeeds at step 456 the timing generator 404 is reset to synchronize to the first active carrier and scattered pilot phase The signal pilotjock 412 is then set high at step
• step 460 the scattered pilot search is repeated periodically, and evaluated at decision step 462 This can be done at each cycle of operation, or less frequently, depending upon propagation conditions
• the predicted movement of the scattered pilot correlation peak is reflected by appropriate timing in the timing generator 404, and can be used as a test that timing has remained synchronized Failure of the test at decision step 462 is reported at step 464, and the signal pilotjock 412 is set low
• the task of locating the continual pilots is simplified considerably As the continual pilots are inserted at a known sequence of positions, the first of which is offset by a multiple of 3 positions with respect to start of the frame, as specified by the ETS 300744 telecommunications standard Two of three possible location sets in the data space can therefore be immediately excluded, and it is only necessary to search the third set Accordingly the continual pilot search is repeated, each iteration beginning at a location 3 carriers higher New accumulated values and the current start location are stored if they are larger than the previous accumulated value This is repeated until all continual pilot start positions have been searched The carrier corresponding to the largest peak value stored will be the first active carrier in the symbol It is unnecessary to evaluate the "quality" of the continual pilot correlation peak
• the scattered pilot search represents a correlation of 142 samples, and has higher noise immunity that of the search for 45 continual pilots The continual pilot search is almost certain to be succeed if scattered pilot search completed successfully
• the above sequences locate scattered pilot positions within 1/4 symbol period, assuming accumulation at 40MHz, and locate continual pilots in less than 1 symbol period (45 x 115 clock cycles assuming 40MHz operation)
• the I and Q data is provided to the pilot locate block 408 by the FFT calculation circuitry 168 (Fig 14) in bit-reversed order on ne 416 This complicates the problem of utilizing a minimum amount of RAM while computing the correlations during pilot localization Incoming addresses are therefore bit reversed, and computed modulo 12 in order to determine which of 12 possible bins is to store the data In order to avoid the square root function needed to approximate the carrier amplitude, the absolute values of the data are summed instead as a practical approximation The scattered pilots are determined "on the fly" The continual pilots are located on frames which succeed the frames in which the scattered pilots were located
• the operation of the timing generator 404 is now disclosed in further detail
• the addressing sequence for the RAM buffer 406 is synchronized by a symbol pulse from the FFT calculation circuitry 168 (Fig 14)
• the FFT calculation process runs continuously once the first symbol from has been received following FFT Window acquisition Addressing alternates between bit-reversed and linear addressing for successive symbols
• the timing generator 404 also generates all read-write timing pulses
• Signals u_symbol 466 and c_symbol 468 are symbol timing pulses indicating the start of a new uncorrected symbol or corrected symbol
• the signal u_symbol 466 is delayed by latency of the interpolating filter 470 and the complex multiplier 472 which are synchronized to RAM Address Sequence Timing
• pilot timing signals us_p ⁇ lot(+) 476, uc_p ⁇ lot(+) 478, cJps_p ⁇ lot( * ) 480 and odd_symbol pulse 482 are referenced to a common start pulse sequence
• a base timing counter (not shown) is synchronized by the pilot locate sync timing pulse 484, and is therefore offset from symbol timing Pilot timing outputs are also synchronized to uncorrected symbol output from the buffer 406 or the corrected symbol output delayed by the interpolating filter 470 and the complex multiplier 472
• the transmitted pilot at carrier k be P k and the received pilot be P' k
• the interpolating filter 470 realized in this embodiment with 6 taps and 12 coefficients, is utilized to estimate the portion of the channel between the scattered pilots
• pilots are transmitted at known power levels relative to the data carriers and are modulated by a known reference sequence according to the ETS 300 744 teiecommunicationsstandard
• Interpolation coefficients are selected from the 0-11 cyclic count in the timing generator 404 synchronized to data availability
• Appropriate correction factors may be selected for data points to provide on-the-fiy correction
• the input and output signals, and signals relating to the microprocessor interface 142 of the channel estimation and correction block 170 are described in tables 18, 19 and 20 respectively
• the circuitry of the channel estimation and correction block 170 is disclosed in Verilog code listings 18 and 19 TPS Sequence Extract
• the tps sequence extract block 172 (Fig 14), although set out as a separate block for clarity of presentation, is in actuality partially included in the channel estimation and correction block 170 It recovers the 68-b ⁇ t TPS data carried in a 68-symbol OFDM frame, and is shown in further detail in Fig 38 Each bit is repeated on 17 differential binary phase shift keyed ("DBPSK") modulated carriers, the tps pilots, within a COFDM symbol to provide a highly robust transport channel
• DBPSK binary phase shift keyed
• the 68-b ⁇ t tps sequence includes 14 parity bits generated by a BCH code, which is specified in the ETS 300 744 telecommunications standard
• BCH code which is specified in the ETS 300 744 telecommunications standard
• a clipper 486 clips incoming corrected spectrum data to ⁇ 1
• the sign bit can be optionally evaluated to obtain the clipped result in comparison block 488 clipped received tps pilot symbols are compared against a reference sequence input
• a value of 0 in the reference sequence matches -1 in the pilot and a value of 1 in the reference sequence matches +1 in the pilot Majority vote comparisons are used to provide an overall +1 or -1 result
• a result of +1 implies the same modulation as the reference sequence, and a result of -1 implies inverse modulation
• the DBPSK demodulator 490 converts the +/-1 sequence from the majority vote form to a binary form
• the sequence converts to a value of 0 if the modulation in current and previous symbols was the same, and to 1 if modulation between successive symbols is inverted
• Decoded data is provided to output store block 498, which stores tps data that is found in a full OFDM frame
• the output store block 498 is updated only at the end of an OFDM frame Only 30 bits of interest are made available Presently some of these bits are reserved for future use The length indicator is not retained
• the BCH decoder 496 has been implemented in a manner that avoids the necessity of performing the Berlekamp Algorithm and Chien Search which are conventional in BCH decoding
• the Galois Field Multiplier used in the BCH decoder496 is an improvement of the Galois Field Multipiierwhich is disclosed in our copending U S
• the particular BCH code protecting the tps sequence is specified in the ETS 300
• the syndromes are stored in storage registers R[2:0] 502.
• data flow from the registers R[2:0] 502 into search block 512 is enabled by a signal EOF 514, indicating the end of a frame.
• Three feedback shift registers 516, 518, 520 having respective Galois Field multipliers 522, 524, 526 for or 1 - cf 3 in the feedback loop are initialized to 50H, 20H, and 3dH (wherein the notation "H" refers to hexadecimal numbers).
• the feedback shift registers 516, 518, 520 are clocked each time a new data bit is available.
• the syndromes and outputs of the feedback shift registers 516, 518, 520 are clocked into to a search module, which performs a search for the error positions using an iterative substitution search technique, which will now be described.
• the outputs of feedback shift registers 516, 518 are multiplied in a Galois Field Multiplier 528. Considering the case of one error, S 0 is added, modulo 2, preferably using a network of XOR gates 530, to the output of the first feedback shift register 516 ( ⁇ -gen 0 ). If the relationship
• the Galois Field Multiplier 528 is a clocked digital circuit and is disclosed with reference to Fig. 40.
• the tps data is received very slowly, relative to the other processes occurring in the multicarrier digital receiver 126. It is thus possible to execute the iterative substitution search slowly, and the Galois Field Multipliers are designed for minimum space utilization. They do not require alpha generators, but rely on small constant coefficient multipliers, with iterative feedback to produce the required alpha values.
• the arrangementtakes advantage of the relationship in Galois Field arithmetic ⁇ n ⁇ 1 • ⁇ n " 1 (54)
• the multiplicand A 542 is accumulated in register 544 and repeatedly multiplied by the value ⁇ 1 in multiplier 546.
• the output on line 548 is repeatedly ANDed bitwise with the multiplicand B held in a shift register 550.
• the output of the shift register is provided on a one bit line 552 to the gate 554.
• the output of the gate 554 is accumulated in register
• the input and output signals and signals relating to the microprocessor interface 142 of the tps sequence extract block 172 are described in tables 21 , 22, and 23.
• Circuitry of the tps sequence extract block 172 and the BCH decoder 496 is disclosed in Verilog code listings 20 and 21.
• Automatic Fine Frequency Control and Automatic Sampling Rate Control are disclosed in Verilog code listings 20 and 21.
• a non ideal oscillator present in the transmission chain of an orthogonal frequency division multiplexed (“OFDM”) signal affects all carriers in the OFDM symbols.
• the OFDM carriers adopt the same phase and frequency disturbances resulting from the noisy local oscillator. Variations in the frequency of the Local Oscillator lead to phase shifts, and consequent loss of orthogonality within the OFDM symbol. Therefore competent automatic frequency control is required in the receiverto track the frequency offsets relative to the transmitter in order to minimize these phase shifts and hence maintain orthogonality. All the carriers within an OFDM symbol are equally affected by the phase shifts.
• AFC Automatic Frequency Control
• phase slope is proportional to the timing error.
• the phase slope can be determined by calculating the phase difference between successive OFDM symbols, using reference pilots, and estimating the slope of these phase differences. A least squares approach is used for line fitting.
• the ASC signal is low-pass filtered and fed back to the sine interpolator 158 (Fig. 13).
• the AFC signal is generated over time by low pass filtering ⁇ .
• the value of the frequency deviation is then used to control the IQ demodulator 144 (Fig. 13).
• the AFC and ASC control signals are effective only when a guard interval is passing indicated by the assertion of signal IQGI on line 154 (Fig 3) This prevents a symbol from being processed under two different conditions
• Frequency error values output on line 560 are calculated by determining the average of the differences of phase values of corresponding pilots in a current symbol and the previous symbol
• the resulting frequency error value is filtered in low pass filter 562 before being fed-back to the IQ demodulator 144 (Fig 13)
• Sampling rate error, output on line 564 is determined by looking at the phase difference between pilots in a symbol and the same pilots in a previous symbol
• the differences vary across the symbol, giving a number of points through which a line can be fitted using the well known method of least squares regression
• the slope of this line is indicative of the magnitude and direction of the sampling rate error
• the sampling rate error derived in this way is filtered in low pass filter 566 before being fed back to the sine interpolator 158 (Fig 13)
• a separate store 568 for the scattered pilots contained in 4 symbols is shared by the frequency error section 570 and the sampling rate error section 5
• the computations are done at a resolution of 14 bits
• the phase extract block 574 is illustrated in greater detail in Fig 43
• the quadrant of ⁇ is first determined in block 576
• a positive integer division operation is performed in division block 584 Although this operation requires 11 clock cycles, there is more than enough time allocated for phase extraction to afford it
• ⁇ 1 56)
• Block 586 is shown in greater detail in the schematic of Fig 44
• the value x is calculated once in block 588 and stored for use in subsequent iterations Powers of x are then iteratively computed using feedback line 590 and a mult ⁇ pl ⁇ er592
• the divisions are calculated using a constant multiplier 594 in which the coefficients are hardwired
• the sum is accumulated using adder/subtractor 596
• the entire computation requires 47 - 48 clock cycles at 40 MHz
• Fig 43 quadrant mapping, and the output of special cases is handled in block 598 under control of block 576
• the square error of the result of the Taylor Expansion rises rapidly as ⁇ approaches 45 degrees, as shown in Fig 45 and Fig 46, which are plots of the square error at different values of ⁇ ofthe Taylor expans ⁇ on to 32 and 31 terms respectively
• the Taylor expansionsto 31 and 32 terms are averaged, with the result that the square error drops dramatically, as shown in Fig 47
• a memory (not shown) for holding intermediate values for
• Constant Phase Error across all scattered Pilots is due to frequency offset at IQ Demodulator Frequency Error can be defined as
• ⁇ , m and T. have the same meanings as given above ⁇ is determined by taking the average of the difference of phase values of corresponding pilots between the current symbol and a symbol delayed for m symbol periods
• m 1 in the case of continual pilots
• This computation uses accumulation block 600 which accumulates the sum of the current symbol minus the symbol that preceded it by 4
• Accumulation block 602 has an x multiplier, wherein x varies from 1 to a minimum of 142 (in 2K mode according to the ETS 300744 telecommumcationsstandard)
• the low pass filters 562, 566 can be implemented as moving average filters having 10 - 20 taps
• the data available from the accumulation block 602 is the accumulated total of pilot phases each sampled m symbols apart
• the frequency error can be calculated from
• N 142 in the case of scattered pilots, and 45 for continual pilots, assuming 2K mode of operation according to the ETS 300 744 telecommunications standard
• the technique for determining sampling rate error is illustrated in Fig. 48, in which the phase differences of pilot carriers, computed from differences of every fourth symbol (S n - S n ⁇ ⁇ are plotted against frequency of the carriers. The line of best fit 604 is indicated. A slope of 0 would indicate no sampling rate error.
• a frequency sweep is initiated by block 608, which inserts an offset into the low-pass filtered frequency error output using adder 610.
• a frequency sweep is initiated by block 612, which inserts an offset into the low-pass filtered sampling rate error output using adder 614.
• the frequency sweeps are linear in increments of 1/8 of the carrier spacing steps, from 0 - 3.5kHz corresponding to control signal values of 0x0-0x7.
• a preferred embodiment of the correction circuitry 174 (Fig. 14) is shown in greater detail in Fig. 49.
• Continual pilots rather than scattered pilots are held in a memory store 616 at a resolution of 14 bits.
• the generation of the multiplier x for the computation in the accumulation block 618 is more complicated, since in accordance with the noted ETS 300 744 telecommunicationsstandard, the continual pilots are not evenly spaced as are the scattered pilots. However, it is now only necessary to evaluate 45 continual pilots (in 2K mode according to the ETS 300 744 telecommunicationsstandard). In this embodiment only the continual pilots of one symbol need be stored in the store 616.
• the demapping circuitry 176 (Fig. 15) is shown as a separate block for clarity, but in practice is integrated into the channel estimation and correction circuitry. It converts I and Q data, each at 12-bit resolution into a demapped 12-bit coded constellation format (3-bit I, I soft-bit, 3-bit Q, Q soft-bit). The coded constellation is illustrated in Fig. 50 and Fig. 51. For 64-QAM the 3 bits are used for the I and Q values, 2 bits for 16-QAM 2-bits and 1 bit for QPSK.
• the input and output signals of the demapping circuitry 176 are described in tables 28 and 29 respectively.
• the symbol deinterleaver 182 (Fig. 15) reverses the process of symbol interleaving of the transmitted signal. As shown in Fig. 52 the deinterleaver requires a 1512 x 13 memory store, indicated as block 622.
• the address generator624 generates addresses to write in interleaved data and read out data in linear sequence. In practice the address generator 624 is realized as a read address generator and a separate write address generator. Reading and writing occur at different instantaneous rates in order to reduce the burstiness of the data flow.
• the address generator 624 is resynchronized for each new COFDM symbol by a symbol timing pulse 626. Carrier of index 0 is marked by carrierO pulse 628. Addresses should be generated relative to the address in which this carrier is stored.
• the input and output signals of the symbol deinterleaver 182 are described in tables 30 and 31 respectively. Circuitry of the symbol deinterleaver 182 is disclosed in Verilog code listing 22. Bit Deinterleaver
• bit deinterleaver 184 (Fig. 15) reverses the process of bitwise interleaving of the transmitted signal, and is shown further detail in Fig. 53.
• soft encoding circuitry 630 input data is reformatted from the coded constellation format to a 24 bit soft l/Q format.
• the soft encoding circuitry 630 is disclosed for clarity with the bit deinterleaver 184, but is realized as part of the symbol deinterleaver discussed above.
• the deinterleave address generator 632 generates addresses to read the 6 appropriate soft-bits from the 126 x 24 memory store 634, following the address algorithm in the ETS 300 744 telecommunications standard.
• the deinterleave address generator 632 is resynchronized for each new COFDM symbol by the symbol timing pulse 626.
• the output interface 636 assembles I and Q output data streams from soft-bits read from the memory store 634. Three I soft bits and three Q soft bits are extracted from the memory store 634 at each deinterleave operation, and are parallel-serial converted to provide the input data stream to the Viterbi Decoder 186 (Fig. 15).
• bit deinterleaver 184 The input and output signals of the bit deinterleaver 184 are described in tables 32 and 33 respectively. Circuitry of the bit deinterleaver 184 is disclosed in Verilog code listing 23. Host Microprocessor Interface
• the function of the microprocessor interface 142 is to allow a host microprocessor to access control and status information within the multicarrier digital receiver 126 (Fig. 12).
• the microprocessor interface 142 is shown in greater detail in Fig. 55.
• a serial interface 638 and a parallel interface 640 are provided, the latter being primarily of value for testing and debugging.
• the serial interface 638 is of known type and is I2C compatible.
• the microprocessor interface 142 includes a maskable interrupt capability allowing the receiver to be configured to request processor intervention depending on internal conditions It should be noted, that the multicar ⁇ erdigital receiver 126 does not depend on intervention of the microprocessor interface 142 for any part of its normal operation
• Event is the term used to describe an on-chip condition that a user might want to observe An event could indicate an error condition or it could be informative to user software
• There are two single bit registers (not shown) are associated with each interrupt or event These are the condition event register and the condition mask register
• the condition event register is a one bit read/write register whose value is set to one by a condition occurring within the circuit The register is set to one even if the condition only existed transiently The condition event register is then guaranteed to remain set to one until the user's software resets it, or the entire chip is reset
• the condition event register is cleared to zero by writing the value one Writing zero to the condition event register leaves the register unaltered
• the condition event register must be set to zero by user software before another occurrence of the condition can be observed
• the condition mask register is a one bit read/write register which enables the generation of an interrupt request if the corresponding condition event register is set If the condition event is already set when 1 is written to the condition mask register an interrupt request will be generated immediately The value 1 enables interrupts
• the condition mask register clears to zero on chip reset Unless stated otherwise a block will stop operation after generating an interrupt request and will restart soon after either the condition event register or the condition mask register are cleared Event bits and mask bits are always grouped into corresponding bit positions in consecutive bytes in the register map This allows interrupt service software to use the value read from the mask registers as a mask for the value in the event registers to identify which event generated the interrupt There is a single global event bit that summarizes the event activity on the chip
• the chip event register presents the OR of all the on-chip events that have 1 in their respective mask bit A value of 1 in the chip mask bit allows the chip to generate interrupts A value of 0 in the chip mask bit prevents any on-chip events from generating interrupt requests Writing 1 or 0 to the chip event register has
• the system controller 198 (Fig . 15), which controls the operation of the multicarrier digital receiver 126 (Fig. 12), in particular channel acquisition and the handling of error conditions, is shown in further detail in Fig. 56.
• the channel acquisition sequence is driven by four timeouts.
• AGC acquisition timeout 20 ms (80 symbols) are allowed for the AGC to bring up the signal level, shown in step 644. Then the FFT window is enabled to start acquisition search in block 646.
• 35 symbol periods are allocated to pilot location in step 650. Approximately 50 ms are required to process 2K OFDM symbols. An option is provided to exit step 650 as soon as the pilots have been located to save acquisition time in non-extreme situations.
• Control Loop Settling timeout A further 10 ms, representing approximately 40 symbols is allocated to allow the control loops to settle in step 652. An option is provided to exit step 652 and return to an initial step resync 654 if pilots have been lost if control loop settling timeout occurs.
• Viterbi synchronizationtimeout In block 656 approximately 150 symbol periods are allocated for the worst case of tps synchronization, indicated by step 658 and approximately 100 symbol periods for the Viterbi Decoder 186 (Fig. 15) to synchronize to the transmitted puncture rate, shown as step 660. This is approximately 65 ms. In reasonable conditions it is unnecessary to wait this long. As soon as Viterbi synchronization is established, then transition to the system Jock state 662. It is possible to bypass the tps synchronization requirement by setting parameters (see table below) in the receiver parameters register and setting set_rx__parameters to 1.
• step resync 654 If acquisition fails at any stage, the process automatically returns to step resync 654 for retry.
• a Reed-Solomon overload event occurs, i.e. the number of Reed-Solomon packets with uncorrectable errors exceeds a predetermined value (the rsojimit value) in any 1 second period. If any of the 4 synchronizing state machines in the acquisition sequence, FFT window (step 648), pilot locate (step 650), tps synchronization (step 658) and Viterbi synchroni- zation (step 660), lose synchronization once channel acquisition has occurred, no action will be taken until an event, rso_event, occurs and the step resync 654 is triggered automatically.
• a bit is optionally provided in the microprocessor interface 142 ( Fig. 12), which when set extends the timeouts by a factor of 4.
• the input and output signals, and the microprocessor interface registers of the system controller 198 are described in tables 36, 37, 38, and 39 respectively.
• output out_ovf //Overflow flag.
• output [wordlength-1:0] out ⁇ lr // Output I to stage n+1 out_z1i, // Output Q to stage n+1 out_z2r, // Output I to memory.
• out_z2i // Output Q to memory.
• ⁇ z1r_tmp1 [wordlength-1]
• in_x2i // Input Q stage n-1. output outjDvf; //Overflow flag.
• output [wordlength-1 :0] out_z1 r // Output I to stage n+1 out_z1i, // Output Q to stage n+1 out_z2r, // Output I to memory. out_z2i; // Output Q to memory.
• z2r_tmp1 (ex_reg2) ? ⁇ 1'b1, ⁇ wordlength-1 ⁇ 1'b0 ⁇ : ⁇ 1'b0, ⁇ wordlength-1 ⁇ rb1 ⁇ ;
• Verilog code for 8 hardwired coefficients in a lookup table, of which 4 are unique values.
• Verilog code for 32 hardwired coefficients in a lookup table, of which 16 are unique values.
• Verilog code for a lookup table decoder Verilog code for a lookup table decoder.
• This FFT processor computes one pair of l/Q data points every 4 fast elk cycles.
• a synchronous active-low reset flushes the entire pipeline and resets the FFT. Therefore the next pair of valid inputs are assumed to be the start of the active interval of the next symbol.
• the out_ovf flag is raised an overflow has occured and saturation is performed on the intermediate calculation upon which the overflow has occured. If the validjn flag is held low, the entire pipeline is halted and the valid jout flag is also held low. valid jout is also held low until the entire pipeline is full (after the above number of clock cycles).
• RAM control MUX
• ROM lookup quadrant lookup
• Change BF code for unique saturation nets for synthesis
• ovfjdetection correct
• register o/p ovf detection correct
• mpy mpy
• BFs ROM/RAM test stuff
• OUtjDVf enable _Q, enable_1 , enable_2, enable_3, validjDut, ramjaddress, ram_enable, addressjOm3, address_rom4, z2r_4, z2i_4, // RAM input ports.
• parameter wordlength 12; // Data wordlength.
• parameter c_word length 10; // Coeff wordlength.
• parameter AddressSize 13; // Size of address bus.
• II II II Input/Output ports II - input elk, // Master clock, nrst, // Power-up reset. in_2k8k, // 2K mode active low. validjn; // Input data valid. input [9:0] in_xr, // FFT input data, I. in_xi; // FFT input data, Q. input [wordlength-1 :0] x1 r_4, x1i_4, // RAM output ports.
• brj5, bij5 wire [wordlength-1 :0] z2r_0, z2i_0, z2r_1 , z2i_1 , z2r_2, z2i_2, z2r_3, z2i_3; reg [wordlength-1 :0] z2r_4, z2i_4, // Registered outputs z2r_5, z2i_5, // to RAM.
• reg ovfjmpl ovfJmp2, fft_cycle_complete, // End of 1st FFT cycle. output_valid; // Output valid flag. reg [3:0] pipeline_count; // Counts pipeline regs.
• fftjiardwiredjul #(c_word length, rom_AddressSize-8) // Case table instance roml (elk, enable_3, address[4:0], br_1 , bi_1); // for a hardwired ROM.
• fft_ram #(s12_wdlength, 12) ram_12 (elk, enable_1 , enable_3, ram _address[11 :0], // 4096 addrs. z2r_12, z2i_12, // Inputs. x1 r_12, x1 i_12); // Outputs. */ fft_bf2ll #(s11_wdlength) bf2ll_6 (elk, enable_1 , x1 r_11 , x1 i_11 , x2r_11 , x2i_11 , // Inputs.
• fft_sr_1 bit #(1 ) sr_1 bit_11 (elk, enable_3, address[11 ], s[11 ]); // SR 11.
• fft_sr_1bit #(1) sr_1bit_12 (elk, enable_3, address[12], s[12]); // SR 12.
• fft_compiex_mult_mux#(wordlength, c_wordlength, mult scale) m5 elk, control, arj5, aij5, brj5, bij5, // Inputs. x2r_1 OJmpl , x2i_10_tmp1 , // Outputs.
• fft_bf2l #(wordlength) bf2l _5 (elk, enable_1 , x1r_10, x1M0, //Inputs. x2r_10, x2i_10, s[10], x2r_9, x2ij9, // Outputs. z2r_10, z2i_10, ovf_15); fft_bf2ll #(wordlength) bf2ll_5 (elk, enable , ⁇ 1 r 9Jmp, x1 i_9 mp, // Inputs.
• fft srjbit #(4) sr_1bitj5 (elk, enablej, address[5], s[5]); // SR 5.
• fftj3r_1bit #(4) srjbit o (elk, enablej, address[6], s[6]); // SR 6.
• fft_complexjTiult_mux#(wordlength, c_wordlength, multjscale) m2 (elk, control, ar_2, a 2, br_2, bi_2, // Inputs. x2r , x2i _4, II Outputs. ovf_7); fft_bf2l #(wordlength) bf2l_2 (elk, enable_1, xlr jmp, xli jmp, //Inputs. x2r , x2i , s[4], x2r _3, x2i_3, // Outputs.
• fft srjbit #(5) srjbit (elk, enablej, address[4], s[4]); // SR 4. fft srjq #(wordlength, 8) srjq (elk, enable , // Length 8. z2r , z2i , // Inputs, xlr , x1i_3); //Outputs.
• z2r ⁇ z2r_4 mp; // Register FFT outputs to RAM.
• z2i _4 ⁇ z2i _4 mp;
• z2r_5 ⁇ z2r_5 mp;
• z2i_5 ⁇ z2i_5 mp;
• z2r_6 ⁇ z2r_6 mp;
• z2i_6 ⁇ z2i_6Jmp;
• z2r_7 ⁇ z2r_7 mp;
• z2i_7 ⁇ z2i_7 mp;
• z2r ⁇ z2r mp;
• z2i ⁇ z2i mp;
• z2r_9 ⁇ z2r_9 mp;
• z2i_9 ⁇ z2i_9 mp;
• Verilog code for the window lookup table used to determine the variance of the data and hence the F_ratio.
• This module generates the window signal for the FFT in the form of validjn and provides the necessary signals for the l/Q demodulator, sync interpolator and error handler.
• fft_window (in_xr, in_xi, elk, nrst, validjn, valid_out, in_resync, outjqgi, out_sincgi, out_rx_guard, out_acquired, out_fft_window, enable_3_4, outjest, track_ram_address, xrijmpl , xrijmp ⁇ , track_ram_rnotw, track_ram_enable, ram_addr, ram_enable, ram_rnotw, ramlOJn, ram10_put, x1 r_10, // To FFT datapath (I).
• x1 i_10 // To FFT datapath (Q).
• z2r_10 // From FFT datapath (I) z2i_10, // From FFT datapath (Q) fft_ram_rnotw, // From FFT addr gen.
• fft_ram_enable // From FFT addr gen.
• fft_ram_addr // From FFT addr gen.
• parameter FIFO_n 64; // Ace length S(i-n-j).
• parameter FIFO_A 32; // t_offset dly FIFO+1.
• peak2 3'b010, // 2nd pos peak found.
• track2 3'b101 ; // Tracking model .
• out_fft_window // FFT processor st/stp enable_3_4, valid_out, track_ram_rnotw, track_ram_enable, ram_enable, ram_motw; output [FIFO_L_bits-1 :0] track_ram_address; // Tracking ram address output [1 :0] out_rx_guard; // Acquired gu length, output [AddressSize-1 :0] ram_addr; output [wordlength-1 :0] x1 r_10, x1 i_10; // To FFT datapath.
• guard_valid // Guard signal is valid t_retime_acq, // Retime timing counter t_retimejrk, // Retiming for tracking t_offset_valid, // Peak offset valid.
• t_offset_avg_valid // Average offset valid. pulse, // Pulse on states 4 & 5 enable ft, // FFT enabled flag. out_sincgi, // Guard int to sincint. outjqgi, // Guard int to iq demod ram_enable, ram_rnotw; reg [14:0] guard_active; // Guard+active length, reg [3:0] retry, // No failed retry's.
• track_ram_address // Tracking ram address; reg [lu_AddressSize-1 :0] ace; // Holds input variance.
• reg [14:0] t_count // Window timing count.
• t_offset // Peak offset from t_ct reg [14:0] g_a_count; // Guard_active counter.
• reg [14:0] dp_count // Datapath timing count reg [14:0] t_offset_avg; // Averaged offset, reg [2:0] state, // Acq/Track FSM state.
• Isbjn Jmp // even symbols to RAM.
• track_ram_enable // Tracking RAM enable track_ram_motw, // Tracking RAM rnotw. even_symbol, // valid on even symbols inj-esync, // Resync to acqn mode.
• pos_peak // +ve peak, ref only! dp_control, // Datapath acq/trk ctl.
• t_offset_ctl // Trk averager dp ctl.
• t offset_scalled // Scalled to t offset.
• msbj_ut ram10j_ut[2 * wordlength-1 :wordlength]
• lsb_out raml 0 j_ut[wordlength-1 :0]
• guardjactive ⁇ (5120+delta)&& // Test 4096+512+512 guardjactive > (5120-delta))
• guardjactive ⁇ 5120+delta
• parameter wordlength 12; // Data wordlength.
• parameter c_wordlength 10; // Coeff wordlength.
• parameter AddressSize 13; // Size of address bus.
• parameter r_wordlength 10; // ROM data wordlength.
• parameter FIFOJ. 256; // Tracking FIFO length.
• parameter FIFO L_bits 8; // Track FIFO addr bits
• parameter FIFOjN 64; // Ace length S(i-j).
• parameter FIFO_n 64; // Ace length S(i-n-j).
• parameter FIFO_A 32; // tjDffset delay FIFO.
• parameter FIFO A bits 5; // Track FIFO bits.
• Listing 16 // 204 ⁇ point FFT twiddle factor coefficients (Radix 4+2). // Coefficients stored as non-fractional 10 bit integers (scale 1 ). 5 // Real Coefficient (cosine value) is coefficient high-byte.
• 0111111000 1110101000 // W0056_2048 +0.985276 -0.170962 0111111000 1110100111 // W0057 2048 +0.984749 -0.173984 0111111000 " 1110100101 // W005 ⁇ ⁇ 2048 +0.964210 -0.177004 0111111000 1110100100 // W0059_2048 +0.963662 -0.180023 0111110111 1110100010 // W0060_204 ⁇ +0.963105 -0.183040 0111110111 " 1110100001 // W0061 " 2048 +0.962539 -0.186055 0111110111 " 1110011111 // W0062 "' 2046 +0.961964 -0.189069 0111110110 1110011110 // W0063 " 204 ⁇ +0.981379 -0.192080 0111110110 1110011100 // W0064 "' 2046 +0.980785 -0.195090 0111110110 " 1110011011 // W0065 "' 2048 +0.9

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