MXPA99004059A - Single chip vlsi implementation of a digital receiver employing orthogonal frequency division multiplexing - Google Patents

Abstract

The invention provides a single chip implementation of a digital receiver for multicarrier signals that are transmitted by orthogonal frequency division multiplexing. Improved channel estimation and correction circuitry are provided. The receiver has highly accurate sampling rate control and frequecy control circuitry. BCH decoding of tps data carriers is achieved with minimal resources with an arrangement that includes a small Galois field multiplier. An improved FFT window synchronization circuit is coupled to the resampling circuit for locating the boundary of the guard interval transmitted with the active frame of the signal. A real-time pipelined FFT processor is operationally associated with the FFT window synchronization circuit and operates with reduced memory requirements.

Description

IMPLEMENTATION OF INTEGRATION TO VERY LARGE SCALE IN A SINGLE CHIP DE ÜN DIGITAL RECEIVER USING MULTIPLEX ORTHOGONAL FREQUENCY DIVISION DESCRIPTION OF THE INVENTION This invention relates to electromagnetic signal receivers using multiple carrier modulation. More particularly, this invention relates to a digital receiver which is implemented on an electronic VLSI chip or chip (integrating on a very large scale) unique to receive transmissions using orthogonal frequency division multiplexing, and which is suitable for reception of digital video transmissions. Codified orthogonal frequency division multiplexing ("COFDM") has been proposed for digital audio and digital video broadcasting, both of which require the efficient use of limited bandwidth, and a transmission method which is reliable faced with various effects. For example, the impulse response of a typical channel can be modeled as the sum of a plurality of Dirac pulses having different delays. Each pulse is subjected to a multiplication factor, in which the amplitude generally follows the Rayleigh law. Such a chain of pulses can be extended for several mieroseconds, making it unreliable REF: 30103 the decoding of transmission at high bit rates. In addition to random noise, impulse noise and fading, other major difficulties in digital terrestrial transmissions at high data rates include multipath propagation and interference from adjacent channels, where near frequencies have highly correlated signal variations . The COFDM is particularly suitable for these applications. In practical COFDM arrays, relatively small amounts of data are modulated on each of a large number of carriers that are closely spaced in frequency. The duration of the data symbols is increased in the same proportion as the number of carriers or subchannels, so that the difference between symbols is significantly reduced. Figures 1 and 2 illustrate the multiplexing according to COFDM, where the spectrum of a single COFDM carrier or subchannels is indicated by line 2. A set of carrier frequencies is indicated by the superimposed waveforms in Figure 2 , where the orthogonality conditions are satisfied. In general, two functions of real value are orthogonal if Jb dt = K (1) where K is a constant, and K = 0 if p? q; K? 0 if p = q. The coding and practical decoding of signals according to COFDM is based mainly on the fast Fourier transform ("FFT"), as can be seen from the following equations. The signal of a carrier c is given by S? t) = A. (t) ej [? _ t +? _ (_) 3 (2) where Ac is the data at time t,? c is the frequency of the carrier and fc is the phase. The N carriers in the signal COFDM is given by "(3) S. (t) = (1 / N)? An (t) et? "T + *» (t >] n = 0 (4)? _ =? 0 + n ?? Sampling over the symbol period, then ( " - ( 5 ) Ac (T) »Aa (6) with a sampling frequency of 1 / T, the resulting signal is represented by Ss (t) = (l / N)? An (t) eí [(? "+ N ??), cr + * J" = o Sampling over the period of a data symbol T =? T, with? 0 = 0, (8) Sg (kT) = (l / N)? Ae ^ e ^ "'* 1, which compares with the general form of the discrete inverse Fourier transform:, - (9) g (kT) = (1 / N)? G (n / (kT)) ei ™ Wlí) n = 0 In the previous equations A, .ej * n is the input signal in the sampled frequency domain, and ss (kT) is the representation of the time domain. It is known that increasing the size of the FFT provides longer symbol durations and improves the resistance of the system by considering the echoes which exceed the length of the guard interval. However, the computational complexity increases according to? Log2?, and this constitutes a practical limitation. In the presence of intersymbol interference caused by the transmission channel, the orthogonality between the signals is not maintained. One solution to this problem has been to deliberately sacrifice part of the energy emitted by preceding each symbol in the time domain by an interval which exceeds the channel memory, and any multipath delay. The "guard interval" chosen in this way is large enough to absorb any interference between symbols and is established by preceding each symbol by a replication of a portion of itself. Typically replication is a cyclic extension of the terminal portion of the symbol. With reference to Figure 3, a data symbol 4 has an active interval 6 which contains all the data transmitted in the symbol. The terminal portion 8 of the active interval 6 is repeated at the beginning of the symbol in the guard interval 10. The COFDM signal is represented by continuous line 12. It is possible to repeat the initial portion of active interval 6 cyclically at the end of the symbol. The transmission of the COFDM data can be completed according to the known general scheme shown in Fig. 4. A serial data stream 14 is converted to a series of parallel streams 16 in a series-to-parallel converter 18. Each of the currents 16 in parallel is grouped in x bits each to form a complex number, where x determines the signal constellation of its associated parallel current. After encoding outward and interleaving in the carrier block 20 the pilot is inserted via a signal mapper 22 for use in synchronization and channel estimation in the receiver. Pilot carriers are typically of two types. The continuous pilot carriers are transmitted in the same position in each symbol, with the same phase and amplitude. In the receiver, these are used to cancel phase noise, automatic frequency control and time / sample synchronization. The scattered pilot carriers are distributed through the symbol, and their placement typically changes from one symbol to another. These are useful mainly in channel estimation. Subsequently, the complex numbers in the base band are modulated by the fast inverse Fourier transform ("IFFT") in block 24. A guard interval is then inserted in block 26. The discrete symbols are then converted to analog, typically subjected to low pass filtering, and then converted upwardly to radio frequency in the block 28. Subsequently the signal is transmitted through a channel 30 and received in a receiver 32. As is well known in the art, the receiver applies a reverse process to the transmission to obtain the transmitted information. In particular, an FFT is applied to demodulate the signal. A modern application of COFDM has been proposed in the European telecommunications standard ETS 300 744 (March 1997), which specifies the structure of frame elaboration, channel coding and modulation for digital terrestrial television. The specification was designed to adapt digital terrestrial television within the existing spectrum allocation for analog transmissions, and still provide adequate protection against high levels of interference from adjacent channels. A flexible guard interval is specified, so that the system can support various network configurations, and at the same time maintain high spectral efficiency and sufficient protection against co-channel interference and interference from adjacent channels of existing PAL / SECAM services. The European telecommunications standard mentioned above defines two modes of operation. A "2K mode" suitable for single transmitter operation and for small and single frequency networks with limited transmitter distances. An "8K mode" that can be used either for single transmitter operation or for single frequency to large frequency networks. Various levels of quadrature amplitude modulation ("QAM") are supported, because they are in different speeds of internal code, in order to balance the bit rate against the roughness. It is intended that the system be adapted to a transport layer according to the group of film experts ("MPEG"), and that it be directly compatible with MPEG2 encoded TV signals (ISO / IEC 13818). In the indicated European telecommunications standard, data carriers in a COFDM framework can be with a quadrature phase shift key ("QPSK"), 16-QAM, 64-QAM, 16-QAM non-uniform or 64-QAM not uniform, using Gray's transformation.

A major problem in the reception of COFDM transmission is the difficulty in maintaining synchronization due to phase noise and jitter which arises from upconversion before transmission, downward conversion in the receiver and the front end oscillator in the tuner, which is typically a voltage controlled oscillator. Except for the provision of pilot carriers to assist in demodulation during synchronization, these issues are not specifically resolved in the European telecommunications standard, but are left to be resolved by those who implement them. Basically, phase alterations are of two types. First, noisy components which alter the neighboring carriers in a multiple carrier system called "strange noise contribution" ("FNC"). Secondly, a noise component which alters the carrier itself, which is called "own noise contribution". With reference to Figure 5, the position of the ideal constellation samples is indicated by "x" symbols 34. The effect of the contribution of strange noise is stochastic, which results in a noise similar to the Gaussian. Samples disturbed in this way are indicated in Figure 5 as circles 36. The effects of their own noise contribution is a common rotation of all constellation points, indicated as a displacement between each "x" symbol 34 and its associated circle 36. This is referred to as a "common phase error", which changes markedly from one symbol to another, and therefore each symbol period Ts must be calculated again. The common phase error can also be interpreted as a mid phase deviation during the symbol period Ts. In order for the receiver 32 to process the data symbols in a practical system, a mathematical operation is performed on the complex signal representing each data symbol. Generally this is an FFT. For valid results to be obtained, a particular form of timing synchronization is required in order to align the FFT interval with the received data symbols. Therefore, it is a principal object of the invention to provide a low cost, highly integrated apparatus for the reception of digital broadcasts, such as terrestrial digital video broadcasts, which is implemented on a single VLSI electronic chip or chip. Another object of the invention is to provide an improved method and apparatus for synchronizing received data symbols with an FFT interval in signals transmitted in accordance with COFDM.

Another additional objective of the invention is to improve the stability of the digital multiple carrier receivers with respect to the channel estimate. Another additional objective of the invention is to improve the automatic frequency control circuits used in the digital multiple carrier receivers. A further object of the invention is to improve the automatic sampling rate control circuits used in the digital multiple carrier receivers. The invention provides a digital receiver for multiple carrier signals that are transmitted by orthogonal frequency division multiplexing. The multiple carrier signal carries a stream of data symbols having an active range, and a guard interval in which the guard interval is a replication of a portion of the active range. In the receiver, a digital analog converter is coupled to the front end amplifier. An I / Q demodulator is provided to recover the in-phase and quadrature components for data sampled by the analog-to-digital converter, and an automatic gain control circuit is coupled to the analog-to-digital converter. In a low pass filter circuit that accepts I and Q data from the I / Q demodulator, the I and Q data are decimated and provided to a circuit of resampling An interpolator in the resampling circuit accepts the I and Q data decimated at a first speed and transmits the resampled I and Q data at a second speed. An FFT interval synchronization circuit is coupled to the resampling circuit to locate a limit of the guard interval. A real-time channelized FFT processor is operatively associated with the synchronization circuit of the FFT interval. Each stage of the FFT processor has a complex coefficient multiplier, and a memory associated with a search table defined therein for multiplicands that are multiplied in the complex coefficient multiplier. Each multiplicand in the search table is unique in value. A monitor circuit responding to the interval synchronization circuit FFT detects a predetermined indication that a boundary has been located between the active symbol and the guard interval. According to one aspect of the invention, the FFT interval synchronization circuit has a first delay element that accepts the resampled I and Q data currently arriving, and transmits delayed resampled I and Q data. A subtractor produces a signal representative of the difference between the resampled I and Q data currently arriving and the delayed resampled I and Q data. In a first circuit, the output signal of the subtractor is converted to a signal having a unipolar magnitude, which preferably is the absolute value of the signal provided by the subtracter. A second delay element stores the output signal of the first circuit, and a third delay element receives the delayed output of the second delay element. In a second circuit, a statistical relationship is calculated between the data stored in the second delay element and the data stored in the third delay element. The output of the FFT interval synchronization circuit is representative of the statistical relationship. Preferably the statistical relation is the ratio F. The FFT processor is capable of operation in a 2K mode and in an 8K mode. The FFT processor has an address generator for the memory of each stage, which accepts a signal representing the order of dependence of the currently required multiplier and generates an address of the memory where the currently required multiplier is stored. In a further aspect of the invention, each multiplier is stored in the lookup table in order that its respective order dependence for multiplication by the complex coefficient multiplier, so that the order of the dependencies of the multiples defines a sequence Increment. The address generator has an accumulator to store previous addresses that are generated by it, a circuit to calculate an increment value of the currently required multiplier that responds to the increment sequence and an adder to add the increment value to the previous directions . In another aspect of the invention there is a plurality of increment sequences. The multiples are stored in the row order, where the first row the first increment sequence is 0, and a second row where the second increment sequence is 1 and a third row of the first and second breakpoints Bl, B2 of a third increment sequence are determined respectively by the relations N - l _ ?! "" = 4 »B1 -? 4" n * 0 B2"=? 4"n = 0 in a fourth row a third breakpoint B3 of a third increment sequence is determined, by the ratio B3M¡¡ = 2 x 4N + 2 where MN represents the memory of the nth stage of the FFT processor. The receiver provides channel estimation and correction circuits. The circuits of location of the pilot signal receive a digital signal transformed representing a frame of the FFT processor and defines the position of the pilot carriers in it. The pilot carriers are separated in a carrier spectrum from the digital signal transformed at intervals K and have predetermined magnitudes. The pilot location circuits have a first circuit to calculate an order of carriers in the digital signal transformed, positions of the carriers which calculate the K module. There are K accumulators coupled to the second circuit to accumulate magnitudes of the carriers in the digital signal transformed, the accumulated magnitudes define a set. A correlation circuit is provided to correlate the sets K of accumulated magnitude values with the predetermined magnitudes. In the correlation a first member having a position of modulo K calculated in each of the sets K deviates uniquely from a starting position of the frame. According to another aspect of the invention, the pilot positioning circuits also have a bit inversion circuit to reverse the order of the bits of the transformed digital signal. In accordance with another aspect of the invention, amplitudes are used to represent the magnitudes of the carriers. Preferably the magnitudes of the carriers and the predetermined magnitudes are absolute values. In a further aspect of the invention, the correlation circuits also have a peak tracking circuit to determine the separation between a first peak and a second peak of the sets K of accumulated magnitudes, wherein the first peak is the maximum magnitude, and the second peak is the second highest magnitude. The channel estimation and correction circuits also have an interpolation filter to estimate the channel response between the pilot carriers, and a multiplication circuit to multiply the transmission of data carriers by the FFT processor with a correction coefficient produced by the filter of interpolation. The channel estimation and correction circuits also have a phase extraction circuit that accepts a data stream of the I and Q data without phase correction of the FFT processor, and produces a signal representative of the phase angle of the uncorrected data . The phase extraction circuit includes an accumulator for the successive phase I and Q data angles without phase correction. According to one aspect of the invention, the channel estimation and correction circuits include an automatic frequency control circuit coupled to the phase extraction circuit, in which a memory stores the cumulative common phase error of a first transported symbol in the uncorrected phase I and Q data. An accumulator is coupled to the memory and accumulates the differences between the common phase error of a plurality of pilot carriers in a second symbol, and the common phase error of the corresponding pilot carriers of the first symbol. The accumulator output is filtered and coupled to the I / Q demodulator. According to another aspect of the invention, the coupled output of the accumulator of the automatic frequency control circuit is activated in the I / Q demodulator only during the reception of a guard interval therein. According to a further aspect of the invention, the channel estimation and correction circuits also have an automatic sampling rate control circuit coupled to the phase extraction circuit, in which a memory stores the errors accumulated phase of the pilot carriers in a first symbol transported in the uncorrected phase I and Q data. An accumulator is coupled to the memory and accumulates the differences between the phase errors of the individual pilot carriers in a second symbol and the phase errors of the corresponding pilot carriers in the first symbol to define a plurality of phase error differentials of carrier between accumulated symbols. A phase slope is defined by a difference between a first differential of carrier signal between accumulated symbols and a second differential of carrier phase between accumulated symbols. The accumulator output is filtered and coupled to the I / Q demodulator.

In accordance with an aspect of the invention, the sampling rate control rate circuit stores a plurality of carrier phase error between accumulated symbols and calculates a line of best fit between them. According to another aspect of the invention, the coupled output signal of the accumulator of the automatic sampling rate control circuit is activated in the resampling circuit only during the reception of a guard interval therein. According to another aspect of the invention, a common memory is coupled to store the output of the phase extraction circuit to the automatic frequency control circuit and to the automatic sampling speed control circuit. According to another aspect of the invention, the phase extraction circuit also has a channeled circuit to interactively calculate the tangent arc of a rotation angle according to the series ta? X (x) = X - ^ + ^! -?! +?! -. . ., | X | L where x is the proportion of the I and Q data of uncorrected phase.

A channelized circuit includes a constant coefficient multiplier and a multiplexer for selecting one of a plurality of constant coefficients of the series. An output of the multiplexer is connected to an input of the multiplier of the constant coefficient. According to another additional aspect of the invention, the channelized circuit has a multiplier, a first memory for storing the quantity X2, wherein the first memory is coupled to a first input of the multiplier, and a second memory for retaining a transmission of the multiplier. . A feedback connection is provided between the second memory and a second input of the multiplier. The channelized circuit also has a third memory to store the value of the series. Under the direction of a control circuit coupled to the third memory the channeled circuit computes the N terms of the series, and also calculates the N + l terms of the series. An averaging circuit coupled to the third memory is also coupled and calculates the average of N terms and N + l terms of the series. The data transmitted on a pilot carrier of the carrier signal is encoded BCH according to a polynomial code generator h (x). An operational demodulator of the encoded data BCH is provided, which includes an interactive channelized BCH decoding circuit. The decoding circuit of BCH is coupled to the demodulator. It forms a Galois field of the polynomial and calculates a plurality of syndromes with it. The decoding circuit BCH includes a plurality of storage registers, each one stores one of the respective syndromes, and a plurality of feedback shift registers, each accepting data from one of the respective storage registers. The decoding circuit BCH has a plurality of Galois field multipliers. Each of the multipliers is connected in a feedback loop through one of the respective feedback shift registers and multiplies the output in its associated feedback shift register by an alpha value of the Galois field. An output or transmission Galois field multiplier multiplies the outputs of the two feedback displacement registers. A logical network forms an error detection circuit connected to the feedback shift registers and the output Galois field multiplier. The output of the error detection circuit indicates an error in a stream of data bits, and the feedback line is activated by the error detection logic circuit and connected to the storage registers. Through the use of the feedback line, the transmission of the data by the feedback shift registers is again written to the storage registers for use in a second interaction. In accordance with an aspect of the invention, the transmission field Galois multiplier has a first record that initially stores a first multiplying A, a constant coefficient multiplier connected to the first record for multiplication by a value. An output of the constant coefficient multiplier is connected to the first register to define a first feedback circuit, so that in a kaesimo cycle of the clock operation the first record contains a field product of Galois AaA. A second record is provided for store a second multiplying B. And connect to an AND gate (Y) to the second register and to the transmission of the constant coefficient multiplier. An adder has a first input connected to an output of the AND gate. An accumulator is connected to a second inlet of the adder, and the field product of Galois AB is transmitted by the adder. The invention provides a method for estimating a frequency response of a channel. It is performed upon receiving from the channel a multiple carrier analog signal having a plurality of data carriers and scattered pilot carriers. The scattered pilot carriers separate at an N interval and are transmitted at a power that differs from the transmitted power of the data carriers. The multiple carrier analog signal is converted to a digital representation of it. A Fourier transform is performed on the digital representation of the multiple carrier signal to generate a transformed digital signal. The bit order of the transformed digital signal is inverted to generate an inverted signal in bit order. The magnitudes of the carriers in the signal converted in bit order accumulate cyclically in N accumulators, amd accumulated magnitudes correlate with the power of the dispersed pilot carriers. In response to the correlation, a synchronization signal is generated which identifies a carrier position of the multiple carrier signal, preferably an active carrier. According to another aspect of the invention, the step of accumulating magnitudes is performed by adding absolute values of a real component of the inverted signal in order of bits with respect to the respective absolute values of the imaginary components thereof to generate sums, and store the sums in the accumulators N respectively. According to another aspect of the invention, the step of correlating the accumulated magnitudes is also performed by identifying a first accumulator having the highest of the values of N stored therein, which presents a first carrier position, and identify a second accumulator which has the second highest of the N values stored in the mimus, which represents a second carrier position. The interval between the first carrier position and the second carrier position is determined later. To validate the consistency of the carrier position identification, the position of a carrier of a first symbol in the inverted signal is compared in order of bits with a position of a corresponding carrier of a second symbol therein. Preferably the interpolation is performed between pilot carriers, to determine correction factors for respective intermediate data carriers placed therebetween and respectively adjust the magnitudes of the intermediate data carriers according to the correction factors. In accordance with an aspect of the invention, a mean phase difference between corresponding pilot carriers of successive symbols of the transformed digital signal is determined. A first control signal is provided which represents the average phase difference for controlling the reception frequency of the multiple carrier signal. The first control signal is activated only during the reception of a guard interval.

Preferably a line of best fit is determined for the phase and intersymbol differences of the multiple carriers to define a phase slope. For a better understanding of these and other objects of the present invention, reference is made to the detailed description of the invention, by way of example, which should be read together with the following drawings, in which: Figure 1 illustrates the sub-channel spectrum COFDM; Figure 2 shows a frequency spectrum for multiple carriers in a COFDM signal; Figure 3 is a diagram of a signal according to COFDM and shows a data symbol format; Figure 4 is a block diagram illustrating a FFT-based COFDM system; Figure 5 illustrates certain disturbances or alterations in a COFDM signal constellation; Figure 6 illustrates a flow chart of a method for synchronization timing according to a preferred embodiment of the invention; Fig. 7 is a graph of a ratio test F performed on various data symbols for coarse synchronization timing; Figure 8 is a graph of an incomplete beta function for different degrees of freedom; Figure 9 is a graph useful for understanding a test of statistical significance according to the invention; Figure 10 is an electrical schematic of a synchronization circuit according to an alternative embodiment of the invention; Figure 11 is an electrical schematic of a synchronization circuit according to another alternative embodiment of the invention; Figure 12 is a block diagram of a single-chip or electronic chip form of a digital receiver according to the invention; Figure 13 is a block diagram illustrating the front end of the digital receiver shown in Figure 12, in greater detail; Fig. 14 is a block diagram illustrating the FFT circuits, channel estimation and correction circuits of the digital receiver shown in Fig. 12; Fig. 15 is a block diagram illustrating another portion of the digital receiver shown in Fig. 12; Fig. 16 is a more detailed block diagram of the channel estimation and correction circuits shown in Fig. 14; Figure 17 is a schematic of the automatic gain control circuits of the digital receiver shown in Figure 12; Figure 18 is a schematic of the I / Q demodulator of the digital receiver shown in Figure 12; Figure 19 illustrates in more detail a low pass filter shown in Figure 13; Figure 20 shows the response of the low pass filter shown in Figure 19; Figure 21 shows the resampling circuits of the digital receiver shown in Figure 12; Figure 22 illustrates a portion of an interpolator of the resampling circuits of Figure 21; Figure 23 is a more detailed block diagram of the FFT interval circuits shown in Figure 14; Fig. 24 is a schematic of a butterfly unit in the FFT calculation circuit shown in Fig. 14; Figures 25 and 26 are diagrams of butterfly units according to the prior art; Figure 27 is a schematic of a radix processor 22 + 2 FFT according to the invention; Figure 28 is a 32-point flow chart of the FFT processor shown in Figure 27; Fig. 29 is a schematic of a unique radix 2K / 8K path configurable 22 + 2 only, with a channelized delay feedback FFT processor according to the invention; Figure 30 is a detailed schematic of a complex multiplier used in the circuits shown in Figure 29; Figure 31 is a detailed schematic of an alternative embodiment of complex multipliers used in the circuits shown in Figure 29; Figure 32 is another diagram that illustrates the organization of singing factors for each of the multipliers in the circuits shown in Figure 29; Figure 33 illustrates the organization of the singing factors for each of the multipliers in the circuits shown in Figure 29; Fig. 34 is a schematic of the address generator used in the circuits shown in Fig. 29; Fig. 35 is a schematic of a generalization of the address generator shown in Fig. 34; Fig. 36 is a flow chart illustrating the pilot location process conducted by the channel estimation and correction circuits shown in Fig. 26; Fig. 37 is a flowchart of an embodiment of the pilot location method according to the invention; Fig. 38 is a more detailed block diagram of the sequence block tps of the circuits shown in Fig. 14; Fig. 39 is a schematic of a BCH decoder used in the processing circuits tps shown in Fig. 38; Figure 40 is a more detailed scheme of the Galois field multiplier shown in Figure 39; Figure 41 is a block diagram that generally illustrates the automatic sampling control and automatic frequency control circuits of the digital receiver shown in Figure 12; Figure 42 is a more detailed block diagram of the automatic sampling control and the automatic frequency control circuits shown in Figure 41; Figure 43 is a more detailed block diagram of the phase extraction block of the circuits shown in Figure 42; Figure 44 is a schematic of the circuits used to calculate a tangent arc in the block diagram shown in Figure 43; Figure 45 is a graph of the square error at different values of • ex in the Taylor expansion to 32 terms; Figure 46 is a graph of the square error in different values of c. of Taylor's expansion to 31 terms; Figure 47 is a graph of the square error in different values of c. from Taylor's average expansion to 31 and 32 terms; Figure 48 is a graph of the phase differences of the pilot carriers showing the line of best fit, - Figure 49 is a more detailed block diagram of an alternative mode of automatic sampling control and control circuits of automatic frequency shown in Figure 41; Figure 50 illustrates a coded constellation format used in the transformation elimination circuits of Figure 15; Figure 51 illustrates the conversion data I, Q of binary data values using the format shown in Figure 50; Fig. 52 is a more detailed block diagram of the symbol deinterleaving circuits shown in Fig. 15; Figure 53 is a more detailed block diagram of the bit de-interleaving circuits shown in Figure 15; Figure 54 illustrates the conversion from a coded constellation format to a soft 24 bit I / Q format by the deinterleaving circuits shown in Figure 53; Figure 55 is a more detailed block diagram of the microprocessor phase of the clear receiver in the figure 12; Fig. 56 is a more detailed block diagram of the receiver system controller shown in Fig. 12; and Figure 57 is a state diagram in relation to the channel acquisition in the receiver system controller shown in Figure 56.

Alignment of the FFT interval With reference again to FIGS. 3 and 4, according to the invention a statistical method is applied to COFDM signals to find the end of guard interval 10. This method is explained with reference to the European telecommunication standard indicated above, but it is applicable to many forms of frequency division multiplexing having fixed or later fixed guard intervals. It allows the receiver 32 to find the end of the guard interval given only the complex signal shown received (continuous line 12) and the size of the active interval 6. The method is based on the fact that the guard interval 10 is a copy of the last part of the data symbol 4. In the receiver 32, due to echoes and channel noise and errors in the local oscillator, the guard interval 10 and the last part of the data symbol 4 will differ. If the errors introduced are randomizers then a statistical method can be applied. According to the invention, the received complex signal is sampled at a speed which is almost identical to that used in the transmitter. A difference signal is found for a pair of received samples which are separated by a period of time which is as close as possible to the active interval 6. This period can be equal to the size of the last Fast Fourier Transform ("FFT") (that is, 2048 or 8192 samples). Suppose"i = I Yes I" I Yes - amaí.c- fft I (14) where S ± is the signal, Si and s-i.,. ^^ -, fft are the current and previous complex input samples from which the modules are taken. That is, the subscript "i" indexes a linear time sequence of input values. Assuming that the input signal is random, then Si is also random. Within the guard intervals s ± and Si_size fft will be similar, but not identical, due to the effects of the channel.

Therefore, s.¡. it will be a random signal with a small dispersion. As used herein, the term "dispersion" generally means the range of values, and is not restricted to a particular mathematical definition. In general, the active part of a symbol is not related to the active part of the following symbol. Outside the interval S ^ of guard, it will be random with a much larger dispersion. In order to find the end of the guard interval, the spread of the difference signal Sx is monitored to find a significant increase which will occur at the limit of the guard interval 10 and the active interval 6. The inventors have also observed that a large decrease in dispersion is observed at the beginning of the guard interval. According to a preferred embodiment of the invention the samples of the input signal are stored over a range which includes at least one symbol period Ts. The dispersion of the difference signal S1 on a block of samples is calculated. The block moves backward in time over several of the samples, n, and the dispersion is recalculated. The ratio of a current dispersion in a first comparison block to the dispersion in a previous comparison block is found. Then the F-ratio significance test is used to find significant differences in the dispersions of the two comparison blocks. The F ratio is defined as _, = VAR (i) (1? -5) 'VAR (i -n) where n is a positive integer, i indexes the input samples, and VAR (i) is the variance of a block of values of N length samples. The variance can be defined as While the significance test of ratio F is used in the preferred embodiment, other functions of the two scattering values can be used which provide a signal in relation to a change in dispersion. There are many such functions. An advantage of the F ratio is that for a random input signal there is a known probability distribution, which allows a convenient statistical analysis for the purposes of carrying out the analysis and system design. In addition, the F ratio intrinsically normalizes the signal, making it independent of the signal level result. The method is described with reference to Figure 6, in which a first member of a sample pair in a current evaluation block is measured in step 38. In step 40 a delay of an active interval 6 is experienced ( figure 3). This can be carried out with a digital delay such as FIFO, or equivalently by damping samples for an active interval in a memory and by accessing appropriate cells in the memory. The second member of the pair of samples is measured in step 42, and the difference between the first and second member is determined and stored in step 44. The end of the current block is tested in decision step 46. The size of the evaluation block must not exceed the length of a guard interval, and must be considerably smaller. In the event that the end of the current block has not yet been reached, another sample is acquired in step 48 and the control returns to step 38. If the end of the current block has been reached, it is measured in the stage 50 the dispersion of the current block, and it is treated as one of two blocks of comparison data. A test is carried out in decision stage 52 to determine if a group of two comparison blocks has been evaluated. If this test is negative, then another data block is acquired in step 54, after which the control returns to step 38. The other data block does not need to be contiguous with the newly completed block. In the case where the test in decision step 52 is positive, the F ratio is calculated for the group of two comparison blocks in step 56. The result obtained in step 56 is sent for peak detection in the stage 60. Optionally, peak detection includes statistical tests of significance, as explained in the following. If peaks are detected, then the limit of a guard interval is set in step 62 for purposes of synchronization of the FFT interval which is necessary for further reconstruction of the signal. If no peaks are detected, the previous process is repeated with a block of samples taken from another portion of the data stream.

Example 1: Referring now to Figure 7, a complete signal is generated in accordance with the European telecommunications standard indicated above using a random number generator and transmitted through a Ricean channel model together with aggregate white Gaussian noise (SNR = 3.7 ). The data symbols were then analyzed according to the method described above. The data symbol results 6 is shown in Figure 7, where the F ratio is plotted for convenience of representation as a logarithmic axis such as line 64, due to the tips 66, 68 at the beginning and end of the intervals respectively, are very large. Although it is very evident from Figure 7 that the ends of the guard intervals are easy to find using any of several well-known peak detectors, it is possible to apply a statistical test to more accurately answer the question: do the two blocks of Do samples have the same dispersion? This is the null hypothesis, H0, that is, the dispersion in it and the peak observed in F is due solely to random fluctuations. If H0 has a very low probability it can be rejected, which would correspond to the detection of the start or end of the guard interval. From the way in which the COFDM symbol is constructed, H0 is expected to be true for comparison blocks that are completely within the guard interval or within the active range, but false when the comparison blocks attach a limit to the start of the end of the guard interval. If the random sample comparison blocks are drawn from the same population, then the probability of F is given by Q (F \ vvv2) = lx (^ -, ^.) (17) where I () is the incomplete Beta function, v2 x s = (18) v_ + v, F and Vx and V2 are the numbers of degrees of freedom with which the first and second dispersions are estimated. In this example vl = v2 = (N-l) if n > = N. Figure 8 shows the form of the function. From the statistical point of view, n must be large enough so that the two blocks do not overlap, that is, n > = N. If the blocks overlap, then the calculation of the second dispersion will use samples used for the calculation of the first dispersion. This effectively reduces the number of degrees of freedom and therefore the significance of the result. It has been determined that the set n = N works well. The function Q () in equation (13) actually provides the probability of a tail. H0 can be rejected if F is very large or very small, and thus the two-tailed test is required. Actually, the two tails are identical, so for the two-tailed test the probability is double that given in equation (13). However, this results in probability values greater than 1 for F < 1. Therefore, the probability, p, is calculated as follows: and then, if (p> 1), p = 2 - p. This probability reflects the viability of H0. Therefore, if p is small, H0 can be rejected and it can be established, with a certain degree of certainty, that the comparison blocks come from sample populations with different dispersion. The specification of the European telecommunications standard indicated establishes that the block size, N, must be 32 for a correlation algorithm. It has been tried successfully N =. { 32.64} . Figure 9 shows the probability functions obtained using these values for N. In the preferred embodiment, p < = 0.05 for the rejection of H0. An accurate implementation can calculate F, then x, and then the incomplete Beta function, then p and then apply the threshold test. This algorithm is very difficult to carry out in physical elements (hardware), since the Beta function is very complicated. In the preferred embodiment it is much simpler, and provides the same results, to establish the acceptance threshold and the parameter N and therefore to define the upper and lower limit for F. Afterwards it is only necessary to calculate F and compare it with the limits. In order to simply find the end of guard interval can be safely assumed that F >; 1 . Only the upper limit in F is needed. To accurately calculate the limits in F, an appropriate root finding method, such as Newton-Raphson, can be used. Typical values are given in Table 1.

Table 1 This method has been successfully tested using the specified channel model with additive white Gaussian noise (SNR = 3.7). The formula for the dispersion provided in equation (12) requires a multiplier for implementation in silicon. The calculation of F is a division in which the normalization constant (N - 1) is canceled insofar as the two blocks have the same size. Precise multiplication and division can be expensive in silicon. In the preferred embodiment, simplifications have been implemented which result in less precise but still viable values for F. The assumption can be made that Sx has a zero mean so that it is not necessary to calculate the mean of the sample block. This also increases the degree of (N - l) to N. Instead of calculating variance using the standard sum of formula of squares, we can estimate the dispersion by the mean absolute deviation. The formula for VAR (i) becomes The factor (1 / N) divides in the calculation of F silos two blocks have the same size. But there is still the division of the two dispersions and the required square. This can be attacked using logarithms for base 2. Substituting from equation (16) in equation (11) provides Taking the logarithms to base 2 you get logF = 2 (1098, - logsb) = y (22) Then it is only necessary to calculate y and compare it with the logarithm to the base 2 of the upper limit of F. The comparison can be made by subtracting the log from the limit of 2 (log2sa-log2sb) and comparing it with zero. The factor of 2 can be absorbed in the limit.

The calculation of the log to base 2 is relatively linear in physical elements (hardware) if the numbers are stored as fixed point fractions. The fractions can be divided into an exponent and a frational mulberry: x = A2B. When log 2 is taken, logx = logA + B is obtained. Since A is a fraction, it is practical to find its logarithm using a search table. Exponent B can be found from the position of the MSB (since sa and sb will be both positive numbers). Therefore the calculation can be reduced so that only arithmetic addition and subtraction operations are required. The limit must also be calculated again using vl = v2 = N if this method is used. In practice, the level of significance can be adjusted empirically for a particular application, preferably p = 0.05. It will be appreciated by those familiar with the art that various dispersion measures may be used without departing from the spirit of the invention, for example standard deviation, skew, various moments, histograms, and other calculations known in the art. In a first alternative embodiment of the invention, the method described above is used either in the real or imaginary parts of the signal instead of the modules. This mode provides economy in the physical elements (hardware).

In a second alternative embodiment of the invention, parameter n of equation (11) has been optimized. At the end of the guard interval, the two blocks are coupled more than the transition of the active interval, which provides a well-defined increase in the dispersion. Using any value n > 2 has the disadvantage that several successive points will provide significant increases as the back block moves up to the limit. This small problem is easily solved by entering a dead period after detection of the limit. That is, once a peak has been detected, a set of samples equal to the size of the FFT interval is accepted before additional attempts are made to locate another peak. The dead period has added the benefit of not introducing false peaks. When larger values of n are used, the peaks 66, 68 are increased (FIG. 7), while the noisy signal F0 H remains the same in many ways.

Example 2: The maximum peak F height has been measured systematically as a function of n along with the background variation in F. The results are shown in Table 2.

Table 2 Table 2 was developed using the first five frames of the signal analyzed in Figure 7. The statistics in columns (2) and (3) of Table 2 are made by excluding any point where F > = 3.0 to exclude peaks from the calculations. The peaks would otherwise affect the values of the mean and the standard deviation even if they come from a different statistical population. The results indicate that the background variation in F, Fsd,, is affected by n, increasing asymptotically to a value of approximately 0.28. It is likely that this is the effect that overlaps blocks. For example, for N = 64 and n < 64, the blocks on which the dispersions are calculated will contain some of the same values and will therefore be correlated. To test this theory, Fß.d. for n > N, and the results are shown in Table 3.

Table 3 The dependency becomes linear to n > = N / 2 If F is calculated every n samples, instead of each sample, then this dependence can be reduced. However, this creates a risk that small guard intervals that do not have the first block completely within the guard interval and the second place the entire block within the active range. A third alternative embodiment of the invention is described with reference to FIG. 10, which schematically illustrates a timing synchronization circuit 70. The circuit accepts a complex input signal 72, and includes a circuit module 74 which develops the module of its input, which is taken from the node 83. The circuit module 74 ensures that the value that is processed subsequently is a number not signed. The input circuit module 74 is a difference signal which is developed by a subtractor 75 which takes as input the input signal 72 and a delayed version of the input signal 72 which has been proposed through a circuit 79 of delay, preferably performed as FIFO 77 of length L, where L is the size of the FFT interval. As explained above, it is also possible to operate this circuit where the input signal 72 is real, imaginary or complex, or even the module of a complex number. In the case where the input signal 72 is real, or imaginary, the circuit module 74 can be modified and can be any known circuit that removes the sign of the output of the subtractor 75, or equivalently sets the sign so that exits accumulate monotonically; that is, the circuit has a unipolar output. The circuit output of the module 74 is finally synchronized into a digital delay, which is preferably implemented as a FIFO 78. When the FIFO 78 is full, a SIG1 80 signal is assigned, and the output of the FIFO 78 becomes available, as it is indicated by the gate 82 AND (Y). And an add / subtractor circuit 84 is also connected to the node 76 and its output is stored in a register 86. A delayed version of the output of the add / subtractor circuit 84 is taken from the register 86 and fed back as a second input into the circuit 84 addition / subtractor on line 88. In the case where the signal SIG1 80 has been assigned, a version of the output of the circuit module 74, delayed by a first predetermined interval N, is subtracted from the signal at node 76. , where N is the number of samples in the comparison block. The signal on line 88 is an index within the Search table, preferably implemented as a read-only memory ("ROM") and shown as ROM 90. The address of ROM 90 contains the logarithm of the base 2 of the magnitude of the signal on line 88 , which then appears at node 92. Node 92 is connected to a subtracter 94, and a delay circuit, shown as FIFO 98, which is used to develop the denominator of the middle term of equation (17). The subtractor 94 produces a signal which is compared against the log2 of a predetermined threshold value FLIMIT in a comparison circuit 106, shown by simplicity as an adder 108 connected to a comparator 110. The output signal SYNC 112 is determined when located the limit of a guard interval.

Although not implemented in the present preferred embodiment, it is also possible to configure the size of the FIFO 77 dynamically, so that the size of the interval being evaluated can be adjusted according to the operating conditions. This can be conveniently accomplished by storing values on the node 92 in a RAM 114 for calculating its dispersion. In a fourth alternative embodiment of the invention, explained with reference to Figure 11, components similar to those shown in the embodiment shown in Figure 10 have the same reference numerals. A timing synchronization circuit 116 is similar to the timing synchronization circuit 70, except that the delay circuit 79 is now performed as the FIFO 77, and another FIFO 100, one of which is selected by a multiplexer 102. Both FIFO's < 77 and 100 provide the same delay; however, the capacities of the two are different. The FIFO 100 provides for storage of samples taken in an interval equal to the size of the FFT interval, and is normally selected in a first mode of operation, for example during channel acquisition, when it is necessary to evaluate a complete symbol in order to locate a limit of a guard interval. In the indicated European telecommunications standard, up to 8 K of data storage is required, with commensurate resource requirements. During the subsequent operation, the approximate location of the guard interval limits will be known from the background of the previous symbols. In a second mode of operation, therefore, it is necessary to evaluate a much smaller interval in order to verify the exact position of the guard interval limit. The number of samples used in the calculation of the dispersion can be maintained in a small number, preferably 32 or 64, and the much smaller FIFO 77 is accordingly selected to maintain the calculated values. The resources saved in this way can be used for other functions in the demodulator, and the memory used by the larger FIFO 100 can also be reassigned for other purposes. A control block 81 optionally advances the evaluation interval in relation to the symbol limits in the data stream in successive symbols, and can also be used for delay for the dead period. Finally, the moving evaluation interval is coupled to the limit of the guard interval of the current symbols and then the synchronization is determined. The size of the evaluation interval is chosen to minimize the use of memory, although it must be large enough to obtain statistical significance in the evaluation interval. The size of the evaluation interval, and the FIFO 77 can be configured statically or dynamically.

Implementation on a single chip of a COFDM demodulator Generalities Referring initially to Figure 12, a high-level block diagram of a multi-carrier digital receiver 126 according to the invention is shown. The modality described in the following is adapted to the telecommunications standards ETS 300 744 (2K mode), but can be adapted by those familiar with the art to operate with other standards without departing from the spirit of the invention. A radio frequency signal is received from a channel such as an antenna 128, to a tuner 130, which is conventional, and preferably has a first and second intermediate frequency amplifiers. The output of the second intermediate frequency amplifier (not shown) is conducted on line 132 to an analog-to-digital converter 134. The digitized output of the analog-to-digital converter 134 is provided to the block 136 in which the I / Q, FFT demodulation, channel estimation and correction, internal and external deinterleaving and forward error correction are carried out. The recovery of the carrier and the timing are performed in block 136 completely in the digital domain, and the only feedback to the tuner 130 is the automatic gain control signal ("AGC") which is provided on the line 138. A stable 120 MHz clock is provided on the line 140 for use as a sampling clock for the external analog-to-digital converter 134. A host microprocessor interface 142 may be in parallel or in series. The system has been arranged to operate with a minimum of host processor support. In particular, acquisition of a particular channel can be obtained without any intervention of the host processor. Functions performed within block 136 are grouped by display convenience at a front end (Figure 13), FFT and a channel correction group (Figure 14) and a rear end (Figure 15). As shown in Figure 13, the I / Q samples that are received by a demodulator 144 IQ of the analog-to-digital converter 134 (Figure 12) on a common link 146 at a rate of 20 mega-samples per second. An AGC circuit 148 also takes its common link input 146. A frequency rate control circuit is implemented using a numerically controlled oscillator 150, which receives frequency error signals on line 152, and error update information of frequencies on line 154. Frequency and sampling rate control are obtained in the frequency domain, based on information from the pilot carrier. The frequency error signals, which are derived from the pilot carriers, and the frequency error update information will be described in more detail briefly. The data output I and Q of the demodulator 144 IQ are both passed through identical low-pass filters 156, decimated at 10 mega-samples per second, and provided in a synchronous interpolator 158. Sampling rate control is obtained using a numerically controlled oscillator 160 which receives rate control information from samples derived from the pilot signals on line 162, and receives sample error update timing information on line 164. As shown in Figure 14, acquisition and control of the FFT interval is performed in block 166, which receives signals from synchronous interpolator 158 (Figure 13). The FFT calculations are performed in the FFT calculation circuits 168. Channel estimation and correction are performed in block 170 for channel estimation and correction and involves the location of the pilot carriers, as will be described in more detail below. The tps information obtained during the pilot location is processed in block 172 of tps sequence extract. The uncorrected pilot carriers are provided by the circuits of the channel estimation and correction block 170 to the correction circuits 174, which develops sampling rate error and frequency error signals that are fed back to the controlled oscillators 150, 160 numerically (figure 13).

With reference to FIG. 15, the output of corrected I and Q data from the channel estimation and correction block 170 is provided to the detransformation circuit 176. The current constellation and hierarchical constellation parameters derived from the tps data are also entered into the lines 178, 180. The resulting symbols are deinterleaved in the symbol deinterleaver 182 using a memory storage 1512 x 13. One bit of each cell in the Memory storage is used to mark carriers that have insufficient signal strength for reliable channel correction. Then the bit deinterleaver 184 provides the deinterleaved I and Q data to a Viterbi decoder 186, which discards the tagged carriers, so that the unreliable carriers do not influence the rollback metric. A deinterleaver 188 Forney accepts the output of the Viterbi decoder 186 and is coupled to a Reed-Solomon decoder 190. The front error correction provided by the Viterbi and Reed-Solomon decoders is based on the recovery of lost data in the case of tagged carriers. With reference to Figure 16, in the currently preferred embodiment an average value is calculated in block 192 for uncorrected carriers with reference to the previous symbol. The data carriers whose interpolated channel response is below a certain fraction, preferably 0.2, of this average will be marked with a label 194 bad_carrier (bad carrier). The bad_carrier tag 194 is transported through the detransformation circuits 176, the deinterleaver 182 of symbols and the deinterleaver 184 of bits, to the decoder 186 Viterbi where it is used to discard data in relation to the unreliable conveyors. The parameters used to set the label bad4carrier 194 can be varied by the interface 142 of the microprocessor. An output interface 196 produces an output which can be an MPEG-2 transport stream. The deinterleaver 182 of symbols and the deinterleaver 184 of bits are conventional. The Viterbi decoder 186, the Forney deinterleaver 188, the Reed-Solomon decoder 190 and the output interface 196 are conventional. They may be components described in copending application No. 638,273 entitled "An Error Detection and Correction System fos a Stream of Encoded Data" ("An error detection and correction system for a coded data stream"), filed on April 26. of 1996, the request 480,976, entitled "Signal Processing System", filed on June 7, 1995, and application 481107, entitled "Signal Processing Apparatus." ("Signal Processing Apparatus"), filed June 7, 1995, all of which is commonly assigned herein and incorporated herein by reference. The operation of the multi-carrier digital receiver 126 (FIG. 12) is controlled by a system controller 198. Optionally, the parameters of 'hierarchical constellation can be programmed to accelerate channel acquisition, instead of being derived from the tps data. The input and output signals and the registration map of the multiple carrier digital receiver 126 are described in Tables 4 and 5 respectively.

Automatic gain control The purpose of the AGC circuit 148 (FIG. 13) is to generate a control signal to vary the gain of the COFDM input signal to the device before it is converted from analog to digital. As shown in greater detail in Figure 17, a Sigma-Delta 200 modulator is used to provide a signal which can be used as a gain control to a tuner, once it has been subjected to low pass filtering by an external RC network. The magnitude of the control voltage signal 202 is given by: control_voltage = control_volt je - error (23) voltage control = voltage control - error where error = K (| data | - media) (24) where K is a constant (usually K <<1) which determines the gain in the AGC control circuit. The average value can be determined from the Gaussian noise statistics, which is a close approximation to the properties of the COFDM input signal, where the input data is scaled to +/- 1. The voltage signal 202 from 'control is set back to its initial value when the signal resynchronization 204 is set low, indicating a channel change or some other event that requires resynchronization. The input and output signals and the registers of the interface 142 of the microprocessor of the AGC circuit 148 are described in Tables 6, 7 and 8, respectively.

Q Demodulator The function of the demodulator 144 IQ (FIG. 13) is to recover the in-phase and quadrature components of the sampled data received. It is shown in greater detail in Figure 18.

The oscillated 150 numerically controlled generates sinusoids in quadrature phase at a speed of (32/7) MHz, which are then multiplied with the data samples in the multipliers 206. The steering generator 208 linearly advances the phase. The frequency error input 210 increases or decreases the phase advance value. The samples are multiplied with the sinusoids in multipliers 206 using multiplication operations of 10 bits x 10 bits. In one embodiment, the demodulator 144 IQ is operated at 20 MHz and then is re-timer at 40 MHz in the re-timing block 212. In a preferred embodiment, the demodulator 144 IQ is operated at 40 MHz, in which case the re-timing block 212 is omitted. The sinusoids are generated by the address generator 208 on the lines 214, 216. The phase value is used as an address in a search table ROM 218. Only cycle rooms are stored in the search table ROM 218 to store area. Full cycles of stored room cycles can be generated by manipulating data from ROM 218 and reversing the data in the case of negative cycles. Two values of the ROM 218 of the search table are read for each input sample - one cosine and one sine, which differ in phase by 90 degrees. The input and output signals of demodulator 144 IQ are described in Tables 9 and 10, respectively.

Low pass filter The purpose of the low pass filters 156 (Figure 13) is to remove randomized frequencies after IQ demodulation - frequencies greater than 32/7 MHz. Second IFs are suppressed by 40 dB. The I and Q data are filtered separately. The data transmitted is decimated at 10 mega-samples per second ("Msps") because the filter removes any frequency above 1/4 of the original 20 Msps of sampling rate. The filter is constructed with approximately 60 intermediate connections which are symmetric around the center, which allows the filter structure to be optimized to reduce the number of multipliers 220. Figure 19 is a block diagram of one of the filters 156 low step, the other is identical. Figure 19 shows a representative symmetric intermediate connection 222 and a middle intermediate connection 224. The required filter response of the low pass filters 156 is shown in Figure 20. Tables 11 and 12 describe the low pass filters 156 input and output signals, respectively.

Resampling With reference to Figure 13, the purpose of the resampling is to reduce the output of 10 Msps data streams from the low pass filters 156 by decreasing to a speed of (64/7) Msps, which is the nominal sample rate of a terrestrial digital video broadcast modulator ("DVB-T") in the transmitter. The resampling is accompanied by the synchronous interpolator 158, and the oscillator 160 controlled numerically. The latter generates a nominal signal of 64/7 MHz. Figure 21 shows the resampling circuits in greater detail. The numerically controlled oscillator 160 generates a valid pulse on line 226 and a signal 228 representing the interpolation distance for each 40 MHz clock cycle at which a 64/7 MHz sample can be produced. interpolation to select the appropriate set of interpolation filter coefficients which are stored in coefficient ROM 230. It should be noted that in Figure 21 only the synchronization interpolator for data I is illustrated. The structures for the Q data are identical. Figure 22 illustrates the generation of the interpolation distance and the valid pulse. Nominally, Ta = 1/10 Msps and T = 1 / (64/7) Msps. The synchronous interpolation circuit described in our application indicated No. 08 / 638,273, is suitable, with the appropriate adjustment of the operating frequencies. The input and output signals of the synchronization interpolator 158 and the numerically controlled oscillator 160 are described in Tables 13 and 14, respectively.

FFT Interval As I have explained in detail in the above, the function of the FFT interval is to locate the "active interval" of the COFDM symbol, as different from the "guard interval".

This function is referred to herein as "FFT window" for convenience. In this modality of the active interval it contains the domain representation of the time of the 2048 carriers which will be recovered by FFT itself. The FFT interval operates in two modes; acquisition and follow-up. In the acquisition mode, the entire incoming sample stream is analyzed by the guard interval / active interval limit. This is indicated when the F ratio reaches a peak, as discussed above.

Once this limit has been located, the interval timing is activated and the stream of samples entering by the next guard interval / active interval limit is investigated again. When this has been located, the length of the guard interval is known and the position of the next guard / asset limit can be predicted. The FFT window function then switches to tracking mode. This modality is similar to the fourth alternative modality discussed earlier with respect to the tracking mode. In tracking mode, only a small section of the sample stream entering around the point where the guard / asset limit is expected is analyzed. The position of the active interval is derived slightly in response to the IF frequency and the sampling rate offsets at the leading end before FFT is calculated. This derivation is followed and the timing of the FFT interval is corrected, the corrections are inserted only during the guard interval. It will be appreciated by those familiar with the art that in the implementation of a single chip practice as described herein, memory is a costly resource in terms of chip area, and therefore should be minimized. With reference to Figure 23, during the acquisition mode, the FFT calculation process is not active so that the physical elements (hardware) can be shared between the FFT interval and the FFT calculation, most notably, it is used a RAM 232 of 1024 x 22 as a FIFO by the FFT interval, and is selected for reception of FFT data on the line 234 by a multiplexer 236. Once in the tracking mode, the FFT calculation process is activated in a manner that other control circuits can be started to recover the sampling rate and frequency, which depend on the FFT data (for example, pilots in the COFDM symbol). Therefore, the tracking mode requires a dedicated tracking FIFO 238, which is selected by a multiplexer 240. The input and output signals, and the signals in relation to the microprocessor interface 142 of the FFT interval circuits shown in figure 23 they are described in Tables 15, 16 and 17, respectively. In one embodiment, a threshold level, established from statistical concentrations, is applied to the F-ratio signal (see Figure 7) to detect the negative and positive peaks which occur at the beginning and at the end of an extreme guard interval, respectively. The distance between peaks is used to estimate the size of the guard interval. Repeated detection of positive peaks is used to confirm correct synchronization. However, with this method under noisy conditions, the F-ratio signal becomes noisy and the peaks are not always reliably detectable.

In another embodiment, peak detection is used to find the peaks in proportions F. It has been found that a fixed threshold is reliable only at or exceeding approximately the carrier-to-noise ratio ("C / N") of 12 dB. Peak detection is generally more sensitive and more specific, with a generally reliable operation at 6-7 dB. The maximum must be presented at the end of the guard interval. The difference in time between two maxima is checked against the possible guard interval sizes. With a tolerance for noise, the difference in time indicates the most probable guard interval size and the maximum in itself provides a good indication of the start of the active part of the symbol. Preferably this process is confirmed for several symbols to confirm the detection, and it is expected to improve operation when the C / N ratio is low. The data stream is passed to accumulators 242, 244, each has modules 64. The conversion to logarithms and subtraction of the logarithms is performed in block 246. The peaks are detected in block 248 peak detector. The averaging of the symbol peaks is performed in block 250. Under noise conditions, the maximum may be due to noise that provides possibly inaccurate indications of the length of the guard interval and the start of the active symbol. The general strategy to solve this is to make a limited number of retries. Currently, the calculation of the F ratio is done "in the process", that is, only once at each point. The variance estimates are calculated from 64 values only. Under noisy conditions, the variance estimates become very noisy and the peaks may be obscured. In an optional variation, this problem is solved by obtaining more values for the variance estimate, by storing the variance estimate during the acquisition for each of the possible points T + Gmax in the storage block 256. The estimates of variance itself can be formed by accumulating variances for each point, and then filtering in time for a number of symbols. An average moving filter on an infinite impulse response filter ("IIR") is adequate. A running movement of symbols, preferably between 16 and 32, is integrated into block 252, and which increases the reliability of peak detection under noisy conditions. The storage block 256 maintains the integrated F-ratio values and is examined to find the maximum value. This is of length T + Gmax where Gmax is the maximum guard interval size, T / 4. Preferably, the memory for the storage block 256 is assigned dynamically, depending on whether the acquisition mode or the tracking mode is operative.

Any unused memory is released to other processes. Similarly, in the tracking mode the integrated data stream is stored in the tracking integration buffer 254. This method has been tested with up to 4 symbols, without an IIR filter, and it has been found that peaks can be recovered. However, this approach requires increased memory.

FFT processor The discrete Fourier transform ("DFT") has the following well-known formula L-1 x () = 1 ?? (n) Wnk = 0.1 N-1 (25) i- n «_ where N = number of points in the DFT; x (k) = the kth output in the frequency domain; x (n) = the nth entry in the time domain, W «" ß e --nnUD (26) W is also known as the "singing factor".

For N > 1000, the DFT imposes a heavy calculation load and becomes impractical. Instead of using the continuous Fourier transform, given by t_ + » The continuous Fourier transform, when calculated according to the well-known FFT algorithm, decomposes the original sequence of point N into two shorter sequences. In the present invention, the FFT is implemented using the basic butterfly unit 258 as shown in Fig. 24. The outputs C and D represent equations of the form C = A + B, and D = (A-B) Wk. The butterfly unit 258 takes advantage of the fact that the power of W is really only complex additions or subtractions. A real-time FFT processor, performed as an FFT calculation circuit 168 (Fig. 14) is a key component in the implementation of the multiple carrier digital receiver 126 (Fig. 12). We have implemented known 8K FFT channeling chips with 1.5 M transducers that require an area of 100 mm2 in 0.5 μ technology, based on the architecture of Bi and Jones. Even using a memory implementation with digital delay line technique of three transients, they are necessary on the 1M transistors. This has been further reduced with an alternative architecture to 0.6M, as reported in the document A New Approach to Pipeline FFT Processor (A new approach for a channelized FFT processor). Shousheng He and Mats Torkelson, Teracom Svensk RundRadio. DTTV-SA180, TM 1547. This document proposes a radix-22 algorithm oriented in physical elements (hardware), which has a radix-4 multiplicative complexity. However, the requirements of the FFT calculation in the present invention require the implementation of an FFT radix-22 + 2 processor. With reference to Figure 25 and Figure 26, the butterfly structures BF2I 260 and BF2II 262, known from the indicated publication of Torkelson, are shown. The butterfly structure BF2II 262 differs from the butterfly structure BF2I 260 in that it has a logic 264 and has a crossing 266 to cross the real and imaginary inputs to facilitate multiplication by -j. Figure 27 illustrates the retemporized architecture of a FFT radix 22 + 2 processor 268 according to the invention, which is completely channelized, and which comprises a plurality of stages, stage 0 270 to step -6 272. Except for in step 0 270, each of the steps comprises a butterfly structure BF2I 260 and a butterfly structure BF2II 262, and storage RAM 274, 276 associated with them, stage 0 270 has only a single butterfly structure BF2I 260. This architecture performs direct linear 32 point FFT. Step 6 272 has a control logic associated therewith, which includes a demultiplexer 278 and a multiplexer 280, which allows step 6 272 to be derived, and therefore provides a 2 K implementation of the FFT. The counters 282 configure the butterfly structures BF2I 260 and BF2II 262 to select one of the two possible possible diagonal calculations, during which the data is written simultaneously and read from the storage RAM 274, 276. Figure 28 illustrates a point 32 of a flow chart of the FFT 268 processor using the radix 22 + 2 channeling architecture. The calculations are made using 8 four point FFT and 4 eight point FFT. These are decomposed in turn into 2 FFT of four points and 4 FFT of two points. Fig. 29 illustrates the retemporized architecture of a single configurable path of 2K / 8K radix 22 + 2, a delayed feedback channeling FFT processor 284, in which similar elements in Fig. 27 are given the same numbers of reference. The stages have a plurality of channelization registers 286 which are required for an appropriate timing of the butterfly structures BF2I 260 and BF2II 262 in the various stages. As you can see, the addition of each channeled stage multiplies the FFT range by a factor of 4. There are 6 complex multipliers 288, 290, 292, 294, 296, 298 which operate in parallel. This processor calculates a pair of I / Q data points every four clock cycles, which is equivalent to the sampling rate rate. Using the 0.35 μm technology, the worst case performance is 140 μs for the 2 K mode of operation, and 550 μs for the 8 K mode, exceeding the requirements of the ETS 300 744 telecommunications standard. The data enters the canalization of the left side of figure 29, and emerge from the right side. The buffering requirements are 2 K / 8 K for I data and 2 K / 8 K for Q data, and it is mode dependent. In practice, the radix-4 stage is implemented as a cascade of two adapted radix-2 stages that take advantage of the radix-4 algorithms to reduce the number of complex multipliers needed. Figure 30 is a schematic of one modality of the multipliers 288, 290, 292, 294, 296, 298 to perform the complex multiplication C = A x B, where A is the data, and B is a coefficient. Because the FFT processor 284 has six complex multipliers, each requires three multipliers 300 of physical elements (hardware), so a total of 18 hardware multipliers 300 would be required. It is preferable to use the modality of figure 31. , in which some of the hardware multipliers 300 are replaced by multiplexers 302, 304. Returning again to FIG. 29, there is a plurality of RAM 306, 308, 310, 312, 314, 316 which are preferably performed as ROM and they contain search tables containing complex coefficients comprising cosine for the multipliers 288, 290, 292, 294, 296, 298, respectively. It has been found that when addressing RAM 306, 308, 310, 312, 314, 316 according to a particular addressing scheme, the size of these RAMs can be greatly reduced. The balance between the complexity of addressing circuits and the reduction in RAM size becomes favorable starting at step 3 318. Referring again to FIG. 28, there are two columns 320, 323. Column 320 maintains values 2 - W14, followed by W1 - 7, and then W3 - 21. These coefficients are stored in RAM 308, needed by the particular multiplier 290. Column 322 contains values Wß, 4, W12, which are repeated three times. Note further that between the values 8, 4, and W12, are the connections 324, 326 to the preceding throttle unit located in column 328. In practice, the connections 324, 326 are implemented as multiplications by W °. When moving from one multiplier to another to the left in Figure 29, the space of the search table is multiplied by a power of 4 in each stage. In Figure 32, Table 330, the lookup table for multiplier M3 contains 512 entries. It can be deduced by extrapolation that the multiplier Ms must contain 8192 singing factors, and corresponds to the size of FFT that is being made by the FFT processor 284 (figure 29). Before examining the space of the search table in greater detail it is useful to consider the plurality of horizontal lines 332. Moving down from the top of Figure 28, the line starting at x (3) extends to W8, which is the required singing factor and is in the third effective stage in the flow chart. Figures 33 and 32 show the organization of the singing factors for each of the multipliers, where the terminology Mk represents the multiplier associated with the twentieth stage. Therefore, Table 334 is related to the Ms. multiplier. The notation for the W values (singing factors) is shown in the rectangle 336. The subscript "B" in the lower right represents a mark in time, which it is an order of dependency in which the factors of singing through the channeling are required. The subscript "A" represents the address of the sing factor in your search table. The superscript "N" is the index of the singing factor. Therefore, Table 334 can be observed that ° is necessary at time 0, W1 at time 1, and W ° is required again at time 2. An additional inspection of the tables to figures 33, 32 reveals that Half of the entries in each table are redundant. The storage requirement for the search tables can be reduced by 50% by eliminating redundant entries. This has been done by organizing the values of W in ascending order by index, so that the values can be stored in the memory in ascending order. Therefore, in the case of Table 338, the index values vary from 0 to 21, with spaces in 11, 13, 16, 17, 19 and 20. The procedure for organizing the lookup table and the addressing scheme to access the singing factors are explained with reference to Table 338, but it is applicable to the other Tables in figure 33. (1) Each row is assigned a line number as illustrated. (2) Each singing factor is assigned a dependency of order which is noted in the lower right part of its respective cell in Table 338. (3) The assumption is established that Table 338 in its reduced form concentrates only factors sing songs in ascending order by index within the memory address space. In consecuense, each singing factor is assigned a memory address as shown in the upper left part of its respective cell. During address generation, for line 3 of Table 338 the address is simply kept at 0. For line 1 the address is incremented by 1 at the end of the line. However, lines 0 and 2 do not contain trivial addressing sequences. For line 0, the search in Table 340, which contains 64 values, it will be observed that the direction sequence changes according to the intervals 2,2,2,2 and then later 1,1,2,1,1 , 2 ... For line 2, the address is first increased by 3, then by 2 and finally by 1. The positions in which the changes in address increment in the present refer to as "breakpoints". These values of the breakpoints vary between 0, which corresponds to the first point on line 2, until the last position on the line. By inspection, it can be observed that the frequency of presentation of the first break point changes from one table to another following the recurrence relationship with the initial condition B1 «. = 1 (29) where MN is the multiplier of the nth stage of the 284 FFT processor. Expanding the recurrence relationship you get: B1 ,,, - < ((4B1Mú-1) x4-1) x4-1) .... { 30) B1MM = 4 «B1Mo- N -3-4N-2 ...- 4 ° (31) N-1 B1«. - * "B -? 4" (32) n-0 Similarly, the second breakpoint B2 for line 2 is determined from the recurrence relation B MN = B2MM_t + 1 (33) with the initial condition B2 • UMt = 1 (34) O well B2M = (((4B2M +1) x4 + 1) x4 + 1) (35) B2M =? 4 * (36) n = 0 Breakpoint B3 for line 0, in which the increment sequence of 2.2.2.2 changes to the pattern 1,1,2,1,1,2 ... can be placed when inspecting Tables 338 , 343 and 330. In Table 338, the breaking point B3 occurs very late in the line, so that in the second sequence it only presents its first two elements. When examining the address positions in the larger annotated Tables, it can be deduced that the position at breakpoint B3 is related in the number of entries in a particular table as B3 (37) 4 where K is the number of entries in the table. In the tables, in figure 29, K = 8, 32, 128, 2048, 8192. Therefore, in terms of the nth complex multiplier, the breaking point B3 can be expressed as B3M = 2 x 4N + 2 (38) where N > 0 The address generators 342, 344, 346, 348 are operative for the search tables in the RAM 310, 312, 314, 316. The silicon area savings for the smaller tables 308, 306 are too small to perform in this scheme in the meantime. Fig. 34 schematically illustrates a direction generator 342 for the address generation scheme described above, and is specific to Table 340 and multiplier M2. 128 possible states of entry are accepted in the in_Addr 350 lines and a multiplexer 352 selects the two most significant bits to decode 1 of 4 values. The output of the multiplexer 352 is related to the number of lines of the input state. Currently the output is the address increment applicable to the line number of the input state, and is used to control a counter 354 whose incremental address changes according to the value on line 356. Therefore, the increment is provided for line 3 of Table 340 to multiplexer 352 on line 358, and has a value of 0, as explained above. Similarly, the increment is provided by the line of Table 340 to multiplexer 352 on line 360 and has a value of 1. The situations of line 0 and line 2 are more complicated. For line 0, the output of the decoding logic circuit 362 is provided by the multiplexer 364, and has an increment value of 2, or the output of the multiplexer 366. The latter can be 1 or 2, depending on the state of a counter 368. 2-bit, which feeds a value of 0 or 1, such as a 370 signal count. The decoding logic circuit 372 decodes the states for line 2 of Table 340. The relationship of the current input state to the two breakpoints of line 2 is tested by comparators 374, 376. The breaking point is actually is set to a sample earlier than the comparator output to allow re-timing.

The outputs of comparators 374, 376 are selectors for multiplexers 378, 380, respectively. The current address, which is maintained in the accumulator 382, is increased by the output of the multiplexer 352 by the adder 384. A simple logic circuit 386 resets the output address which is contained in the ACC register 388, by determining the signal rst 390 before the completion of each line of Table 340. This ensures that at the beginning of the next line the address points to the singing factor °. The new address is an output on the 6-bit common link out_address (address_exit) 392, which is a smaller bit of the input in_Addr (address_input) 350. Figure 35 is a generalization of the address generator 342 (figure 34), in which the input address has a path of B bits. Similar elements in Figure 34 and 35 are given the same reference numbers. The structure of the address generator 394 is similar to that of the address generator 342, except that now the various lines of the input in_addr 396 and the output out_addr [B-2: 0] 398 are indicated in terms of B. Therefore, the multiplexer 352 in FIG. 35 is selected by the input in_addr [Bl: B-2] 400. Similarly, one of the inputs of the comparator 374 and the comparator 376 is in_addr [B-3: 0] 402. Out_addr [B- 2: 0] 398 form the exit. The advantage of this structure is a reduction in RAM search size of 50%.

The FFT calculation circuits 168 (Figure 14) are described in Verilog code lists 1-17. The Verilog code for the address generator 394 is generic, which allows any power table of four to be implemented.

Channel estimation and correction The function of the channel estimation and correction circuits shown in block 170 of channel estimation and correction (figure 14) is to estimate the frequency response of the channel based on the values received from the continuous and dispersed pilots specified in the standard. telecommunications ETS 300 744 and generates compensation coefficients which correct the channel effects and therefore reconstruct the transmitted spectrum. A more detailed block diagram of block 170 of channel estimation and correction is shown in Figure 16. In the acquisition mode, the channel estimation and correction block 170 needs to locate the pilot signals before any channel estimation takes place. The circuits perform a convolution through 2048 carriers to locate the positions of the dispersed pilots, which are always evenly separated, separated by 12 carriers. Having found scattered pilot, continuous pilot can be located; once this is done, the exact position of the 1705 active carriers within the 2048 outputs of the FFT calculation circuits 168 is known (Figure 14). At that time a timing generator 404 can be initialized within the block, which then generates reference timing pulses to locate pilots for estimation and calculation of channels and for use in other functions of the demodulator as well. The channel estimation is performed using the scattered pilot evenly spaced, and then interpolating between them to generate the frequency response of the channel. The received carriers (pilots and data) are complex divided by the interpolated channel response to produce a corrected spectrum. In a buffer 406 a complete symbol is maintained. This is corrected for the inverted bit order of the data received from the FFT calculation circuits 168. It should be noted that uncorrected data is required, untreated by the frequency and sampling rate error circuits. The task of synchronizing the OFDM symbol in the frequency domain data received from the FFT calculation circuits 168 (Figure 14) begins with the location of scattered and continuous pilots, which occurs in the pilot locator block 408. The dispersed pilots, which according to the telecommunications standard ETS 300 744 are produced every 12 data samples, are deviated by three samples with respect to the start of the frame in each successive frame. Since the power of the pilot carriers is 4/3 at maximum power of any data carrier, correlation sequences are made using separate carrier sets at 12-hour intervals. One of the 12 possible sets is highly correlated with the power of the reinforced pilot carrier. A first embodiment of the pilot search procedure is now described with reference to FIGS. 36 and 16. It should be noted that the search procedure of the dispersed pilot is performed in the process, and storage is required only to the extent that it is necessary to perform the subsequent stage of continuous pilot location, discussed later. In step 410, after determination of the signal resynchronization 204, which generally occurs after a channel change or when activated, the signal pilot immobilizer 412 is set low or inactive. Then, in step 414 the process waits for the first symbol pulse of the FFT calculation circuit 168 (FIG. 14) on line 416 indicating the beginning of the first symbol. The first symbol is received and stored. In one mode of the pilot search procedure, each point is read from 0 to 2047, accumulating each value (| l | + | Q |) in one of 12 accumulators (not shown). In turn, the accumulators are selected in a cycle of 12, by - ßl - so that possible dispersed pilot positions are convoluted. Two well-known peak followers indicate the accumulator with the highest value (Peak 1) and the accumulator with the second highest peak (Peak 2). The accumulator that has the highest value corresponds to the scattered pilot orientation. The second highest value is tracked or tracked so that the difference between the highest peak and the second highest peak can be used as a measure of "quality". In decision step 418, if the two peaks are not sufficiently separated, a test is performed to complete a full-range frequency sweep in decision step 420. If the test fails, a fault of the scattered pilot search is reported in step 422. Otherwise, in step 424 the IQ demodulator of the LO frequency increases +1/8 of the separated carrier by increasing the magnitude of the control signal freq_sweep 426. Then, the search is repeated by the scattered pilot after delaying 3 symbols in step 428 to allow time to carry out the change for propagation through the FFT calculation circuits 168 and the intermediate memories The peak difference threshold can be altered by the control microprocessor via the microprocessor interface 142 and block 430.

In a variation of the first mode there is only a single peak tracking which indicates the accumulator with the highest value, which corresponds to the scattered pilot orientation. The true scattered pilot orientation in this way is in one of 12 possible orientations. If the test in the decision stage 418 is successful, the continuous pilot search in step 432 is started by establishing an initial pilot displacement from the 0 position in the RAM, storing the FFT data, according to the formula pilot displacement = (accumulator # mode 3) (39) Therefore, if the dispersed pilot peak is in accumulator 0, 3, 6 or 9, the deflected pilot is 0. If the scattered pilot peak is in an accumulator 1, 4, 7 or 10, then the pilot displacement is 1, etc. Then the positions of the carrier 45 expected for continuous pilots are read, adding a pilot displacement value to the addresses, and accumulating values (| l | + | q |). This procedure is repeated until the first 115 continuous pilot start positions have been examined. From the telecommunication standard ETS 300 744, the number of first possible carrier positions among the active carriers that are in a contiguous block between the carrier 0 and the carrier 2047 is easily calculated as (2048-1705) / 3 «115 , as explained in the following. Therefore, it is guaranteed that the active interval begins with the first carrier position (2048-1705). The carrier that corresponds to the peak value stored in the first active carrier in the symbol. Upon completion of the continuous pilot search, in step 434, the timing generator 404 is reset to synchronize the first active carrier and the scattered pilot phase. The pilot_lock signal 412 is then activated in step 436, indicating that the pilots have been successfully located, and then in step 436 the timing generator 404 is readjusted to synchronize with the first active carrier and the scattered pilot phase. In the operation tracking mode, shown in step 438, the dispersed pilot search is periodically repeated, and evaluated in decision step 440. This can be done on each symbol, or less frequently, based on the propagation conditions. The predicted movement of the correlation peak of the scattered pilot signal is reflected by timing appropriately at the timing generator 404, and can be used as a proof that the timing has remained synchronized. A failure of the test in the decision step 440 is reported in step 442, and the pilot_lock signal 412 is inactivated. A second mode of the search procedure for the pilot signal is now described with reference to figures 16 and 37. In step 444, the determination of the signal resynchronization 204 occurs after a channel change or when activated, the pilot_lock signal 412 is inactivated. Then, a symbol is accepted for evaluation in step 446. In step 448 a dispersed pilots search is carried out according to any of the procedures explained above. A search for continuous pilots is then performed as described above in step 450. In decision step 452 it is determined whether the two symbols have been processed. If the test fails, the control returns to step 446 and another symbol is processed. If the test is successful in step 454, another test is performed to determine consistency in scattered and continuous pilot positions in the two symbols. If the test in step 454 fails, then the procedure begins with decision step 420 which is carried out in the same manner as previously described with reference to figure 36. If the test in step 454 succeeds in In step 456, the timing generator 404 is reset to synchronize with the first active carrier and the phase of the scattered pilot. The pilot_lock signal 412 is then activated in step 458, which indicates that the pilots have been located successfully. In the tracking operation mode, shown in step 460, the search for the scattered pilot is repeated periodically, and evaluated in decision step 462. This can be done in each operation cycle, or less frequently, based on the propagation conditions. The predicted movement of the correlation peak of the scattered pilot is reflected by appropriate timing in the timing generator 404 and can be adjusted as a proof that the timing has remained synchronized. The failure of the test in the decision stage 462 is reported in step 464, and the pilot_lock signal 412 is inactivated. It will be appreciated that after the scattered pilot has been located, the task of locating the continuous pilot is considerably simplified. As continuous pilots are inserted in a known sequence of positions, the first of which is deviated by a multiple of three positions with respect to the beginning of the frame, as specified by the telecommunications standard ETS 300 744. Therefore, it is they can exclude two of three possible location sets in the data space, and it is only necessary to look for the third set. Consequently, the search for the continuous pilot is repeated, and each interaction begins at a position 3 carriers above. The new accumulated values and the current start position are stored if they are greater than a previous accumulated value. This is repeated until all the continuous pilot start positions have been examined. The carrier corresponding to the largest stored peak value will be the first active carrier in the symbol. It is unnecessary to evaluate the "quality" of the correlation peak of the continuous pilot. The search for the dispersed pilot represents a correlation of 142 samples, and has a greater immunity to noise compared to the search of 45 continuous pilots. The search for continuous pilot is almost certain to be successful if the search for the dispersed pilot has been successfully completed. The previous sequences locate the positions of the scattered pilot within 1/4 of the symbol period, assuming an accumulation at 40 MHz, and locating the continuous pilot in less than 1 symbol period (45 x 115 clock cycles, assuming an operation 40 MHz). The I and Q data are provided to the pilot locator block 408 by the FFT calculation circuits 168 (FIG. 14) in the reverse order of bits on the line 416. This complicates the problem of using a minimal amount of RAM while the correlations are calculated during the pilot's location. Therefore, the bits of the input addresses and the calculated module 12 are inverted in order to determine which of the 12 possible deposits is for storing the data. In order to avoid the square root function necessary to approximate the carrier amplitude, the absolute values of the data are added instead, as a practical approximation. The dispersed pilot is determined "in the process". Continuous pilots are located in frames which follow the frames in which the dispersed pilots are located. The operation of the timing generator 404 will now be described in more detail. The addressing sequence for the buffer 406 RAM is synchronized by the symbol pulse of the FFT calculation circuits 168 (FIG. 14). The FFT calculation process runs continuously once the first symbol has been received after the acquisition of the FFT interval. The address alternates between an inverted address in bits and a linear address for successive symbols. The timing generator 404 also generates all the read-write timing pulses. The signals u_symbol 466 and c_symbol 468 are symbol timing pulses indicating the start of a new uncorrected symbol or a corrected symbol. The signal u_symbol 466 is delayed by a latency of the interpolation filter 470 and the multiplier 472 complex, which is synchronized in the RAM address sequence timer.

For timing the carrier, the signals c_carrier 474, the pilot timing signals us_pilot (+) 476, uc_pilot (+) 478, c_tps_pilot (*) 480 and the pulse 482 odd_symbol are referred to as a common start pulse sequence. A base timing counter (not shown) is synchronized by a synchronization timing pulse 484 to locate the pilot, and thus deviates from the symbol timing. The pilot timing outputs are also synchronized to an uncorrected symbol output from the buffer 406 or the corrected symbol output delayed by the interpolation filter 470 and the complex multiplier 472. When the signal resynchronization 204 is determined all timing outputs are set to inactive states until the first symbol is received. Assume that the pilot transmitted on carrier k is Pk and that the pilot received is P'k.

Pk / = Hk • wk • Pk (40) where Pk is described below, and PA = I "+ JQk (41) where k indexes the pilot carriers, Hk is the channel response and wk is the reference sequence. We interpolate Hk to generate compensation values for the received data carriers, D'k: D_ - «. + JQk t42 > where k indexes data carriers. The received pilot can be demodulated using a locally generated reference sequence and then passed to the interpolation filter. The interpolation filter 470, performed in this modality with 6 caps and 12 coefficients, is used to estimate the channel portion among the dispersed pilots. As explained above, the pilots are transmitted at known power levels in relation to the data carriers and are modulated by a known reference sequence according to the telecommunications standard ETS 300 744. The amplitudes of the transmitted pilot carrier are ± 4/3 of the nominal data carrier power (± 4/3 for the reference bit of 1, -4/3 for the reference bit of 0, the quadrature component = 0 in both cases). The interpolation coefficients of the cyclic count 0-11 are selected in the timing generator 404 synchronized with the data availability. You can select the appropriate correction factors for data points to provide correction in the process. The coefficients vary based on the scattered pilot phase. Since the positions of the reference pilots vary, therefore the coefficients to compensate for a given data carrier also vary. The input and output signals and the signals in relation to the microprocessor interface 142 of the channel estimation and correction block 170 are described in tables 18, 19 and 20 respectively. The circuits of the channel estimation and correction block 170 are described in the Verilog code listings 18 and 19.

TPS sequence extract Block 172 of sequence extract tps (see Figure 14), although set as a separate block for clarity of representation, is actually partially included in block 170 for channel estimation and correction. It retrieves the 68-bit TPS data transported in the OFDM frame of 68 symbols, and is shown in greater detail in Figure 38. Each bit is repeated in a differential binary phase shift 17 of key-modulated carriers ("DBPSK"), the pilot tps, inside a COFDM symbol to provide a highly robust transport channel. The 68 bit tps sequence includes 14 parity bits generated in a BCH code, which is specified in the telecommunications standard ETS 300 744. Of course, appropriate modifications can be made by those familiar with the art for other standards that have different BCH encoding, and for other modes than 2K mode. A cutter (cutter circuit) 486 trims the corrected spectrum data that enters ± 1. The sign bit can be optionally evaluated to obtain the trimmed result. In comparison block 488, the trimmed received tps pilot symbols are compared against the reference sequence input. In the described embodiment a value of 0 in the reference sequence coincides with -1 in the pilot, and a value of 1 in the reference sequence coincides with +1 in the pilot. Most of the voting comparisons are used to provide a total result of +1 or -1. A result of +1 implies the same modulation as the reference sequence, and a result of -1 implies inverse modulation, and a result of -1 implies inverse modulation. The DBPSK 490 demodulator converts the sequence +/- 1 for most of the voting form to a binary form. The sequence converts to a value of 0 if the modulation of the current and the previous symbols have the same, and of 1 if the modulation between successive symbols is inverted. From a non-initialized condition, a search is carried out either by two synchronization words in the 68 bit tps sequence (4 x 68 bits = 1 super frame) in the frame synchronizer block 492. The synchronization words of a superframe are as follows: 0011010111101110 synchronization words for frames 1 and 3 1100101000010001 synchronization words for • Frames 2 and 4 Having acquired any of the synchronization words, a search is carried out by the other in the appropriate position in the following OFDM frame. By finding the second synchronization word, a sync signal generating tps_sync 494. The data after BCH decoder 496, which operates on 14 parity bits at the end of an OFDM frame against data received in the frame they are passed declaring . Errors are corrected as necessary. The decoded data is provided in the block 498 outbound storage, which stores the tps data that is found in the entire OFDM framework. The output storage block 498 is updated only at the end of an OFDM frame. Only 30 bits of interest become available. Currently, some of these bits are reserved for future use. The length indicator is not retained. A 496 BCH decoder has been implemented in a manner that avoids the need to perform the Berlekamp algorithm and the Chien search, which are conventional in BCH decoding. The Galois field multiplier used in decoder 496 BHC is an improvement of the Galois field multiplier which is described in our co-pending US application No. 08 / 801,544. The particular BCH code that protects the tps sequence is specified in the telecommunications standard ETS 300 744 as BCH (67.53, t = 2), which has a code generator polynomial h (x) = x14 + x9 + xβ + x6 + x5 + x4 + x2 + x + 1 (44) or equivalently h (x) = (x7 + x3 + 1) (x7 + x3 + x2 + x + 1) (45) The left factor is used to generate the Galois field which is necessary for error detection. With reference to Figure 39, this is calculated in the syndrome calculation block 500 which is implemented using a conventional feedback shift register to generate the a values. The first three syndromes then calculated by dividing the received signal R (x) by c.1 values, ce2 I; 3 again using an implementation of shift register conventional feedback, as is well known in the art decoding BCH . It can be shown that the syndromes are S. = (a2) e ° + (a2) * 1 (47) S, = < a3) to + (a3) ß1 (48) During the syndrome calculation, the syndromes are stored in storage registers R [2: 0] 502. In the case where S0 is 0, then it can be concluded immediately that there are no errors in the current tps sequence, and that determines a signal on line 504 which is provided to error detection block 506, and the data of the received signal R (x) is transmitted unchanged or switched in accordance with the output of error detection block 506 in line 508. As explained in the following, if Sx O S0 = S2 (49) then exactly an error is present, a condition which is communicated to the error detection block 506 on the line 510. Otherwise, the assumption that two errors are present is established. No more than two errors can be detected in the present implementation. In order to solve the system of three non-linear equations shown above, the data stream from the registers R [2: 0] 502 in the search block 512 is activated by an EOF signal 514, which indicates the end of a framework. three shift registers feedback 516, 518, 520 having multipliers Galois field respective, 522, 524, 526 for '1 are initialized -. c "3 in the feedback loop, to 50H, 20H and 3DH (in where the notation "H" means hexadecimal numbers). the shift registers feedback 516, 518, 520 are immobilized each time is available a new data bit. syndromes and outputs the shift registers feedback 516 , 518, 520 are synchronized to a search module which performs a search for position error using a search technique interactive substitution, which will now be described. the outputs of the registers 516, 518 shift feedback multiply in a field 528 multiplier of Galois.

Consider the case in which an error is added S0, module 2, preferably using a gate network 530 XOR (XO), at the output of the first feedback shift register 516 (a.-gen0). If the relationship it is maintained, it is concluded that there is an error in the current data bits. The bit that is currently transmitted from frame storage is switched. The search is stopped and the data is transmitted from the frame storage. Consider the case of two errors, if the following relationship is maintained, there is an error in the current bit that is transmitted from the same storage: (S0 + a9ß "0) O (S, + agen?) = (S2 + apß" 2) (51) Now it is necessary to store the three terms calculated in the immediately preceding equation in the registers R [2: 0] 502 which is previously stored in the syndromes S0-S2. This is represented by line 532.

The process continues, now looking for a second error, and the data of the registers R [2: 0] 502 is re-supplied, which now contains the syndromes as they are adjusted by the previous interaction. Adjusted syndromes are indicated S0 '- S2'.

Yes now the second error was found and the bit that is currently transmitted from frame storage is switched by gate 534 XOR). If the search fails, more than two errors may be present and an error signal (not shown) is set. The Galois field multiplier 528 is a synchronized or clocked digital circuit and is described with reference to FIG. 40. The tps data is received very slowly, in relation to the other processes that are carried out in the digital receiver 126. multiple carrier It is therefore possible to execute the interactive substitution search slowly, and the Galois field multipliers are designed for minimum space utilization. They do not require alpha generators, but are based on small constant coefficient multipliers, with interactive feedback to produce the required alpha values. The arrangement takes advantage of the relation of Galois field arithmetic cf = a1 • o; "- 1 (54) After initialization by an init 536 signal which selects multiplexers 538, 540, multiply A 542 is accumulated in register 544 and multiplied repeatedly by the value c.1 in multiplier 546. The output in line 548 is subjected to AND repeatedly by bits with the multiplier B kept in a shift register 550. The output of the shift register is provided on a line 552 of bit one to gate 554. The output of gate 554 is accumulated in register 556 using the add-on 558. The signals of input and output of the signals in relation to the microprocessor interface 142 in the tps sequence of the extraction block 172 are described in tables 21, 22 and 23. The circuits in the tps sequence of the extraction block 172 and the BCH decoder 496 are described in listings 20 and 21 of the Verilog code.

Fine frequency automatic control and automatic sampling speed control A non-ideal oscillator present in the transmission chain of an orthogonal frequency division multiplexed signal ("OFDM") affects all carriers in the OFDM symbols. The OFDM carriers adopt the same phase-frequency alterations that result from the noisy local oscillator. Variations in the frequency of the local oscillator lead to phase shifts, and consequently to loss of orthogonality within the OFDM symbol. Therefore, an automatic frequency control is required in the receiver to follow the frequency shifts in relation to the transmitter in order to minimize these phase shifts and thus maintain orthogonality. All carriers within an OFDM symbol are affected equally by phase shifts. This is similar to the common phase error caused by phase noise. The common phase error present in all carriers is used to generate an automatic frequency control signal ("AFC"), which is completely in the digital domain, since the I / Q demodulation is done in the digital domain. The argument taken is the calculation of the common phase error for each OFDM symbol. This is obtained by using the reference pilot. The change in the common phase error is measured over time to detect the frequency shift and is used to derive the AFC control signal. The generic approach to the AFC control circuit and the automatic sampling rate control circuit described below is illustrated in Figure 41. An automatic sampling rate control is required when the master clock of the receiver does not align with that of the receiver. transmitter. A misalignment causes two problems: (l) the demodulation carriers have an incorrect separation; and (2) the range of the FFT calculation is also wrong. The effect of this timing error is to introduce a phase slope onto the demodulated OFDM data. This phase slope is proportional to the timing error. The phase slope can be determined by calculating the phase difference between the successive OFDM symbols, using the reference pilot and estimating the slope of these phase differences. At least one square approach is used for a line adjustment. The ASC signal is subjected to a low pass filter and fed back to the synchronization interpolator 158 (Fig. 13). The mean phase difference between the reference pilot and the subsequent OFDM symbols is used to calculate the frequency deviation. Assuming that the frequency deviations of the local oscillator are constant, then the phase rotates with a, where c = 2IIfdmTt. Here fd is the frequency deviation, m is the number of symbols between repetitions of identical pilot positions and Tt is the period comprising the sum of the active interval and the guard interval. The AFC signal is generated over time by a low pass filter of a. The value of the frequency offset is then used to control the demodulator 144 IQ (FIG. 13). The AFC and ASC control signals are effective only when the guard interval is being based indicated by the determination of the IQGI signal on line 154 (Figure 13). This prevents the symbol from being processed under two different conditions. In Figure 42 the correction circuits 174 are shown in more detail (Figure 14). The frequency error output on line 560 is calculated by determining the average of the phase value differences of the corresponding pilot signals in a current symbol and the previous symbol. The resulting frequency error value is filtered in a low pass filter 562 before being fed back to the IQ modulator 144 (Figure 13). It is also optional to evaluate the continuous pilot in order to solve larger frequency errors. The sampling speed error, the output on line 564, is determined by examining the phase difference between the pilot and a symbol in the same pilot and in a previous symbol. The differences vary through the symbol, which provides a number of points through which a line can be placed using the well-known method of least squares regression. The slope of this line is indicative of the magnitude and direction of the sampling rate error. The sampling rate error derived in this way is filtered in a low pass filter 566 before being fed back to the synchronous interpolator 158 (see FIG. 13). A separate storage 568 for the scattered pilots contained in four symbols is shared by the frequency error section 570 and the sampling rate error section 572. The direct comparison of the pilot symbols disseminated in this way is facilitated, since the disseminated pilot phase is repeated every four symbols. In an alternative mode where disseminated pilots are used to control information, storage must be provided for four symbols. In the preferred embodiment, where the control information is derived from continuous pilot signals, only storage for a symbol is needed. The recovery of the angle of rotation ce of the data I and Q is carried out in the phase extraction block 574, where a = tan "1 (Q / I) (55) In the currently preferred mode, the calculations are made at a resolution of 14 bits. The phase extraction block 574 is illustrated in greater detail in Fig. 43. The ce quadrant is determined first in block 576. Special cases in which I or Q have a magnitude of zero or I = Q are resolved with the determination of the signals on lines 578. If the magnitude of Q exceeds that of I, the quotient inversion is carried out in block 580, using a control signal 582. A positive integer division operation is performed on the division block 584. Although this operation requires 11 clock cycles, there is more than enough time allocated for phase extraction to carry it out. The calculation of the tangent arc of the quotient is carried out by a truncated interactive calculation channeled in block 586 of the Taylor series tan 1 (x) = x- x3 + x5 - x7 x9 - < 1 (56) 3 5 7 Block 586 is shown in greater detail in the scheme of Figure 44. The value x2 is calculated once in block 588 and stored for use in subsequent interactions. The powers of x are then computed interactively using the feedback line 590 and a multiplier 592. The divisions are calculated using a constant 594 multiplier in which the coefficients are connected. The sum is accumulated using an adder / subtractor 596. The entire calculation requires 47-48 clock cycles at 40 MHz. Returning again to Fig. 43, the quadrant transformation in the output of special cases is handled in block 598 under the control of block 576. It should be noted that the square error of the Taylor expansion result increases rapidly as it approaches 45 degrees, as shown in figure 45 and figure 46, which are graphs of the square error in different values of ce from Taylor expansion to 32 and 31 terms, respectively. The expansions of Taylor to 31 and 32 terms are averaged, with the result that the square error decreases markedly, as shown in Figure 47. In block 598 a memory (not shown) is provided to retain intermediate values for the calculation of averaged. The constant phase error across all scattered pilot signals is due to the frequency shift in the IQ demodulator. The frequency error can be defined as: f .__ = ce (57) 2IImTt where ce, m and Tt have the same meanings indicated above. It is determined by taking the average of the difference of the phase values of the corresponding pilot signals between the current symbol and a symbol delayed by m symbol periods. In the above equation, m = 1 in the case of continuous pilot signals. This calculation uses the accumulation block 600 which accumulates the sum of the current symbol minus the symbol that was preceded by 4. The accumulation block 602 has a multiplier x, where x varies from 1 to a minimum of 142 (in the mode 2K in accordance with the telecommunications standard ETS 300 744). You can implement the low pass filters 562, 566 as average moving filters that have 10-20 intermediate connections. The available data of the accumulation block 602 is the cumulative total of pilot signal phases each sampled with m separate symbols. The error frequency can be calculated from faith: __ = Acc { new old} (58) (N) (2) pmTt N = 142 in the case of dispersed pilot signals, and 45 for continuous pilot signals, assuming a 2K mode of operation in accordance with the telecommunications standard ETS 300 744. The technique for determining the Sampling rate error is illustrated in Figure 48, in which the phase differences of the pilot carriers, calculated from the differences of each fourth symbol (Sn - Sn_4) are plotted against the frequency of the carriers. The line of the best fit 604 is indicated. A slope of 0 may indicate that there is no sampling rate error. Upon receipt of the control signal 606 from block 408 for locating the pilot signal (figure 14), a frequency sweep is initiated by block 608, which inserts a deviation into the low pass filter frequency error output using the adder 610. Similarly, a frequency sweep is initiated by block 612, which inserts a shift in the low-pass filter sampling rate error output using an addendum 614. Frequency sweeps are linear in 1/8 increments of the Bearer Repair stages, from 0-3.5 kHz which corresponds to control signal values of 0x0-0x7. In Figure 49, a preferred embodiment of the correction circuit 174 is shown in greater detail (Figure 14). The continuous pilot signals instead of the scattered pilot signals are maintained in a memory storage 616 at a resolution of 14 bits. The generation of the multiplier x for the calculation in the accumulation block 618 is more complicated since, according to the telecommunication standard ETS 300 744 indicated, the continuous pilot signals are not evenly separated as are the scattered pilot signals. However, it is only necessary to evaluate 45 continuous pilot signals (in 2K mode according to the telecommunications standard ETS 300 744). In this mode, only the continuous pilot signals of a symbol need to be stored in storage 616. The inclusion of the guard interval size is necessary to calculate the total duration of the symbol Tt, which is received from the FFT interval circuit (block 166, FIG. 14) in line 620. The input and output signals and the signals in relation to the microprocessor interface 142 of the circuits illustrated in FIG. 42 are described in tables 24, 25, 26 and in the table. 27 respectively. The circuits are further described in listings 24-35 of the Verilog code.

Transformation eliminator The transformation elimination circuits 176 (Figure 15) are shown as a separate block for clarity purposes, but in practice it is integrated into the channel estimation and correction circuits. It converts I and Q data, each to a 12-bit resolution in a 12 bit coded constellation format where the transformation has been removed (3 bits I, 1 soft bit, 3 Q bits, Q soft bit). The coded constellation is illustrated in Figure 50 and Figure 51. For 64-QAM the 3 bits are used for the I and Q values, 2 bits for 16-QAM of 2 bits and 1 bit for QPSK. For example, in Figure 51 the values of I = 6.2, Q = -3.7 the transformation to: I-data = 001 would be eliminated; soft bit I = 011, Q-data = 101; soft bit Q = 101. The input and output signals of the transformation elimination circuits 176 are described in tables 28 and 29 respectively.

Symbol deinterleaver Symbol deinterleaver 182 (FIG. 15) inverts the symbol interleaving process of the transmitted signal. As shown in Figure 52, the deinterleaver requires 1512 x 13 memory stores, indicated as block 622. Address generator 624 generates addresses for writing to interleaved data and reading data in linear sequence. In practice, the address generator 624 is carried out as a read address generator and a separate write address generator. Reading and writing occur at different instantaneous speeds in order to reduce data flow loads. The address generator 624 is resynchronized for each new COFDM symbol by a pulse 626 of symbol timing. The zero index carrier is marked by pulse 628 of carrier 0. The addresses must be generated in relation to the address in which the carrier is stored. The input and output signals of the symbol deinterleaver 182 are described in tables 30 and 31, respectively. The circuits of the symbol deinterleaver 182 are described in the Verilog code listing 22.

Bit deinterleaver With reference to FIG. 54, the bit deinterleaver 184 (FIG. 15) inverts the bit-based interleaving process of the transmitted signal, and is shown in greater detail in FIG. 53. In the soft encoding circuits 630, they are reformatted. the input data of the coded constellation format to a 24 bit soft I / Q format. The smooth encoding circuits 630 are described for clarity with the bit deinterleaver 184, but are considered as part of the symbol deinterleaver discussed above. The deinterleaver address generator 632 generates addresses to read the appropriate 6 soft bits of the memory store 634 of 126 x 24, following the address algorithm in the telecommunications standard ETS 300 744. The deinterleaver address generator 632 is resynchronized for each new COFDM symbol by symbol timing pulse 626. The output interface 636 assembles the output data streams I and Q of the soft bit reading of the memory storage 634. Three soft bits I and three soft bits Q are extracted from the memory store 634 in each deinterleaving operation, and are converted into serial-parallel to provide an input data stream to the Viterbi decoder 186 (Fig. 15). The input and output signals of the bit deinterleaver 184 are described in tables 32 and 33 respectively. The circuits of the bit deinterleaver 184 are described in list 23 of the Verilog code.

Host microprocessor interface The function of the microprocessor interface 142 is to allow the guest microprocessor to have access to control and status information within the multi-carrier digital receiver 126 (see Figure 12). In Figure 55, the microprocessor interface 142 is shown in greater detail. An interface 638 in series and a 640 interface in parallel are provided, the latter is mainly of value for testing and debugging. The serial interface 638 is of known type and is compatible with I2C. The microprocessor interface 142 includes a maskable interruption capability that allows the receiver to be configured to request processor intervention in phase in the internal conditions. It should be noted that the multiple carrier digital receiver 126 does not depend on the intervention of the microprocessor interface 142 for any part of its normal operation. The use of interrupts from the point of view of the host processor is described below. "Event" is the term used to describe a condition on the chip that the user may wish to observe. An event may indicate an error condition or may be informative for the user's programming elements (software). There are two unique bit registers (not shown) that are associated with each interrupt or event. These are conditions sale records and the registration of conditions masks. The condition event record is a one-bit read / write register whose value is set to one by a condition that occurs within the circuit. The record is adjusted to one even if the condition exists only transiently. The condition event record is then guaranteed to remain set to one until the users' programming elements (software) reset it, or the entire chip is reset. The condition event record is cleared to zero when writing the value of 1. The write to zero of the condition event record leaves the record unchanged. The condition event record must be set to zero by the user's programming (software) elements before another presentation of the condition can be observed. The condition mask record is a one-bit read / write register which allows the generation of an interrupt request if the corresponding condition event record is set. If the condition event has already been established when 1 is described to the condition mask record, an interrupt request will be generated immediately. The value 1 activates the interruptions. The condition mask record is cleared to zero when the chip is readjusted. Unless stated otherwise, a block will stop the operation after generating an interrupt request and it will be restarted shortly after the event registration condition in the condition mask record is cleared. Event bits and mask bits are always grouped into bit positions in consecutive octets in the registration map. This allows interrupting the service of programming elements (software) to use the value read from the mask registers as a mask for the value in case the registers are identified event which is generated by the interruption. There is a single global bit event that summarizes the activity of the event on chi. The chip event record represents the OR of all the events of a chip that have 1 in their respective mask bit. A value of 1 in the mask bit of the chip allows the chip to generate interrupts. A value of 0 in the chip mask bit prevents any chip events from being generated from interrupt requests. Writing 1 or 0 to the chip event record has no effect. The chip event record only clears when all the events enabled by a 1 in their respective mask bits have been erased. The 642 IRQ signal is determined if both the chip event bit and the chip event mask are set. Signal 642 IRQ is an active "open collector", whose output requires an extraction chip inactivation resistor. When the active IRQ output is inactivated by an impedance of 100O or less, a stop resistor of approximately 4kO is suitable.

The input and output signals of the microprocessor interface 142 are described in tables 34 and 35 respectively.

System controller The system controller 198 (FIG. 15), which controls the operation of the multi-carrier digital receiver 126 (FIG. 12), in particular the channel acquisition and the handling of error conditions, is shown in greater detail in FIG. With reference to the state diagram in Figure 57, the channel acquisition sequence is established by four elapsed intervals. (1) AGC acquisition elapsed interval. 20 ms (80 symbols) are allowed for the AGC to acquire a signal level, shown in step 644. The FFT interval is activated at the start of acquisition search in block 646. (2) Elapsed interval of symbol acquisition: 200 symbol periods, the maximum guard interval plus the active symbol length, which is assigned to acquire the FFT interval in step 648. Other periods of 35 symbols are assigned to the pilot location in step 650. Approximately 50 are required ms to process 2K OFDM symbols. An option is provided in the output stage 650 as soon as the pilot signals have been located to save acquisition time in non-extreme situations. (3) Control circuit adjustment time elapsed: an additional 10 ms, representing approximately 40 symbols that are assigned to allow the control circuits to be adjusted in step 652. An option is provided to exit step 652 and return to the initial resynchronization stage 654 if the pilot signals have been lost or if the elapsed time of control circuit adjustment has elapsed. (4) Viterbi synchronization elapsed intervals: In block 656 approximately 150 symbol periods are allocated for the worst case of synchronization tps, indicated by step 658 and approximately 100 symbol periods for Viterbi decoder 186 (figure 15) to synchronize with the transmitted score rate, shown in step 660. This is approximately 65 ms. Under reasonable conditions, this is unnecessary to wait for such a long time. As soon as the Viterbi synchronization is established, then the transition is to the 662 state of system_lock. It is possible to derive the tps synchronization requirement by establishment parameter (see table below) in the receiver parameter register and set set_rx_parameters to 1.

If the acquisition fails at any stage, the process automatically returns to the resync 654 stage for retry. Having acquired immobilization, the system will remain in immobilization unless there is a Reed-Solomon overload event, that is, the number of Reed-Solomon packets with incorrigible errors that exceeds a predetermined value (the value rso_limit), in any period of 1 second. If any of the 4 synchronizing state machines in the acquisition sequence, the FFT interval (step 648), the location of the pilot signal (step 650), tps synchronization (step 658), synchronization is lost once the channel acquisition has occurred, no action will be taken until a rso_event phenomenon occurs, and the resynchronization step 654 is automatically activated. In poor signal conditions the acquisition can be difficult, particularly the Viterbi synchronization. Therefore, a bit is optionally provided at the interface 142 of the microprocessor (see FIG. 12), which then extends the adjustment of the elapsed intervals by a factor of 4. The input and output signals and the interface registers of the system controller 198 are described in tables 36, 37, 38 and 39 respectively.

Boards Ta the 4 Ta a 5 Table 6 Ta the 8 IQGI Pulse valid to activate the frequency error signal. The effect of the frequency control circuit is kept inactive until a guard interval passes through the IQ demodulator block (IQGI is generated by the FFT interval and indicates the time at which a guard interval passes). te, tdin Scan Test Entries Table 9 Tab to 10 te, tdin Scan test entry Table 11 Ta the 12 Ta a 14 upsel Address decoding output to select the FFT interval block Table 15 Ta to 16 Table 17 Ta a 19 Ta the 20 Table 21 Signal Description tps_data [29: 0] Data outputs tps (which remain static for the OFDM 1 frame): tps_dat [1: 0] = frame number tps_data [3: 2] = constellation tps_data [6: 4] = hierarchy tps_data [9: 7] = code rate, HP stream tps_data [12: 10] = code rate, LP stream tps_data [14: 13] = guard interval tps_data [16: 15] = transmission mode tps_data [29: 17] = future use bits Note that the parameters are transmitted for the next frame; the outputs must be stored in memory twice so that the parameters appear in the outputs of the blocks in the correct frame (used by the transformation elimination and symbol / bit deintercalation blocks to decode the incoming data) tps_sync Status output of the synchronization frame FSM - set to 1 when FSM is synchronized, that is, when two valid synchronization words have been received in the expected positions of the correct AND data TPS which are available in block outputs Table 22 Table 26 Ta the 27 Signal Description clk40M 40MHz clock (2x sample clock) valid in Valid input data signal; when the valid signal is low, the input data i_data [ll: 0], estimation input data and channel correction must be ignored q_data [ll: 0] bad carrier in Carrier status flag - adjust if the carrier is find below an acceptable level; indicates to Viterbi that the data of this carrier must be discarded from the error correction calculations c_symbol Timing synchronization signal - activated for the first data sample the corrected COFDM symbol const the lat ion Control signal which defines the constellation. - 00 [1: 0] QPSK, 01 = 16-QAM, 10 = 64-QAM alpha [2: 0] Control signal that defines the hierarchical transmission parameter, alpha: 000 = non-hierarchical transmission, 001 = alpha value of 1,010 = alpha value of 2.011 = alpha value of 4 (Note that the first release of the chip will not support the hierarchical transmission Table 28 Ta the 29 Ta a Ta 32 Ta a 33 Tab a 34 Signal Description Ta to 37 0x09 7: 0 R / 0 rso count Transport packet account not correctable per second (saturates to 255). Write to record a bolt to a stable account value which can then be read again. OxOa-OxOb 15: 0 R / 0 ber BER (before RS) is deducted from the RS corrections in a period of 1 second - maximum correctable bit errors ~ 1.35M / sec for 7/8, 64-QAM, 1 / 32 Gl (equivalent to 43.e-3 BER assuming a useful bit rate of 31.67e-6) Only the top 16 bits of the 21-bit counter are visible - resolution of ~ le-6 depends on code rate, length Gl of constellation Write to record bolt a stable account value which can then be read back Table 38 Ta the 39 Listing 1 - // Sccsld:% W%% G% / ************************************ ********************** Copyright (c) 1997 Pioneer Digital Design Center Limited Author: Dawood Alam. Description: Verilog code for butterfly processor BF21. (RTL) Notes: Computes first stage in radix 4 calculation. ******************** 'timescale lns / lOOps module fft_bf21 (clk, enable_l, in_xlr, in_xli, in_x2r, in_x2i, in_s, óut_zlr, out_zli , out z2r, out_z2i, out_ovf); parameter wordlength = 5; // Data ordlength. input clk, // Master clock. enable_l, // Enable on clock 3. in_s; // Control line. input [ordlength-1: 0] in_xl r, // Input I from memory. in_xli, // Input Q from memory. in_x2r, // Input I stage n-l. in_x2i; // Input Q stage n-l. output out_ovf; // Overflow flag. output [wordlength-l: 0] out_zl r, // Output I to stage n + l out_zli, // Output Q to stage n + l out_z2r, // Output I to memory. out_z2i; // Output Q to memory. wire [wordlength-l: 0] in_xl r, in_xli, in_x2r, in_x2i, out_zlr, out_zli, out_z2r, out_z2i wire in_s, enable_l, • OUt_Ovf; reg [wordlength-1: 0] zlr_tmpl, zli_tmpl, z2r_tm.pl, z2i_tmpl, zlr_tmp2, zli_tmp2, z2r_tmp2, z2i_tmp2; reg ovf_tmp, ovf_tmpO, ovf_tmpl, ovf_tmp2, ovf_tmp3, ex_regO, ex_reg 1, ex_reg2, ex_reg3; always @ (in_s or in_xl r or in_xl i or in_x2r or in_x2i) 'begin. { ex_reg0, zlr_tmpl } = in_xl r + in_x2r; ovf_tmpO = in_xlr [wordlength-1] & __ // Overflow check. in_x2r [wordlength-1] & & ~ zlr_tmpl [wordlength-l] ~ in_xlr twordlength-l] _. & ~ in_x2r [wordlength-1] & & zlr_tmp 1 [wordlength-1]; if (ovf_trnpO) // Satúrate logic. zlr_tmpl = (ex_regO)? . { l'bl,. { wordlength-l. { l 'b ?} } } : { l'bO,. { wordlength-l. { l'bl} } }; . { ex_regl, zli_tmpl } = in_xli + in_x2i; ovf_tm.pl = in_xli [wordlength-1] & amp; // Overflow check. in_x2i [wordlength-l] & & ~ zli_tm.pl [wordlength-1] II ~ in_xli [wordlength-1] & Xin_x2i [wordlength-1] & _. zli_tm.pl [wordlength-1]; if (ovf_tmpl) // Satúrate logic. zli_tmpl = (ex_regl)? . { l'bl,. { wordlength-l. { l'b ?} } } : { l'bO,. { wordlength-l. { l'bl} } }; . { ex_reg2"z2r_tmpl.} = in_xlr - in_x2r; ovf_tmp2 = in_xlr [wordlength-1] && // Overflow check. ~ in_x2r [wordlength-1] && ~ z2r_tmpl [wordlength-1] ~ in_xlr [wordlength -1] &. _. In_x2r [wordlength-1] _. & z2r_tm.pl [wordlength-1]; if (ovf_tmp2) // Sature logic. Z2r_tmpl = (ex_reg2)?. {L'bl,. { wordlength-l {lb.}..}..}.: { l'bO, { wordlength-l { l. bl.}..}..}.; { ex_reg3, z2i_tmpl.}. = in_xli - in_x2i; ovf_tmp3 = in_xli [wordlength-1] _._ // Overflow check. ~ in_x2i [wordlength-1] _. & ~ z2i_tm.pl [wordlength-1] ~ in_xli [wordlength-1] S. & in_x2i [wordlength-1] & & z2i_tmpl [wordlength-1] if (ovf_tmp3) // Sature logic. z2i_tmpl = (ex_reg3)? . { l'bl,. { wordlength-l. { l'b ?} } } : { l'bO,. { wordlength-l. { l 'bl} } }; // Output stage with two channel mux. if (! in_s) begin: mux_passthru z1r_tmp2 = in_xlr; zli_tmp2 = in_xli; z2r_tmp2 = in_x2r; z2i_tmp2 = in_x2i; end else begin: mux_computing z1r_tmp2 = z1r_tmp1 zli_tmp2 = zl i_tmpl z2r_tmp2 = z2r_tmp1; z2i_tmp2 = z2i_tmp1; end end assign out_zlr = zlr_tmp2 assign out_zli = zli_tmp2; assign out_z2r = z2r_tmp2; assign out_z2i = z2i_tmp2; always @ (posedge clk) if (enable_l) // Butterfly completes at the end of clock cycle 0. ovf_tmp < = in_s & & (ovf_tmpO // ovf_tmpl // ovf_tmp2 //? vf_tmp3); assign out_ovf = ovf_tmp; if_def 0VERFL0 _DEBUG L0 _LEVEL // Debug code to display overflow output of a particular adder.

II Concurrently monitor overflow flag and halt on overflow. always @ (ovf_tmp or ovf_tmpO or ovf_tm.pl or ovf_tmp2 or ovf_tm 3) i'f (ovf_tmp) begin if (ovf_tmpO) $ display ("ovf_tmpO on BF21 =", ovf_tmpO) if (ovf_tm.pl) $ display ("ovf_tmpl on BF21 = ", ovf_tmpl) if (ovf_tmp2) $ display (" ovf_tmp2 on BF21 = ", ovf_tmp2) if (ovf_tmp3) $ display (" ovf_tmp3 on BF21 = ", ovf_tmp3) $ stop; end endif endmodule Listing 2 // Sccsld: _W%% G% ******************************* **** Copyright (c) 1997 Pioneer Digital Design Center Limited Author: Dawood Ala. Description: Verilog code for butterfiy processor BF2 //. (RTL) Notes: Computes second stage in radix 4 calculation. ************************************** / timescale Ins / lOOps module fft_bf2 | | (clk, enable_l, in_xlr, in_xli, in_x2r, in_x2i, in_s, in_t, out_zlr, out_zli, out_z2r, out_z2i, out_ovf); parameter wordlength = 5; // Data wordlength. input clk, // Master clock. enable_l, // Enable on clock 3. in_s, // Control line. in_t; // Control line. input [wordlength-l: 0] in_xlr, // Input I from memory. in_xli, // Input Q from memory. in_x2r, // Input I stage n-l. in_x2i; // Input Q stage n-l. output out_ovf; // Overflow flag. output [wordlength-l.-O] out_zl r, // Output I to stage n + l out_zli, // Output Q to stage n + l out_z2r, // Output I to memory. out_z2i; // Output Q to memory. wire [wordlength-1: 0] in_xlr, in_xli, in_x2r, in_x2i, out_zlr, out_zli, out_z2r, out_z2i; wire in_s, in_t, enable_l, out_ovf, control; reg [wordlength-1: 0] zl r_tm.pl, zli_tmpl, z2r_tmpl, z2i_tmpl, zlr_tmp2, zl i_tmp2, z2r_tmp2, z2i_tm 2, x2ri_tmpl, x2ri_tmp2; reg ovf_tm, ovf_tmpO, ovf_tmp1, ovf_tmp2, ovf_tmp3, ex_regO, ex_reg 1, ex_reg2, ex_reg3; assign control = in_s & _. ! in_t; always @ (in_s or control or in_xlr or in_xli or in_x2r or in_x2i) begin // Crosspoint switch, used in computing complex j valúes. if (control) begin: switch_crossed x2ri_tmpl = in_x2i; // i - > r. x2ri_tmp2 = in_x2r; // r- > i. end else begin: switch_th.ru x2ri_tmpl = rn_x2r; // r - > r. x2ri_tmp2 = in_x2i; // i - > i. end { ex_regO, zlr_tm.pl} = in_xlr + x2ri_tm.pl; ovf_tmpO = in_xlr [wordlength-1] && amp; // Overflow check. x2ri_tmpl [wordlength-1] & _. ~ zlr_tmpl [wordlength-1] ~ in_xlr [wordlength-1] & _. ~ x2ri_tmpl [wordlength-l] _._. zlr_tmpl [wordlength-1]; if (ovf_tmpO) // Sature logic. zlr_tmpl = (ex_regO)? . { l'bl,. { wordlength-1 { l'bO} } } : { l'bO,. { wordlength-l. { l'bl} } }; . { ex_regl, zli_tmpl } = (control)? in_xli - x2ri_tmp2: in_xli + x2ri_tmp2; ovf_tmpl = in_xli [wordlength-1] £. & // Overflow check. (control A x2ri_tmp2 [wordlength-1]) & amp; // Deals with a ~ zli_tmpl [wordlength-1] // +/- input. -in_xli [wordlength-1] && amp; - (control? x2ri_tmp2 [wordlength-1]) & & amp; zli_tmpl [wordlength-1]; if (ovf_tm.pl) // Sature logic. zli_tmpl = (ex_regl)? . { l'bl,. { wordlength-l. { l'b ?} } } : { l'bO,. { wordlength-l. { l'bl} } }; . { ex_reg2, z2r_tmpl } = in_xlr - x2ri_tmpl; ovf_tmp2 = in_xl r [wordlength-1] && amp; // Overflow check. ~ x2ri_tmpl twordlength-1] _. & // Deals with a -z2r_tmpl [wordlength-1 3 I I // - input. ~ in_xlr [wordlength-1] & & x2ri_tmpl [wordlength-1] && amp; z2r_tmpl [wordlength-1]; if (ovf_tmp2) // Sature logic. z2r_tmpl = (ex_reg2)? . { l'bl,. { wordlength-l. { l'b ?} } } : { l'bO,. { wordlength-l. { l'bl} } }; . { ex_reg3, z2i_tmpl } = (control)? in_xli + x2ri_tmp2: in_xli x2ri_tmp2; ovf_tmp3 = in_xli [wordlength-1] && amp; // Overflow check. - (control A x2ri_tmp2 [wordlength-1]) & & amp; // Deals with a ~ z2i_tmpl [wordlength-1] II // -1+ input. ~ in_xli [wordlength-1] & & (control A x2ri_tmp2 [wordlength-1]) & amp; z2i_tmpl [wordlength-1] if (ovf_tmp3) // Sature logic. z2i_tmpl = (ex_reg3)? . { l'bl,. { wordlength-l. { l'b ?} } } : { l'bO,. { wordlength-l. { l'bl} } }; // Output stage with two channel mux. if (! in_s) begin: mux_passthru zlr_tmp2 = in_xlr; zli_tmp2 = in_xli; z2r_tmp2 = x2ri_tm.pl; z2i_tmp2 = x2ri_tmp2; end else begin: mux_computing zlr_tmp2 = zlr_tm.pl; zli_tmp2 = zli_tmpl; z2r_tmp2 = z2r_tm.pl; z2i_tmp2 = z2i_tm.pl; end end assign out_zlr = zlr_tmp2 assign out_zli = zli_tmp2 assign out_z2r = z2r_tmp2 assign out_z2i = z2i_tmp2 always @ (posedge clk) if (enable_l) // Butterfly completes at the end of clock cycle O. ovf_tmp < = in_s & & (ovf_tmpO | | ovf_tm.pl | | ovf_tmp2 | | ovf_tmp3); assign out_ovf = ovf_tmp; ifdef OVERFLO _DEBUG_LOW_LEVEL // Debug code to display overflow output of a particular adder.

// Concurrently monitor overflow flag and halt on overflow. always @ (ovf_tmp or ovf_tmpO or ovf_tmpl or ovf_tmp2 or ovf_tmp3) if (or f_tmp) begin if (ovf_tmpO) $ display ("ovf_tmpO on BF2II =", ovf_tmpO); if (ovf_tmpl) $ display ("ovf_tm.pl on BF2II =", ovf_tmpl) if (ovf_tmp2) $ displa ("ovf_tmp2 on BF2II =", ovf_tmp2), if (ovf_tmp3) $ display ("ovf_tmp3 on BF2II =", ovf_tmp3 ); $ stop; end endif endmodule Listing 3 // Sccsld:% W% _G% ******************************* ****** Copyright (c) 1997 Pioneer Digital Design Center Limited Author: Dawood Alam. Description: Verilog code for a variable size ROM with complex data store.

(RTL) Notes: Used to store complex Twiddle factors. *************************************** * timescale 1 ns / 1 OOps module fft_rom (clk, enable_3, address, rom_data); parameter c_wordlength = 1; // Coeffwordlength. parameter rom_AddressSize = 1; // Address size. p a r a m e t e r F I L E "../../../fft/src/lookup_tables/lu_10bit_2048pt_scaleX", // Lookup tab filename. (Listings 16, 17) input clk, enable_3; input [rom_AddressSize-l: 0] address; output [c_wordlength-l: 0] rom_data; reg [c_wordlength * 2-l: 0] rom [0: (1 < < rom_AddressSize) -1]; reg [c_wordlength * 2-l: 0] b_tmpl, rom_data, -always © (address) b_tmpl = rom [address]; always @ (posedge clk) if (enable_3) rom_data < = b_tmpl; initial $ readmemb (F // E, rom); endmodule Listing 4 // Sccsld:% W%% G% ******************************** ************ Copyright (c) 1997 Pioneer Digital Design Center Limited Author: Dawood Alam. Description: Verilog code for variable length single bit shift register. Notes: Used to delay pipeline control sign by "length" clocks. ***************************************** * . timescale 1 ns / lOOps module fft_sr_lbit (clk, enable_3, in data, out_data), -parameter length = 1; // Shift reg length. input clk, // Master clock; enable_3; // Enable on clock 3. input in_data; // Input data. output out_data; // Output data. reg shift_reg [length-l: 0; // Shift register. wire out_data; wire clk, enable_3; integer i; always (posedge clk) if (enable_3) begin for (i = (length-1); i> = 0; i = i - 1) if (i == 0) shift_reg [0] < = in__data; // Forcé input to SR. else shift_reg [i] c = shift_reg [i-l]; // Shift data eleven, end assign out_data = shift_reg [length-1]; endmodule Listing 5 // Sccsld:% W%% G% ****************************** Copyright ( c) 1997 Pioneer Digital Design Center Limited Author: Dawood Alam. Description: Verilog code for a dual-port FIFO. (RTL) Notes: Used as a pipeline register to delay address into the address decoder. .timescale 1 ns / 1 OOps module fft_sr_addr (clk, enable_3, in_data, out_data); parameter wordlength = 1; // Datawordlength 1 / Q. parameter length = 1; // Shift reg length. input clk, // Master clock; enable_3; // Enable on clock 3. input [wordlength-l: 0] in_data; // SR input data. output [wordlength-l: 0] out_data; // SR output data. reg [wordlength-l: 0] shift_reg [length-1: 0]; // Shift register. wire [wordlength-1: 0] out_data; wire clk, enable_3; integer i; always @ (posedge clk) if (enable_3) begin for (i = (length-1); i> = 0; i = i -1) if (i == 0) shift_reg [0] = < in_data; // Forcé input to SR. else shift_reg [i] = shift_reg [i-l]; // Shift dates eleven. end assign out_data = shift_reg [length-1]; endmodule Listing 6 // Sccsld:% W%% G% / Copyright (c) 1997 Pioneer Digital Design Center Ltd. Author: Dawood Alam. Description: Verilog code for an signed twiddle multiplier factor. (RTL) Notes: Single multiplexed multiplier and 2 adders employed to perform 3 multiplies and 5 additions. Pipeline depth = 2. ar / ai = Complex data, br / bi = Complex coefficient. bi +/- br could be pre-calculated in the ROM lookup, however in this implementation it is NOT an overhead as this path is shared by ar + ai. * / 'Timescale 1 ns / 1 OOps fft_complex_mult_mux module (clk, c2, in_ar, in_ai, in_br, in_bi, out_cr, out_ci, out_ovf); parameter wordlength = 12; // Data wordlength. parameter c_wordlength = 10; // Coeff wordlength. parameter mult_scale = 4; // multiplier scalling, // l = / 4096, 2 = / 2048, // 3 = / 024, 4 = 1512. input [wordlength-1: 0] in_ar, // Data input I. in_ai; // Data input Q. input [c_wordlength-l: 0] in_br, // Coefficient input 1. in_bi; // Coefficient input Q. input clk; // Master clock. input [1: 0] c2; // Two bit count line. output out_ovf; // Overflow flag. output [wordlength-1: 0] out_cr, // Data output 1. out_ci; // Data output Q. wire [wordlength-1: 0] in_ar, In_ai, br_tmp, bi_tmp, out_cr, o'ut ci; wire [c_wordlength-l: 0] in_br, in_bi; wire enable_0, enable_l enable_2, enable_3; wire [1: 0] c2; reg [wordlength-1: 0] in_ai_tmp, in_ar_tmp, abr_tm, abi_tmp, abri_ttnpl, opened TMP2, abri_tmp4 coef f_tmpi, mpy_tm l, sum_tmpO, sum_tmp 1 sum_tmp2, acc_tmp, store_tmp, cr_tmp, ci_tmp; reg [wordlength * 2-l: 0] abri_tmp3, mpy tmp2, coeff_tmp2; reg ovf_tmpO, ovf_tm.pl, ovf_tmp2 ovf_tmp3, ex_regO, ex_reg 1, cl, c3, C4; // Enable sign for registers. assign enable_0 = ~ c2 [1] __ & ~ c2 [0]; assign enable_l = ~ c2 [1] & & c2 [0]; assign enable_2 = c2 [1] & ~ c2 [0]; assign enable_3 = c2 [1] & & c2 [0]; // Sign extend coefficients from c_wordlength bits to wordlength. assign br_tmp =. { . { (wordlength-c_wordlength). { in_br [c_wordlength-l]} } , in_br}; a s s i g n b i _ t m p =. { . { (wordlength-c_wordlength). { in_bi [c_wordlength-l]} } , in_bi}; // Combinational logic before pipeline register. always @ (in_ar or br_tmp or in_ai or bi_tmp or c2) begin cl = c2 [0] II C2 [l]; C3 = C2 [1]; if (! cl) begin abr_tmp = in_ar; abi_tmp = in_ai; end else begin abr_tmp = br_tmp; abi_tmp = bi_tmp; end if (c3). { ex_regO, abri_tmp4} = abi_tmp - abr_tmp; else { ex_regO, abri_tmp4} = abi_tmp + abr_tmp; ovf_tmpO = abi_tmp [wordlength-l] && amp; // Overflow check. (c3 To abr_tmp [wordlength-1]) & & // Deals with a ~ abri_tmp4 [wordlength-1] // +/- input. ~ abri_tmp [wordlength-1] && amp; ~ (c3? abr_tmp [wordlength-1]) & & amp; abri_tmp4 [wordlength-l]; if (ovf_tmpO) // Sature logic. abri_tmpl = (ex_regO)? . { l'bl,. { wordlength-l. { l'b ?} } } : { l'bO,. { wordlength-l. { l'b 1} } }; else abri_tm.pl = abri_tmp4; end // Combinational logic after pipeline register. always @ (in_ar_tmp or in_ai_tmp or br_tmp or c2 or store_tmp or abri_tmp2) begin c4 = c2 [1] && amp; ~ c2 [0]; case (c2) 2'bOO: begin coeff_tm.pl = in_ar_tmp; sum_tmpO = store_tmp; end 2'b? l: begin coeff_tmpl = br_tmp-sum_tmpO =. { wordlength-1 { 1 B?} }; end 2'bl 0: begin coeff_tm.pl = in_ai_tmp; sum_tmp0 = store_tmp; end 2'bll: begin coeff_tm.pl = in_ar_tmp; sum_tmpO = store_tmp; end endcase abri_tmp3 =. { . { wordlength. { abri_tmp2 [wordlength-1] } } , abri_tmp2}; // extnd coeff_tmp2 =. { . { wordlength. { coeff _tmpl [wordlength-1]} } , coef f_tmpl}; // extnd mpy_tmp2 = (abri_tmp3 coeff_tmp2), -m p and _ t m p l mpy_tmp2 [wordlength * 2-mult_scale: wordlength- (mult_scale-l)]; if (c4). { ex_regl, sum tmp2} = sum_tmpO- mpy_tmpl- mpy tmp2 [wordlength-mult_scale]; else { ex_regl, sum_tmp2} = mpy_tm.pl + sum_tmpO + mpy_tmp2 [wordlength-muít_scale]; ovf_tmpl = (c4 To mpy_tmpl [wordlength-1]) & & amp; // Overflow check. sum_tmpO [wordlength-1] _. & // Deals with a ~ sum_tmp2 [wordlength-1] II // +/- input. ~ (C4 To mpy_tmpl [wordlength-1]) & & amp; ~ sum_tmpO [wordlength-l] && amp; sum_tmp2 [wordlength-1]; if (ovf_tm.pl) // Sature logic. sum_tmpl = (ex_regl)? . { l 'bl,. { wordlength-l. { l'b ?} } } : { l'bO,. { wordlength-l. { l'bl} } }; else sum_tmpl = sum_tmp2; end // Pipeline registers for 1 / Q data paths and intermediary registers. always @ (posedge clk) begin if (enable_2) // Enable on 2nd clock. acc_tmp < = sum_tmpl; // Temp store. if (enable_3) // Enable on 3rd clock. cr_tmp < = acc_tmp; // Pipeline reg cr if (enable_3) // Enable on 3rd clock. ci_tmp < = sum_tmpl; // Pipeline reg ci if (enable_l) store_tmp < = sum_tmpl; // Temp store. if (enable_2) in_ar_tmp < = in_ar; // Reg i / p to mpy. if (enable_l) in_ai_tmp < = in_ai; // Reg i / p to mpy. if (enable_0 // enable _ // enable_2) abri_tmp2 < = abri_tm.pl; // Pipeline reg. end // Register ovf outputs before end OR, else whole complex multiplier is // treated as combinational, and the intermediary pipeline reg is ignored. always @ (posedge clk) // if (enable_0 // enable_l // enable_2) or f_tmp2 < = ovf_tmpO; always © (posedge clk) ovf_tmp3 < = ovf_tm.pl; assign out_ovf = ovf_tmp2 // ovf_tmp3; .ifdef OVERFLOW_DEBUG_LO _LEVEL // Debug code to display overfiow output of a particular adder.

// Concurrently monitor overflow flag and halt on overflow. always @ (posedge clk) if (out_ovf) begin if (ovf_tmp2) $ display ("ovf_tmpO on complex multiplier = ", ovf_tmp2); if (ovf_tmp3) $ display (" ovf_tmpl on complex multiplier = ", ovf_tmp3); $ stop; end 'else' endif assign out_cr = cr_tmp; assign out_ci = ci_tmp; endmodule Listing 7 / - / Sccsld:% W%% G% ******************************* **** Copyright (c) 1997 Pioneer Digital Design Center Limited Author: Dawood Alam. Description: Verilog code for a dual-port FIFO with complex data store. (RTL) Notes: A variable bitwidth FIFO shift register for intermediary 1 / Q calculations. ************************ 'i scale lns / lOOps module fft_sr_iq (clk, enable_3, in_xr, in_xi, out_xr, out xi); parameter wordlength = 1; // Data wordlength 1 / Q. parameter length = 1; // Shift reg length. input clk, // Master clock; enable_3; // Enable on clock 3. input [wordlength-1: 0] in_xr, // SR inputdata, I. in_xi; // SR input data, Q. output [wordlength-l: 0] out_xr, // SR output data 1. out_xi; // SR output data Q. reg [wordlength-1: 0] shift_r [length-1: 0]; // SR for I data. reg [wordlength-l: 0] shift_i [length-1: 0]; // SR for Q data / wire [wordlength-l: 0] out_xr, out_xi; wire clk, enable_3; integer i; always® (posedge clk) if (enable_3) begin for (i = (length-1), - i> = 0; i = i - 1) begin if (i == O) begin shift_r [0] < = in_xr; // Force input I to SR. shift_i [0] < = in_xi; // I forced input Q to SR. end else begin shift_r [i] < = shift_r [i-1]; // Shift data I once. shift_i [i] < = shif t_i [i-1]; // Shift data Q eleven. end end end assign out_xr = shift_r. { length-1]; assign out_xi = shift_i [length-1]; endmodule Listing 8 // Sccsld:% W%% G% ******************************** *********** Copyright (c) 1997 Pioneer Digital Design Center Limited Author: Dawood Alam. Description: Verilog code for 8 hardwired coefficients in a lookup table, of which 4 are unique valúes. Notes: Used to store complex Twiddle factors. 8 point FFT twiddle factor coefficients (Radix 4 + 2). Coefficients stored as non-fractional 10 bit integers. Real Coefficient (cosine valué) is coefficient high-byte. Imaginary Coefficient (sine valué) is coefficient low-byte. Coefficient addresses are delayed by a pipeline depth of 5, i.e. equivalent to case table valúes being advanced by . ********************************************** * timescale lns / lOOps module fft_hardwired_luO (clk, enable_3, address, out_br, out_bi); parameter c_wordlength = 10; // Coeff wordlength. parameter rom_AddressSize = 3; // Address bus size. input clk, enable 3; input [rom_AddressSize-l: 0] address; output [c_wordlength-l: 0] out_br, out_bi; reg [c_wordlength * 2-l: 0] b_tm.pl, b_tmp2; always @ (address) case (address) 3'd6: b_tmpl = 20'b0000000000_1000000000; // W2_8 = +0.000000 -1.000000 3'dO: b_tmpl = 20'b0101101010_1010010110; // Wl_8 = +0.707107 -0.707107 3'd2: b_tmpl = 20'bl010010110_1010010110; // W3_8 = -0.707107 -0.707107 default: b_tmpl = 20'b011111111_0000000000; // 0_8 = +1.000000 -0.000000 endcase always © (posedge clk) if (enable_3) b_tmp2 < = b_tm.pl; assign out_br = b_tmp2 [c_wordlength2-l: c_wordlength]; assign out_bi = b_tmp2 [c_wordlength-l: 0]; endmodule Listing 9 // Sccsld:% W%% G% ******************************** ******** Copyright (c) 1997 Pioneer Digital Design Center Limited Author: Dawood Alam.

Description: Verilog code for 32 hardwired coefficients in a lookup table, of which 16 are unique valúes. Notes: Used to store complex Twiddle factors. 32 point FFT twiddle factor coefficients (Radix 4 + 2). Coefficients stored as non-fractional 10 bit integers. Real Coefficient (cosine valué) is coefficient high-byte. Imaginary Coefficient (sine valué) is coefficient low-byte. Coefficient addresses are delayed by a pipeline depth of 4, i.e. equivalent to case table valúes being advanced by 4. *********************************** ********************* / timescale lns / lOOps module fft_hardwired_lul (clk, enable_3, address, out_br, out_bi); parameter c_wordlength = 10; // Coeff wordlength. parameter rom_AddressSize = 5; // Address bus size. input clk, enable_3; input [rom_AddressSize-l: 0] address; output [c_wordlength-l: 0] out_br, out_bi; reg [c_wordlength * 2-l: 0] b_tm.pl, b_tmp2; always © (address) case (address) 5'd5, 5'dl4: b_tmpl = 20'bO111011001_1100111100; // W02_32 = +0.923880 -0.382683 5'd6, 5'dl6: b_tmpl = 20'bO101101010_1010010110; // W04_32 = +0.707107 -0.707107 5'd7, 5'dl8, 5'd22: b_tmpl = 20 'b0011000100_1000100111; // 06_32 = +0.382683 -0.923880 5'd8: b_tmpl = 20'bO000000000_1000000000; // 08_32 == +0.000000 -1.000000 5'd9: b_tmpl = 20 'bll00111100_1000100111; // W10_32 = -0.382683 -0.923880 5 'dlO, 5'd24: b_tmpl = 20'bl010010110_1010010110; // W12_32 = -0.707107 -0.707107 5'd //: b_tmpl = 20'bl000100111_1100111100; // 14_32 = -0.923880 -0.382683 5'dl3: b_tmpl = 20'bO111110110_1110011100; // 01_32 = +0.980785 -0.195090 5'dl5, 5'd21: b_tmpl = 20'bO110101010_1011100100; // W03_32 = +0.831470 -0.555570 5'dl7: b_tmpl = 20'bO100011100_1001010110; // W05_32 = +0.555570 -0.831470 5'dl9: b_tmpl = 20'bO001100100_1000001010, // 07_32 = + 0.195090-0.980785 5'd23: b_tmpl = 20 'blll0011100_1000001010; // 09_32 = -0.195090-0.980785 5'd25: b_tmp 1 = 20'b 1000001010 _ // 100 // 100; // 15_32 = -0.980785 -O.195090 5'd26: b_tmpl = 20'b 1000100 // 1 _00 // 000100; // W18_32 -0.923880 +0.382683 5'd27: b_tmp 1 = 20'b 1011100100_0 // 0101010; // 21 _32 = -0.555570 +0.831470 default: b_tmpl =; // W00_32 = +1.000000 -0.000000 endcase always © (posedge clk) if (enable_3) b_tmp2 < = b_tm.pl; assign out_br = b_tmp2 [c_wordlength * 2-l: c_wordlength]; assign out_bi = b_tmp2 [c_wordlength-l: 0]; endmodule Listing 10 // Sccsld:%%% G% / S * lr ***************************** ****** Copyright (c) 1997 Pioneer Digital Design Center Limited Author: Dawood Alam. Description: Verilog code for 128 hardwired coefficients in a lookup table, of which 64 are unique valúes. Notes: Used to store complex Twiddle factors. 128 point FFT twiddle factor coefficients (Radix 4 + 2). Coefficients stored as non-fractional 10 bit integers. Real Coefficient (cosine valué) is coefficient high-byte. Imaginary Coefficient (sine valué) is coefficient low-byte. Coefficient addresses are deed by a pipeline depth of 3, i.e. equivalent to case table valúes being advanced by 3. ********************************. timescale lns / lOOps module fft_hardwired_lu2 (clk, enable_3, address, out_br, out_bi); parameter c_wordlength = 10; // Coeff wordlength. parameter rom_AddressSize = 7; // Address bus size. input clk, enable_3; input [rom_AddressSize-l: 0] address; output [c_wordlength-l: 0] out_br, out_bi; reg [c_wordlength * 2-l: 0] b_tmpl, b_tmp2; always © (address) case (address) 7'd36: b_tmpl = 20'b0111111111_1111100111; // W01_128 = + 0.998795 -0.049068 7 'd4, 7'd37: b_tmpl = 20'bO111111110_1111001110; // W02_128 = + 0 95185 -0.098017 7'd38, 7 'd68: b_tmpl = 20'; // W03_128 = + 0 989177 -O. 146730 7 'd5, 7'd39: b_tmpl = 20'bO111110110_1110011100; // O4_128 = + 0.980785 -O.195090 7'd40: b_tmpl = 20 'bO111110001_1110000100; // W05_128 = + 0.970031 -0.242980 7'd6, 7'd41, 7'd69: b_tmpl = 20, bO111101010_1101101011; // W6_128 = + 0.956940 -0.290285 7'd42: b_tmpl = 20'bO111100010_11010l0100; // W07_128 = + 0.941544 -0.336890 7'd7, 7'd43: b_tmpl = 20 'bO111011001_1100111100; // 08_128 = + 0.923880 -0.382683 7'd44, 7'd70: b_tmpl = 20'bO111001111_1100100101; // W09_128 = + 0.903989 -0.427555 7'd8, 7'd45: b_tmp 1 = 20'bO 111000100_1100001111; // W10_128 = +0.881921 -0.471397 7'd46: b_tmpl = 20'bO110110111_1011111001; // Wll_128 = + 0.857729 -0.514103 7'd9, 7'd47, 7'd71: b_tmpl = 20'bO110101010_1011100100; // W12_128 = + Ó .831470 -0.555570 7'd48: b_tmpl = 20'bO110011011 1011001111; // W13 128 = + 0.803208 -0.595699 7 'dlO, 7'd49: b_tmpl = 20'bO110001100_1010111011; // W14_128 = + 0.773010 -0.634393 7'd50, 7'd72: b_tmpl = 20'bO101111011_1010101000; // W15_128 = + 0.740951 -0.671559 l 'd //, 7'd51: b_tmpl = 20'bO101101010_1010010110; // W16_128 = + 0.707107 -0.707107 7'd52: b_tmpl = 20'bO101011000_1010000101; // W17_128 = + 0.671559 -0.740951 7'dl2, 7'd73, 7'd53: b_tmpl = 20, bO101000101_1001110100, // W18_128 = + 0.634393 -0.773010 7'd54: b_tmp 1 = 20 'bO 1001100011001100101, // W19 128 = +0.595699 -0.803208 7' dl3, 7'd55: b_tmpl = 20'bO100011100_l001010110, // W20_128 = + 0.555570 -0.831470 7'd74, 7'd56: b_tmp 1 = 20'bO 100000111_1001001001, // W21128 = + 0.514103 -0.857729 7'dl4, 7'd57: b_tmpl = 20'bO011110001_1000111100, // W22_128 = + 0.471397 -0.881921 7'd58: b_tmpl = 20 'bOOllOUOll 1000110001, // W23 128 = + 0.427555 -0.903989 7'dl5, 7'd75, 7'd59: b_tmpl = 20'bO011000100_1000100111, // W24_128 = + 0.382683 -0.923880 7'd60: b_tmpl = 20'bO010101100_1000011110, // W25_128 = + 0.336890 -0.941544 7'dl6, 7'd61: b_tmpl = 20'bO010010101_1000010110, // W26_128 = + 0.290285 -0.956940 7'd76, 7'd62: b_tmpl = 20, b0001111100_1000001111; // W27_128 = + 0.242980 -0.970031 7'dl7, 7'd63: b_tmpl = 20 'bO001100100_1000001010, // W28_128 = + 0.195090 -0.980785 7'd64: b_tmpl = 20'bO001001011_1000000110, // W29_128 = + 0.146730 -0.989177 7'dl8, l 'dll, 7'd65: b_tmpl = 20'bO000110010_1000000010; // W30_128 = + 0.098017 -0.995185 7'd66: b_tmpl = 20'bO000011001_1000000001; // W31_128 = + 0.049068 -0.998795 7'd 19: b_tmp 1 = 20 'bO000000000_1000000000; // W32_128 = +0.000000 -1.000000 7'd78: b_tmpl = 20'blllll00111_1000000001; // W33_128 = -0.049068 -0.998795 7'd20: b_tmp 1 = 20'b 1111001110_1000000010; // W34_128 = -0.098017 -0.995185 7'd79, 7'd21: b_tmpl = 20'blll0011100_1000001010, // W36_128 = -0.195090 -0.980785 7'd22: b_tmp 1 = 20'b 1101101011_1000010110, // W38_128 = -0.290285 -0.956940 7'd80: b_tmpl = 20'bll01010100_1000011110, // W39_128 = -0.336890 -0.941544 7'd23: b_tmpl = 20'bll00111100_100010011, // W40_128 = -0.382683 -0.923880 7'd81, 7'd24: b_tmpl = 20'bll00001111_1000111100; // W42_128 = -0.471397 -0.881921 7'd25: b_tmp 1 = 20'b 1011100100_1001010110; // W44_128 = -0.555570 -0.831470 7'd82: b_tmpl = 20'bl011001111_1001100101; // W45_128 = -0.595699 -0.803208 7'd26: b_tmpl = 20 'bl010111011_1001110100; // W46 128 = -0.634393 -0.773010 7'd83, 7'd27: b_tmpl = 20 'bl010010110_1010010110; // W48_128 = -0.707107 -0.707107 7'd28: b_tmp 1 = 20'b 1001110100_1010111011, // W50_128 = -0.773010 -0.634393 7'd84: b_tmp 1 = 20'b 1001100101_1011001111; // W51_128 = -0.803208 -0.595699 7'd29: b_tmpl = 20'bl001010110_1011100100; // W52_128 = -0.831470 -0.555570 7'd85, 7'd30: b_tmpl = 20 'bl000111100_1100001111; // W54_128 = -0.881921 -0.471397 7'd31: b_tmpl = 20'bl000100111_1100111100; // W56_128 = -0.923880 -0.382683 7'd86: b_tmpl = 20'bl000011110_1101010100; // W57_128 = -0.941544 -0.336890 7'd32: b_tmpl = 20'bl000010110_1101101011; // W58_128 = -0.956940 -0.290285 7'd87, 7'd33: b_tmpl = 20'bl000001010_1110011100; // W60_128 = -0.980785 -0.195090 7'd34: b tmpl = 20'bl000000010_1111001110; // W62_128 = -0.995185 -0.098017 7'd88: b_tmpl = 20'bl000000001_1111100111, // W63_128 = -0.998795 -0.049068 7'd89: b_tmpl = 20 'bl000000010_0000110010, // W66_128 = -0.995185 +0.098017 7'd90: b_tmpl = 20'bl000001111_0001111100, // W69_128 = -0.970031 +0.242980 7'd91: b tmpl = 20'bl000100111_0011000100; // W72_128 = -0.923880 +0.382683 7'd92: b_tmpl = 20 'bl001001001_0100000111; // W75_128 = -0.857729 +0.514103 7'd93: b_tmpl = 20'bl001110100_0101000101; // W78_128 = -0.773010 +0.634393 7'd94: b tmp 1 = 20'b 1010101000_0101111011; // W81_128 = -0.671559 +0.740951 7'd95: b_tmpl = 20'bl011100100_0110101010; // W84_128 = -0.55570 +0.831470 7'd96: b tmpl = 20'bll00100101_0111001111, // W87_128 = -0.427555 +0.903989 7'd97: b tmp 1 = 20'bll01101011_0111101010, // W90_128 = -0.290285 +0.956940 7'd98: b_tmpl = 20 'blll0110101_0111111010, // W93_128 = -0.146730 +0.989177 default: b tmpl // W00_128 = + l.000000 -0.000000 endcase always © (posedge clk) if (enable_3) b_tmp2 < = b_tmpl; assign out_br = b_tmp2 [c_wordlength * 2-l: c_wordlength]; assign out_bi = b_tmp2 [c_wordlength-l: 0]; endmodule Listing 11 // Sccsld:% W%% G% ******************************** ************* Copyright (c) 1997 Pioneer Digital Design Center Limited Author: Dawood Alam. Description: Verilog code for a lookup table decoder. Notes: Used to generate addresses for each coefficient, based on the in_Address. Addresses are dependent on one of 4 rows (see figures) and on the sequence length (rom_AddressSize). Each row gives rise to a unique address sequence based on an algorithm. N refers to the index of the twiddle factor, NOT the absolute address Breakpoints determine where the valúes change on line 2. ************************** ****** timescale lns / lOOps module fft_coeff_dcd (clk, enable_3, in_address, out_address, nrst); parameter rom_AddressSize = 1; // Twice ROM address. parameter break_point2 = 1; // 2nd break pt line 2 parameter break_point3 = 1; // 3rd break pt line 2 input [rom_AddressSize-l: 0] in_address; input clk, nrst, enable 3 output [rom_AddressSize-2: 0] out_address; wire [rom_AddressSize-2: 0] out_address; wire [1: 0] line_number; wire nrst; reg [rom_AddressSize-2: 0] out_address_tmp; reg [1: 0] inc, count; reg rst; // Decode which of the 4 lines are being addressed and assign it to line no. // Only need upper two bits of in_address since 4 lines in sequence length. assign line_number =. { in_address [rom_AddressSize-l], in_address [rom_AddressSize-2]}; // Check for end of line and force out_address to zero on next clock edge. always @ (in address) if (in_address [rom_AddressSize-3: 0] == { rom_AddressSize-2 { l'bl.}..}.) rst = 0; else rst = 1; // Check for line number and decode appropriate out_address using algorithm // derived by studying coefficient tables for mpys MO, Ml and M2. always © (line_number or in_address or count) case (line_number) // 2'dO: 11 LINE 0, inc by 2, then run the inc sequence 1 -_, 1 -_., 2_, 1 _ ,, 1 _ ,, 2_ ... begin if (in address [rom AddressSize-3] &(in_address [rom_AddressSize4: 0])) begin if (count == 2 'di I count == 2'dO) inc = 2' di; else inc = 2'd2; end else inc = 2'd2; end // 2 'di: 11 LINE 1"inc by 1. inc = 1; / 2'd2: 11 LINE 2 inc by 3, (inc by 2 at N / 4 + 1), (inc by 1 at N / 2-1). begin if (in_address [rom_AddressSize-3: 0] > = break_point3) inc - 2 'di; 11 Third stage, inc by 1. else if (in_address [rom_AddressSize-3: 0] > = break_point2) inc = 2'd2; 11 Second stage, inc by 2. else inc = 2'd3; 11 First stage, inc by 3. end // 2'd3: 11 LINE 3, fixed at address 0. inc = 2'dO; • endcase always (posedge clk) if (enable_3) begin if (Inrst 1 1! Rst) // out_address = 0 at end of line or pwr Reset out_address_tmp = 0; else out_address_tmp c = out_address tmp + inc; // Onl'y count if at the correct point on line 2. if (in_address [rom_AddressSize-3] &(1 in_address [rom_AddressSize: 0])) count < = ((count == 2'd2)? 2'dO: count + 2'dl); // Only count to 2. else count < = 2'dO; end assign out_address = out_address tmp; endmodule Listing 12 // Sccsld:% W%% G% ******************************** **************** Copyright (c) 1997 Pioneer Digital Design Center Limited Author: Dawood Alam. Description: Verilog code for a configurable 2K / 8K radix 2 ^ 2 + 2 singlepath-delay-feedback, decimation in frequency, (r22 + 2sdf DIF) Fast Fourier Transform (FFT) processor. (RTL) Notes: This FFT processor computes one pair of 1 / Q data points every 4 fast clk cycles. A synchronous active-low reset flushes the entire pipeline and resets the FFT. Therefore the next pair of valid inputs are assumed to be the start of the active interval of the next symbol. There is a latency of 2048/8192 sample points + 7 slow clock cycles. This equates to (2048/8192 + 7) * 4 fast clk cycles. When the out_ovf flag is raised overflow has occured and saturation is performed on the intermediary calculation upon which the overflow has occured. If the valid_in_flag is held low, the entire pipeline is halted and the valid_out flag is also held low. valid_out is also held low until the entire pipeline is full (after the above number of clock cycles). To Do: RAM control (MUX), ROM lookup (quadrant lookup), Change BF code for unique saturation nets for synthesis. ovf_detection (correct) register o / p ov detection (correct) for mpy and BFs ROM / RAM test stuff. ***************************************** 'timescale Ins / lOOps module fft_r22sdf (in_xr, in_xi, clk, nrst, in_2k8k, valid_in, out_xr, out_xi, out_ovf, enable_0, enable_l, enable_2, enable_3, valid_out, ram_address, ram_enable, address_rom3, address_rom4, z2r_4, z2i_4, // RAM input ports. Z2r_5, z2i_5, // Output data from this z2r 6, z2i 6, // module. z2r_7, z2i_7, z2r_8, z2i_8, z2r_9, z2i_9, z2r_10, z2i_10, xl r_4, xli_4, // RAM output ports. xl r_5, xli_5, // Input data to this xl r_6, xli_6, // module. xlr_7, xli_7, xlr_8, xli_8, xlr_9, xli_9, xlr_10"xli_10, br_3, bi_3, br_4, bi_4); // // Parameter dehnitions. // parameter wordlength = 12; // Data wordlength. parameter c_wordlength = 10; / / Coeff wordlength. Parameter AddressSize = 13; // Size of address bus parameter rom_AddressSize = 13; // ROM address bus size, parameter mult_scale = 3; // Multiplier sca // ing: // l - / 4096, 2 = / 2048, // 3 = / 1024, 4 = / 512. parameter sl2 wdlength = 11; // Sectn 12 wordlength.parameter if l_wdlength = 12; // Sectn 11 wordlength.

II s // > = sl2 > = wordlen // // InpuVOutput ports. // input clk, // Master clock. nrst, // Power-up reset. in_2k8k, // 2K mode active low. valid_in; // Input data valid. input [9: 0] in_xr, // FFT input data, I. in_xi; // FFT input data, Q. input [wordlength-l: 0] xlr_4, xli_4, // RAM output ports xlr_5, xli_5, xlr_6, xli_6, xlr_7, xli_7, xlr_8, xli_8, xlr_9, xli_9, xlr_10, xli_10; input [c_wordlength-l: 0] br_3, bi_3, br_4, bi_4; output out_ovf, // Overflow flag. enable_0, // Enable clock 0. enable_l, // enable clock 1. enable_2, // enable clock 2. enable_3, // enable clock 3. valid_out, // Output data valid. ram_enable; output [wordlength-l: 0] out_xr, // FFT output data, I. out_xi; // FFT output data, Q. output [wordlength-l: 0] z2r_4, z2i_4, // RAM input ports. z2r 5, z2i_5, z2r_6, z2i_6, z2r_7, z2i_7, z2r_8, z2i_8, z2r_9, z2i_9, z2r_10, z2i_10; output [rom_AddressSize-6: 0] address_rom3; output [rom_AddressSize4: 0] address_rom4; output [AddressSize-1: 0] ram_address; // // Wlre / register declarations. // wire [1: 0] control; // clk decode. wire [AddressSize-1: 0] address, // FFTmain address bus. s, // Pipeline SRs to BFs. ram_address; // RAM address bus. wire [wordlength-l.-O] xl r_0"xl i_0, // Couples the 1 / Q data xlr_l, xl i_l, // outputs from the xlr_2, xl i_2, // memory to the xlr_3, xl i_3, // respective butterfly xlr_4, xl i_4, // processors, via an xlr_5, xl i_5, // input register xlr_6, xli_6, xlr_7, xli_7, xlr_8, xli_8, xlr_9, xli_9, xlr_10, xli_10, x2r_0, x2i_0, // Couples the 1 / Q data x2r_l, x2i_l, // outputs from BF21 x2r_2, x2i_2, // to the 1 / Q inputs of x2r_3, x2i_3, // BF211. Also connects x2r_4, x2i_4, 1 / the 1 / Q ouputs of the x2r_5, x2i_5, // complex multiplier x2r_6, x2i_6, // to the inputs of the x2r_7, x2i_7, // next radix 2 ^ 2 stage. x2r_8, x2i_8, x2r_9, x2i_9, x2r_10, x2i_10; reg [wordlength-1: 0] xlr_4_tmp, xli_4_tmp, // Registered inputs xl r_5_tmp, xli_5_tmp, // from RAM xl r_6_tmp, xli_6_tmp, xl r_7_tmp, xli_7_tmp, xl r_8_tmp, xli_8_tmp, xl r_9_tmp, xli_9_tmp, xl r_l0_tmp, xli_l0_tmp; wire [sll_wdlength-l: 0] xl r_ll, xliALl, // Different bit-widths x2r_ll, x2i_ll; // for 1 / Q lines, but wire [sl2_wdlength-l: 0] xlr_12, xli_12; // similar to the above. wire [wordlength-l: 0] ar_0, ai_0, // Couples the 1 / Q data ar_l, ai_l, // outputs of the ar_2, ai_2, 1 / previous radix 2A2 ar_3, ai_3, // stage into the ar_4, ai_4 , // complex multiplier ar_5, ai_5; // of the next stage. wire [c_wordlength-l: 0] br_0, bi_0, // Couples the 1 / Q br_l, bi_l, // coefficient outputs br_2, bi_2, // from the ROM demapper br_3, bi_3, // to the complex br_4, bi_4, // multiplier br_5, i_5; wire [wordlength-1: 0] z2r_0, z2i_0, z2r_l, z2i_l, z2r_2, z2i_2, z2r_3, z2i_3, reg [wordlength-1 0] z2r_4, z2i_4, // Registered outputs z2r_5, z2i_5, // to RAM z2r_6, z2i_6 z2r 7, z2i 7, z2r_8, z2i_8, z2r_9, z2i_9; wire [wordlength-l: 0] z2r_10, z2i_10; // WILL CHANGE WHEN RAM RIGHT 2 rg wire [wordlength-l: 0] z2r_4_tmp, z2i_4_tmp, // Coupie the 1 / Q data z2r_5_tmp, z2i_5_tmp, // outputs of each BF z2r_6_tmp, z2i_6_tmp, // processor to their z2r_7_tmp, z2i_7_tmp, // respective memory z2r_8_tmp, z2i_8_tmp, // inputs via an output z2r_9_tmp, z2i_9_tmp, // register. z2r_10_tmp, z2i_l 0_tmp; wire [sll_wdlength-l: 0] z2r_ll, z2i_ll; // Different bit-widths wire [if 2_wdlength-l: 0] z2r_12, z2i_12; // for the lst 2 stages. wire [rom_AddressSize-8: 0] address_rom2; // Couples the address wire [rom_AddressSize-6: 0] address_rom3; // decoders outputs to wire [rom_AddressSize4: 0] address_rom4; // respective ROMs. wire [rom_AddressSize-2: 0] address_rom5; wire [rom_AddressSize-7: 0] dcd_address2; // Couples part of the wire [rom_AddressSize-5: 0] dcd_address3; // address bus to the wire [rom_AddressSize-3: 0] dcd_address4; // coefficient decoder. wire [rom_AddressSize-l: 0] dcd_address5; wire ovf_0, ovf_l, // Couples overflow ovf_2, ovf_3, // flag outputs from ovf_4, ovf_5, // each butterfly ovf_6, ovf_7, // processor and complex ovf_8, ovf_9, // multiplier into one ovf_10, ovf_ll, // overflow status flag ovf_12, ovf_13, // called "out_ovf A ovf_1, ovf_15, ovf_16, ovf_17, OVf_l 8; wire clk, nrst, in_2k8k, ovf_2k, out_ovf, enable_0, enable_l, enable_2, enable_3, ram_enable; // RAM enable signal .reg ovf_tm.pl, ovf_tmp2, fft_cycle_complete, // End of lst FFT cycle: output_valid; // Output valid flag. reg [3: 0] pipeline_count; // Counts pipeline regs. reg [AddressSize-l: 0] q, t; reg [1: 0] r, -reg [wordiength-1: 0] xl r_0_reg, xl i_0_reg, xr_tmp2, // Output data reg, I. xi_tmp2; // Output data reg, Q. reg [sl2_wdlength-l: 0] in_xr_tmp, in_xi_tmp; reg [9: 0] xr_reg, // lnputdata reg, 1. xi_reg; // lnput data reg, Q. reg [wordlength-1: 0] x2r_10_tmp2, x2i_10_tmp2, x2r_10_tmp3, x2i_10_tmp3; wire [wordlength-1: 0] xr_tmpl, // Final BF21 (0) out, 1. xi_tmpl; // End BF21 (0) out, Q. wire [wordiength-1: 0] x2r_10_tmpl, x2i_10_tm.pl; wire [sl2_wdlength-l: 0] x2r_ll_tmp, x2i tmp; // Address decoders / Quadrant mappers + pipeline shift registers. // / * fft_sr_addr # (rom_AddressSize-6, 3) sr_addr_2 (clk, enable_3, address [6: 0], // Input, dcd_address2); // Output. fft_coeff_dcd # (rom_AddressSize-6, 11, 21) coeff_dcd_2 (clk, enable_3, dcd_address2, address_rom2, nrst), - * / / fft_sr_addr # (rom_AddressSize4, 2) sr_addr_3 (clk, enable_3, address [8: 0], // Input. Dcd_address3); // Output. fft_coeff_dcd # (rom_AddressSize4, 43, 85) coeff_dcd_3 (clk, enable_3, dcd_address3, address_rom3, nrst); / fft_sr_addr # (rom_AddressSize-2, 1) sr_addr_4 (clk, enable_3, address [10: 0], // Input, dcd_address4); // Output. fft_coeff_dcd # (rom_AddressSize-2, 171, 341) coeff_dcd_4 (clk, enable_3, dcd_address4, address_rom4, nrst); // / * fft_coeff_dcd # (rom_AddressSize, 683, 1365) coeff_dcd_5 (clk, enable_3, address, address_rom5, nrst); // // // ROM lookup tables. // fft_hardwired_luO # (c_wordlength, rom_AddressSize-10) // Case table instance romO (clk, enable_3, address [2: 0], br_0, bi_0); // for a hardwired ROM. m-hardwired.-luí # (c_wordlength, rom_AddressSize-8) // Case table instance roml (clk, enable_3, address [4: 0], br_l, bi_l), - // for a hardwired ROM. fft_hardwired_lu2 # (c_wordlength, rom_AddressSize-6) // Case table instance rom2 (clk, enable_3, address [6: 0], br_2, bi_2), - // for a hardwired ROM. / * fft_hardwired_lu3 # (c_wordlength, rom_AddressSize4) // Case table instance - rom3 (clk, enable_3, address [8: 0], br_3, bi_3); / I for a hardwired ROM. * / / * Fft_hardwired_lu3 # (c_wordlength, rom_AddressSize-5) // Case table instance rom3 (clk, enable_3, acidress_rom3, br_3, bi_3); // for a hardwired ROM. * / / * fft_rom # (c_wordlength, rom_AddressSize-6, ". /.. / ../fft/src/lookup_tables/lu_l 0bit_128pt_scalel") rom2 (address [6: 0], br_2, bi_2), // 128 addresses x 20 bits, does not decode. * / / * fft_rom # (c_wordlength, rom_AddressSize-7, "... / .. / .. / fft / src / lookup_tables / lu_l Obit_l 28pt_scalel") rom2 (address_rom2, br_2, bi_2 ); // 64 addresses x 20 bits, coeff decode. * / / fft_rom # (c_wordlength, rom_AddressSize4, "../../ ./fft/src/lookup_tables/lu_10bit_5l2pt_scalel") rom3 (address [8: 0], br_3, bi_3); // 512 addresses x 20 bits, does not decode. * / / * fft_rom # (c_wordlength, rom_AddressSize-5, "./. ./ ./fft/src/lookup_tables/lu_l 0bit_512pt_scalel") rom3 (clk, enable_3, address_rom3, br_3, bi_3); // 256 addresses x 20 bits. * / / * Fft_rom # (c_wordlength, rom_AddressSize-2, ".. /.. / .. / fft / src / lookup_tables / lu_l 0bit_2048pt_scalel") rom4 (address [10: 0], br_4, bi_4); // 2048 addresses x 20 bits, do not decode. * / / * Fft_rom # (c_wordlength, rom_AddressSize-3, "../../ .. / fft / src / lookup_tables / lu_10bit_2048pt_scalel") rom4 (clk, enable_3, address_rom4 , br_4, bi_4); // 1024 addresses x 20 bits. * / / * Fft_rom # (c_wordlength, rom_AddressSize "../../../fft/src/lookup_tables/Iu_10bit_8192pt_scalel") rom5 (address, br_5, bi_5); // 8192 addresses x 20 bits, does not decode. * / / * Fft_rom # (c_wordlength, rom_AddressSize-l, "../../../fft/src/lookup_tables/lu_10bit_8192pt_scalel") rom.5 (clk, enable_3 , address_rom5, br_5, bi_5); // 4096 addresses x 20 bits. * / // // Section 12 and 11, tail end of FFT pipeline (input stage).

// Section 12 is 11 bits wide and incorporates the 2K / 8K control logic. / Always @ (xr_reg or xi_reg or in_2k8k or x2r_10_tm.pl or x2i_l 0_tm.pl or x2r_10_tmp3 or x2i_10_tmp3) if (! In_2k8k) // Configuring for 2K mode. begin x2r_10_tmp2 = x2r_l 0_tmp3; x2i_10_tmp2 = x2i_10_tmp3; in_xr_tmp = 0; in_xi_tmp = 0; end else // Configuring for 8K mode. begin x2r_10_tmp2 = x2r_10_tmpl x2i_10_tmp2 = x2i_10_tm.pl; // Sign extend frorn 10 bits, as section 12 is sl2_wdlength bits. in_xr_tmp =. { . { (sl2_wdlength-9) { xr_reg { 9]} } , xr_reg [8: 0]}; in_xi_tmp =. { . { (sl2_wdlength-9) { xi_reg [9]} } , xi_reg [8: 0]}; end always © (posedge clk) // Pipeline register to enable correct operation in if (enable_3) // 2K mode without retiming the entire pipeline since begin // 8 mode introduces 1 additional pipeline register.

// Sign extended 10 bit inputs to wordlength bit inputs. // for bypass lines into stage 5. x2r_10_tmp3 < =. { . { (wordlength-9). { xr_reg [9]} } , xr_reg [8: 0]}; x2i_10_tmp3 < =. { . { (wordlength-9). { xi_reg [9]} } , xi_reg [8: 0]}; end assign x2r_10 = x2r_10_tmp2; assign x2i_10 = x2i_10_tmp2; // Sign extend from sl2_wdlength bits to if l_wdlength bits between // sections 12 and //. Uncomment below if s _ // < > s_12. assign x2r _ // =. { . { (if l_wdlength-sl 2_wdlength + l). { x2r_l 1 _tmp [sl 2_wdlength-l]} } , x2r_l 1 _tmp [sl 2_wdlength-2: 0]}; assign x2i_l 1 =. { . { (if l_wdlength-sl 2_wdlength + l). { x2i_l l_tmp [sl 2_wdlength-l]} } , x2i_l l_tmp [sl 2_wdlength-2: 0]} , - // Uncomment below if s _ // = s_12. / assign x2r _ // = x2r_l l_tmp; assign x2i _ // = x2i_l l_tmp; * / fft_bf21 # (sl2_wdlength) bf21_6 (clk, enable_l, xlr_12, xli_12, in_xr_tmp, in_xi_tmp, // Ext In s [l 2], x2r_l l_tmp, x2i_l l_tmp, z2r_12, z2i_12, // Outputs. ovf_l 8); / Fft_ram # (sl2_wdlength, 12) ram_12 (clk, enable_l, enable_3, ram_address [// 0], // 4096 Addrs z2r_12, z2i_12, // Inputs r_12 xl xl i_12..); // Outputs. / fft_bf2 // # (sl l_wdlength) bf2 // _ 6 (clk, enable_l, xlr _ //, xli _ //, x2r _ //, x2i _ //, // Inputs. s [//], s [12], ar_5 , ai_5, z2r _ //, z2i _ //, // Outputs, ovf_l 7); fft_sr_lbit # (1) sr_lbit _ // (clk, enable_3, address [//], s //]), - // SR //. fft_sr_lbit # (1) sr_lbit_12 (clk, enable_3, address [12], S [12]); // SR 12. / fft_ram # (sl l_wdlength "//) ram_l 1 (clk, enable_l, enable_3, ram_address [10: 0], // 2048 addrs, z2r _ //, z2i _ //, // inputs xl r_l 1 xl i_l 1). // Outputs * / // // // Section 10 and 9. fft_com.plex_mult_mux # (wordlength, c_wordlength, mult_scale) m.5 (clk, control, ar_5, ai_5, br_5, bi_5 , // Inputs x2r_10_tmp 1 x2i_10_tmp 1 // Outputs vf_16)..? fft_bf21 # (wordlength) bf2l_5 (clk, enable_l, r_10 xl xl i_10, // Inputs x2r_10, x2i_10, S [10], x2r_9. , x2i_9, // Outputs, z2r_10, z2i_10, Ovf_15), fft_bf211 # (wordlength) bf211_5 (clk, enable_l, xlr_9_tmp, xli_9 tmp, // Inputs, x2r_9, x2i_9, s [9], s [10], ar_4, ai_4, // Outputs, z2r_9_tmp, z2i_9_tmp, ovf_14), -fft_sr_l bit # (2) sr_l bit_9 (clk, enable_3, address [9], s [9]); // SR 9. fft_sr_l bit # (2) sr_l bit_10 (clk, enable_3, address [10], s [10]); // SR 10. // // // Section 8 and 7. fft_complex_mult_mux # (wordlength, c_wordlength, mult_scale) m4 (clk, control, ar_4, ai_4, br_4, bi_4, // Inputs x2r_8, x2i_8, // Outputs ovf_13..); fft_bf21 # (wordlength) bf21_4 (clk, enable_l, xlr_8_tmp, xli_8_tmp, // Inputs, x2r_8, x2i_8, s [8], x2r_7, x2i_7, // Outputs, z2r_8_tmp, z2i_8_tmp, ovf_l 2); fft_bf211 # (wordlength) bf211_4 (clk, enable_l, xlr_7 tmp, xli_7_tmp, // Inputs, x2r_7, x2i_7, s [7], s [8], ar_3, ai_3, // Outputs, z 2 r_7_tmp, .z 2 i_7_tmp , Ovf_ll); fft_sr_lbit # (3) sr_lbit_7 (clk, enable_3, address [7], s [7]); // SR 7. fft_sr_l bit # (3) sr_l bit_8 (clk, enable_3, address [8], s [8]); // SR 8 / // // Section 6 and 5. fft_complex_mult_mux # (wordlength, c_wordlength, mult_scale) m3 (clk, control, ar_3, AI_3, br_3, bi_3, // Inputs. X2r_6, x2i_6, // Outputs. ovf_10); fft_bf21 # (wordlength) bf21_3 (clk, enable_l, xlr 6_tmp, xli_6_tmp, // Inputs, x2r_6, x2i_6, s [6], x2r_5, x2i_5, // Outputs, z2r_6_trnp, z2i_6_tmp, ovf_9); fft_bf2ll # (wordlength) bf21l_3 (clk, enable_l, xlr 5_tmp, xl i_5_tmp, // Inputs x2r_5, x2i_5 s [5]. s [6]. ar_2, ai_2, // Outputs. z2r_5_tmp, z2i_5_tmp, ovf 8); fft_sr_l bit # (4) sr_lbit_5 (clk, enable_3, address [5], s [5]); // SR 5. fft_sr_lbit # (4) sr_lbit_6 (clk, enable_3, address [6], s [6]); // SR 6. // // Section 4 and 3. // fft_complex_mult_mux # (wordlength, c_wordlength, mult_scale) m2 (clk, control, ar_2, ai_2, br_2, bi_2, // Inputs, x2r_4, x2i_4, // Outputs. Ovf_7); fft_bf21 # (wordlength) bf2l_2 (clk, enable_l, xlr_4_tmp, xli_4_tmp, // Inputs, x2r_4, x2i_4, S [4], x2r_3, x2i_3, // Outputs, z2r_4_tmp, z2i_4_tmp, ovf_6); fft_bf2 // # (wordlength) bf211_2 (clk, enable_l, xl r_3, xl i_3, // Inputs, x2r_3, x2i_3, s [3], s [4], ar_l, ai_l, // Outputs. z2r_3, z2i_3, Ovf_5); fft_sr_l bit # (5) sr_l bit_3 (clk, enable_3, address [3] s [3]), // SR 3. fft_sr_l bit # (5) sr_l bit_4 (clk, enable_3, address [4] s [4]) , // SR 4. fft_sr_iq # (wordlength, 8) sr_iq_3 (clk, enable_3, // Length = 8. z2r_3, z2i_3, // Inputs. Xlr_3, xli_3); // Outputs. / // Section 2 and 1. // _ fft_complex_mult_mux # (wordlength, c_wordlength, mult_scale) ml (clk, control ar_l, ai_l, br_l, bi_l, // Inputs. X2r_2, x2i_2, // Outputs. Ovf_4); fft_bf2l # (wordlength) bf21_l (clk, enable_l, xlr_2, xli_2, // Inputs x2r_2, x2i_2, s [2] x2r_l, x2i_l, // Outputs, z2r 2, z2i 2, ovf_3); fft_sr_iq # (wordlength, 4) sr_iq_2 (clk, enable_3, // Length = 4. z2r_2, z2i_2, // Inputs. xlr_2, xli_2); // Outputs. fft_bf211 # (wordlength) bf211_l (clk, enable_l, xlr_l, xli_l, // Inputs x2r_l, x2i_l, s [l], s [2], ar_0, ai_0, // Outputs, z2r_l, z2i_l, ovf_2); assign s [l] = -address [1]; // Invert s [l] (see count sequence), SRl not req. // fft_sr_l bit # (6) sr_l bit_l (clk, enable_3, address [1], s [l]); // SR 1. fft_sr_lbit # (6) sr_lbit_2 (clk, enable_3, address [2], s [2]); // SR 2. fft_sr_iq # (wordlength, 2) sr_iq_l (clk, enable_3, // Length = 2. z2r_l, z2i_l, // Inputs xlr_l, xli_l); // Outputs. // // Section 0, front end of FFT pipeline (output stage), mult scale = 4. // fft_complex_mult_mux # (wordlength, c_wordlength, 4) mO (clk, control, ar_0, ai_0, br_0, bi_0, // Inputs, x2r_0, x2i_0, // Outputs, avfXL); fft_bf21 # (wordlength) bf21_0 (clk, enable_l, xlr_0, xli_0, // Inputs, x2r_0, x2i_0, s [0], xr_tmp 1, xi_tmp 1, // Outputs, z2r_0, z2i_0, ovf_0); assign s [0] = -address [0]; // Invert s [0] (see count sequence), SRO not req. // fft_sr_lbit # (7) sr_lbit_0 (clk, enable_3, address [0], s [0]); // SR 0. II Last stage should be just to single register as only 1 location needed. always © (posedge clk) // No reset required as data clocked through registers. if (enable_3) begin xlr_0_reg < = z2r_0 xli_0_reg c = z2i_0; end assign xlr_0 = xlr_0_reg assign xli_0 = xli_0_reg; // // Reglster Inputs / Outputs 'ifdef BIN_SHIFT always © (posedge clk) // Registered inputs. if (enable_3 & &address [0]) // == freq bin shift by pi. begin xr_reg < = in_xr; xi_reg < = in_xi; end else if (enable_3 &&address [0]) // == freq bin shift by pi. begin xr_reg < = -in_xr + l'bl; // This is equivalent to multiplying by xi_reg < = ~ in_xi + l'bl; // exp (j * pi * n) == (-lXn. end 'else always © (posedge clk) // Registered inputs. if (enable_3) begin xr_reg < = in_xr; xi_reg < = in_xi; end 'endif always © (posedge clk) // Registered outputs. if (enable_3) begin xr_tmp2 < = xr_tmpl; xi_tmp2 < = xi_tm.pl; end assign out_xr = xr_tmp2; assign out_xi = xi_tmp2; always © (posedge clk) // RAMs are latched on outputs so do not begin // need to enable. z2r_4 < = z2r_4_tmp; // Register FFT outputs to RAM. z2i_4 < = z2i_4_tmp z2r_5 < = z2r_5_tmp z2i_5 < = z2i_5_tmp z2r_6 < = z2r_6_tmp z2i_6 < = z2i_6_tmp z2r_7 < = z2r_7_tmp z2i_7 < = z2i_7_tmp z2r 8 < = z2r_8_tmp z2i_8 < = z2i_8_tmp z2r_9 < = z2r_9_tmp z2i_9 < = z2i_9_tmp // z2r_10 < = z2r_10_tmp; // z2i_10 < = z2i_10_tmp; xlr_4_tmp < = xlr_4; // Register FFT inputs from RAM. xli_4_tmp < = xli_4, xlr_5_tmp < = xlr_5, xli_5_tmp < = xli_5, xlr_6 tmp < = xlr_6, xli_6_tmp < = xli_6, xlr_7_tmp < = xlr_7; xli_7_tmp < = xli_7, xlr_8_tmp < = xlr_8, xli_8_tmp < = xli_8, xlr_9_tmp < = xlr_9, xli_9_tmp < = xli_9, // xlr_l 0_tmp < = xlr_10; // Xli_l 0_tmp < = Xli_10; end // // Synchronoue butterfly controller. // always © (posedge clk) if (nrst) // Synchronous power-up reset. q < = 0; else if (enable_3) q < = q + l'bl; assign address = q; // // Synchronous RAM address generator. // always © (posedge clk) if (nrst) // Synchronous power-up reset. t < = 0; else if (enable_2) t < = t + l'bl, assign ram_address = t; assign ram_enable = enable_3 // enable_2; // ram enable signal. // valid_out status flag generation. // _ always © (posedge clk) if (nrst) fft_cycle_complete < = l'bO; // Detect end of lst fft cycle i.e. 2K or 8K. else if ((~ in_2k8k & fcaddress [10: 0]) // (in_2k8k & & amp; &address [12: 0])) fft_cycle_complete < = l'bl; else fft_cycle_complete < = fft_cycle_complete; always © (posedge clk) // Account for pipeline and 1/0 registers. if (¡nrst) pipeline_count < = 4'bO; // Stop at pipeline_depth - 1. else if (enable_3 & fft_cycle_complete &pipeline_count < 8) // pipe depth = 8 pipeline_count < = pipeline_count + l'bl; always (posedge clk) // Test if the pipeline is fu // and the input if (nrst) // is valid before asserting valid_out. output_valid < = l'bO; else if (enable_2 & pipeline_count [3]) output_valid < = l'bl; else output_valid < = l'bO; assign valid_out = output_valid; // // Fast 40 MHz clock decoder and valid_in control. // always © (posedge clk) if (nrst) // Synchronous power-up reset. r < = O; else if (valid_in) // Count if input data valid. r < = r + l'bl; assign control =. { valid_in & r [1], valid_in _? r [0]}; assign enable_0 = valid_in & (~ r [l] & -r [0]); // Gate valid_in with assign enable_l = valid_in & (-r [l] & r [0]); // decoded enable signáis assign enable_2 = valid_in & (r [l] & -r [0]); // to control a // reg 's. assign enable_3 = valid_in & (r [l] &r [O]), - // // Overflow detection, OR overflows from each stage to give overflow flag. // assign ovf_2k = ovf_0 // ovf_l // ovf_2 // ovf_3 // ovf_4 // ovf_5 // ovf_6 // ovf_7 // ovf_8 // ovf_9 // ovf_10 // ovf // ovf 12 // ovf 13 //? vf_14 ((ovf_15; // 2kJ8k Overflow flag configuration. always @ (in_2k8k or ovf_16 or ovf_17 or ovf 18 or ovf_2k) if (in_2k8k) ovf_tm.pl = ovf_2k // ovf 16 // ovf_17 // ovf_18; else ovf_tmpl = ovf 2k; always © (posedge clk) // Register overflow if (enable_3 & fft_cycle_complete) // flag to change when ovf_tmp2 < = ovf_tm.pl; // I / Q samples are valid // from FFT processor. out_ovf = ovf_tmp2; ifdef 0VERFL0W_DEBUG // Debug code to display overflow output of a particular instance.

// Concurrently monitor overflow flag and halt on overFlow. always @ (out_ovfl // ovf_x wires are a // registered at lower level. if (out_ovf) begin $ display ("Overflow has occurred, type. to continue."); $ display ("Overflow flag, out_ovf =", out_ovf ); if ovf 18) $ display "Overflow on port ovf 18") if ovf_17) $ display "Overflow on port ovf_ _17") if ovf_16) $ display "Overflow on port ovf_ _16") if ovf_15) $ display "Overflow on port ovf_ _15") if? vf_14) $ display" Overflow on port ovf_ _14") if? vf_13) $ display" Overflow on port ovf_ _13") if ovf_12) $ display" Overflow on port ovf_ _12") if Ovf_ll) $ display "Overflow on port ovf_ _11") if ovf 10) $ display "Overflow on port ovf 10") if ovf_9) $ display "Overflow on port ovf_9"); if ovf_8) $ display "Overflow on port ovf_8"); if ovf_7) $ display "Overflow on port ovf_7"); if ovf_6) $ display "Overflow on port ovf_6"); if ovf_5) $ display "Overflow on port ovf_5"); if ovf_4) $ display "Overflow on port ovf_4"); if ovf_3) $ display "Overflow on port ovf_3"); if ovf_2) $ display "Overflow on port ovf_2"); if ovf_l) $ display "Overflow on port ovf_l"); if (ovf_0) $ display ("Overflow on port ovf_0"), - $ stop; end endif endmodule Listing 13 // Sccsld:% W%% G% ****************************** *** Copyright (c) 1997 Pioneer Digitai Design Center Limited Author: Dawood Alam. Description: Verilog code for the window lookup table, used to determine the variance of the data and henee the F_ratio. Notes: ************************************ timescale 1 ns / l OOps module fft_window_lu (clk, enable_3, in_address, out_data); parameter r_wordlength = 10; // Data wordlength. parameter lu_AddressSize = 13; // Address bus size. input clk, enable_3; input [lu_AddressSize-l: 0] in_address; output [r_wordlength-l: 0] out_data; reg [r_wordlength-l: 0] data_tm.pl, data_tmp2; always @ (in_address) casez (in_address) 13'b0000000000000: data_tmpl = 10'blOOOOOOOOO; 13'bOOOOOOOOOOOOl: data_tmpl = 10'b0000000000; 13'b0000000000010: data_tmpl = 10'bOOOOlOOl l; 13'b0000000000011: data_tmpl = 10'bOOOOlllllO; 13'b0000000000100: data_tmpl = 10'bOOOlOOlllO; 13'b0000000000101: data_tmpl = 10'bOOOlOllOll; 13'b0000000000110: data_tmpl = 10'bOOOllOOllO; 13'bOOOOOOOOOOlll: data_tmpl = 10'bOOOllOlllO; 13'b0000000001000: data_tmpl = 10'bOOOlllOllO; 13'bOOOOOOOOOlOOl: data_tmpl = 10'bOOOlllllOl; 13'b0000000001010: data_tmpl = 10'bOOlOOOOOll; 13'b0000000001011: data_tmpl = 10'bOOlOOOlOOO; 13'b0000000001100: data_tm.pl = 10'bOOlOOOllOl; 13'b0000000001101: data_tmpl = 10'bOOlOOlOOOl; 13'b0000000001110: data_tm.pl = 10'bOOlOOlOllO; 13'b0000000001111: data_tmpl = 10'bOOlOOllOlO; 13'b0000000010000: data_tmpl = 10'bOOlOOlllOl; 13'bOOOOOOOOlOOOl: data_tmpl = 10'bOOlOlOOOOl; 13'b0000000010010: data_tmpl = 10'bOOlOlOOlOO; 13'b0000000010011: data_tmpl = 10'bOOlOlOOlll; 13'b0000000010100: data_tmpl = 10'bOOlOlOlOlO; 13'b0000000010101: data_tmpl = 10'bOOlOlOllOl; 13'b0000000010110: data_tm.pl 10'bOOlOlOllll; 13'b0000000010111: data_tmpl = 10'bOOlOllOOlO; 13'b0000000011000: data_tmpl = 10'bOOlOllOlOO; 13'b0000000011001: data_tmpl = 10'bOOlOllOlll; 13'b0000000011010: data_tmpl = 10'bOOlOlllOOl; 13'b0000000011011: data_tm.pl = 10'bOOlOlllOll; 13'b0000000011100: data_tmpl = 10'bOOlOllllOl; 13'bOOOOOOOOlllOl: data_tm.pl = 13'b0000000011110: data_tmpl = 10'bOOllOOOOOl; 13'bOOOOOOOOlllll: data_tmpl = 10'bOOllOOOOll; 13'b0000000100000: data_tmpl = 10'bOOllOOOlOl; 13'bOOOOOOOlOOOOl: data_tmpl = 10'bOOllOOOllO; 13'b0000000100010: data_tmpl = 10'bOOllOOlOOO; 13'b0000000100011: data_tmpl = 10'bOOllOOlOlO; 13'b0000000100100: data_tmpl = 10'bOOllOOlOll; 13'bOOOOOOOlOOlOl: data_tmpl = 10'bOOllOOllOl; 13'b0000000100110: data_tm.pl = 10'bOOllOOlllO; 13'b0000000100111: data_tmpl = 10'bOOllOlOOOO; 13'b0000000101000: data_tmpl = 10'bOOllOlOOOl; 13'b0000000101001: data_tmpl = 10'bOOllOlOOll; 13'b0000000101010: data_tmpl = 10'bOOllOlOlOO; 13'b0000000101011: data_tm.pl = 10'bOOllOlOlOl; 13'b0000000101100: data_tmpl = 10'bOOllOlOlll; 13'bOOOOOOOlOllOl: data_tmpl = 10'bOOllOllOOO; 13'b0000000101110: data_tmpl = 10'bOOllOllOOl; 13'b0000000101111: data_tmpl 10'bOOllOllOlO; 13'b0000000110000: data_tmpl = 10'bOOllOlllOO 13'b0000000110001: data_tmpl = 10'bOOllOlllOl 13'b0000000110010: data_tmpl = 10'bOOllOllllO 13'b0000000110011: data_tmpl = 10'bOOllOlllll 13'b0000000110100: data_tmpl = 10'bOOlllOOOOO 13'b0000000110101: data_tmpl = 10 'bOOlllOOOOl 13'b0000000110110: data tmpl = 10'bOOlllOOOlO 13'b0000000110111: data_tmpl = 10'bOOlllOOOll 13'b0000000111000: data_tmpl = 10' bOOlllOOlOO 13'b0000000111001: data_tmpl = 10'bOOlllOOlOl 13'b0000000111010: data_tmpl = 10'bOOlllOOllO 13'b0000000111011: data_tmpl = 10'bOOlllOOlll 13'b0000000111100: data_tmpl = 10'bOOlllOlOOO 13'b0000000111101: data_tmpl = 10'bOOlllOlOOl 13'b0000000111110: data_tmpl = 10'bOOlllOlOlO 13'b0000000111111: data_tmpl = 10 'bOOlllOlOll 13'b0000001000000: data_tmpl = 10'bOOlllOllOO 13'bOOOOOOlOOOOOl: data_tmpl = 10 'bOOlllOUOl 13'b0000001000010: data_tmpl = 10'bOOlllOlllO 13'b0000001000011: data_tmpl = 10'bOOlllOllll 13'b0000001000100: data_tmpl = 10'bOOlllOllll 13'b0000001000101: data_tmpl = 10'bOOllllOOOO 13'b0000001000110: data_tmpl = 10'bOOllllOOOl 13'bOOOOOOlOOOlll: data_tmpl = 10'bOOllllOOlO 13'b000000100100z: data_tmpl = 10 'bOOllllOOll 13'b0000001001010: data_tmpl = 10'b0011110100 13'b0000001001011: data_tmpl = 10'b0011110101 13' b000000100110z: data_tmpl = 10'b0011110110 13'b0000001001110: data_tmpl = 10'b0011110111 13'b0000001001111: data_tmpl = 10'b0011111000 13'b000000101000z: data_tmpl = 10'b0011111001 13'b0000001010010: data_tmpl = 10'b0011111010 13'b0000001010011: data_tmpl = 10 'b0011111011 13'b0000001010100: data_tmpl = 10'b0011111011 13'b0000001010101: data_tmpl = 10'b0011111100 13'b000000101011z: data_tmpl = 10'b0011111101 13'b0000001011000: data_tmpl = 10'b0011111110 13'b0000001011001: data_tmpl = 10'b0011111111 13'b0000001011010: data_tmpl = 10'b0011111111 13'b0000001011011: data_tmpl = 10'b0100000000 13'b000000101110z: data_tmpl = 10 'b0100000001 13 'b000000101111z: data_tmpl = 10'b0100000010 13'b0000001100000: data_tmpl = 10'b0100000011 13'b0000001100001: data_tmpl = 10' bOlOOOOOlOO 13'b0000001100010: data_tmpl = 10'b0100000100 13'b0000001100011: data_tmpl = 10'b0100000101 13'b0000001100100: data_tmpl = 10 'bOlOOOOOlOl 13'b0000001100101: data_tmpl = 10'b0100000110 13'b0000001100110: data_tmpl = 10'b0100000110 13'b0000001100111: data_tmpl = 10'b0100000111 13'b000000110100z: data_tmpl = 10'b0100001000 13'b000000110101z: data_tmpl = 10'b0100001001 13' bOOOOOOllOllOz: data_tmpl = 10'b0100001010 13'bOOOOOOllOlllz: data_tmpl = 10'b0100001011 13'b000000111000z: data_tmpl = 10'b0100001100 13'b000000111001z: data_tmpl = 10'b0100001101 13'b000000111010z: data_tmpl = 10'b0100001110 13'b000000111011z: data tmpl = 10'b01 00001111 13'b000000111100z: data_tmpl = 10'b0100010000 13'b000000111101z: data_tmpl = 10'bOlOOOlOOOl; 13'b000000111110z: data_tmpl = 10'b0100010010; 13'b0000001111110: data_tmpl = 10'b0100010010 13'b0000001111111: data_tmpl = 10'b0100010011 13'b0000010000000: data_tmpl = 10'b0100010011 13'b0000010000001: data_tmpl = 10'bOlOOOlOlOO; 13'b0000010000010: data_tmpl = 10'b0100010100; 13'b0000010000011: data_tmpl = 10'b0100010101; 13'b0000010000100: data_tmpl = 10'bOlOOOlOlOl; 13'b00000100001zl: data tmpl = 10'b0100010110; 13'b0000010000110: data_tmpl = 10'bOlOOOlOllO; 13'bOOOOOlOOOlOOz: data_tmpl = 10'b0100010111; 13'b000001000101z: data_tmpl = lO'bOlOOOHOOO; 13'b0000010001100: data_tmpl = 10'b0100011000; 13'b0000010001101: data_tmpl = 10'bOlOOOllOOl; 13'b0000010001110: data_tmpl = 10'b0100011001; 13'bOOOOOlOOOllll: data_tmpl = 10'b0100011010; 13'b000001001000z: data_tmpl = 10'b0100011010; 13'b000001001001z: data_tmpl = 10'bOlOOOllOll; 13'b000001001010z: data_tmpl = 10'b0100011100; 13'b0000010010110: data t pl = 10'b0100011100; 13'bOOOOOlOOlOlll: data_tmpl = 10'bOlOOOlllOl; 13'bOOOOOlOOllOOz: data_tmpl = 10'b0100011101 13'b000001001101z: data_tmpl = 10 'bOlOOOllllO I3'b000001001110z: data_tmpl = 10'b0100011111 13'b0000010011110: data_tmpl = 10'b0100011111 13'b0000010011111: data_tmpl = 10'b0100100000 13'b000001010000z: data_tmpl = 10'b0100100000 13'bOOOOOlOlOOOlz: data_tmpl = 10 'b0100100001 13'b0000010100100: data_tmpl = 10'b0100100001, 13'b00000101001zl: data_tmpl = 10' b0100100010; 13'b0000010100110: data_tmpl = 10'b0100100010; 13'b000001010100z: data_tmpl = 10'bOlOOlOOOll 13'b0000010101010: data_tmpl = 10'bOlOOlOOOll 13'b0000010101011: data_tmpl = 10'bOlOOlOOlOO 13'b000001010110z: data_tmpl = 10'bOlOOlOOlOO 13'b000001010111z: data_tmpl = 10'bOlOOlOOlOl 13'b0000010110000: data_tmpl = 10'b0100100101 13'b00000101100zl: data_tmpl = 10'bOlOOlOOllO 13'b0000010110010: data_tmpl = 10'bOlOOlOOllO, 13'b000001011010z: data_tmpl = 10'bOlOOlOOlll; 13'b0000010110110: data_tmpl = 10'bOlOOlOOlll 13'bOOOOOlOllOlll: data_tmpl = 10'bOlOOlOlOOO 13'bOOOOOlOlllOOz: data_tmpl = 10'bOlOOlOlOOO 13'b000001011101z: data_tmpl = 10'bOlOOlOlOOl 13'b000001011110z: data_tmpl = 10'bOlOOlOlOOl 13'b000001011111z: data_tmpl = 10'bOlOOlOlOlO 13'b0000011000000: data_tmpl = 10 'bOlOOlOlOlO 13'b00000110000zl: data_tmpl = 10'bOlOOlOlOll 13'b0000011000010: data_tmpl = 10'bOlOOlOlOll 13'bOOOOOllOOOlzz: data_tmpl = 10'bOlOOlOllOO 13'b000001100100z: data_tmpl = 10'bOlOOlOllOl 13 'bOOOOOllOOlOlO: data_tmpl = 10'bOlOOlOllOl 13'b0000011001011: data_tmpl = 10'bOlOOlOlllO 13'b000001100110z: data_tmpl = 10'bOlOOlOlllO 13'b0000011001110: data_tmpl = 10'bOlOOlOlllO 13'b0000011001111: data_tmpl = 10'bOlOOlOllll 13'b000001101000z: data_tmpl = 10'bOlOOlOllll 13'b0000011010010: data_tmpl = 10'bOlOOlOllll 13'b0000011010011: data_tmpl = 10'bOlOOllOOOO 13'b000001101010z: data_tmpl = 10'bOlOOllOOOO 13'b000001101011z: data_tmpl = 10'bOlOOllOOOl 13'b000001101100z: data_tmpl = 10 'BOlOOllOOOl 13'b000001101101z: data_tmpl = 10'bOlOOllOOlO 13'bOOOOOllOlllOz: data_tmpl = 10'bOlOOllOOlO 13'b000001101111z: data_tmpl = 10'bOlOOllOOll 13'b000001110000z: data_tmpl = 10'bOlOOllOOll 13'b000001110001z: data_tmpl = 10'bOlOOllOlOO 13'bOOOOOlllOOlOz : data_tmpl = 10'bOlOOllOlOO 13'b000001110011z: data t pl = 10'bOlOOllOlOl 13'b000001110100z: data_tmpl = 10'bOlOOllOlOl 13'b000001110101z: data_tmpl = 10 'bOlOOHOHO 13'b000001110110z: data_tmpl = 10'bOlOOllOllO 13'b000001110111z: data_tmpl = 10'bOlOOllOlll 13'b000001111000z: data_tmpl = 10'bOlOOllOlll 13'b000001111001z: data_tmpl = 10'bOlOOlllOOO 13'b000001111010z: data_tmpl = 10'bOlOOl 11000; 13'b0000011110110: data_tmpl = 10'bOlOOlllOOO; 13'b0000011110111: data_tmpl = 10'bOlOOlllOOl 13'b000001111100z: data_tmpl = 10 'bOlOOlllOOl 13'b0000011111010: data_tmpl = 10' bOlOOlllOOl, 13'b0000011111011: data_tmpl = 10'bOlOOlllOlO; 13'b000001111110z: data_tmpl = 10'bOlOOlllOlO 13'b0000011111110: data_tmpl = 10'bOlOOlllOlO data_tmpl = 10'bOlOOlllOll 13'b00001000000z: data_tmpl = 10'bOlOOlllOll 13'b00001000001z: data_tmpl = 10'bOlOOllllOO 13'b0000100001000: data_tmpl = 10 'bOlOOllllOO; 13'b00001000010zl: data_tmpl = 10'bOlOOllllOl; 13'b0000100001010: data_tmpl = 10'bOlOOllllOl 13'b0000100001100: data_tmpl = 10'bOlOOllllOl, 13'bOOOOlOOOOllzl: data_tmpl = 10'bOlOOlllllO 13'bOOOOlOOOOlllO: data_tmpl = 10'b? L ?? lllll? 13'b000010001000z: data_tmpl = 10'bOlOOlllllO 13'b000010001001z: data_tmpl = 13'b000010001010z: data_tmpl = 13'b0000100010110: data_tmpl = 13'b0000100010111: data_tmpl = 10'bOlOlOOOOOO 13'b0000100011077: data_tmpl = 10'bOlOlOOOOOO 13'b00001000111z: data_tmpl = 10'bOlOlOOOOOl 13'b0000100100000: data_tmpl = 10'bOlOlOOOOOl 13'bOOOOlOOlOOOzl: data_tmpl = 10'bOlOlOOOOlO 13'b0000100100010: data_tmpl = 10'b0101000010 13'b000010010010z: data_tmpl = 10'bOlOlOOOOlO 13'bOOOOlOOlOOllz: data_tmpl = 10'bOlOlOOOOll 13'b000010010100z: data_tmpl = 10'bOlOlOOOOll 13'b0000100101010: data_tmpl = 10 'bOlOlOOOOll 13'b0000100101zll: data_tmpl = 10'bOlOlOOOlOO 13'b000010010110z: data_tmpl = 10'bOlOlOOOlOO 13'b0000100101110: data_tmpl = 10'bOlOlOOOlOO 13'b0000100110000: data_tmpl = 10'bOlOlOOOlOO 13'b00001001100zl: data_tmpl = 10'bOlOlOOOlOl 13'b0000100110010: data_tmpl = 10'b0101000101 13'b000010011010z: data_tmpl = 10'b0101000101 13'b000010011011z: data_tmpl = 10'b0101000110 13 'b000010011100z: data_tmpl = 10'b0101000110 13'bOOOOlOOlllOlO: data_tmpl = 10'b0101000110 13'bOOOOlOOlllzll: data_tmpl = 10'b0101000111 13'b000010011110z: data_tmpl = 10'b0101000111 13'b0000100111110: data_tmpl = 10'b0101000111 13'b0000101000000: data_tmpl = 10'b0101000111 13'b00001010000zl: data_tmpl = 10'b0101001000 13'b0000101000zl0: data_tmpl = 10'b0101001000 13'b000010100010z: data_tmpl = 10'b0101001000 13'b0000101000111: data_tmpl = 10'b0101001001 13'b00001010010zz: data_tmpl = 10'b0101001001 1 3'b0000101001100: data_tmpl = 10'b0101001001 13'b00001010011zl: data_tmpl = 10'bOlOlOOlOlO; 13'b0000101001110: data_tmpl = 10 'b0101001010 13'b000010101000z: data_tmpl = 10' b0101001010 13'b0000101010zlz: data_tmpl = 10'b0101001011 13'b000010101010z: data_tmpl = 10'b0101001011 13'b00001010110zz: data_tmpl = lQ'b0101001100 13'b000010101110z: data_tmpl = 10 'bOlOlOOHOO 13'b0000101011110: data_tmpl = 10'b0101001100 13'b0000101011111: data_tmpl = 10'b0101001101 13'b00001011000zz: data_tmpl = 10'b0101001101 13'b0000101100100: data_tmpl = 10'b0101001101 13'b00001011001zl: data_tmpl = 10'b0101001110 13 'b0000101100110: data_tmpl = 10'b0101001110 13'b000010110100z: data_tmpl = 10'b0101001110 13'b0000101101010: data_tmpl = 10'b0101001110 13'b0000101101zll: data_tmpl = 10'b0101001111 13'b000010110110z: data_tmpl = 10'b0101001111 13'bOOOOlOllOlllO: data_tmpl = 10'b0101001111 13'b0000101110000: data_tmpl = 10'b0101001111 13'b00001011100zl: data_tmpl = 10'b0101010000 13'bOOOOlOlllOzlO: data_tmpl = 10'b0101010000 13'b000010111010z: data_tmpl = 10'b0101010000 13'b0000101110111: data_tmpl = 10'b0101010000 13 ' b0000 1011110zz: data_tmpl = 10'b0101010001 13'b000010111110z: data_tmpl = 10'b0101010001 13'b0000101111110: data_tmpl = 10'b0101010001 13'b0000101111111: data_tmpl = 10'b0101010010 13'b00001100000z: data_tmpl = 10'bOlOlOlOOlO 13'b000011000010z: data_tmpl = 10 'bOlOlOlOOlO 13'b000011000011z: data_tmpl = 10'bOlOlOlOOll 13'b00001100010zz: data_tmpl = 10'b? í? lOlOOll 13'b00001100011z: data_tmpl = 10'bOlOlOlOlOO; 13'b000011001000z: data_tmpl = 10'bOlOlOlOlOO 13'b0000110010010: data_tmpl = 10 'b0101010100 13'b0000110010zll: data_tmpl = 10'b0101010101 13'b000011001010z: data_tmpl = 10' b0101010101 13'b0000110010110: data_tmpl = 10'b0101010101 13'b000011001100z: data_tmpl = 10'b0101010101 13'b0000110011010: data_tmpl = 10'b? L? L? L? L? 13'bOOOOllOOllzll: data_tmpl = 10'b? L? L? L? Ll? 13'b000011001110z: data_tmpl = 10'bOlOlOlOllO 13'b0000110011110: data_tmpl = 10'bOlOlOlOllO 13'b000011010000z: data_tmpl = 10'bOlOlOlOllO 13'b0000110100zlz: data_tmpl = 10'b? L? L? L? Lll 13'b000011010010z: data_tmpl = 10'b? L? L? L? Lll 13'b0000110101000: data_tmpl = 10'b? L? L? L? Lll 13'b00001101010zl: data_tmpl = 10'bOlOlOllOOO 13'b0000110101zl0: data_tmpl = 10'bOlOlOllOOO 13'b000011010110z: data_tmpl = 10'bOlOlOllOOO 13'b0000110101111: data_tmpl = 10'bOlOlOllOOO 13'b0000110110000: data_tmpl = 10'bOlOlOllOOO 13'b00001101100zl: data_tmpl = 10'bOlOlOllOOl 13'b0000110110zl0: data_tmpl = 10'bOlOlOllOOl 13'b000011011010z: data_tmpl = 10'bOlOlOllOOl 13'-b0000110110111: data_tmpl = 10'bOlOlOllOOl 13'b0000110111000: data_tmpl = 10'bOlOlOllOOl 13'b00001101110zl: data_tmpl = 10'bOlOlOllOlO 13'b0000110111zl0: data_tmpl = 10'bOlOlOllOlO 13'b000011011110z: data_tmpl = 10'bOlOlOllOlO 13'b0000110111111: data_tmpl = 10'bOlOlOllOlO 13'b0000111000777: data_tmpl = 10'b? l? l? ll? ll 13'b000011100177: data_tmpl = 10 ' bOlOlOlllOO; 13'b0000111010777: data_tmpl = 10'b? L? L? Lll; l; 13'b0000111011000: data_tmpl = 10'b? L? L? Lll; l; 13'b00001110110zl: data_tmpl = 10'b? L? L? Llll? 13'bOOOOlllOllzlO: data_tmpl = 10'bOlOlOllllO 13'bOOOOlllOlllOz: data_tmpl = 10'bOlOlOllllO 13'bOOOOlllOlllll: data_tmpl = 10'bOlOlOllllO 13'b0000111100000: data_tmpl = 10'bOlOlOllllO 13'b00001111000zl: data_tmpl = 10'b? L? L? lllll 13'b0000111100zl0: data_tmpl = 13'b000011110010z: data_tmpl = 13'b0000111100111: data_tmpl = 13, b000011110100z: data_tmpl = 13'b0000111101zlz: data_tmpl = 10'bOlOllOOOOOl 13'b000011110110z: data_tmpl = 10'bOlOllOOOOOl 13'bOOOOlllllOOOz: data_tmpl = 10 'bOlOllOOOOOl 13'b0000111110zlz: data_tmpl = 10'bOlOllOOOOll 13'b000011111010z: data_tmpl = 10'bOlOllOOOOll data_tmpl = 10'bOlOllOOOOll 13'b0000111111010: data_tmpl = 10' bOlOUOOOOll 13'b0000111111zll: data tmpl = 10'bOlOllOOOlOl 13'b000011111110z: data_tmpl = 10'bOlOllOOOlOl 13'b0000111111110: data_tmpl = 10 'b01011000101 13'b00010000000z: data_tmpl = 10'bOlOllOOOlOl I3'b00010000001z: data_tmpl = 10' bOlOUOOOlll 13'b00010000010z: data_tmpl = 10'bOlOllOOOlll 13'b0001000001100: data_tmpl = 10'bOlOllOOOlll 13 ' b0 0010000011zl: data_tmpl = 10'bOlOllOOlOOl 13'b0001000001110: data tmpl = 10'bOlOllOOlOOl 13'b00010000100z: data_tmpl = 10'b01011001001 13'b000100001010z: data_tmpl = 10'bOlOllOOlOOl 13'b0001000010110: data_tmpl = 10'bOlOllOOlOOl 13'b000100001zlll: data_tmpl = 10'bOlOllOOlOll 13'b00010000110zz: data tmpl = 10'bOlOllOOlOll 13'b000100001110z: data_tmpl = 10'bOlOllOOlOll 13'b0001000011110: data_tmpl = 10'bOlOllOOlOll 13'b0001000100zzz: data_tmpl = 10'bOlOllOOllOl 13'b000100010100z: data_tmpl = 10'bOlOllOOllOl 13 'b0001000101zlz: data_tmpl = 10'bOlOllOOllll 13'b000100010110z: data_tmpl = 10'bOlOllOOllll 13'b00010001100zz: data_tmpl = lO'bOlOllOOllll I3'b00010001101z: data_tmpl = 10'bOlOllOlOOOl I3'b000l000lll0z: data_tmpl = 10'bOlOllOlOOOl 13'b000100011110z: data_tmpl = 10'bOlOllOlOOOl 13'bOOOlOOOlllllz: data_tmpl = 10'bOlOllOlOOll 13'b0001001000zz: data_tmpl = 10'bOlOllOlOOll 13'b0001001001zzz: data_tmpl = 10'b? L? Ll? L? L? L 13'b000100101000z: data_tmpl = 10'b? l? ll? l? l 13'b0001001010zlz: data_tmpl = 10'b? l? ll? l? lll 13'b000100101010z: data_tmpl = 10'b? l? ll? l? lll 13'bOOOlOOlOllOz: data_tm.pl = 10'b? l? ll? l? lll 13 'b0001001011100: data_tmpl = 10'b? l? ll? l? lll 13'bOOOlOOlOlllzl: data_tmpl = 10'bOlOllOllOOl 13'bOOOlOOlQllllO: data_tmpl = 10'bOlOllOllOOl 13'b00010011000z: data_tmpl = 10'bOlOllOllOOl 13'b000100110010z: data_tmpl = 10 'bOlOllOllOOl 13'b0001001100110: data_tmpl = 10'bOlOllOllOOl 13'bOOOlOOllOzlll: data_tmpl = 10'b? l? ll? ll? ll 13'b00010011010zz: data_tmpl = 10'b? l? ll? ll? ll 13'b000100110110z: data_tmpl = 10'b? Ll? Ll? Ll? 13'b0001001101110: data_tmpl = 10'b? Ll? Ll? Ll? Ll 13'b000100111000z: data_tmpl = 10'b? L? Ll? Ll? Ll 13'b0001001110zlz: data_tmpl = 10'b? l? ll? lll? l 13'b000100111010z: data_tmpl = 10'b? l? ll? lll? l 13'bOOOlOOllllOz: data_tmpl = 10'b? l? ll? lll? 13'b0001001111100 : data_tmpl = 10'b? l? ll? lll? l 13'b00010011111zl: data_tmpl = 10'b? l? ll? lllll 13'b0001001111110: data_tmpl = 10'b? l? ll? lllll 13'b0001010000zzz: data_tmpl = 10'b? L? Ll? Lllll 13'b0001010001000: data_tmpl = 10'b? L? Ll? Lllll 13'b00010100010zl: data_tmpl = 10'bOlOlllOOOOl 13'b0001010001zl0: data_tmpl = 10'bOlOlllOOOOl 13'b000101000110z: data_tmpl = 10'bOlOlllOOOOl 13'b0001010001111: data_tmpl = 10 'bOlOlllOOOOl 13'b00010100100zz: data_tmpl = 10'bOlOlllOOOOl 13'b000101001zlzz: data_tmpl = 10'bOlOlllOOOll 13'b00010100110zz: data_tmpl = 10'bOlOlllOOOll 13'bOOOlOlOlOOzz: data_tmpl = 10'bOlOlllOOlOl; 13'b00010101010zz: data_tmpl = 10'b? L? Lll? L? 13'b00010101011zz: data_tmpl = 10'bOlOlllOOlll 13'b0001010110zzz: data_tmpl = 10'bOlOlllOOlll 13'b0001010111zz: data_tmpl = 10'bOlOlllOlOOl; 13'b00010110000zz: data_tmpl = 10'bOlOlllOlOOl 13'b000101100zlz: data_tmpl = 10'b? L? Lll? L? Ll 13'b00010110010zz: data_tmpl = 10'b? L? Lll? L? Ll 13'b0001011010000: data_tmpl = 10 'b? l? lll? l? ll 13'b00010110100zl: data_tmpl = 10'b? l? llll? ll? 13'b0001011010zl0: data_tmpl = 10' bOlOlllOUOl 13'b000101101zl0z: data_tmpl = 10'b? l? lll? ll? 13'b00'01011010111: data_tmpl = 10'b? l? lll? ll? l 13'bOOOllOllOzz: data_tmpl = 10'b? l? llll? ll? 13'b000101101111z: data_tmpl = 10 'bOlOlllOllll 13' b0001011100zzz: data_tmpl = 10'b? l? lll? llll 13'b000101110100z: data_tmpl = 10 'bOlOlllOllll 13'b0001011101010: data_tmpl = 10'b? l? lll? llll 13'b0001011101zll: data_tmpl = 10' bOlOllllOOOl 13'b000101110110z: data_tmpl = 10'bOlOllllOOOl 13'b0001011101110: data_tmpl = 10'bOlOllllOOOl 13'b0001011110zzz: data_tmpl = 10 'OlOllllOOOl 13'b0001011111zzz data_tmpl = 10'bOlOllllOOll; 13'b00011000000zz: data_tmpl = 10'bOlOllllOOll 13'bOOOllOOOOOlOO: data_tmpl = 10'bOlOllllOOll 13'b00011000001zl: data_tmpl = 10'b? L? Llll? L? L 13'b000110000zll0: data_tmpl = 10'b? L? Llll? L ? l 13'b00011000010z: data_tmpl = 10'b? l? llll? l? 13'b000110000110z: data_tmpl = 10'b? l? llll? l? 13'b0001100001111: data tmpl = 10'b? l? llll ? l? l 13'b000110001000z: data_tmpl = 10'b? l? llll? l? 13'b0001100010010: data_tmpl = 10'bOlQllllOlOl 13'b0001100010zll: data tmpl = 10'b? l? llll? lll 13'b000110001zl0z: data_tmpl = 10'b? l? llll? lll 13'b000110001zll0: data_tmpl = 10'b? l? llll? lll 13'bOOOllOOOllOz: data_tmpl = 10'b? l? llll? lll 13'b0001100011111: data_tmpl = 10'b ? l? llll? lll 13'b0001100100000: data_tmpl = 10'b? l? llll? lll 13'b00011001000zl: data_tmpl = 10'bOlOlllllOOl 13'b0001100100zl0: data_tmpl = 10 'bOlOlllllOOl 13'b000110010zl0z: data_tmpl = 10'bOlOlllllOOl 13' b0001100100111: data_tmpl = 10'bOlOlllllOOl 13'b00011001010zz: data_tmpl = 10'bOlOlllllOOl 13'b0001100101110: data_tmpl = 10 'bOlOlllllOOl 13'b0001100 101111: data_tmpl = 10'b? L? Lllll? Ll 13'b0001100110zzz: data_tmpl = 10'b? L? Lllll? Ll 13'b00011001110zz: data_tmpl = 10'b? L? Lllll? Ll 13'b000110011110z: data_tmpl = 10 'bOlOlllllOll 13'b000110011111z: data_tmpl = 13'b0001101000zzz: data_tmpl = 13'b00011010010zz: data_tmpl = 13'b0001101001100: data_tmpl = 13'b00011010011zl: data_tmpl = 13'b0001101001110: data_tmpl = 13'b0001101010zzz: data_tmpl = 13'b00011010110zz: data_tmpl = 13'b00011010111zz: data_tmpl = 10'bOllOOOOOOOl 13'b0001101100zzz data_tmpl = 10'bOllOOOOOOOl; 13'b000110110100z: data_tmpl = 10'bOllOOOOOOOl 13'b0001101101010: data_tmpl = 10'bOllOOOOOOOl 13'b0001101101zll: data_tmpl = 10 'bOHOOOOOOll 13'b000110110110z: data_tmpl = 10'bOllOOOOOOll 13'b0001101101110: data_tmpl = 10'bOllOOOOOOll 13'b0001101110zzz data_tmpl = 10'bOllOOOOOOll; 13'b000110111100z: data_tmpl = 10'bOllOOOOOOll 13'b0001101111zlz: data_tmpl = 10'bOllOOOOOlOl 13'b000110111110z: data_tmpl = 10 'bOHOOOOOlOl 13'b0001110000zzz: data_tmpl = 10'bOllOOOOOlOl 13'b000111000100z: data_tmpl = 10' bOHOOOOOlOl 13'b0001110001zlz: data_tmpl = 10'bOllOOOOOlll 13'b000111000110z: data_tmpl = 10'bOllOOOOOlll 13'b0001110010zzz: data_tmpl = 10'bOllOOOOOlll 13'b000111001100z: data_tmpl = 10'bOllOOOOOlll 13'b0001110011zlz: data_tmpl = 10'bOllOOOOlOOl 13'b000111001110z: data_tmpl = 10'bOllOOOOlOOl 13 'b0001110100zz: data_tmpl = 10'bOllOOOOlOOl; 13'b000111010100z: data_tmpl = 10'bOllOOOOlOOl 13'bOOOlllOlOlOlO: data_tmpl = 10'bOllOOOOlOOl 13'bOOOlllOlOlzll: data_tmpl = 10'bOllOOOOlOll 13'bOOOlllOlOllOz: data_tmpl = 10'bOllOOOOlOll 13'b0001110101110: data_tmpl = 10'bOllOOOOlOll 13'b0001110110zzz: data_tmpl = 10'bOllOOOOlOll 13'b000111011100z: data_tmpl = 10'bOllOOOOlOll 13'b0001110111010: data_tmpl = 10'bOllOOOOlOll 13'b0001110111zll: data_tmpl = 10'bOllOOOOllOl 13'b000111011110z: data_tmpl = 10'bOllOOOOllOl 13'b0001110111110: data_tmpl = 10 'bOHOOOOHOl 13 'b0001111000zzz: data_tmpl = 10'bOllOOOOllOl 13'b00011110010z: data_tmpl = 10' bOHOOOOHOl 13'b00011110011zz: data tmpl = 10 'bOllOOOOllll 13'b0001111010zzz: data_tmpl = 10'bOllOOOOllll 13'b00011110110z: data_tmpl = 10' bOllOOOOllll 13'b0001111011100: data_tmpl = 10'bOllOOOOllll 13'b00011110111zl: data_tmpl = 10 'bOHOOOlOOOl 13'b0001111011110: data_tmpl = 10' bOHOOOlOOOl 13'b0001111100zzz: data_tmpl = 10 'bOHOOOlOOOl 13'b00011111010z: data_tmpl = 10' bOHOOOlOOOl 13'b000111110 110z: data_tmpl = 10'bOllOOOlOOOl 13'b0001111101110: data_tmpl = 10 'bOHOOOlOOOl 13'b00011111zllll: data_tmpl = 10'bOllOOOlOOll 13'b0001111110zzz: data_tmpl = 10' bOHOOOlOOll: data_tmpl = 10'bOllOOOlOOll 13'b000111111110z: data_tmpl = 10'bOllOOOlOOll data_tmpl = 10'bOllOOOlOOll 13'b0010000000000: data_tmpl = 10'bOllOOOlOOll 13'b00100000000zl: data_tmpl = 10'bOllOOOlOlOl 13'b0010000000zl0: data_tmpl = 10'bOllOOOlOlOl 13'b001000000zl0z: data_tmpl = 10 'b01100010101 13'b001000000zlll: data_tmpl = 10'bOllOOOlOlOl 13 'b00100000010zz: data_tmpl = 10'bOllOOOlOlOl 13'b0010000001110: data_tmpl = 10'bOllOOOlOlOl 13'b001000001000z: data_tmpl = 10'bOllOOOlOlOl 13'b0010000010010: data_tmpl = 10'bOllOOOlOlOl 13'b0010000010zll: data_tmpl = 10'bOllOOOlOlll 13'b001000001zl0z: data_tmpl = 10'bOllOOOlOlll 13'b001000001zll0: data_tmpl = 10'bOllOOOlOlll 13'b00100000110zz: data_tmpl = 10'bOllOOOlOlll 13'b0010000011111: data_tmpl = 10 'bOHOOOlOlll 13'b00100001000z: data_tmpl = 10'bOllOOOlOlll 13'b0010000 10010z: data_tmpl = 10'bOllOOOlOlll 13'b001000010zllz: data_tmpl = 10'bOllOOOllOOl 13'b00100001010z: data_tmpl = 10'bOllOOOllOOl 13'b001000010110z: data_tmpl = 10'bOllOOOllOOl 13'b0010000110zzz: data_tmpl = 10'bOllOOOllOOl 13'b0010000111zz: data_tmpl = 10 'bOllOOOllOll; 13'b0010001000zzz: data_tmpl = 10'bOllOOOllOll 13'b00100010010zz: data_tmpl = 10'bOllOOOllOll; 13'b00100010011z: data_tmpl = 10'bOllOOOlllOl; 13'b0010001010zz: data_tmpl = 10'bOllOOOlllOl; 13'b00100010110z: data_tmpl = 10'bOllOOOlllOl 13'b001000101110z: data_tmpl = 10 'bOHOOOlllOl 13'b0010001011110: data_tmpl = 10'bOllOOOlllOl 13'b0010001011111: data_tmpl = 10'bOllOOOlllll 13'b001000110zzzz: data_tmpl = 10'bOllOOOlllll 13'b001000111000z: data_tmpl = 10'bOllOOOlllll 13'b0010001110010: data_tmpl = 10'bOllOOOlllll 13'b0010001110zll: data_tmpl = 10 'bOHOOlOOOOl 13'b001000111zl0z: data_tmpl = 10'bOllOOlOOOOl I3'b001000111zll0: data tmpl = 10'bOllOOlOOOOl 13'b00100011110zz: data_tmpl = 10' bOHOOlOOOOl 13'b0010001111111: data tmpl = 10 'bOHOOlOOOOl 13'b00100100000z: data_tmpl = 10'bOllOOlOOOOl 13'b001001000010z: data_tmpl = 10'bOllOOlOOOOl 13'b0010010000110: data_tmpl = 10'bOllOOlOOOOl 13'b001001000zlll: data_tmpl = 10'bOllOOlOOOll 13'b00100100zl0zz: data_tmpl = 10 'bOHOOlOOOll 13'bOOlOOlOOOllOz: data_tmpl = 10'bOllOOlOOOll 13'b0010010001110: data_tmpl = 10' bOHOOlOOOll 13'b0010010010zzz: data_tmpl = 10'bOllOOlOOOll 13'b00100100111zz: data_tmpl = 10'bOllOOlOOlOl 13'b001001010 zzzz: data_tmpl = 10'bOllOOlOOlOl 13'b0010010110000: data_tmpl = 10'bOllOOlOOlOl 13'bOOlOOlOllOOzl: data_tmpl = 10'bOllOOlOOlll 13'b0010010110zl0: data_tmpl = 10'bOllOOlOOlll 13'b001001011zl0z: data_tmpl = 10'bOllOOlOOlll 13'b001001011zlll: data_tmpl = 10 'bOllOOlOOlll 13'b00100101110zz: data_tmpl = 10'bOllOOlOOlll 13'b0010010111110: data_tmpl = 10'bOllOOlOOlll 13'b00100110000zz: data_tmpl = 10'bOllOOlOOlll 13'b001001100010z: data_tmpl = 10'bOllOOlOOlll 13'b001001100zllz: data_tmpl = 10'bOllOOlOlOOl 13'b00100110zl0zz : data_tmpl = 10'bOllOOlOlOOl 13'b001001100110z: data_tmpl = 10'bOllOOlOlOOl 13'b0010011010zzz: data_tmpl = 10'bOllOOlOlOOl 13'b00100110111zz: data_tmpl = 10'bOllOOlOlOll 13'b001001110zzzz: data_tmpl = 10'bOllOOlOlOll 13'b001001111000z: data_tmpl = 10 'bOHOOlOlOll 13'b0010011110zlz: data_tmpl = 10'bOllOOlOllOl 13'bOOlOOllllzlOz: data_tmpl = 10'bOllOOlOllOl 13'b00100111110zz: data_tmpl = 10'bOllOOlOllOl 13'b001001111111z: data_tmpl = 10'bOllOOlOllOl 13'b0010100000zzz: data_tmpl = 10'bOllOOlOllOl 13'b0010100001zzz: data_tmpl = 10'bOllOOlOllll 13 'b0010100010zzz: data_tmpl = 10'bOllOOlOllll 13'b00101000110zz: data_tmpl = 10' bOllOOlOllll 13'b001010001110z: data_tmpl = 10'bOllOOlOllll 13'b0010100011110: data_tmpl = 10'b? ll? l? llll 13'bOOlOlOOOlllll: data_tmpl = 10 ' bOllOOllOOOl 13'b001010010zzzz: data_tmpl = 10'bOllOOllOOOl 13'b00101001100z: data_tmpl = 10'bOllOOllOOOl 13'b001010011010z: data_tmpl = 10'bOllOOllOOOl 13'b001010011zllz: data_tmpl = 10'bOllOOllOOll 13'b00101001110z: data_tmpl = 10'bOllOOllOOll 13'b00101001 1110z: data_tmpl = 10'bOllOOllOOll 13'b0010101000zzz: data_tmpl = 10 'bOHOOllOOll 13'b00101010010zz: data_tmpl = 10'bOllOOllOOll 13'b001010100110z: data_tmpl = 10' bOHOOllOOll 13'b00101010zlllz: data_tmpl = 10'bOllOOllOlOl 13'b0010101010zz: data_tmpl = 10 'bOllOOllOlOl; 13'b00101010110zz: data_tmpl = 10'bOllOOllOlOl 13'b001010101110z: data_tmpl = 10'bOllOOllOlOl 13'b00101011000zz: data_tmpl = 10'bOllOOllOlOl I3'b0010101100l0z: data_tmpl = 10'bOllOOllOlOl 13'b001010110zllz: data_tmpl = 10 'bOllOOHOlll 13'b00101011zl0zz: data_tmpl = 10 'bOllOOHOlll 13'b00101011zll0z: data_tmpl = 10'bOllOOllOlll 13'b0010101110zzz: data_tmpl = 10'bOllOOllOlll 13'b0010101111110: data_tmpl = 10'bOllOOllOlll 13'b0010101111111: data_tmpl = 10'bOllOOlllOOl 13'b001011000Zzzz data_tmpl = 10' bOHOOlllOOl; 13'b0010110010zzz: data_tmpl = 10 'bOHOOlllOOl; 13'b0010110011zzz data_tmpl = 10'bOllOOlllOll; 13'b001011010zzz: data_tmpl = 10'bOllOOlllOll; 13'b0010110110000: data_tmpl = 10'bOllOOlllOll 13'b00101101100zl: data_tmpl = 10'bOllOOllllOl 13'b0010110110zl0: data_tmpl = 10'bOllOOllllOl 13'b001011011zl0z: data_tmpl = 10'bOllOOllllOl 13'b001011011zlll: data_tmpl = 10'bOllOOllllOl 13'b00101101110zz: data_tmpl = 10'bOllOOllllOl 13'bOOlOllOlllllO: data_tmpl = 10 'bOllOOllllOl 13'b0010111000zzz: data_tmpl = 10'bOllOOllllOl 13'b001011100100z: data_tmpl = lO'bOllOOllllOl 13'bOOlOlllOOlOlO: data_tmpl = 10'bOllOOllllOl 13'b0010111001zll: data_tmpl = 13'b00101110zll0z: data_tmpl = 13'b00101110zlll0: data_tmpl = 13'b0010111010zzz: data_tmpl = 13'b00101110110z: data_tmpl = 10 13'b0010111011111: data_tmpl = 13'b00101111000zz: data_tmpl = 13'b0010111100100: data_tmpl = 13'b00101111001zl: data_tmpl = 10'bOllOlOOOOOl 13 ' b001011110zll0: data_tmpl = 10 'bOHOlOOOOOl I3'b00101111zl0zz: data_tmpl = 10'bOllOlOOOOOl 13'b00101111zll0z: data_tmpl = 10'bOllOlOOOOOl 13'b00101111zllll: data_tmpl = 10'bOllOlOOOOOl 13'bOOlOlllllOzz: data_tmpl = 10'bOllOlOOOO Ol; 13 b0010111111110: data_tmpl = 10'bOllOlOOOOOl 13'b001100000zzzz: data_tmpl = 10'bOllOlOOOOll 13'bOOllOOOOlOzzz: data_tmpl = 10'bOllOlOOOOll I3'b00110000110zz: data_tmpl = 10'bOllOlOOOOll 13'b00110000111zz: data_tmpl = 10 'bOHOlOOOlOl 13'b001100010zzzz: data_tmpl = 10 'b01101000101 13'b00110001100zz: data_tmpl = 10'bOllOlOOOlOl 13'b001100011010z: data_tmpl = 10'bOllOlOOOlOl 13'b0011000110110: data_tmpl = 10'bOllOlOOOlOl 13'b001100011zlll: data_tmpl = 10'bOllOlOOOlll 13'b00110001110zz: data_tmpl = 10'bOllOlOOOlll 13' b001100011110z: data_tmpl = 10 'bOHOlOOOlll 13'b0011001011010: data_tmpl = 10'bOllOlOOOlll 13'b001100100zzzz: data_tmpl = 10'bOllOlOOOlll 13'b00110010100zz: data_tmpl = 10' bOHOlOOOlll 13'b001100101zlz: data_tmpl = 10'bOllOlOOlOOl 13'b00110010110zz: data_tmpl = 10 'bOllOlOOlOOl 13'b00110110zzz: data_tmpl = 10' b01101001001; 13'b001100111zzzz: data_tmpl = 10'bOllOlOOlOll; 13'b0011010000z: data_tmpl = 10'bOllOlOOlOll; 13'b00110100010zz: data_tmpl = 10'bOllOlOOlOll 13'bOOllOlOOOllOz: data_tmpl = 10'bOllOlOOlOll 13'b00110100zlllz: data_tmpl = 10'bOllOlOOllOl 13'b0011010010zz: data_tmpl = 10'bOllOlOOllOl; 13'b00110100110z: data_tmpl = 10'bOllOlOOllOl 13'b001101001110z: data_tmpl = 10'bOllOlOOllOl 13'b0011010100zzz: data_tmpl = 10'bOllOlOOllOl 13'b001101010100z: data_tmpl = 10 'bOHOlOOHOl 13'b0011010101010: data_tmpl = 10' bOHOlOOHOl 13'b0011010101zll: data_tmpl = 10'bOllOlOOllll 13'b00110101zll0z: data_tmpl = 10'bOllOlOOllll 13'b00110101zlll0: data_tmpl = 10'bOllOlOOllll 13'b0011010110zzz: data_tmpl = 10'bOllOlOOllll 13'b00110101110zz: data_tmpl = 10'bOllOlOOllll data_tmpl = 10 'bOllOlOOllll 13'b0011011000zzz: data_tmpl = 10'bOllOlOOllll 13'b001101100100z: data_tmpl = 10'bOllOlOOllll 13'b0011011001zlz: data_tmpl = 10'bOllOlOlOOOl 13'b00110110zll0z: data_tmpl = 10'bOllOlOlOOOl 13'b0011011010zzz: data_tmpl = 10'bOllOlOlOOOl 13'b00110110110zz: data_tmpl = 10'bOllOlOlOOOl 13 'b001101101111z: data_tmpl = 10'bOllOlOlOOOl 13'b0011011100zzz: data_tmpl = 10' bOHOlOlOOOl 13'b0011011101000: data_tmpl = 10'bOllOlOlOOOl 13'b00110111010zl: data_tmpl = 10'bOllOlOlOOll 13'b0011011101zl0: data_tmpl = 1 0'bOllOlOlOOll 13'b00110111zll0z: data_tmpl = 10'bOllOlOlOOll 13'b00110111zllll: data_tmpl = 10'bOllOlOlOOll 13'b0011011110zzz: data_tmpl = 10'bOllOlOlOOll 13'b00110111110zz: data_tmpl = 10'bOllOlOlOOll; 13'b0011011111110: data_tmpl = 10'bOllOlOlOOll; l'3'b0011100000zZz data_tmpl = 10'bOllOlOlOOll 13'b00111000zlzzz data_tmpl = 10'b? Ll? L? L? L 13'b0011100010zzz data_tmpl = 10'b? Ll? L? L? L 13'b0011100100zzz data_tmpl = 10'b? Ll? L? L? L 13'b00111001zlzzz: data_tmpl = 10'b? Ll? L? L? Lll; 13'b0011100110zzz: data_tmpl = 10'b? Ll? L? L? Lll; 13'b0011101000zz: data_tmpl = 10'b? Ll? L? L? Lll; 13'b00111010zlzzz: data_tmpl = 10'bOllOlOllOOl; 13'b0011101010zz: data_tmpl = 10'bOllOlOllOOl; 13'b0011101100zzz data_tmpl = 10'bOllOlOllOOl; 13'b0011101101000: data_tmpl = 10'bOllOlOllOOl; 13'b00111011010l: data_tmpl = 10'b? Ll? Ll? Ll? Ll; 13'b0011101101zl0: data_tmpl = 10'b0110101101-l; 13'b00111011zll0z: data_tmpl = 10'b? Ll? Ll? Ll? Ll; 13'b00111011zllll: data_tmpl = 10'b? Ll? Ll? Ll? Ll; 13'b0011101110 zz data_tmpl = 10'b? Ll? Ll? Ll? Ll; 13'b00111011110zz: data_tmpl = 10'b? Ll? Ll? Ll? Ll; data_tmpl = 10'b? ll? ll? ll? ll; 13'b0011110000 zz data_tmpl = 10'b? Ll? Ll? Ll? Ll; 13'bOOllllQOOlOOz: data_tmpl = 10'b? Ll? Ll? Ll? Ll 13'b0011110001010: data_tm? L = 10'b? Ll? Ll? Ll? Ll 13'b0011110001zll: data_tmpl = 10'b? Ll? L? Lll? 13'b00111100zll0z: data_tmpl = 10'b? Ll? L? Lll? L 13'bOOllllOOzlllO: data_tmpl = 10'b? Ll? L? Lll? l 13'b0011110010zzz: data_tmpl = 10'b? ll? l? lll? l 13'bOOllllOOllOzz: data_tmpl = 10'b? ll? l? lll? 13'b0011110011111: data_tmpl = 10'b? ll? l? lll ? l 13'b0011110100zzz: data_tmpl = 10'b? ll? l? lll? 13'b00111101010z: data_tmpl = 10'b? ll? l? lll? 13'b0011110101100: data_tmpl = 10'b? ll? l? lll? l 13'b00111101011zl: data_tmpl = 10'b? ll? l? lllll 13'b00111101zlll0: data_tmpl = 10'b? ll? l? lllll 13'b0011110110zzz: data tmpl = 10'b? ll? l? lllll 13 'b00111101110zz: data tmpl = 10'b? ll? l? lllll 13'b001111011110z: data_tmpl = 10'b? ll? l? lllll 13'b0011110111111: data_tmpl = 10'b? ll? l? lllll 13'b001111100zzzz: data_tmpl = 10'b? Ll? L? Lllll 13'b001111101zzzz: data_tmpl = 10'bOllOllOOOOl 13'b001111110zzzz: data_tmpl = 10 'bOHOHOOOOl 13'b00111111100zz: data_tmpl = 10'bOllOllOOOOl 13'b001111111zlzz: data_tmpl = 10'bOllOllOOOll 13'b00111111110z: data_tmpl = 10'bOllOllOOOll 13'b010000000z zzz: data_tmpl = 10'bOllOllOOOll 13'b0100000010zzz: data_tmpl = 10'bOllOllOOOll 13'b0100000011zzz: data_tmpl = 10'bOllOllOOlOl 13'bOlOOOOOlOzzzz data_tmpl = 10'bOllOllOOlOl; 13'b0100000110zzz: data_tmpl = 10'bOllOllOOlOl; 13'b01000001110zz: data_tmpl = 10'bOllOllOOlOl; 13'b0100000111100: data_tmpl = 10'bOllOllOOlOl 13'b01000001111zl: data_tmpl = 10'bOllOllOOlll 13'b0100000111110: data_tmpl = 10'bOllOllOOlll 13'b01000010zzzZZ data_tmpl = 10'bOllOllOOlll; 13'b010000110000z: data_tmpl = lO'bOllOUOOlll 13'b0100001100zlz: data_tmpl = 10'bOllOllOlOOl 13'b010000110zl0z: data_tmpl = 10'bOllOllOlOOl 13'b01000011zl0zz: data_tmpl = 10'bOllOllOlOOl 13'b01000011zlllz: data_tmpl = 10 'bOHOHOlOOl 13'bOlOOOOlllOzzz: data_tmpl = 10'bOllOllOlOOl 13'b010000111110z: data_tmpl = 10'bOllOllOlOOl 13'b0100010000zzz: data_tmpl = 10'bOllOllOlOOl 13'b01000100zlzz: data_tmpl = 10 'bOHOllOlOll; 13'b0100010010zzz: data_tmpl = 10'b? Ll? Ll? Ll? Ll 13'b0100010100zzz: data_tmpl = 10'b? Ll? Ll? Ll? Ll 13'b01000101010zz: data_tmpl = 10'b? Ll? Ll? L? ll 13'b010001010110z: data_tmpl = 10'b? ll? ll? ll? ll 13'b0100010101110: data_tmpl = 10 'bOHOllOlOll 13'b01000101zllll: data_tmpl = 10' bOllOUOHOl 13'b0100010110zzz: data_tmpl = 10'b? ll? ll? ll? 13'b01000101110zz: data_tmpl = 10'b? ll? ll? ll? 13'b010001011110z: data_tmpl = 10 'bOllOUOHOl 13'b0100010111110: data_tmpl = 10'b? ll? ll? ll? 13'b010001100zzzz: data_tmpl = 10'b? ll? ll? ll? 13'b01000110100z: data_tmpl = 10'b? ll? ll? ll? 13'b010001101010z: data_tmpl = 10'b? ll? ll? ll? 13'bOlOOOllOlOllO : data_tmpl = 10'b? ll? ll? ll? 13'bOlOOOllOlzlll: data_tmpl = 10'b? ll? ll? llll 13'b0100011zll0zz: data_tmpl = 10'b? ll? ll? llll 13'b0100011zlll0z: data_tmpl = 10'b? Ll? Ll? Llll 13'b0100011zllll0: data_tmpl = 10'b? Ll? Ll? Llll 13'b010001110zzzz: data_tmpl = 10'b? Ll? Ll? Llll 13'b0100011110zz: data_tmpl = 10'b? Ll ? ll? llll; 13'b0100011111111: data_tmpl = 10'bOllOlllOOOl 13'b01001000zzzzz: data_tmpl = 10'bOllOlllOOOl 13'b0100100100zzz: data_tmpl = lO'bOHOlllOOOl 13'b01001001zlzzz: data_tmpl = 10'bOllOlllOOll 13'b0100100110zzz: data_tmpl = 10'bOllOlllOOll 13'b010010100zzzz: data_tmpl = 10'bOllOlllOOll 13'b0100101010000: data_tmpl = 10'bOllOlllOOll 13'b01001010100zl: data_tmpl = 10'b? Ll? Lll? L? L 13'b0lOlOlOzlO: data_tmpl = 10'b? Ll? Lll? L? L 13'b010010101zl0z : data_tmpl = 10'b? ll? lll? l? l 13'b010010101zlll: data_tmpl = 10'b? ll? lll? l? l 13'bOlOOlOlzllOz: data_tmpl = 10'b? ll? lll? l? l 13 ' b0100101011110: data_tmpl = 10 'bOHOlllOlOl 13'b010010110Zzzz: data_tmpl = 10'b? ll? lll? l? l 13'b0100101110zzz: data_tmpl = 10' bOHOlllOlOl 13'b01001011111zz: data_tmpl = 10'b? ll? lll? lll 13'b01001100zzzzz: data_tmpl = 10 'bOllOlllOlll 13'bOlOOllOlOOOzz: data_tmpl = 10'b? ll? lll? lll 13'b010011010010z: data_tmpl = 10'b? ll? lll? lll 13'b0100110100110: data_tmpl = 10'b? Ll? Lll? Lll 13'b010011010zlll: data_tmpl = lO'bOllOllllOOl 13'bOlOOllOlzlOzz: data_tmpl = 10'bOllOllllOOl 13'bOlOOllOlzllOz: data_tmpl = 10'bOllOllllOOl 13'b01001101zlll0: data_tmpl = 10 ' bOllOllllOOl 13'b0100110110zzz: data_tmpl = 10'bOllOllllOOl 13'b0100110111111: data_tmpl = 10'bOllOllllOOl 13'b010011100zzzz: data_tmpl = 10 'bOllOllllOOl 13'b010011101000z: data_tmpl = 10' bOllOllllOOl 13'b0100111010010: data_tmpl = 10'bOllOllllOOl 13'b0100111010zll: data_tmpl = 10'b? ll? llll? ll 13'b010011101zl0z: data_tmpl = 10'b? ll? llll? ll 13'b010011101zll0: data_tmpl = 10 'bOllOllllOll 13'b0100111zll0zz: data_tmpl = 10'b? ll? llll? ll 13'b0100111011111: data_tmpl = 10'b? Ll? Llll? Ll 13'b010011110zzzz: data_tmpl = 10'b? Ll? Llll? Ll 13'b0100111110zzz: data_tmpl = 10'b? Ll? Llll? Ll 13'b010011111110z: data_tmpl = 10'b? Ll? Llll? Ll 13'b0100111111110: data_tmpl = 10'b? Ll? Llll? Ll 13'b0100111111111: data_tmpl = 10'b? Ll? Lllll? L 13'b01010000zzzzz: data_tmpl = 10'b? ll? lllllll 13'b0101000100zzz: data_tmpl = 10'b? ll? lllll? l 13'b01010001010zz: data_tmpl = 10'b? ll? lllll? l 13'b0101000101100: data_tmpl = 10'b? ll? lllll? l 13'b01010001011zl: data tmpl = 13'b01010001zlll0: data_tmpl = 13'b0101000110zzz: data_tmpl = 13'b01010001110z: data_tmpl = 13'b010100011110z: data_tmpl = 13'b0101000111111: data_tmpl = 13'b010100100zzzz: data_tmpl = 13'b0101001010zzz: data_tmpl = 13 'b010100101100z: data_tmpl = 13'b0101001011010: data_tmpl = 13'b0101001011zll: data_tmpl = 10'bOlllOOOOOOl 13'b0101001zlll0z: data_tmpl = 10'bOlllOOOOOOl 13'b0101001zllll0: data_tmpl = 10' bOlllOOOOOOl 13'b010100110 zzz: data_tmpl = 10 'bOlllOOOOOOl 13' b0101001110zzz: data_tmpl = 10'bOlllOOOOOOl 13'b01010011110z: data_tmpl = 10'bOlllOOOOOOl 13'b0101001111111: data_tmpl = 10 'bOlllOOOOOOl 13'b0101010000zz_: data_tmpl = 10'bOlllOOOOOOl 13'b01010 1000100_: data_tmpl = 10 'bOlllOOOOOOl 13'b0101010001zlz: data_tmpl = 10'bOlllOOOOOll 13'b01010100zll0z: data_tmpl = 10'bOlllOOOOOll 13'b0101010zl0zz: data_tmpl = 10'b? Ll 1000001 1; 13'b01010100110z: data_tmpl = 10'bOlllOOOOOll 13'b010101001111z: data tmpl = 10 'bOlllOOOOOll 13'b? L? L? L? L? Zzz: data_tmpl = 10'bOlllOOOOOll; 13'bOlOlOlOlllOOz: data_tmpl = 10'bOlllOOOOOll 13'b0101010111zlz: data_tmpl = 10'bOlllOOOOlOl 13'b010101011110z: data_tmpl = 10'bOlllOOOOlOl 13'b01010110zzzz_: data_tmpl = 10'bOlllOOOOlOl 13'b0101011100zzz: data_tmpl = 10'bOlllOOOOlOl 13'b010101110100z: data_tmpl = 10 'bOlllOOOOlOl 13'b0101011101010: data_tmpl = 10'b? Ll 10000101; 13'b0101011101zll: data_tmpl = 10'bOlllOOOOlll 13'b01010111zll0z: data_tmpl = 10'bOlllOOOOlll 13'b01010111zlll0: data_tmpl = 10'bOlllOOOOlll 13'b0101011110zz: data_tmpl = lQ'bOlllOOOOlll 13'b01010111110z: data_tmpl = 10'bOlllOOOOlll 13'b0101011111111: data tmpl = 10'bOlllOOOOlll 13'b010110000zzzz: data_tmpl = 10'bOlllOOOOlll 13'b0101100010_z_: data_tmpl = 10'bOlllOOOOlll 13'b01011000110z: data_tmpl = 10'bOlllOOOOlll 13'b0101100zlllz: data_tmpl = 10'bOlllOOOlOOl 13'b010110010zz data_tmpl = 10'bOlllOOOlOOl; 13'b0101100110zz: data_tmpl = 10 'bOlllOOOlOOl; 13'b01011001110z: data_tmpl = 10'bOlllOOOlOOl; 13'b010110100zzz: data_tmpl = 10'bOlllOOOlOOl; 13'b01011010010z: data_tmpl = 10'bOlllOOOlOOl 13'b010110100110z: data_tmpl = 10 'bOlllOOOlOOl 13'b0101101001110: data_tmpl = 10'bOlllOOOlOOl 13'b01011010zllll: tmpl = 10'bOlllOOOlOll 13'b0101101zl0zzz data: data tmpl = 10'bOlllOOOlOll 13'b0101101zll0z : data tmpl = 10'bOlllOOOlOll 13'b0101101zlll0z: data_tmpl = 10 'bOlllOOOlOll 13'b0101101zllll0: data_tmpl = 10'bOlllOOOlOll 13'b010110110zzzz: data_tmpl = 10' bOlllOOOlOll data_tmpl = 10'bOlllOOOlOll 13'b010111000000z: data_tmpl = 10'bOlllOOOlOl; 13'b0101110000zlz: data_tmpl = 10'bOlllOOOllOl 13'b010111000zl0z: data_tmpl = 10'bOlllOOOllOl 13'b01011100zl0zz: data_tmpl = 10'bOlllOOOllOl 13'b01011100zlllz: data_tmpl = 10'bOlllOOOllOl 13'b0101110010zzz: data_tmpl = 10'bOlllOOOllOl 13'b010111001110z: data_tmpl = 10'bOlllOOOllOl 13'b010111010zzzz: data_tmpl = 10'bOlllOOOllOl 13'b01011101100z: data_tmpl = 10'bOlllOOOllOl 13'b010111011010z: data_tmpl = 10'bOlllOOOllOl 13'b0101110110110: data_tmpl = 10'bOlllOOOllOl 13'b? L? Lll? Llzlll: data_tmpl = 10'bOlllOOOllll 13'b01011101110zz: data tmpl = 10'bOlllOOOllll 13'b010111011110z: data_tmpl = 10'bOlllOOOllll 13'b0101110111110: data_tmpl = 10'bOlllOOOllll 13'b01011110zzzz: data_tmpl = lO'bOlllOOOllll; 13'b0101111100zzz data_tmpl = lO'bOlllOOOllll; 13'b01011111010z: data_tmpl = lO'bOlllOOOllll; 13'b01011111zllz: data_tmpl = 10'bOlllOOlOOOl data_tmpl = 10'bOlllOOlOOOl 13'b01011111110z: data_tmpl = 10'bOlllOOlOOOl 13'b01100000zzzzz data_tmpl = 10'bOlllOOlOOOl; 13'b011000010000z: data_tmpl = 10'bOlllOOlOOOl 13'b0110000100zlz: data_tmpl = 10'bOlllOOlOOll 13'b011000010zl0z: data_tmpl = 10'bOlllOOlOOll 13'b01100001zl0zz: data_tmpl = lO'bOlllOOlOOll 13'b01100001zlllz: data_tmpl data tmpl = lO'bOlllOOlOOll 13'b0110000110zzz = 10'bOlllOOlOOll; 13'b011000011110z: data_tmpl = lO'bOlllOOlOOll; 13'b011000100zzzz: data_tmpl - lO'bOlllOOlOOll; 13'b0110001010zz: data_tmpl = 10'bOlllOOlOOll; 13'b0110001011000: data_tmpl = 10'bOlllOOlOOll 13'b01100010110zl: data_tmpl = 10 'b011Í0010101 13'b0110001011zl0: data_tmpl = 10'bOlllOOlOlOl 13'b0110001zlll0z: data_tmpl = 10'bOlllOOlOlOl 13'b0110001zlllll: data_tmpl = 10'bOlllOOlOlOl 13'b011000110zzzz: data_tm .pl = 10'bOlllOOlOlOl 13'b0110001110zzz: data_tmpl = 10'bOlllOOlOlOl 13'b01100011110zz: data_tmpl = 10'bOlllOOlOlOl 13'b0110001111110: data_tmpl = 10'bOlllOOlOlOl 13'b011001000zzzz: data_tmpl = 10'bOlllOOlOlOl 13'b0110010010000: data_tmpl = 10 ' bOlllOOlOlOl 13'b01100100100zl: data_tmpl = 10 'bOlllOOlOlll 13'b0110010010zl0: data_tmpl = 10'bOlllOOlOlll 13'b011001001zl0z: data_tmpl = 10'bOlllOOlOlll 13'b011001001zlll: data_tmpl = lO'bOlllOOlOlll 13'b0110010zll0z: data tmpl = 10'bOlllOOlOlll 13'b0110010zllll0 : data_tmpl = lO'bOlllOOlOlll 13'b011001010zzzz: data_tmpl = 10'bOlllOOlOlll 13'b0110010110zzz: data_tmpl = 10'bOlllOOlOlll 13'b011001011110z: data_tmpl = 10'bOlllOOlOlll 13'b0110010111111: data_tmpl = lO'bOlllOOlOlll 13'b01100 11000zzz: data_tmpl = 10'bOlllOOlOlll 13'b011001100100z: data_tmpl = 10'bOlllOOlOlll 13'b0110011001010: data_tmpl = 10'bOlllOOlOlll 13'b0110011001zll: data_tmpl = 10'bOlllOOllOOl 13'b01100110zll0z: data_tmpl = 10'bOlllOOllOOl 13'b01100110zlll0: data_tmpl = 10 'bOlllOOllOOl 13'b0110011zl0z: data_tmpl = 10'bOlllOOllOOl; 13'b0110011zll0z: data_tmpl = 10'bOlllOOllOOl 13'b0110011zlllll: data_tmpl = 10'bOlllOOllOOl 13'b011001110zzzz: data_tmpl = 10'bOlllOOllOOl 13'b011001111110z: data_tmpl = 10'bOlllOOllOOl 13'b0110011111110: data_tmpl = 10'bOlllOOllOOl 13'b01101000000zz: data_tmpl = 10 'bOlllOOHOOl 13'b0110100000100: data_tmpl = 10'bOlllOOllOOl 13'b01101000001zl: data_tmpl = 10'bOlllOOllOll 13'b011010000zll0: data_tmpl = 10' bOlllOOHOll 13'b01101000zl0zz: data_tmpl = 10'bOlllOOllOll 13'b01101000zll0z: data_tmpl = 10'bOlllOOllOll 13 'b?' llOlOOOzllll: data_tmpl = 10'bOlllOOllOll 13'b0110100zl0zzz: data_tmpl = 10'bOlllOOllOll 13'bOllOlOOzllllO: data_tmpl = 10'bOlllOOllOll 13'b011010010zzzz: data_tmpl = 10'bOlllOOllOll 13'bOllOlOOlllOzz: data_tmpl = 10 'bOlllOOHOll 13'bOllOlOOllllOz : data_tmpl = 10'bOlllOOllOll 13'b0110100111111: data_tmpl = 10'bOlllOOllOll 13'b01101010zzzzz: data_tmpl = 10'bOlllOOlllOl 13'b011010110zzzz: data_tmpl = 10'bOlllOOlllOl 13'b0110101110zzz: data_tmpl = 10'bOlllOOlllOl 13'b01101011 110z: data_tmpl = 10'bOlllOOlllOl 13'b01101011111z: data_tmpl = 10'bOlllOOlllll 13'b01101100zzzz: data_tmpl = 10 'bOlllOOlllll; 13'b011011010zzzz: data_tmpl = 10'bOlllOOlllll 13'b0110110110zzz: data_tmpl = 10 'bOlllOOlllll 13'b0110110111000: data_tmpl = 10'bOlllOOlllll 13'b01101101110zl: data_tmpl = 10'bOlllOlOOOOl 13'b0110110111zl0: data_tmpl = 10'bOlllOlOOOOl 13'b011011011110z: data_tmpl = 10'bOlllOlOOOOl 13'b0110110111111: data_tmpl = 10'bOlllOlOOOOl 13'b01101110zzzzz: data_tmpl = 10'bOlllOlOOOOl 13'b011011110zzzz: data_tmpl = 10'bOlllOlOOOOl 13'b0110111110zzz: data_tmpl = 10'bOlllOlOOOOl 13'b0110111111zzz: data_tmpl = 10'bOlllOlOOOll 13'b01110000zzzzz: data_tmpl = 10'bOlllOlOOOll 13'b011100010zzzz: data_tmpl = 10'bOlllOlOOOll 13'b01110001100zz: data_tmpl = 10'bOlllOlOOOll 13'b011100011010z: data_tmpl = 10'bOlllOlOOOll 13'b0111000110110: data_tmpl = 10, b01110100011 13'b011100011zlll: data_tmpl = 10'bOlllOlOOlOl 13'b01110001110z: data_tmpl = 10 'bOlllOlOOlOl 13'b011100011110z: data_tmpl = 10'bOlllOlOOlOl 13'b0111000111110: data_tmpl = 10 'bOlllOlOOlOl 13'b01110010zzzzz: data_tmpl = 10'bOlllOlOOlOl 13'b011100110zzzz: data_tmpl = 10'bOlllOlOOlOl 13'b0111001110zzz: data_tmpl = 10'bOlllOlOOlOl 13'b0111001111zzz: data_tmpl = 10'bOlllOlOOlll 13'b01110100zzzzz: data_tmpl = 10'bOlllOlOOlll 13'b011101010zzzz: data_tmpl = 10'bOlllOlOOlll 13'b0111010110zzz: data_tmpl = 10'bOlllOlOOlll 13'b01ll0l011100z: data_tmpl = 10'bOlllOlOOlll 13'b0111010111zlz: data_tmpl = 10'bOlllOlOlOOl 13'b011101011110z: data_tmpl = 10'bOlllOlOlOOl 13'b01110110zzzzz: data_tmpl = 10'bOlllOlOlOOl 13'b011101110zzzz: data_tmpl = 10'bOlllOlOlOOl 13'b0111011110zz: data_tmpl = 10'bOlllOlOlOOl; 13'b01110111110zz: data_tmpl = 10'bOlllOlOlOOl; 13'b0111011111100: data_tmpl = 10'bOlllOlOlOOl; 13'b01110111111zl: data_tmpl = 10'b? Lll? L? L? Ll 13'b0111011111110: data_tmpl = 10'b? Lll? L? L? Ll 13'b0111100Zzzzzz: data_tmpl = 10'b? Lll? L? L? ll 13'b0111101000000: data_tmpl = 10'b? lll? l? l? ll 13'b01111010000zl: data_tmpl = 10'b? lll? l? ll? 13'b0111101000zl0: data_tmpl = 10'b? lll? l? ll ? l 13'b011110100zl0z: data_tmpl = 10'b? lll? l? ll? l 13'b011110100zlll: data_tmpl = 10'b? lll? l? ll? 13'b01111010zl0zz: data_tmpl = 10'b? lll? l? ll? 13'b01111010zlll0: data_tmpl = 10'b? lll? l? ll? 13'b0111101zl0zzz: data_tmpl = 10'b? lll? l? ll? l 13'b? llll? lzlll? z: data_tmpl = 10 'b? lll? ll? l 13'b0111101zlllll: data_tmpl = 10'b? lll? l? ll? l 13'b011110110zzzz: data_tmpl = 10'b? lll? l? ll? l 13'b01111011110zz: data_tmpl = 10'b? Lll? L? Ll 13'b0111101111110: data_tmpl = 10'b? Lll? L? Ll? 13'b01111100000zz: data_tmpl = 10'b? Lll? L? Ll? 13'b011111000010z: data_tmpl = 10 'bOlllOlOUOl 13'b011111000zllz: data_tmpl = lO'bOlllOlOllll 13'b01111100zl0zz: data_tmpl = 10'b? Lll? L? Llll 13'b0lllll00zll0z: data_tmpl = 10'b? Lll? L? Llll 13'b? Lllll? Zl ? zzz: data_tmpl = 10 'bOlllOlOllll 13'b0111110zllllz: data_tmpl = 10'b? lll? l? llll 13'b011111010zzzz: data_tmpl = 10'b? lll? l? llll 13'b? lllll? lll? zz: data_tmpl = 10'b? Lll? L? Llll 13'b? Lllll? Llll? Z: data_tmpl = lO'bOlllOlOllll 13'b0111111000zzz: data_tmpl = 10'b? Lll? L? Llll 13'b01111110010z: data_tmpl = 10'b? Lll ? l? llll 13'b111111001100: data_tmpl = 10'b? lll? l? llll 13'b01111110011zl: data_tmpl = 10'bOlllOllOOOl 13'b01111110zlll0: data_tmpl = 10 'bOlllOUOOOl 13'b0111111zl0zzz data_tmpl = 10'bOlllOllOOOl; 13'b0111111zll0z: data_tmpl = 10'bOlllOllOOOl 13'b0111111zlll0z: data_tmpl = 10'bOlllOllOOOl data_tmpl = 10'bOlllOllOOOl 13'b011111110zzz: data_tmpl = 10'bOlllOllOOOl; 13'b0111111111110: data_tmpl = 10'bOlllOllOOOl 13'bl00000000zzzz: data_tmpl = 10'bOlllOllOOOl I3'bl0000000100z: data_tmpl = 10 'bOlllOUOOOl 13'bl00000001zlzz: data_tmpl = 10' bOlllOUOOll 13'bl000000zll0z: data_tmpl = 10'bOlllOllOOll 13'bl00000010zzzz: data_tmpl = 10 'bOlllOUOOll 13'bl000000110zz: data_tmpl = 10'bOlllOllOOll 13'bl0000001111z: data_tmpl = 10'bOlllOllOOll 13'blOOOOOlOOZzzz: data_tmpl = 10'bOlllOllOOll 13'bl000001010zz: data_tmpl = 10' bOlllOUOOll 13'bl0000010110z: data_tmpl = 10'bOlllOllOOll 13 'bl00000101110z: data_tmpl = 10'bOlllOllOOll 13'bl000001zllllz: data_tmpl = 10'b? lll? ll? l? l 13'bl00000110zzzz: data_tmpl = 10'b? lll? ll? l? 13'bl000001110zz: data_tmpl = 10' b? lll? ll? l? l; 13'bl0000011110z: data_tmpl = 10'b? Lll? Ll? L? 13'bl00000111110z: data_tmpl = 10'b? Lll? Ll? L 13'bl0000100zzzzz: data_tmpl = 10'b? Lll? Ll? L? l 13'bl000010100zzz: data_tmpl = 10'b? lll? ll? l? l 13'bl0000101zlzzz: data_tmpl = 10 'bOlllOUOlll 13'bl000010110zzz: data_tmpl = 10'b? lll? ll? lll 13'bl0000110zzzzz: data_tmpl = 10' b? lll? ll? lll 13'bl00001110zzzz. data_tmpl = 10'b? lll? ll? lll 13'bl0000111100zz: data_tmpl = 10'b? lll? ll? lll 13'bl00001111zlzz: data_tmpl = 10'bOlllOlllOOl 13'bl0000111110zz: data_tmpl = 10'bOlllOlllOOl 13'bl000100zzzzzz: data_tmpl = lO'bOlllOlllOOl 13'bl000101000000: data_tmpl = 10 'bOlllOlllOOl 13'bl0001010000zl: data_tmpl = lO'bOlllOlllOll 13'bl000101000zl0: data_tmpl = 10'b? lll? lll? ll 13'bl00010100zl0z: data_tmpl = 10'b? lll? lll? ll 13'bl00010100zlll: data_tmpl = 10'b? lll? lll? ll 13'bl0001010zl0zz: data_tmpl = 10'b? lll? lll? ll 13'bl0001010zlll0: data_tmpl = 10'b? lll? lll? ll 13'bl000101zl0zzz: data_tmpl = 10'b? Lll? Lll? Ll 13'bl000101zlll0z: data_tmpl = 10'b? Lll? Lll? Ll 13'bl000101zlllll: data_tmpl = 10'b? Lll? Lll? Ll 13'bl00010110zzzz: data_tmpl = 10'b? Lll? Lll? Ll 13'bl0001011110z: data_tmpl = 10'b? Lll? Lll? Ll 13'bl000101111110: data_tmpl = 10'b? Lll? Lll? Ll 13'bl000110000zz: data_tmpl = 10 'bOlllOlllOll 13 'bl0001100010z: data_tmpl = 10'b? lll? lll? ll 13'bl00011000110z: data_tmpl = 10'b? lll? lll? ll 13'bl000110001110: data_tmpl = 10'b? lll? lll? ll 13'bl0001100zllll: data tmpl = 10'b? Lll? Llll? L 13'bl000110zl0zz: data_tmpl = 10'b? Lll? Llll? L 13'bl000110zll0zz: data_tmpl = 10'b? Lll? Llll? L 13'bl000110zlll0z: data_tmpl = 10'b? lll? llll? l 13'bl000110zllll0: data tmpl = 10'b? lll? llll? l 13'bl00011010zzzz: data_tmpl = 10'b? lll? llll? l 13'bl000110111111: data_tmpl = 10'b? lll? llll? l 13'bl00011100zzz: data_tmpl = 10'b? lll? llll? l 13'bl000111010zz: data tmpl = 10'b? lll? llll? l; 13'bl0001110110z: data_tmpl = 10'b? Lll? Llll? L 13'bl00011101110z: data_tmpl = 10'b? Lll? Llll? L 13'bl000111011110: data_tmpl = 10'b? Lll? Llll? L 13'bl000111zlllll: data_tmpl = 13'bl00011110z z: data_tmpl = 13'bl000111110zzz: data_tmpl = 13'bl0001111110zz: data_tmpl = 13'bl00011111110z: data_tmpl = 13'bl000111111110: data_tmpl = 13'bl0010000zzzz: data_tmpl = 13'bl00100010Zzz: data_tmpl = 13'bl00100zllzzz: data_tmpl = 10'bOllllOOOOOl; 13'bl0010010zzzz: data_tmpl = 10'bOllllOOOOOl; 13'bl00100110zzz: data_tmpl = 10'bOllllOOOOOl; 13'bl00101000000z: data_tmpl = 10'bOllllOOOOOl 13'bl001010000010: data_tmpl = 10'bOllllOOOOOl 13'blOOlOlOOOOzll: data_tmpl = 10'bOllllOOOOll 13'bl00101000zl0z: data_tmpl = 10'bOllllOOOOll 13'bl00101000zll0: data_tmpl = 10'bOllllOOOOll 13'blOOlOlOOzlOz: data_tmpl = 10'bOllllOOOOll 13'bl0010100zllll: data_tmpl = 10 'bOllllOOOOll 13'bl001010zl0zz: data_tmpl = 10'bOllllOOOOll; 13'bl001010zlll0z: data_tmpl = 10'bOllllOOOOll 13'bl001010zllll0: data_tmpl = 10 'bOllllOOOOll 13'bl00101010z z: data_tmpl = 10'bOllllOOOOll 13'bl0010101110zz: data_tmpl = 10'bOllllOOOOll 13'bl001010111111: data_tmpl = 10'bOllllOOOOll; 13'bl00101100zzzz: data_tmpl = 10'bOllllOOOOll 13'bl0010110100z: data_tmpl = 10 'bOllllOOOOll 13'bl00l01101010z: data_tmpl = 10'bOllllOOOOll 13'bl001011010110: data_tmpl = 10'bOllllOOOOll 13'b lOOlOUOlzlll: data_tmpl = 10'bOllllOOOlOl 13'bl001011zll0z: data_tmpl = 10'bOllllOOOlOl; 13'bl001011zlll0z: data_tmpl = 10 'bOllllOOOlOl 13'bl001011zllll0: data_tmpl = 10'bOllllOOOlOl 13'bl00101110zzzz: data_tmpl = 10' bOllllOOOlOl 13'blOOlOllllOzzz: data_tmpl = 10 'bOllllOOOlOl data_tmpl = 10'bOllllOOOlOl 13'blOOllOOOzzzzz: data_tmpl = 10'bOllllOOOlOl I3'bl001100100zzz: data_tmpl = 10 'bOllllOOOlOl 13'b 10011001010Z: data_tmpl = 10'bOllllOOOlOl 13'blOOllOOlOllOO: data_tmpl = 10'bOllllOOOlOl 13'bl0011001011zl: data_tmpl = 10'bOllllOOOlll 13'blOOllOOlzlllO: data_tmpl = 10'bOllllOOOlll 13'blOOllOzllOzzz data_tmpl = 10'bOllllOOOlll; 13'blOOllOzlllOz: data_tmpl = 10 'bOllllOOOlll, -13'bl00110zllll0z: data_tmpl = 10'bOllllOOOlll; data_tmpl = 10 'bOllllOOOlll; 13'bl0011010zzzzZ data_tmpl = 10'bOllllOOOlll; 13'b lOOHOHOzzz: data_tmpl = 10 'bOllllOOOlll; 13'bl001101111110: data_tmpl = lO'bOllllOOOlll; 13'bl0011100000z: data_tmpl = 10 'bOllllOOOlll; 13'b lOOlllOOOzlz: data_tmpl = 10'bOllllOOlOOl; 13'b lOOlllOOzlOzz: data_tmpl = 10'bOllllOOlOOl; 13'bl001110zl0zz: data_tmpl = 10'bOllllOOlOOl; 13'bl001110zlllz: data_tmpl = 10'bOllllOOlOOl; 13'b lOOlllOlOZzzz: data_tmpl = 10'bOllllOOlOOl; 13'bl0011101110z: data_tmpl = lO'bOllllOOlOOl; 13'bl00111100zzz: data_tmpl = 10 'bOllllOOlOOl; 13'b lOOllllOlOzz: data_tmpl = lO'bOllllOOlOOl; 13'blOOllllOllOz: data_tmpl = 10'bOllllOOlOOl; 13'b 1001111011100: data_tmpl = 10'bOllllOOlOOl; 13'bl0011110111zl: data_tmpl = 10'bOllllOOlOll 13'bl001111zllll0: data_tmpl = lO'bOllllOOlOll 13'bl00111110zzzz: data_tmpl = 10'bOllllOOlOll 13'b: data_tmpl = lO'bOllllOOlOll; 13'bl0011111110zz: data_tmpl = 10'bOllllOOlOll 13'bl00111111110z: data_tmpl = 10'bOllllOOlOll 13'bl001111111111: data_tmpl = 10'bOllllOOlOll 13'b lOlOOOOOzzzzz: data_tmpl = 10'bOllllOOlOl 13'b IOIOOOOIOZZZZ: data_tmpl = lO'bOllllOOlOll; 13'bl0100001100z: data_tmpl = 10'bOllllOOlOl; 13'bl01000011010z: data_tmpl = 10'bOllllOOlOll 13'bl010000110110: data_tmpl = 10'bOllllOOlOll 13'bl01000011zlll: data_tmpl = 10'bOllllOOllOl 13'bl01000zlll0zz: data_tmpl = 10'bOllllOOllOl 13'bl01000zllll0z: data_tmpl = 10 'bOllllOOHOl 13'bl01000zlllll0: data_tmpl = 10 'bOllllOOHOl 13'b IOIOOOIOZZZZZ: data_tmpl = 10'bOllllOOllOl; 13'b IOIOOOIIOZZZ: data_tmpl = 10'bOllllOOllOl 13'bl010001110zzz: data_tmpl = 10 'bOllllOOHOl 13'bl010001111111: data_tmpl = 10' bOllllOOHOl 13'bl01001000zzz: data_tmpl = 10'bOllllOOllOl; 13'b 101001001000Z: data_tmpl = 10'bOllllOOllOl; 13'b 1010010010010: data_tmpl = 10'bOllllOOllOl; 13'bl010010010zll: data_tmpl = 10'bOllllOOllll; 13'bl01001001zl0z: data_tmpl = 10'bOllllOOllll 13'bl0lOOlOOlzllO: data_tmpl = 10'bOllllOOllll 13'bl010010110zzz: data_tmpl = 10'bOllllOOllll 13'blOlOOlOzlllll: data_tmpl = 10'bOllllOOllll 13'bl01001zl0zzzz: data_tmpl = 10'bOllllOOllll 13'bl010010110zzz: data_tmpl = 10'bOllllOOllll 13'bl01001011110z: data_tmpl = 10'bOllllOOllll 13'bl010010111110: data_tmpl = 10'bOllllOOllll 13'bl0100110zzzz: data_tmpl = lO'bOllllOOllll; 13'bl01001111zzzz: data_tmpl = 10'bOllllOlOOOl 13'blOlOlOOzzzzzz: data_tmpl = lO'bOllllOlOOOl 13'bl01010100zzzz: data_tmpl = lO'bOllllOlOOOl 13'bl010101zlzzzz: data_tmpl = 10'bOllllOlOOll 13'bl01010110zzzz: data_tmpl = 10'bOllllOlOOll 13'bl0101100Zzzz data_tmpl = 10'bOllllOlOOll; 13'bl01011010 zzz: data_tmpl = 10'bOllllOlOOll 13'bl01011zllzzzz: data_tmpl = 10'b? Llll? L? L? L 13'bl0101110zzzz: data_tmpl = 10'b? Llll? L? L? L 13'bl01011110zzzz: data_tmpl = 10'b? Llll? L? L 13'blOllOOOOOzzzz data_tmpl = 10'b? Llll? L? L? L; 13'bl01100001000z: data_tmpl = 10'b? Llll? L? L? L 13'bl011000010010: data_tmpl = 10 'bOllllOlOlOl 13'bl011000010zll: data_tmpl = 10'b? Llll? L? Lll 13'bl01100001zl0z: data_tmpl = 10'b ? llll? l? lll 13'bl01100001zll0: data_tmpl = 10 'bOllllOlOlll 13'bl011000zll0zz: data_tmpl = lO'bOllllOlOlll; 13'blOllOOOzlllll: data_tmpl = lO'bOllllOlOlll; 13'bl01100zl0zzzz data_tmpl = lO'bOllllOlOlll; 13'bl011000110zzz: data_tmpl = lO'bOllllOlOlll 13'bl01100011110z: data_tmpl = lO'bOllllOlOlll 13'blOllOOOlllllO: data_tmpl = lO'bOllllOlOlll 13'bl0110010ZzzzZ data_tmpl = lO'bOllllOlOlll; 13'blOllOOlllOOzz: data_tmpl = lO'bOllllOlOlll 13'bl01100111010z: data_tmpl = lO'bOllllOlOlll 13'bl011001110110: data_tmpl = 10'b? Llll? L? Lll 13'blOllOOlllzlll: data_tmpl = 10 'bOllllOUOOl 13'bl0110011110zz: data_tmpl = 10' bOllllOllOOl 13'bl01100111110z: data_tmpl = 10'bOllllOllOOl data_tmpl = 10'bOllllOllOOl 13'bl011010zzzzzZ: data_tmpl = 10'bOllllOllOOl 13'bl01101100zzzz data_tmpl = 10'bOllllOllOOl; ???? 13'bl ll ll l zz: data_tmpl = 10'bOllllOllOOl 13'bl0110110110zz: data_tmpl = 10 'bOllllOUOOl 13'bl01101101110z: data_tmpl = 10'bOllllOllOOl 13'bl011011zllllz: data_tmpl = 10'b llll ll ll??? 13'bl01101110z z: data_tmpl = 10'b? Llll? Ll? Ll 13'.bl011011110zz: data_tmpl = 10'b? Llll? Ll? Ll; 13'bl0110111110zz: data_tmpl = 10'b 13'bl01101111110z llll ll ll?????? Data_tmpl = 10'b llll ll ll 13'bl011100zzzzzz:? Data_tmpl llll ll l = 10'b 13'bl0111010000zz: data_tmpl = 10'b? Llll? Ll? Ll; 13'bl01110100010z: data_tmpl = 10'b? Llll? Ll? Ll; 13'bl01110100zllz: data_tmpl = 10'b? Llll? Lll? L; 13'bl0111010zl0z: data_tmpl = 10'b? Llll? Lll? L; 13'bl0111010zll0z: data_tmpl = 10'b? Llll? Lll? L; 13'bl011101zl0zz: data_tmpl = 10'b? Llll? Lll? L; 13'bl011101zllllz: data_tmpl = 10'b? Llll? Lll? L; 13'bl01110110zzz: data_tmpl = 10'b? Llll? Lll? L; 13'bl0111011110zz: data_tmpl = 10'b? Llll? Lll? L; 13'bl01110111110z: data_tmpl = 10'b? Llll? Lll? L; 13'bl0111100zzzz: data_tmpl = 10'b? Llll? Lll? L; 13'bl011110100zz: data_tmpl = 10'b? Llll? Lll? L; 13'bl0111101010zz: data_tmpl = 10'b? Llll? Lll? L; 13'bl01111010110z: data_tmpl = 10'b? Llll? Lll? L; 13'bl011110101110: data_tmpl = 10 'bOllllOlllOl; 13'bl0111101zllll: data_tmpl = 10'b? Llll? Lllll; 13'bl01111zll0zzz: data_tmpl = 10'b? Llll? Lllll; 13'bl01111zlll0z: data_tmpl = 10'b? Llll? Lllll; 13'bl01111zllll0z: data_tmpl = 10 'bOllllOlllll; 13'bl01111zlllll0: data_tmpl = 10 'bOllllOlllll; 13'bl0111110zzz: data_tmpl = 10'b? Llll? Lllll; 13'bl01111110zzzz: data_tmpl = 10'b? Llll? Lllll; data_tmpl = 10'b? llll? lllll; 13'bll0000000zzz: data_tmpl = 10 'bOllllOlllll; 13'bll00000010zzz: data_tmpl = 10'b? Llll? Lllll; 13'bll0000001100z: data_tmpl = 10'b? Llll? Lllll 13'bll00000011010: data_tmpl = 10 'bOllllOlllll I3'bll00000011zll: data_tmpl = 10'bOlllllOOOOl 13'bll00000zlll0z: data_tmpl = 10'bOlllllOOOOl 13'bll00000zllll0: data_tmpl = 10'bOlllllOOOOl I3'bll0000zl0zzz: data_tmpl = 10'bOlllllOOOOl; I3'bll0000zll0zz: data_tmpl = 10'bOlllllOOOOl; 13'bll0000zlll0zz: data_tmpl = 10'bOlllllOOOOl; data_tmpl = 10'bOlllllOOOOl; 13'bll000010zzz: data_tmpl = 10 'bOlllllOOOOl; 13'bll0000111110z: data_tmpl = 10'bOlllllOOOOl; 13'bll00001111110: data_tmpl = 10'bOlllllOOOOl; 13'bll00010000zz: data_tmpl = 10'bOlllllOOOOl; 13'bll00010001000: data_tmpl = 10'bOlllllOOOOl 13'bll000100010zl: data_tmpl = 10'bOlllllOOOll 13'bll00010001zl0: data_tmpl = 10 'bOlllllOOOll 13'bll000100zll0z: data_tmpl = 10'bOlllllOOOll 13'bll000100zllll: data_tmpl = 10'bOlllllOOOll 13'bll00010zl0zz: data_tmpl = 10'bOlllllOOOll; 13'bll00010zll0zz: data_tmpl = 10 'bOlllllOOOll; 13'bll00010zllll0: data_tmpl = 10 'bOlllllOOOll; 13'bll0001zl0zzz: data_tmpl = 10'bOlllllOOOll; 13'bll0001011110z: data_tmpl = 10'bOlllllOOOll; 13'bll00010111111: data_tmpl = 10'bOlllllOOOll; 13'bll000110zzz: data_tmpl = 10'bOlllllOOOll; 13'bllOOOllllOzzz: data_tmpl = 10'bOlllllOOOll; 13'bllOOOlllllzzz: data_tmpl = 10'bOlllllOOlOl; 13'bll00100Zzzzz: data_tmpl = 10'bOlllllOOlOl; 13'bll001010zzzzz: data_tmpl = 10'bOlllllOOlOl 13'bll00101100zzz: data_tmpl = 10'bOlllllOOlOl 13'bllOOlOllOlOOz: data_tmpl = 10'bOlllllOOlOl 13'bllOOlOllOlzlz: data_tmpl = 10'bOlllllOOlll 13'bll001011zll0z: data_tmpl = 10'bOlllllOOlll 13'bllOOlOlllOzzz: data_tmpl = 10'bOlllllOOlll 13'bllOOlOllllOzz: data_tmpl = 10'bOlllllOOOOl 13'bll0010111111z: data_tmpl = 10'bOlllllOOOOl 13'bllOOllOZzzzzz: data_tmpl = 10'bOlllllOOOOll 13'bll0011100zzz: data_tmpl = = lO'bOlllllOOlll; 13'bll00111010zz: data_tmpl = = lO'bOlllllOOlll; 13'bll001110110z: data_tmpl = = lO'bOlllllOOlll; 13'bll00111011100: data_tmpl = lO'bOlllllOOlll 13'bll001110111zl: data_tmpl = 10'bOlllllOlOOl 13'bll00111zllll0: data_tmpl = 10'bOlllllOlOOl 13'bll0011110zzzz: data_tmpl = 10'bOlllllOlOOl 13'bll00111110zz: data_tmpl = = 10'bOlllllOlOOl; 13'bll001111110z: data_tmpl = = 10'bOlllllOlOOl; 13'bll0011111110z: data_tmpl = lO'bOlllllOlOOl; 13'bll00111111111: data_tmpl = lO'bOlllllOlOOl; 13'bll01000zzzz: data_tmpl = lO'bOlllllOlOOl; 13'bll0100100Zzzz: data_tmpl = 10'bOlllllOlOOl; 13'bll0100101000z: data_tmpl = 10'blllllOlOOl; 13'bll01001010010: data_tmpl = lO'bOlllllOlOOl 13'bll01001010zll: data_tmpl = 10'b? Lllll? L? Ll 13'bll0100101zl0z: data_tmpl = 10'b? Lllll? L? Ll 13'bll0100101zll0: data_tmpl = 10'b? Lllll ? ll? 13'bll01001zll0z: data_tmpl = 10'b? lllll? l? ll; 13'bll01001zlllll: data_tmpl = 10'b? Lllll? L? Ll 13'bll0100110ZzZ: data_tmpl = 10'b? Lllll? L? Ll; 13'bll01001110zz: data_tmpl = 10'b? Lllll? L? Ll; 13'bll0100111110z: data_tmpl = 10 'bOlllllOlOll 13'bll01001111110: data_tmpl = 10' bOlllllOlOll 13'bll01010ZZZzzz: data_tmpl = 10'b? Lllll? L? Ll 13'bll01011000zz: data_tmpl = 10'b? Lllll? L? Ll; 13'bll0101100100z: data_tmpl = 10'b? Lllll? L? Ll 13'bll01011001zlz: data_tmpl = 10'b? Lllll? Ll? L 13'bll010110zll0z: data_tmpl = 10'b? Lllll? Ll? L 13'bll01011zl0zzz: data_tmpl = 10'b? Lllll? Ll? 13'bll01011zll0zz: data_tmpl = 10'b? Lllll? Ll? L 13'bll01011zllllz: data_tmpl = 10'b? Lllll? Ll? L 13'bll0101110zz: data_tmpl = 10'b? lllll? ll? l; 13'bll0101111110z: data_tmpl = 10'b? Lllll? Ll? L; 13'bll01100zzzz: data_tmpl = 10'b? Lllll? Ll? L; 13'bll011010000zz: data_tmpl = 10 'bOlllllOUOl; 13'bll0110100zlz: data_tmpl = 10'b? Lllll? Llll; 13'bll011010zl0zz: data_tmpl = 10'b? Lllll? Llll; 13'bll? Ll? Lzl? Zz: data_tmpl = lO'bOlllllOllll; 13'bll? Ll? Lzlllz: data_tmpl = lO'bOlllllOllll; 13'bll0110110zzzz: data_tmpl = 10'b? Lllll? Llll 13'bll011011110zz: data_tmpl = lO'bOlllllOllll 13'bll01110zzzzz_: data_tmpl = lO'bOlllllOllll 13'bll? Llllzzzzzz: data_tmpl = 13'blll00000zzzz: data_tmpl = 13'blll000010zzzz: data_tmpl = 13'blll0000110zz: data_tmpl = 13'blll00001110zz: data_tmpl = 13'blll000011110z: data_tmpl = 13'blll000zlllllz: data_tmpl = 13'blll00010zzzzz: data_tmpl = 13'blll000110zzzZ: data_tmpl = 13'blll0001110zzz: data tmpl = 13'blll00011110z: data_tmpl = 13'blll000111110z: data_tmpl = 13'blll00100zzz: data_tmpl = 13'blll001010z_z_: data_tmpl = 13'blllOOlOllOzzz: data_tmpl = 13'blll00101110z: data_tmpl = 13'blll001011110z: data_tmpl = 13'blll0010111110: data_tmpl = data_tmpl = 10 13'blll00110zzzz: data_tmpl = 13'blll001110zz: data_tmpl = 13'blll0011110zz data_tmpl = 13'blll00111110z: data_tmpl = data_tmpl = 13'blll0011111110: data_tmpl = 13'blll0100zz_zz: data_tmpl = 13'blll010100000z: data_tmpl = 13'blll0101000zlz: data_tmpl = 13'blll010100zl0z: data_tmpl = 13'blll01010zl0z: data_tmpl = 10 13'blll01010zlllz: data_tmpl = 13'blll0101zl0zz: data_tmpl = 10 13'blll0101zlll0z: data_tmpl = 13'blll010110zzz: data_tmpl = 10; 13'blll01011110zz: data_tmpl = 10, - 13'blll010111111z: data_tmpl = 10 13'blll0110zzzzz: data_tmpl = 13'blll01110000zz: data_tmpl = 10 13'blll011100010z: data_tmpl = 13'blll0111000110: data_tmpl = 13'blllOlllOOzlll: data_tmpl = 13'blll01110zl0z : data_tmpl = 13'blll01110zll0z: data_tmpl = 13'blll01110zlll0: data_tmpl = 13'blll0111zl0zz: data_tmpl = 13'blll? lllzlllll: data_tmpl = 13'blll011110zzzz: data_tmpl = 13'blll01111110z: data_tmpl = 13'blll011111110z: data_tmpl = 13'blll0111111110 : data_tmpl = 13'bllll000zzzzzz: data_tmpl = 13'bllll001000zzz: data_tmpl = 13'bllll0010010z: data_tmpl = 13'bllll00100110z: data_tmpl = 13'bllll0010zlllz: data_tmpl = 10 13'bllll001zl0zzz: data_tmpl = 10'b011111110111 13'bllll001zll0 z: data_tmpl = 13'bllll001zlll0z: data_tmpl = 13'bllll00110zzzz: data_tmpl = 10 13'bllll00111111z: data_tmpl = 10 13'bllll010zzzzzz: data_tmpl = 13'bllll01100zzzz: data_tmpl = 13'bllll011010zz: data_tmpl = 13'bllll? Llzllzzz: data_tmpl = 10 13'bllll01110zzzz : data_tm pl = 10 'b01111111101¡ 13'bllll? llll? zzz: data_tmpl = 13'blllll00zzzzzz: data_tmpl = 10 13'blllll01,0zzzz: data_tmpl = 13'blllll011000z: data_tmpl = 13'blllll0110zlz: data_tmpl = 10, 13'blllll? llzl ? z: data_tmpl = 13'blllllzlll? zzz: data_tmpl = 13'blllllzlllllz: data_tm? l = data_tmpl = data_tmpl = 10 data_tmpl = 10 data_tmpl = default: data_tmpl = 10'bxxxxxxxxxx; endcase always © (posedge clk) if (enable_3) data_tmp2 < = d ta_tmpl; assign out_data = data_tmp2; endmodule Listing 14 // Sccsld:% W%% G% ******************************** Copyright (c) 1997 Pioneer Digital Design Center Limited Author: Dawood Alam. Description: Verilog code for windowing algorithm to enable detection of the "active interval" of the COFDM symbol for guard Values of: 64, 128, 256, 512 and an active interval of 2048. (RTL) Notes: This module generates the window signal for the FFT in the form of valid_in and provides the necessary sign for the 1 / Q demodulator; sync interpolator and error handler. To DO: Check between successive symbols acquires for consistency in timing. Window timing pulse tracking mode, filter peaks IQ and sync interpolator guard pulses. Override functions for timing. Gain confidence by comparing symbol_acq vs retrys ************************************** ** timescale lns / 1 OOps module fft_window (in_xr, in_xi, clk, nrst, valid_in, valid_out, in_resync, out_iqgi, out_sincgi, out_rx_g uard, out_acquired, out_fft_window enable_3_4, out test, track_ram_address xri_tmp 1, xri_tmp5, track_ram_rnotw track_ram_enable, ram addr , ram_enable, ram_rnotw, ram_10_in ram 10_out, xlr LO, // To FFT datapath (I). xli_10, // To FFT datapath (Q). z2r_10, // From FFT datapath (I) z2i_10, // From FFT datapath ( Q) ff t_r am_r no w, // From FFT addr gene, fft_ram_enable, // From FFT addr gene, fft ram addr); // From FFT addr gene.

// - // Parameter definitions. // parameter wordlength = 12; // Data wordlength. parameter r_wordlength = 10; // ROM datawordlength. parameter AddressSize = 13; // Size of address bus. parameter FIF0_L = 256; // Tracking FIFO length. parameter FlFO_L_bits = 8; // Track FIFO addr bits parameter FIFO_N = 64; 11 Acc length S (ij). parameter FIFO_n = 64; // Acc length S (i-nj). parameter FIFO_A = 32; // t_offset dly FIFO + 1. parameter FIFO_A_bits = 5; // Track FIFO bits. parameter lu_AddressSize = 15; // log lu address size. delta parameter = 20; // Gu threshold distance parameter acquired_symbols = 2; // Acq symbls before trk parameter pos threshold = 3; // Forinfo only. parameter t_offset_threshold = 10, // t_offset valid thresh parameter w_advance = 10; // win trig frm boundary parameter sincint_latency = 2; // Latency to sync intep parameter iqdemod_latency = 168; // Latency to IQ demod. parameter start = 3'bOOO, // Search for neg peak. peakl = 3'bO01, // lst pos peak found. peak2 = 3'bO10, // 2nd pos peak found. peak3 = 3'bO //, // 3rd pos peak found. trackl = 3'bl00, // Tracking model. track2 = 3'bl? l; // Tracking mode 1. // // InpuVOutput ports. // input clk, // Master clock. nrst, // Power-up reset. valid_in, // Input data valid. in_resync, // Sync FSM into Acqure. fft_ram_rnotw, fft_ram_enable; input [AddressSize-l: 0] fft_ram_addr; input [wordlength-3: 0] in_xr, // FFT input data, I in_xi, // FFT input data, Q. xri_tmp5; // Track RAM output. input [wordlength * 2-l: 0] ramlO_out; // From 1 K x 24 bit RAM input [wordlength-1: 0] z2r_10, z2i_10; // From FFTdatapath. output [wordlength2-l: 0] raml0_in; // To 1K x 24 bit RAM. output [wordlength-3: 0] xri_tm.pl; // Track RAM input. output [14: 0] out_test; // Temp testpin output. output out_iqgi, // I / Q demod guard info. out_sincgi, // Sync int. guard info out_acquired, // Symbol acquired flag. out_fft_window, // FFT processor st / stp enable_3_4 valid_out, track_ram_rnotw, track_ram_enable ram_enabie, ram_rnotw; output [FlFO_L_bits-l: 0] track_ram_address; // Tracking ram address output [1: 0] out_rx_guard; // Acquired gu length. output [AddressSize-1: 0] ram_addr; output [wordlength-l: 0] xl r_10, xl i_10; // To FFT datapath. // _ // Wire / register declarations. // reg out_acquired, // Symbol acquired flag. out_fft_window, // FFT window signal. tracking, // Tracking mode data. acc_add, // Acc add only flag. acc_add_sub, // Acc add / sub flag. fifo_a_add_sub, // FIF0_A add / sub flag. f_ratio_valid, // F ratio is valid read, // Track FIFO read flag. write, // Track FIFO write flag track_mode, // Track / JAcq status flag dpctl_reset, // Datapath control rst. t_reset, // Timing counter reset. g_a_reset, // Guard_active cnt rst. guard_valid, // Guard signal is valid t_retime_acq, // Retime timing counter t_retime_trk, // Retiming for tracking t_offset_valid, // Peak offset valid. t offset_avg valid, // Averageoffsetvalid. p-ulse, R Pulse on states 4 & 5 enable_fft, // FFT enabled flag out_sincgi, // Guard int to sincint. out_iqgi, // Guard int to iq demod ram_enable, ram_rnotw; reg [14: 0] guard_active; // Guard + active length. reg [3: 0] retry, // No failed retry's. acq_symbols; // No of acquired symbls reg [wordlength-2: 0] xri_tmp7; // Delayed difference. reg [wordlength-3: 0] xr_reg, // (10 bits) xi_reg, xri_tmpl, IlSum of // + / Q / xri_tmp3, // Delayed I difference 1. xri_tmp6; // FIFO 2K / L output. reg [FlFO_L_bits-l: 0] read_address, // Track FIFO read addr. write_address, // Track FIFO write adr. track_ram_address; // Tracking ram address; reg [lu_AddressSize-l: 0] acc; // Holds input variance. reg [wordlength4: 0] xr_tmpl, // I. xi_tmpl; II Q reg [2: 0] r; // Clock decode counter. reg [1: 0] out_rx_guard; // Determined guard. reg [r_wordlength: 0] f_ratio; // Statistical F ratio. reg [10: 0] fft_valid_count; // Counts noof FFTvids reg [AddressSize-1: 0] window_ram_addr, // ram_address counter. ram_addr; reg [14: 0] t_count, // Window timing count. t_offset; // Peak offset from t_ct reg [14: 0] g_a_count; // Guard_active counter. reg [14: 0] dp_count; // Datapath timing count reg [14: 0] t_offset_avg; // Averaged offset. reg [2: 0] state, // Acq / Track FSM state. old_state; // Listen tracking state. reg [9: 0] guard_length; // Thresholded guard len reg [FlFO_A_bits: 0] fifo_a_count; // Count ti // fifo_a ful // l bit more - > remove reg [r_wordlength-l: 0] max_j? eak; // Maximum positive peak reg [wordlength-1: 0] msb out_tmp, // Temporary stores for Isb_in_tmp; / reven symbols to RAM. wire [AddressSize-1: 0] fft_ram_addr; // From FFT RAM addr gen wire clk, // Masterclock. nrst, // Power-up reset. enable_0_4, // clock enable 0 in 4. enable_l_4, // clock enable 1 in 4. enable_2_4, // clock enable 2 in 4. enable_3_4, // clock enable 3 in 4. enable_0_8, // clock enable 0 in 8. enable_l_8, // clock enable 1 in 8. enable_2_8, // clock enable 2 in 8. enable_3_8, // clock enable 3 in 8. enable_4_8, // clock enable 4 in 8. enable 5 8, // clock enable 5 in 8 enable_6_8, // Clock enable 6 in 8 enable_7_8, // Clock enable 7 in 8. ram_enable_8, // Acq FIFO enable. track_ram_enable, // Tracking RAM enable track_ram_rnotw, // Tracking RAM rnotw. even_symbol, // valid on even symbols in resync, // Resync to acqn mode. pos_peak, // + ve peak, ref only! dp_control, // Datapath acq / trk ctl. t_offset_ctl, // Trk averager dp ctl fft_ram_rnotw, fft_ram_enable; wire [lu_AddressSize-l: 0] lu_address; wire [r_wordlength-l: 0] lu_data, xri_tmp9; wire [wordlength-3: 0] xri_tmp2, xri_tmp4, xri_tmp5, n_q. out_q; wire [wordlength-1: 0] ram_in; reg [wordlength-1: 0] Isb_out, msb_out; reg [wordlength-1: 0] ram_out, msb in, Isb_ln; wire [wordlength * 2-l: 0] raml 0_out; reg [wordlength2-l: 0] raml0_in; reg [wordlength-l: 0] xlr_10, xli_10; wire [wordlength-l: 0] z2r_10, z2i_10; wire [14: 0] out_test; wire [14: 0] t_offset_diff, // Current +/- difference t_offset_thresh, // Valid offset (maybe) t_offset_dly, // Delayed of above. t_offset_sca // ed, // Sca // ed to t_offset. read_pos, // read trig, + ve offset read_neg, // read trig, -ve offset write_pos, // write trg, + ve offset write_neg; // write trg, -ve offset assign out_test = t_offset_diff; // // Fast 40 MHz clock decoder and valid_in control. // always © (posedge clk) if (nrst) // Synchronous power-up reset. r < = 0; else if (valid_in) // Count if input data valid. r < = r + l'bl; assign enable_0_4 = valid_in & (~ r [l] & ~ r [0]) II Gate valid_in with assign enable_l_4 = valid_in & (~ r [l] & r [0]); il decoded enable sign assigning enabie_2_4 = valid_in & (r [l] & ~ r [0]) 11 to control a // reg's. assign enable_3_4 = valid_in & (r [l] & r [0]); il Enables every 4 clk's assign enable_l_8 = valid_in & (~ r [2] & -r [l] __ r [0]) assign enable_2_8 = valid_in & (-r [2] & r [l] &-r [0]) assign enable_3_8 = valid_in & (-r [2] & r [l] & r [0]) assign enable_4_8 = valid_in & (r [2] & -r [l] & r [0]); // Enables every 8 assign enable_5_8 = goes // d_ln & (r [2] & r [l] & r [0]); // clk's assign enable_6_8 = valid_in & (r [2] & r [l] & ~ r [0]) assign enable_7_8 = valid_in & (r [2] & r [l] & r [0]); // // The entire data path incorporating the FIFO's, ROM and comparators. // // Register the data inputs to the windowing module. always © (posedge clk) if (in_resync // nrst) begin xr_reg < = in_xr; xi_reg < = in_xi; end else if (enable_3_4) begin xr_reg < = in_xr; xi_reg < = in_xi; end // Take the modulus of in_xr and in_xi and add together (| in_xr | + 1in_xi | ). always © (xr_reg or xi_reg) begin if (xr reg [wordlength-3]) // Checking MSB for negative number. xr tmpl = -xr_reg; else xr_tmpl = xr_reg; if (xi_reg [wordlength-3]) // Checking MSB for negative number. xi_tmpl = -xi_reg; else xi_tm.pl = xi_reg; xri_tmpl = xr_tm.pl + xi tmpl; end assign even_symbol = r [2], - always © (even_symbol or msb_out_tmp or ram_in or Isb_out) // Mux MSB / LSB to if (even_symbol) // to // ow 1 K RAM begin // to act as to 2K ram_out = Isb_out; // FIFO, possible Isb_in_tmp = ram_in; // since data end 11 bitwidth is 2b else // bits wide in begin // the 1 K RAM and ram_out = msb_out_tmp; // only b bits are msb_in = ram_in; // required in the end // data path. always © (posedge clk) // Delay even begin // symbols by one if (enable_5_8) // symbol so that Isb_in <; = Isb_in_tmp; // two symbols are if (enable_7_8) // written & read msb_out_tmp < = msb_out; // to the ram. end assign xri_tmp2 = ram_out; // Map RAM 1/0 assign ram_in = xri_tmpl; // to dp wires. always @ (raml0_out or msb_in or Isb_in or z2r_10 or z2i_10 or ram_enable_8 or enable_3_8 or fft_ram_enable or fft_rarn_rnotw or window_ram_addr or fft_ram_addr or tracking) // FFT / WINDOW FIFO begin // RAM Mux code. if (tracking) // In window acq begin // mode. msb_out = raml0_out [2wordlength-l: wordlength], -Isb_out = * raml0_out [wordlength-l: 0]; // Connect window raml0_in [2wordlength-l: wordlength] = msb_in; // datapath & RAM ramlO_in [wordlength-l: 0] = Isb_in; // control you sign ram_enable = ram_enable_8; ram_rnotw = enable_3_8; ram_addr = window_ram_addr; end else // In tracking beg in // mode, therefore xl r_10 = raml0_out [2 * wordlength-l: wordlength]; // functional FFT xli_10 = raml0_out [wordlength-1: 0]; raml0_in [2 * wordlength-l: wordlength] = z2r_10; // Connect FFT raml O_in [wordlength-l: 0] = z2i_10; //? atapath & RAM ram_enable = fft ram_enable; // control you sign ram_rnotw = fft = ram_rnotw; ram_addr = fft_ram_addr; end end assign track_ram_rnotw = enable_3_4 & read; assign track_ram_enable = (enable_3_4 & read) // (enable_l_4 &write); // Select which FIFO we 'read from depending on tracking or acquire mode. always @ (xri_tmp5 or xri_tmp2 or tracking) if (tracking) xri_tmp6 = xri_tmp5; // Tracking mode else // data. xri_tmp6 = xri_tmp2; // Acquisition // mode data. II Perform computation of s (ij) always @ (xri_tmpl or xri_tmp6) xri_tmp7 = xri_tmpl - xri_tmp6; // Take the modulus of xri_tmp7; always @ (xri_tmp7) if (xri_tmp7 [wordlength-2]) // Check MSB for xri_tmp3 = -xri_tmp7; // neg number. else xri_tmp3 = xri_tmp7; // FIFO Setup to perform moving summation of s (ij) valúes. fft_sr_addr # (wordlength-2, FIFO_N) sr_N (clk, dp_control, // Length = FlFO_N. xri_tmp3, // Input. xri_tmp4); // Output. II Compute the moving summation ie S (ij) = s (il, jl) + s (i-2, j-2) + ... II We must NOT truncate or round the error wi // grow across a symbol . always © (posedge clk) if (in_resync // nrst I dpctl_reset) // clear accumulator at acc < = 0; // power-up or Resync or trk. else if (dp_control &acc_add) // Wait until acc valid.

// Subtract as we // as add when 2K / 8K FIFO is fu //. acc < = acc + xri_tmp3 - ((acc_add_sub)? xri_tmp4: 0); assign lu_address = acc; // Ensure lu_address is large enough to // accomodate acc number range. fft_window_lu # (r_wordlength, lu_AddressSize) // Case table instance log_lu (clk, dp_control, lu_address, lu_data); // for a log lookup. // Setup 5 bit FIFO to determine the delayed variance. fft_sr_addr # (r_wordlength, FlF0_n) sr_n (clk, dp_control, // Length = FlFO_n. Iu_data, // Input. xri_tmp9); // Output. // Determine difference of logs and henee the f_ratio when it is valid. always @ (lu_data or xri_tmp9 or f_ratio_valid) f_ratio = (f_ratio_valid)? lu_data - xri_tmp9: l'bO; // Positive threshold (for information only) // assign pos_peak = ((f_ratio > = pos_threshold & f_ratio < (1 < < r_wordlength))? L'bl: l'bO); // // FFT window datapath control registers. // always © (posedge clk) if (in_resync // nrst // dpctl_reset) // Synchronous reset. beg in f_ratio_valid < = l'bO; // Initalize datapath acc_add < = l'bO; // control registers. acc_add_sub < = 1 'bO; end else if (enable_3_4 && -read) // Acquisition mode begin // Use 2K / 8K FIFO. if (dp_count == 2047 + FIFO_N + FlFO_n + 1 + 1) // f_ratio only valid f_ratio_valid < = l'bl II after sum of FIFO if (dp_count == 2047j // + acc + ROM latencys acc_add < = l'bl; // Add if acc fu //, if (dp_eount == 2047 + FIFO_N) // Add / sub when FIFO acc_add_sub < = 1 'bl; // N is fu //. Else else if (enable_3_4 & amp) // Tracking mode begin // Use FIFO_L. If (dp_count == FIFO_L + FIFO_N + FIFO_n + 1 + 1) // f_ratio only valid f_ratio_valid < = l'bl, // after sum of FIFO if (dp_count == FIFO_L) // + acc + ROM latencys acc_add < = l'bl; // Add if acc fu //. If (dp_count == FIFO_L + FIFO_N) // Add / sub when FIFO acc_add_sub < = l'bl; 11 N is fu //. End always © (posedge clk) if (in_resync // Nrst) // Synchronous reset. Fifo_a_add_sub < = 0; else if (enable_3_4 & fifo_a_count == FIF0_A) // fifo_a is fu // fifo_a_add_sub < = 1; // so add and sub. Always (posedge clk) if (in_resync // nrst) // Synchronous reset. t offset_avg_valid < = l'bO; // Average value is else if (enable_3_4 &&fifo_a_count == FIFO_A + 1) // valid one c ycle t_offset avg_valid < = l'bl; // afteradd-sub sig. assign dp_control = enable_3_4 && // Datapath enable (~ track_mode || track_mode & & read); // in acq / track mode. assign t_offset_ctl = enable_3_4 && amp; t_offset_valid // clock averager _._. press & & Read & & tracking; // dp control signal. // // FFT window timing and sync acquisition / tracking timing counters. // always © (posedge clk) if (in_resync // nrst // t_reset) // Synchronous power-up reset. t_count < = 0; // Reset main timing counter. else if (enable_3_4 && t_retime_acq) // Retime to count from last t_count < = t_count - guard_active; // peak to current time. else if (enable_3_4 && ~ track_mode) // Count if not in track mode t_count < = t_count + l'bl; else if (enable_3_4 && t_retime_trk) // Otherwise must be in track t_count < = t_count - guard_active // so advance timing for acq + (2 * FIFO_N + FlFO_n + 2); // FIFO_L read trig point then else if (enable_3_4) begin // wrap round t_count at if (t_count == 2047 + guard_length) // end of guard + active length. t_count < = 0; // Needed as a reference to else // track peak movement in t_count < = t_count + l'bl; // capture window. end always © (posedge clk) if (in_resync // nrst // g_a_reset) // Synchronous power-up reset. g_a_count <; = 0; // Reset guard_active counter. else if (enable_3_4 && f_ratio_valid) // g_a count when f_ratio vald g_a_count < = g_a_count + l'bl; // Guard active timing counter always © (posedge clk) // Datapath timing counter. if (in_resync // nrst // dpctl_reset) // Synchronous reset. dp_count < = 0; // Reset datapath control. else if (enable_3_4 & & -track_mode) // Always count in acquire dp_count < = dp_count + l'bl; // mode on clk 0. else if (enable_3_4 && track_mode & read) // Count when reading data in dp_count < = dp_count + l'bl; // tracking mode. always © (posedge clk) if (in_resync // nrst) // Synchronous reset. fifo_a_count < = 0; else if (enable_3_4 && t_offset_ctl) // Only clock averager if Trk fifo_a_count < = fifo_a_count + l'bl; // and t_offset is valid. always © (posedge clk) // Create click on entering if (enable_3_4) // track 4 or track 5 to clk begin // t_offset_ctl once per state if ((state == trackl && // transition.) We need to old_state! = trackl) // clock the averager only (state == track2 & // eleven on entering state 4 or old_state! = track2)) // state 5 henee t_offset_ctl press < = l'bl; // is gated with pulse. else press < = l'bO; old_state < = state; end always @ (posedge clk) if (in_resync // nrst) tracking < = l'bO; // Read from 2K / 8K FIFO first. else if (enable_3_4 & & track_mode & __ dp_count - = FIFO_L + l) // Check if FIFO_L fu // in trk tracking < = l'bl; // then read tracking FIFO_L. // // FFT window timing and sync acquisition / tracking FSM // always © (posedge clk) // Acquisition mode FSM. if (in_resync // nrst) // Synchronous power-up reset begin state < = start; // FSM starts in resync. track_mode < = l'bO; // Start in acquisition mode. t_reset < = l'bO; // Reset main timing counter. dpctl_reset < = l'bO; // dp_ctl out of reset. g_a_reset < = l'bO; // Reset guard_active counter. max_peak < = l'bO; // Reset max peak value. retry < = O; // Reset no of retry 's. acq_symbols < = O; // Reset acquired no symbols guard_valid < = 1'bO; // Guard data is valid. t_retime_acq < = 1 'bO; // Do not retime at resync. t_retime_trk < = 1 'bO, - // Do not retime at resync. end else if (enable_3_4) case (state) / * SO * I start: begin g_a_reset < = l'bO; // g_a_reset out of rst t_reset < = l'bO; // t_count out of reset. guard_valid < = l'bO; // Guard invalid. // MUST ACT ON RETRYS TOO! ! state < = peakl; // Enter peakl state. end / * S 1 * 1 peakl: begin t_reset < = l'bO; // t_count out of reset. if (g_a_count < 2048 + 512) // Search for post peakl begin if (f_ratio> max_peak & _. f_ratio < (1 < < r_wordlength) // Is new peak larger? begin max_peak < = f_ratio; // If so assign max_peak t_reset < = 1; // Reset timing counter, end end else // First block complete, begin t_reset = l'bO; // t_count out of reset. G_a_reset < = l'bl, // Reset g_a_count. Max_peak < = l'bO; // Reset max peak vaiue. State < = peak2; // Next block search. End end // S2 * / peak2: begin g_a_reset < = l'bO; // Next block start cnt if (g_a_count <2048 + 512) // Search for post peak2 begin if (f_ratio> max_peak & f_ratio < (1 < < r_wordlength)) // Is new peak larger ? begin maxjpea = f_ratio, // If so assign max_peak guard_active < = t_count; // Assign guard_active. end end // Second block complete else If (II First, one peak per block situation (large guards) (guard_active < (2560 + delta) && // Test for 2048 + 512 guard_active> (2560-delta)) // // pt guard length. (guard_active < (2304 + delta) && // Test for 2048 + 256 guard_active> (2304-delta)) // // pt guard length. (guard_active < (2176 + delta) && // Test for 2048 + 128 guard_active> (2176-delta)) // // pt guard length. (guard_active < (2 // 2 + delta) && // Test for 2048 + 64 guard_active> (2 // 2-delta)) // // pt guard length. // Now two peaks per block situation (sma // guards) (guard_active < (5120 + delta) && // Test 4096 + 512 + 512 guard_active> (5120-delta)); // pt guard length. (guard_active < (4608 + delta) _. & // Test 4096 + 256 + 256 guard_active > (4608-delta)) // // pt guard length. (guard_active < (4352 + delta) && // Test 4096 + 128 + 128 guard_active> (4352-delta)) // // pt guard length. (guard_active < (4224 + delta) && // Test 4096 + 64 + 64 guard_active> (4224-delta))) // pt guard length. begin state < = peak3; // Next peak search. g_a_reset < = l'bl; // Reset g_a_count. max_peak < = l'bO; // Maximum peak reset. guard_valid < = l'bl; t_retime_acq < = l'bl; end else // Acquisition failed so begin // jump to start and state < = start; // increment the retry retry = retry + l'bl; // counter. t reset < = l'bl; // Reset t count. g_a_reset < = l'bl, // Reset g_a_count. max-peak < = l'bO; // Maximum peak reset. • end end / * S3 * / peak3: begin t_retime_acq < = l'bO; g_a_reset < = l'bO, // Next block start cnt if (g_a_count < 2048 + 512) // Search for post peak2 begin if (f_ratio> max_peak &&f_ratio < (1 < < r_wordlength)) / / Is new peak larger? begin max_peak < = f_ratio; // If so assign max_peak guard_active < = t_count; // Assign guard_active. end end // third block complete else if (II First, one peak per block situation (large guards) (guard_active < (2048 + guard_length // Peak test 2048 + delta) && // + guard length. guard_active > (20 8 + guard_length-delta)) // // Now two peaks per block situation (sma // guards) (guard_active < (4096+ (2 * guard_length) // Peak 4096 + 2 + delta) && // guard length. guard_active > (4096+ (2 * guard_length) -delta)) ) begin acq_symbols < = acq_ symbols + 1'bl; // Another sy acqurd g_a_reset < = l'bl, // Reset g_a_count. max_peak < = l'bO; // Maximum peak reset. t_retime_trk < = l'bl; // Retime t_count to trk track_mode < = l'b 1; // Enter track mode. dpctl_reset < = l'bl; // Reset datapath count state < = trackl; // Enter trackl state. end else // Acquisition failed so begin // jump to start and state < = start; // increment the retry retry < = retry + l'bl; // counter. t_reset < = l'bl; // Reset t_count. g_a_reset < = l'bl; // Reset g_a_count. max_peak < = l'bO; // Maximum peak reset. end end / * S4 * / trackl: begin t_retime_trk < = l'bO; // t_count out retime dpctl_reset < = l'bO; // dp ctl out of reset. if (read & amp_ratio_valid) // Peak detect on rd & vld begin if (f_ratio> max_peak && ph_ratio < (1 < < r_wordlength)) // Is new peak larger? begin max_peak < = f_ratio; // If so assign max_peak t_offset < = t_count; // Store peak offset. '' end if (read_address == FIF0_L-1) // If at end of FIFO_L begin // move to next state. state < = track2, // (read_Addr < > FIFO_L) max_peak < = l'bO; // Reset max peak value. end end else state < = trackl; // else wait in trackl. end / * S5 * / track2: begin if (read & &f_ratio_valid) // Peak detect on rd &vld begin if (f_ratio> max_peak & f_ratio < (1 < < r_wordlength)) / / Is new peak larger? begin max_peak < = f_ratio; // If so assign max_peak t_offset < = t_count; // Store peak offset end if (read_address == FIF0_L-1) // At end of FIF0_L begin // move to next state. state < = trackl; // (read_Addr < > FIFO_L) max_peak < = l'bO; // Reset max peak value. end end else state < = track2; // Wait in this state. end default: state < = 3'bXXX; endcase // // FFT window output decode logic. // always © (posedge clk) if (in_resync // nrst) // Synchronous reset. out_iqgi < = O; else if (enable_3_4 & & tracking & t_count == 15 'dO - iqdemod_latency) // iqgi guard start. out_iqgi < = l'bl; else if (enable_3_4 & & tracking __ & t_count == iqdemod_latency) // iqgi guard stop. out_iqgi < = 1'bO; always © (posedge clk) if (in_resync // nrst) // Synchronous reset. out_sincgi < = O; else if (enable 3_4 & & tracking & t_count == 15 'dO - sincint_latency) // sincgi guard start. out_sincgi < = l'bl; else if (enable_3_4 & & tracking && // TO COMPLETE LATENCY STUFF t_count = - sincint latency) // sincgi guard stop. out syngi < = l'bO; always © (posedge clk) // Count over active if (in_resync j ¡nrst) // interval to generate enable_fft < = l'bO; // FFT valid press. else if (enable_3_4 & & tracking & t_count == guard_length + FIFO_L / 2 - w_advance) // FFT start point is enable_fft < = l'bl; // in middle of write else if (enable_3_4 & tracking & & // into FiFO_L + adveed. fft_valid_count == 2047) // FFT stop after 2048 enable_fft < = l'bO; // samples. always © (posedge clk) if (ih_resync // nrst) // Synchronous reset. fft_valid_count < = O; else if (enable_3_4 & & tracking & -enable_fft) // Valid count = O. fft_valid_count < = O, // until fft is enabled. else if (enable_3_4 & tracking & enable_fft) fft_valid_count < = fft_valid_count + l'bl; // Count when enabled. assign valid_out = enable_fft & valid_in; // MUST SYNCHROS Vid every 3 clks? ll-ll Synchronous RAM address generators, // _ always © (posedge clk) // Acqsition FIFO address gen. if (¡nrst || in_resync) // Synchronous reset. window_ram_addr < = O; // Address gen for acq mode. else if (enable_2_8) window_ram_addr < = window_ram_addr + l'bl; assign ram_enable_8 = enable_2_8 | | enable_3_8 enabie_4_8 || enable_5_8; always © (posedge clk) // Tracking FIFO address gen. begin if (nrst || in_resync) begin read_address < = O; // Reset track FIFO read addr. write_address < = 0; // Reset track FIFO write addr write < = l'bO; // Track FIFO, write disabled. read < = 1 'bO; // Track FIFO, read disabled. end else if (enable_3_4) begin if (track_mode £. & t_count == O) // Track FIFO read read < = l'bl; // trigger point. if (read) // Read if 'read' begin // flag is set. if (read_address == FIFO_L-l) // Stop read at begin // end of FIFO. read_address < = 0; read < = l'bO; // Clr read flag. end else read_address < = read_address + l'bl; // Ine r address. end if (track_mode & &t_count == guard_length + l) // Write if the write < = l'bl; // read is guard // depth into FIFO if (write) begin if (write_address == FIF0_L-1) // Stop write at begin // end of FIFO. write_address < = 0; write < = l'bO; end else write_address < = write_address + l'bl; // Ine w address. end end end always @ (enable_l_4 or enable_3_4 or read or write or // Assign read and read_address or write_address) // write addresses if (enable_3_4 & amp) // onto common track_ram_address = read_address; // address bus else if (enable_l_4 & write) // for tracking track_ram_address = write_address; // tsyncram RAM. // // Thresholding function to determine precise guard interval. // always © (posedge clk) if (enable_3_4 & &guard_valid) begin // First, one peak per block situation (large guards) if (guard_active < (2560 + delta) && amp; // Test for 2048 +512 guard_active > (2560-delta)) // pt guard length. begin out_rx_guard < = 2'b //; guard_length < = 512; end if (guard_active < (2304 + delta) && // Test for 2048 + 256 guard_active> (2304-delta)) // pt guard length. begin out_rx_guard < = 2'blO; guard_length < = 256; end if (guard_active < (2176 + delta) && // Test for 2048 + 128 guard_active> (2176-delta)) // pt guard length. begin out_rx_guard < = 2'b? L guard_length < = 128; end if (guard_active < (2 // 2 + delta) && // Test for 2048 + 64 guard_active > (2 // 2-delta)) // pt guard length. begin out_rx_guard < = 2'b00; guard_length < = 64; end // Now two peaks per block situation (small guards) if (guard_active < (5120 + delta) && // Test for 4096 + 512 + 512 guard_active> (5120-delta)) // 512 pt guard length begin out_rx_guard < = 2'b // guard_length < = 512; end if (guard_active < (4608 + delta) && // Test for 4096 + 256 + 256 guard_active> (4608-delta)) // 256 pt guard length. begin out_rx_guard c = 2'blO; guard_length < = 256; end if (guard_active c (4352 + delta) && // Test for 4096 + 128 + 128 guard_active > (4352-delta)) // 128 pt guard length. begin out_rx_guard < = 2'b? L guard_length < = 128; end if (guard_active < (4224 + delta) && // Test for 4096 + 64 + 64 guard_active> (4224-delta)) // 64 pt guard length. begin out_rx_guard c = 2'bOO guard_length < = 64; end end // - // Averager for t_offset in tracking mode. // assign t_offset_diff = t_offset - (2FIFO_N + FlFO_n); // dly 2 for latency? always © (posedge clk) if (in_resync // nrst) // NEED TO ENABLE THIS! ! ! ! ! ! t offset_valid < = O erse if ((t_offset_diff < (1 < < 14 + 1) - t_offset_threshold && amp; // Neg t_? Ffset_diff > (1 c < 14- 1)) || (t_offset_diff > t offset_threshold && // Pos t offset diff < (1 «14)) // CORRECT TO DETECT vid = 1 not 0 t_offset_valid < = 0; else t_offset_valid < = 1; assign t_offset_thresh = (t_offset_valid)? t_offset_diff: 0; // FIFO Setup to perform moving summation of t_offset valúes. fft_sr_addr # (15, FIFO_A) sr_A (clk, t_offset_ctl, t_offset_thresh, // input, t_offset_dly); // Output. // Compute the moving summation i.e t_offset (i-1) + t_offset (i-2) + ... // We must NOT truncate or round the error wiil grow across a symbol. always © (posedge clk) if (in_resync // nrst) // clear accumulator at t_offset_avg < = 0; // power-up or Resync. else if (t_offset_ctl) // Wait until t_offset valid. // Subtract as we // as add when averager is fu //. t_offset_avg < = t_offset_avg + t_offset_thresh - ((fifo_a_add_sub)? t_offset_dly: 0); assign t_offset_sca // ed =. { . { (FlFO_A_bits). { t_offset_avg [14]} } , t_offset_avg [14: FlF0_A_bi ts]}; // // Code to determine conditions for advancing / retarding tracking window. // assign read_pos = t_offset_sca // ed; // + ve (late) so // delay read assign read_neg = 2047 + guard_length + 1 - // - ve (early) so (~ t_offset_sca // ed + 1); // advance read assign write_pos = guard_length + 1 + // + ve (late) so t_offset_sca // ed; // delay write // PROBLEMS WHEN offset > guard_length + 1 // (should not happen as we range check peaks in acq mode) assign write_neg = guard_length + 1 - // - ve (early) so (~ t_offset_sca // ed + 1); // advance write endmod ule Listing 15 // Sccsld:% W% _G% **************************** ****************** Copyright (c) 1997 Pioneer Digital Design Center Limited Author: Dawood Alam. Description: Verilog code for a structural netlist coupling the Fast Fourier Transform (FFT) processor to the hardware acquisition window. Notes: ********************************** 'timescale 1 ns / 1 OOps module fft_top (i_data, q_data, • clk, nrst, in_resync, in_2k8k, valid_in, ram4_in, ram5_in, ram6_in, ram7_in, ram8_ih, ram9_in, raml 0_in, i_out, q_out, out_ovf, enable_0, enable_l enable_2, enable_3, valid_out, rarn4_out , ram5_out, ram.6 out ram7_out, ram8_out, ram9_out, raml O_out, ram_addr ram_enable, ram_rnotw, rom3_addr, rom4_addr, rom3_data, rom4_data, track_add r, track_data_in, track_data_out, track_rnw track_ram_enable, out_rx_guard, out_iqgi, out_sincgi, out_test); // // Parameter definitions. / parameter wordiength = 12; // Data wordlength. parameter c ~ wordlength = 10; // Coeff wordlength. parameter AddressSize = 13; // Size of address bus. parameter rom_AddressSize = 13, // ROM address bus size. parameter mult_scale = 3; // Multiplier sca // ing: // 1 = / 4096, 2 = / 2048, // 3 = / 1024, 4 = / 512. parameter r_wordlength = 10; // ROM data wordlength. parameter FIF0_L = 256; // Tracking FIFO length. parameter FlFO_L_bits = 8; // Track FIFO addr bits parameter FIF0_N = 64; // Acc length S (ij). parameter FIFO_n = 64; // Acc length S (i-nj). parameter FIFO_A = 32; // t_offset delay FIFO. parameter FIFO_A_bits = 5; // Track FIFO bits. parameter lu_AddressSize = 15; // log rom address size. delta parameter = 20; // Gu threshold distance parameter acquired_symbols = 2; // Acq symbls before trk parameter pos_threshold = 3; // for info only. parameter t_offset_threshold = 10; // t_offset valid thresh parameter w_advance = 10; // win trig frm boundary parameter sincint_latency = 2; // Latency to sync intep parameter iqdemod_latency = 168; // Latency to IQ demod.

// Input / Output ports. // input clk, // Master clock. nrst, // Power-up reset. in_2k8k, // 2K mode active low. valid_in, // Input data valid. in_resync; input [9: 0] i_data, // FFT input data, I. g_data, // FFT input data, Q. input [wordlength-3: 0] track_data_out; input [wordlength * 2-l: 0] ram4_out, // Couple the i / Q data ram5_out, // outputs from the ram6_out, // memory to the ram7_out, // respective butterfly ram8_out, // processors. ram9_out, ram 10_out; input [c_wordlength2-l: 0] rom3_data, rom4_data; output [rom_AddressSize-6: 0] rom3_addr; output [rom_AddressSize4: 0] rom4_addr; output [14: 0] out_test; // Temp testpin output. output [1: 0] out_rx_guard; // Acquired gu length. output [wordlength-3: 0] track_data_in; output [wordlength * 2-l: 0] ram4_in, // Couple the 1 / Q data ram5_in, // outputs of each BF ram6_in, // processor to their ram7_in, // respective memory ram8_in, // inputs. ram9 in, ram 10_in; output [AddressSize-l: 0] ram_addr; // RAM address bus, output out_ovf, // Overflow flag. enable_0, // Enable clock 0. enable_l, // enable clock 1. enable_2, // enable clock 2. enable_3, // enable clock 3. valid_out, // Output data valid. ram_enable, // RAM enable. ram_rnotw, track_rnw, track_ram_enable, out_iqgi, out_sincgi; -output [FlFO_L_bits -l: 0] track_addr; output [wordlength-l: 0] i_out, // FFT output data, I. q_out; // FFT output data, Q. // // Wire / register declarations. // wire [9: 0] i_data, // FFT / WIN input 1. q_data; // FFT / WIN output Q. wire [wordlength-l: 0] i_out, // FFT output data, I. q_out; // FFT output data, Q. wire [wordlength2-l: 0] ram4_in, ram5_in, ram6_in, ram7_in, ram8_in, ram9_in, ramlO_in; wire [wordlength.2-1: 0] ram4_out, ram5_out "ram6_out, ram7_out, ram8_out, ram9_out, raml0_out; wire [AddressSize-l: 0] ram_addr, // RAM address bus. ram addr fft 2 win wire clk, nrst, in_2k8k, in_resync valid_in, out_ovf, enable_0, enable_l, enable_2, enable 3, valid_out, ram._enable, // RAM enable signal. ratn_rnotw, valid_win_2_f ft ram_rnotw_f ft_2_win, ratn_enable_f f t_2_win, track_rnw, track_ram_enable, out_iqgi, out_sincgi; wire [wordlength -l.-O] xlr_10, xli_10, z2r_10, z2i_10; wire [wordlength-3: 0] track_data_in, track_data_out; wire [FlFO_L_bits -l: 0] track_addr; wire [1: 0] out_rx_guard; // Determined guard. [c_wordlength * 2-l: 0] rom3_data, rom4_data; wire [rom_AddressSize-6: 0] rom3_addr; wire [rom_AddressSize: 0] rom4_addr; wire [14: 0] out_test; // // Instance FFT processor. // fft_r22sdf # (wordlength, c_word length, AddressSize, rom_AddressSize, muit_scale) fft (.in_xr (i_data), // FFT input data, I. . in_xi (q_data), // FFT input data, Q .clk (clk), // Master clock. .nrst (nrst), // Power-up reset. . in_2k8k (in_2k8k), // 2K active low. .valid_in (vaiid_win 2_fft), // lnput valid. . out_xr (i_out), // FFT output data, I. out_xi (q_out), // FFT output data, Q.. out_ovf (out_ovf), // Overflow flag. .enable_0 (enable_0), enable_l (enable_l), enable_2 (enable_2), enable_3 (ram_rnotw_fft_2_win), .valid_out (valid_out), ram_address (ram_addr_fft_2_win), ram_enable (ram_enable_fft_2_win) address_rom3 (rom3_addr), address_rom4 (rom4_addr), // RAM input ports. . z2r_4 (ram4_in [wordlength-1: 0]), z2i_4 (ram4_in [wordlength * 2-l: wordlength]),. z2r_5 (ram5_in [wordlength-1: 0]), z2i_5 (ram5_in [wordlength * 2-l: wordlength]),. z2r_6 (ram6_in [wordlength-1: 0]), z2i_6 (ram6_in [wordlength * 2-l: wordlength]), z2r_7 (ram7_in [wordlength-l: 0]), z2i_7 (ram7_in [wordlength2-l: wordlength]), . z2r_8 (ram8_in [wordlength-1: 0]) z2i_8 (ram8_in [wordlength * 2-l: wordlength]),. z2r_9 (ram9_in [wordlength-1: 0]), z2i_9 (ram9_in [wordlength * 2 - l: wordlength]), .z2r_l 0 (z2r_10), // Frm FFT datapath to window (I z2i_l 0 (z2i_10), // Frm FFT datapath to window (Q) // RAM output ports. .xlr_4 (ram4_out [wordlength-1: 0]) xli_4 (ram4_out [wordlength * 2-l -.wordlength]), .xlr_5 (ram5_out [wordlength-1: 0]), xli_5 (ram5_out [wordlength * 2-l: wordlength]), .xlr_6 (ram6_out [wordlength- 1: 0]), xli_6 (ram6_out [wordlength * 2-l: wordlength]), .xlr_7 (ram7_out [wordlength-1: 0]) xli_7 (ram7_out [wordlength * 2-l: wordlength]), .xlr_8 (ram8_out [wordlength-1: 0]), xli_8 (ram8_out [wordlength * 2-l: wordlength]), .xlr_9 (ram9_out [wordlength-1: 0]), xli_9 (ram9_out [wordlength * 2-l: wordlength]). xlr_l O (xl r_10), // To FFT datapath frm window (I) xli_l 0 (xl i_10), // To FFT datapath frm window (Q). // ROM output ports. br_3 (rom3_data [c_wordlength * 2-l : c_wordlength]), bi_3 (rom3_data [c_wordlength-l: 0]), br_4 (rom4_data [c_wordlength * 2-1: c_wordlength]) bi_4 (rom4_data [c_wordlength-l: 0])), // // Instance FFT window process r. // fft_window # (wordlength, r_wordlength, AddressSize, FIFO_L, FlFO_L_bits, FIFO_N, FlFO_n, FIFO_A, FlFO_A_bÍtS, lu_AddressSize, delta, acquired_symbols, pos_threshold t_offset_th reshold, w advance, sincint_latency iqdemod_latency) window (.in_xr (i_data), .in_xi ( q_data), .clk (clk), .nrst (nrst), .valid_in (valid_in), .valid_out (valid_win_2 fft),. i n_resync (in_resync),. out_iqgi (out_iqgi), .out_sincgi (out_sincgi),. out_rx_guard ( out_rx_guard),. out_acquired (out_acquired),. out_fft_window (out_fft_window),. enable_3_4 (enable_3), .out_test (out_test),. track_ram_address (track_addr), .xri_tmpl (track_data_in), .xri_tmp5 (track_data_out),. track_ram_rnotw (track_rnw) .track_ram_enabie (track_ram_enable),. ram_addr (ram_addr),. ram_enable (ram_enable),. ram_rnotw (ram_rnotw) ". raml0_in (ramio in), // To 1K x 24 bit RAM. . ramlO_out (ramlO_out), // From 1K x 24 bit RAM. .xlr_10 (xlr_10), // To FFTdatapath (1). .xl i_l O (xli_10), // To FFT datapath (Q). .z2r_10 (z2r_10), // From FFT datapath (I). z2i_10 (z2i_10), // From FFT datapath (Q). fft_ram_rnotw (ram_rnotw_fft_2_win),. fft_ram_enable (ram_enable_fft_2_win),, fft_ram_addr (ram_addr_fft_2_win)); endmodule Listing 16 // 2048 point FFT twiddle factor coeffcients (Radix 4 + 2). // Coefficients stored as non-fractional 10 bit integers (scale 1). // Real Coefficient (cosine valué) is coeffcient high-byte. // Imaginary Coefficient (sine valué) is coeffcient low-byte. 0111111111_0000000000 //W0000_2048=+l.000000 -0.000000 0111111111_1111111110 //W0001_2048=+0.999995 -0.003068 0111111111_1111111101 //W0002_2048=+0.999981 -0.006136 0111111111_1111111011 //W0003_2048=+0.999958 -0.009204 0111111111_1111111010 //W0004_2048=+0.999925 -0.012272 0111111111_1111111000 //W0005_2048=+0.999882 -0.015339 0111111111_1111110111 //W0006_2048=+0.999831 -0.018407 0111111111_1111110101 //W0007_2048=+0.999769 -0.021474 0111111111_11__1110011 //W0008_2048=+0.999699 -0.024541 0111111111 1111110010 // W0009 2048 = + 0.999619 -0.027608 0111111111_1111110000 //W0010_2048=+0.999529 -0.030675 0111111111_1111101111 //W0011_2048=+0.999431 -0.033741 0111111111_1111101101 //W0012_2048=+0.999322 -0.036807 0111111111_1111101100 //W0013_2048=+0.999205 -0.039873 0111111111_1111101010 //W0014_2048=+0.999078 -0.042938 0111111111_1111101000 // W0015_2048 = + 0. 98941 -0.046003 0111111111_1111100111 //W0016_2048=+0.998795 -0.049068 0111111111_1111100101 //W0017_2048=+0.998640 -0.052132 0111111111_1111100100 //W0018_2048=+0.998476 -0.055195 0111111111_1111100010 //W0019_2048=+0.998302 -0.058258 0111111111_1111100001 //W0020_2048=+0.998118 -0.061321 0111111111_1111011111 //W0021_2048=+0.997925 -0.064383 0111111111_1111011101 //W0022_2048=+0.997723 -0.067444 0111111111_1111011100 //W0023_2048=+0.997511 -0.070505 0111111111_1111011010 //W0024_2048=+0.997290 -0.073565 0111111110_1111011001 //W0025_2048=+0.997060 -0.076624 0111111110_1111010111 //W0026_2048=+0.996820 -0.079682 0111111110_1111010110 //W0027_2048=+0.996571 -0.082740 0111111110_1111010100 //W0028_2048=+0.996313 -0.085797 0111111110_1111010011 //W0029_2048=+0.996045 -0.088854 0111111110_1111010001 //W0030_2048=+0.995767 -0.091909 0111111110_1111001111 //W0031_2048=+0.995481 -0.094963 0111111110_1111001110 //W0032_2048=+0.995185 -0.098017 0111111101_1111001100 //W0033_2048=+0.994879 -0.101070 0111111101 1111001011 // W0034 2048 = + 0.994565 -0.104122 0111111101_1111001001 //W0035_2048=+0.994240 -0.107172 0111111101_1111001000 //W0036_2048=+0.993907 -0.110222 0111111101_1111000110 //W0037_2048=+0.993564 -0.113271 0111111101_1111000100 // W0038_2048 = + 0. 93212 -0.116319 0111111100_1111000011 //W0039_2048=+0.992850 -0.119365 0111111100_1111000001 //W0040_2048=+0.992480 -0.122411 0111111100_1111000000 // W0041_2048 = + 0. 92099 -0.125455 0111111100_1110111110 //W0042_2048=+0.991710 -0.128498 0111111100_1110111101 //W0043_2048=+0.991311 -0.131540 0111111011_1110111011 //W0044_2048=+0.990903 -0.134581 0111111011_1110111010 //W0045_2048=+0.990485 -0.137620 0111111011_1110111000 //W0046_2048=+0.990058 -0.140658 0111111011_1110110110 //W0047_2048=+0.989622 -0.143695 0111111010_1110110101 //W0048_2048=+0.989177 -0.146730 0111111010_1110110011 //W0049_2048=+0.988722 -0.149765 0111111010_1110110010 //W0050_2048=+0.988258 -0.152797 0111111010_1110110000 //W0051_2048=+0.987784 -0.155828 0111111001_1110101111 //W0052_2048=+0.987301 -0.158858 0111111001_11I0101101 //W0053_2048=+0.986809 -0.161886 0111111001_1110101100 //W0054_2048=+0.986308 -0.164913 0111111001_1110101010 //W0055_2048=+0.985798 -0.167938 0111111000_1110101000 //W0056_2048=+0.985278 -0.170962 0111111000_1110100111 //W0057_2048=+0.984749 -0.173984 0111111000_1110100101 // W0058_2048 = + 0.984210 -0.177004 0111111000 1110100100 // W0059 2048 = + 0.983662 -0.180023 0111110111_1110100010 //W0060_2048=+0.983105 -0.183040 0111110111_1110100001 //W0061_2048=+0.982539 -0.186055 0111110111_1110011111 //W0062_2048=+0.981964 -0.189069 0111110110_1110011110 //W0063_2048=+0.981379 -0.192080 0111110110_1110011100 //W0064_2048=+0.980785 -0.195090 0111110110_1110011011 //W0065_2048=+0.980182 -0.198098 0111110110_1110011001 //W0066_2048=+0.979570 -0.201105 0111110101_1110010111 //W0067_2048=+0.978948 -0.204109 0111110101_1110010110 //W0068_2048=+0.978317 -0.207111 0111110101_1110010100 //W0069_2048=+0.977677 -0.210112 0111110100_1110010011 //W0070_2048=+0.977028 -0.213110 0111110100_1110010001 //W0071_2048=+0.976370 -0.216107 0111110100_1110010000 //W0072_2048=+0.975702 -0.219101 0111110011_1110001110 //W0073_2048=+0.975025 -0.222094 0111110011_1110001101 //W0074_2048=+0.974339 -0.225084 0111110011_1110001011 //W0075_2048=+0.973644 -0.228072 0111110010_1110001010 //W0076_2048=+0.972940 -0.231058 0111110010_1110001000 //W0077_2048=+0.972226 -0.234042 0111110001_1110000111 //W0078_2048=+0.971504 -0.237024 0111110001_1110000101 //W0079_2048=+0.970772 -0.240003 0111110001_1110000100 //W0080_2048=+0.970031 -0.242980 0111110000_1110000010 //W0081_2048=+0.969281 -0.245955 0111110000_1110000001 //W0082_2048=+0.968522 -0.248928 0111101111_1101111111 //W0083_2048=+0.967754 -0.251898 0111101111 1101111110 // W0084 2048 = + 0.966976 -0.254866 0111101111_1101111100 //W0085_2048=+0.966190 -0.257831 0111101110_1101111010 //W0086_2048=+0.965394 -0.260794 0111101110_1101111001 //W0087_2048=+0.964590 -0.263755 0111101101_1101110111 //W0088_2048=+0.963776 -0.266713 0111101101_1101110110 //W0089_2048=+0.962953 -0.269668 0111101101_1101110100 //W0090_2048=+0.962121 -0.272621 0111101100_1101110011 //W0091_2048=+0.961280 -0.275572 0111101100_1101110001 //W0092_2048=+0.960431 -0.278520 0111101011_1101110000 //W0093_2048=+0.959572 -0.281465 0111101011_1101101110 //W0094_2048=+0.958703 -0.284408 0111101010_1101101101 //W0095_2048=+0.957826 -0.287347 0111101010_1101101011 //W0096_2048=+0.956940 -0.290285 0111101001_1101101010 //W0097_2048=+0.956045 -0.293219 0111101001_1101101000 //W0098_2048=+0.955141 -0.296151 0111101001_1101100111 //W0099_2048=+0.954228 -0.299080 0111101000_1101100101 //W0100_2048=+0.953306 -0.302006 0111101000_1101100100 //W0101_2048=+0.952375 -0.304929 0111100111_1101100010 //W0102_2048=+0.951435 -0.307850 0111100111_1101100001 //W0103_2048=+0.950486 -0.310767 0111100110_1101011111 //W0104_2048=+0.949528 -0.313682 0111100110_1101011110 //W0105_2048=+0.948561 -0.316593 0111100101_1101011100 //W0106_2048=+0.947586 -0.319502 0111100101_1101011011 //W0107_2048=+0.946601 -0.322408 0111100100_1101011001 //W0108_2048=+0.945607 -0.325310 0111100100 1101011000 // W0109 2048 = + 0.944605 -0.328210 0111100011_1101010110 //W0110_2048=+0.943593 -0.331106 0111100011_1101010101 //W0111_2048=+0.942573 -0.334000 0111100010_1101010100 //W0112_2048=+0.941544 -0.336890 0111100010_1101010010 //W0113_2048=+0.940506 -0.339777 0111100001_1101010001 //W0114_2048=+0.939459 -0.342661 0111100000_1101001111 //W0115_2048=+0.938404 -0.345541 0111100000_1101001110 //W0116_2048=+0.937339 -0.348419 0111011111_1101001100 //W0117_2048=+0.936266 -0.351293 0111011111_1101001011 //W0118_2048=+0.935184 -0.354164 0111011110_1101001001 //W0119_2048=+0.934093 -0.357031 0111011110_1101001000 //W0120_2048=+0.932993 -0.359895 0111011101_1101000110 //W0121_2048=+0.931884 -0.362756 0111011101_1101000101 //W0122_2048=+0.930767 -0.365613 0111011100_1101000011 //W0123_2048=+0.929641 -0.368467 0111011011_1101000010 //W0124_2048=+0.928506 -0.371317 0111011011_1101000000 //W0125_2048=+0.927363 -0.374164 0111011010_1100111111 //W0126_2048=+0.926210 -0.377007 0111011010_1100111110 //W0127_2048=+0.925049 -0.379847 0111011001_1100111100 //W0128_2048=+0.923880 -0.382683 0111011000_1100111011 //W0129_2048=+0.922701 -0.385516 0111011000_1100111001 //W0130_2048=+0.921514 -0.388345 0111010111_1100111000 //W0131_2048=+0.920318 -0.391170 0111010111_1100110110 //W0132_2048=+0.919114 -0.393992 0111010110_1100110101 //W0133_2048=+0.917901 -0.396810 0111010101 1100110011 // W0134 2048 = + 0.916679 -0.399624 0111010101_1100110010 //W0135_2048=+0.915449 -0.402435 0111010100_1100110001 //W0136_2048=+0.914210 -0.405241 0111010011_1100101111 //W0137_2048=+0.912962 -0.408044 0111010011_1100101110 //W0138_2048=+0.911706 -0.410843 0111010010_1100101100 //W0139_2048=+0.910441 -0.413638 0111010001_1100101011 //W0140_2048=+0.909168 -0.416430 0111010001_1100101001 //W0141_2048=+0.907886 -0.419217 0111010000_1100101000 //W0142_2048=+0.906596 -0.422000 0111010000_1100100111 //W0143_2048=+0.905297 -0.424780 0111001111_1100100101 //W0144_2048=+0.903989 -0.427555 0111001110_1100100100 //W0145_2048=+0.902673 -0.430326 0111001101_1100100010 //W0146_2048=+0.901349 -0.433094 0111001101_1100100001 //W0147_2048=+0.900016 -0.435857 0111001100_1100011111 //W0148_2048=+0.898674 -0.438616 0111001011_1100011110 //W0149_2048=+0.897325 -0.441371 0111001011_1100011101 //W0150_2048=+0.895966 -0.444122 0111001010_1100011011 //W0151_2048=+0.894599 -0.446869 0111001001_1100011010 //W0152_2048=+0.893224 -0.449611 0111001001_1100011000 //W0153_2048=+0.891841 -0.452350 0111001000_1100010111 //W0154_2048=+0.890449 -0.455084 0111000111_1100010110 //W0155_2048=+0.889048 -0.457813 0111000110_1100010100 //W0156_2048=+0.887640 -0.460539 0111000110_1100010011 //W0157_2048=+0.886223 -0.463260 0111000101_1100010001 //W0158_2048=+0.884797 -0.465976 0111000100 1100010000 // W0159 2048 = + 0.883363 -0.468689 0111000100_1100001111 //W0160_2048=+0.881921 -0,471,397 0111000011_1100001101 //W0161_2048=+0.880471 -0.474100 0111000010_1100001100 //W0162_2048=+0.879012 -0.476799 0111000001_1100001010 //W0163_2048=+0.877545 -0.479494 0111000001_1100001001 //W0164_2048=+0.876070 -0.482184 0111000000_1100001000 //W0165_2048=+0.874587 -0.484869 0110111111_1100000110 //W0166_2048=+0.873095 -0.487550 0110111110_1100000101 //W0167_2048=+0.871595 -0.490226 0110111101_1100000100 //W0168_2048=+0.870087 -0.492898 0110111101_1100000010 //W0169_2048=+0.868571 -0.495565 0110111100_1100000001 //W0170_2048=+0.867046 -0.498228 0110111011_1100000000 //W0171_2048=+0.865514 -0.500885 0110111010_1011111110 //W0172_2048=+0.863973 -0.503538 0110111010_1011111101 //W0173_2048=+0.862424 -0.506187 0110111001_1011111011 //W0174_2048=+0.860867 -0.508830 0110111000_1011111010 //W0175_2048=+0.859302 -0.511469 0110110111_1011111001 //W0176_2048=+0.857729 -0.514103 0110110110_1011110111 //W0177_2048=+0.856147 -0.516732 0110110110_1011110110 //W0178_2048=+0.854558 -0.519356 0110110101_1011110101 //W0179_2048=+0.852961 -0.521975 0110110100_1011110011 //W0180_2048=+0.851355 -0.524590 0110110011_1011110010 //W0181_2048=+0.849742 -0.527199 0110110010_1011110001 //W0182_2048=+0.848120 -0.529804 0110110001_1011101111 //W0183_2048=+0.846491 -0.532403 0110110001 1011101110 // W0184 2048 = + 0.844854 -0.534998 -0.537587 0110110000_1011101101 //W0185_2048=+0.843208 0110101111_1011101011 //W0186_2048=+0.841555 -0.540171 0110101110_1011101010 //W0187_2048=+0.839894 -0.542751 0110101101_1011101001 //W0188_2048=+0.838225 -0.545325 0110101100_1011100111 //W0189_2048=+0.836548 -0.547894 0110101011_1011100110 //W0190_2048=+0.834863 -0.550458 0110101011_1011100101 //W0191_2048=+0.833170 -0.553017 0110101010_1011100100 //W0192_2048=+0.831470 -0.555570 0110101001_1011100010 //W0193_2048=+0.829761 -0.558119 0110101000_1011100001 //W0194_2048=+0.828045 -0.560662 0110100111_1011100000 //W0195_2048=+0.826321 -0.563199 0110100110_1011011110 //W0196_2048=+0.824589 -0.565732 0110100101_1011011101 //W0197_2048=+0.822850 -0.568259 0110100100_1011011100 //W0198_2048=+0.821103 -0.570781 0110100100_1011011010 //W0199_2048=+0.819348 -0.573297 0110100011_1011011001 //W0200_2048=+0.817585 -0.575808 0110100010_1011011000 //W0201_2048=+0.815814 -0.578314 0110100001_1011010111 //W0202_2048=+0.814036 -0.580814 0110100000_1011010101 //W0203_2048=+0.812251 -0.583309 0110011111_1011010100 //W0204_2048=+0.810457 -0.585798 0110011110_1011010011 //W0205_2048=+0.808656 -0.588282 0110011101_1011010010 //W0206_2048=+0.806848 -0.590760 0110011100_1011010000 //W0207_2048=+0.805031 -0.593232 0110011011_1011001111 //W0208_2048=+0.803208 -0.595699 0110011010 1011001110 // W0209 2048 = + 0.801376 -0.598161 -0.600616 0110011001_1011001100 //W0210_2048=+0.799537 0110011000_1011001011 //W0211_2048=+0.797691 -0.603067 0110010111_1011001010 //W0212_2048=+0.795837 -0.605511 0110010111_1011001001 //W0213_2048=+0.793975 -0.607950 0110010110_1011000111 //W0214_2048=+0.792107 -0.610383 0110010101_1011000110 //W0215_2048=+0.790230 -0.612810 0110010100_1011000101 //W0216_2048=+0.788346 -0.615232 0110010011_1011000100 //W0217_2048=+0.786455 -0.617647 0110010010_1011000011 //W0218_2048=+0.784557 -0.620057 0110010001_1011000001 //W0219_2048=+0.782651 -0.622461 0110010000_1011000000 //W0220_2048=+0.780737 -0.624859 0110001111_1010111111 //W0221_2048=+0.778817 -0.627252 0110001110_1010111110 //W0222_2048=+0.776888 -0.629638 0110001101_1010111100 //W0223_2048=+0.774953 -0.632019 0110001100_1010111011 //W0224_2048=+0.773010 -0.634393 0110001011_1010111010 //W0225_2048=+0.771061 -0.636762 0110001010_1010111001 //W0226_2048=+0.769103 -0.639124 0110001001_1010111000 //W0227_2048=+0.767139 -0.641481 0110001000_1010110110 //W0228_2048=+0.765167 -0.643832 0110000111_1010110101 //W0229_2048=+0.763188 -0.646176 0110000110_1010110100 //W0230_2048=+0.761202 -0.648514 0110000101_1010110011 //W0231_2048=+0.759209 -0.650847 0110000100_1010110010 //W0232_2048=+0.757209 -0.653173 0110000011_1010110000 //W0233_2048=+0.755201 -0.655493 0110000010 1010101111 // W0234 2048 = + 0.753187 -0.657807 0110000001AL010101110 //W0235_2048=+0.751165 -0.660114 0110000000_1010101101 //W0236_2048=+0.749136 -0.662416 0101111111_1010101100 //W0237_2048=+0.747101 -0.664711 0101111101AL010101010 //W0238_2048=+0.745058 -0.667000 0101111100_1010101001 //W0239_2048=+0.743008 -0.669283 0101111011_1010101000 //W0240_2048=+0.740951 -0.671559 0101111010_1010100111 //W0241_2048=+0.738887 -0.673829 0101111001_1010100110 //W0242_2048=+0.736817 -0.676093 0101111000__1010100101 //W0243_2048=+0.734739 -0.678350 0101110111_1010100100 //W0244_2048=+0.732654 -0.680601 0101110110_1010100010 //W0245_2048=+0.730563 -0.682846 0101110101_1010100001 //W0246_2048=+0.728464 -0.685084 0101110100_1010100000 //W0247_2048=+0.726359 -0.687315 0101110011_1010011111 //W0248_2048=+0.724247 -0.689541 0101110010_1010011110 //W0249_2048=+0.722128 -0.691759 0101110001_1010011101 //W0250_2048=+0.720003 -0.693971 0101110000_1010011100 //W0251_2048=+0.717870 -0.696177 0101101110_1010011010 //W0252_2048=+0.715731 -0.698376 0101101101_1010011001 //W0253_2048=+0.713585 -0.700569 0101101100_1010011000 //W0254_2048=+0.711432 -0.702755 0101101011_1010010111 //W0255_2048=+0.709273 -0.704934 0101101010_1010010110 //W0256_2048=+0.707107 -0.707107 0101101001_1010010101 //W0257_2048=+0.704934 -0.709273 0101101000_1010010100 //W0258_2048=+0.702755 -0.711432 0101100111 1010010011 // W0259 2048 = + 0.700569 -0.713585 0101100110_1010010010 //W0260_2048=+0.698376 -0.715731 0101100100_1010010000 //W0261_2048=+0.696177 -0.717B70 0101100011_1010001111 //W0262_2048=+0.693971 -0.720003 0101100010_1010001110 //W0263_2048=+0.691759 -0.722128 0101100001_1010001101 //W0264_2048=+0.689541 -0.724247 0101100000_1010001100 /lW0265_2048=+0.687315 -0.726359 0101011111_1010001011 //W0266_2048=+0.685084 -0.728464 0101011110_1010001010 //W0267_2048=+0.682846 -0.730563 0101011100_1010001001 //W0268_2048=+0.680601 -0.732654 0101011011_1010001000 //W0269_2048=+0.678350 -0.734739 0101011010_1010000111 //W0270_2048=+0.676093 -0.736817 0101011001_1010000110 //W0271_2048=+0.673829 -0.738887 0101011000_1010000101 //W0272_2048=+0.671559 -0.740951 0101010111_1010000100 //W0273_2048=+0.669283 -0.743008 0101010110_1010000011 //W0274_2048=+0.667000 -0.745058 0101010100_1010000001 //W0275_2048=+0.664711 -0.747101 0101010011_1010000000 //W0276_2048=+0.662416 -0.749136 0101010010_1001111111 //W0277_2048=+0.660114 -0.751165 0101010001_1001111110 //W0278_2048=+0.657807 -0.753187 0101010000_1001111101 //W0279_2048=+0.655493 -0.755201 0101001110_1001111100 //W0280_2048=+0.653173 -0.757209 0101001101_1001111011 //W0281_2048=+0.650847 -0.759209 0101001100_1001111010 //W0282_2048=+0.648514 -0.761202 0101001011_1001111001 //W0283_2048=+0.646176 -0.763188 0101001010 1001111000 // W0284 2048 = + 0.643832 -0.765167 0101001000_1001110111 //W0285_2048=+0.641481 -0.767139 0101000111_1001110110 //W0286_2048=+0.639124 -0.769103 0101000110_1001110101 //W0287_2048=+0.636762 -0.771061 0101000101_1001110100 //W0288_2048=+0.634393 -0.773010 0101000100_1001110011 //W0289_2048=+0.632019 -0.774953 0101000010_1001110010 //W0290_2048=+0.629638 -0.776888 0101000001_1001110001 //W0291_2048=+0.627252 -0.778817 0101000000_1001110000 //W0292_2048=+0.624859 -0.780737 0100111111_1001101111 //W0293_2048=+0.622461 -0.782651 0100111101_1001101110 //W0294_2048=+0.620057 -0.784557 0100111100_1001101101 //W0295_2048=+0.617647 -0.786455 0100111011_1001101100 //W0296_2048=+0.615232 -0.788346 0100111010_1001101011 //W0297_2048=+0.612810 -0.790230 0100111001_1001101010 //W0298_2048=+0.610383 -0.792107 0100110111_1001101001 //W0299_2048=+0.607950 -0.793975 0100110110_1001101001 //W0300_2048=+0.605511 -0.795837 0100110101_1001101000 //W0301_2048=+0.603067 -0.797691 0100110100_1001100111 //W0302_2048=+0.600616 -0.799537 0100110010_1001100110 //W0303_2048=+0.598161 -0.801376 0100110001_1001100101 //W0304_2048=+0.595699 -0.803208 0100110000_1001100100 //W0305_2048=+0.593232 -0.805031 0100101110_1001100011 //W0306_2048=+0.590760 -0.806848 0100101101_1001100010 //W0307_2048=+0.588282 -0.808656 0100101100_1001100001 //W0308_2048=+0.585798 -0.810457 0100101011 1001100000 // W0309 2048 = + 0.583309 -0.812251 0100101001_1001011111 //W0310_2048=+0.580814 -0.814036 0100101000_1001011110 //W0311_2048=+0.578314 -0.815814 0100100111_1001011101 //W0312_2048=+0.575808 -0.817585 0100100110_1001011100 //W0313_2048=+0.573297 -0.819348 0100100100_1001011100 //W0314_2048=+0.570781 -0.821103 0100100011_1001011011 //W0315_2048=+0.568259 -0.822850 0100100010_1001011010 //W0316_2048=+0.565732 -0.824589 0100100000_1001011001 //W0317_2048=+0.563199 -0.826321 0100011111_1001011000 //W0318_2048=+0.560662 -0.828045 0100011110_1001010111 //W0319_2048=+0.558119 -0.829761 0100011100_1001010110 //W0320_2048=+0.555570 -0.831470 0100011011_1001010101 //W0321_2048=+0.553017 -0 833170 0100011010_1001010101 //W0322_2048=+0.550458 -0.834863 0100011001_1001010100 //W0323_2048=+0.547894 -0.836548 0100010111_1001010011 //W0324_2048=+0.545325 -0.838225 0100010110_1001010010 //W0325_2048=+0.542751 -0.839894 0100010101_1001010001 //W0326_2048=+0.540171 -0.841555 0100010011_1001010000 //W0327_2048=+0.537587 -0.843208 0100010010_1001001111 //W0328_2048=+0.534998 -0.844854 0100010001_1001001111 //W0329_2048=+0.532403 -0.846491 0100001111_1001001110 //W0330_2048=+0.529804 -0.848120 0100001110_1001001101 //W0331_2048=+0.527199 -0.849742 0100001101_1001001100 //W0332_2048=+0.524590 -0.851355 0100001011_1001001011 //W0333_2048=+0.521975 -0.852961 0100001010 1001001010 // W0334 2048 = + 0.519356 -0.854558 0100001001_1001001010 //W0335_2048=+0.516732 -0.856147 0100000111_1001001001 //W0336_2048=+0.514103 -0.857729 0100000110_1001001000 //W0337_2048=+0.511469 -0.859302 0100000101_1001000111 //W0338_2048=+0.508830 -0.860867 0100000011_1001000110 //W0339_2048=+0.506187 -0.862424 0100000010_1001000110 //W0340_2048=+0.503538 -0.863973 0100000000_1001000101 //W0341_2048=+0.500885 -0.865514 0011111111_1001000100 //W0342_2048=+0.498228 -0.867046 0011111110_1001000011 //W0343_2048=+0.495565 -0.868571 0011111100_1001000011 //W03_2048=+0.492898 -0.870087 0011111011_1001000010 //W0345_2048=+0.490226 -0.871595 0011111010_1001000001 // W0346_2048 = + 0. 87550 -0.873095 0011111000_1001000000 //W0347_2048=+0.484869 -0.874587 0011110111_1000111111 //W0348_2048=+0.482184 '-0.876070 0011110110_1000111111 //W0349_2048=+0.479494 -0.877545 0011110100_1000111110 //W0350_2048=+0.476799 -0.879012 0011110011_1000111101 //W0351_2048=+0.474100 -0.880471 0011110001_1000111100 //W0352_2048=+0.471397 -0.881921 0011110000_1000111100 //W0353_2048=+0.468689 -0.883363 0011101111_1000111011 //W0354_2048=+0.465976 -0.884797 0011101101_1000111010 //W0355_2048=+0.463260 -0.886223 0011101100_1000111010 //W0356_2048=+0.460539 -0.887640 0011101010_1000111001 //W0357_2048=+0.457813 -0.889048 0011101001_1000111000 //W0358_2048=+0.455084 -0.890449"0011101000 1000110111 // W0359 2048 = + 0.452350 -0.891841 0011100110_1000110111 //W0360_2048=+0.449611 -0.893224 0011100101_1000110110 //W0361_2048=+0.446869 -0.894599 0011100011_1000110101 //W0362_2048=+0.444122 -0.895966 0011100010_1000110101 //W0363_2048=+0.441371 -0.897325 0011100001_1000110100 //W0364_2048=+0.438616 -0.898674 0011011111_1000110011 //W0365_2048=+0.435857 -0.900016 0011011110_1000110011 //W0366_2048=+0.433094 -0.901349 0011011100_1000110010 //W0367_2048=+0.430326 -0.902673 0011011011_1000110001 //W0368_2048=+0.427555 -0.903989 0011011001_1000110000 //W0369_2048=+0.424780 -0.905297 0011011000_1000110000 //W0370_2048=+0.422000 -0.906596 0011010111_1000101111 //W0371_2048=+0.419217 -0.907886 0011010101_1000101111 //W0372_2048=+0.416430 -0.909168 0011010100_1000101110 //W0373_2048=+0.413638 -0.910441 0011010010_1000101101 //W0374_2048=+0.410843 -0.911706 0011010001_1000101101 //W0375_2048=+0.408044 -0.912962 0011001111_1000101100 //W0376_2048=+0.405241 -0.914210 0011001110_1000101011 //W0377_2048=+0.402435 -0.915449 0011001101_1000101011 //W0378_2048=+0.399624 -0.916679 0011001011_1000101010 //W0379_2048=+0.396810 -0.917901 0011001010_1000101001 //W0380_2048=+0.393992 -0.919114 0011001000_1000101001 //W0381_2048=+0.391170 -0.920318 0011000111_1000101000 //W0382_2048=+0.388345 -0.921514 0011000101_1000101000 //W0383_2048=+0.385516 -0.922701 0011000100 1000100111 // W0384 2048 = + 0.382683 -0.923880 0011000010_1000100110 //W0385_2048=+0.379847 -0.925049 0011000001_1000100110 //W0386_2048=+0.377007 -0.926210 0011000000_1000100101 //W0387_2048=+0.374164 -0.927363 0010111110_1000100101 //W0388_2048=+0.371317 -0.928506 0010111101_1000100100 //W0389_2048=+0.368467 -0.929641 0010111011_1000100011 //W0390_2048=+0.365613 -0.930767 0010111010_1000100011 //W0391_2048=+0.362756 -0.931884 0010111000_1000100010 //W0392_2048=+0.359895 '-0.932993 0010110111_1000100010 //W0393_2048=+0.357031 -0.934093 0010110101_1000100001 //W0394_2048=+0.354164 -0.935184 0010110100_1000100001 //W0395_2048=+0.351293 -0.936266 0010110010_1000100000 //W0396_2048=+0.348419 -0.937339 0010110001_1000100000 //W0397_2048=+0.345541 -0.938404 0010101111_1000011111 //W0398_2048=+0.342661 -0.939459 0010101110_1000011110 //W0399_2048=+0.339777 -0.940506 0010101100_1000011110 //W0400_2048=+0.336890 -0.941544 0010101011_1000011101 //W0401_2048=+0.334000 -0.942573 0010101010_1000011101 //W0402_2048=+0.331106 -0.943593 0010101000_1000011100 //W0403_2048=+0.328210 -0.944605 0010100111_1000011100 //W0404_2048=+0.325310 -0.945607 0010100101_1000011011 //W0405_2048=+0.322408 -0.946601 0010100100_1000011011 //W0406_2048=+0.319502 -0.947586 0010100010_1000011010 //W0407_2048=+0.316593 -0.948561 0010100001_1000011010 //W0408_2048=+0.313682 -0.949528 0010011111 1000011001 // W0409 2048 = + 0.310767 -0.950486 0010011110_1000011001 //W0410_2048=+0.307850 -0.951435 0010011100_1000011000 //W0411_2048=+0.304929 -0.952375 0010011011_1000011000 //W0412_2048=+0.302006 -0.953306 0010011001_1000010111 //W0413_2048=+0.299080 -0.954228 0010011000_1000010111 //W0414_2048=+0.296151 -0.955141 0010010110_1000010111 //W0415_2048=+0.293219 -0.956045 0010010101_1000010110 //W0416_2048=+0.290285 -0.956940 0010010011_1000010110 //W0417_2048=+0.287347 -0.957826 0010010010_1000010101 //W0418_2048=+0.284408 -0.958703 0010010000_1000010101 //W0419_2048=+0.281465 -0.959572 0010001111_1000010100 //W0420_2048=+0.278520 -0.960431 0010001101_1000010100 //W0421_2048=+0.275572 -0.961280 0010001100_1000010011 //W0422_2048=+0.272621 -0.962121 0010001010_1000Ó10011 //W0423_2048=+0.269668 -0.962953 0010001001_1000010011 //W0424_2048-+0.266713 -0.963776 0010000111_1000010010 //W0425_2048=+0.263755 -0.964590 0010000110_1000010010 //W0426_2048=+0.260794 -0.965394 0010000100_1000010001 //W0427_2048=+0.257831 -0.966190 0010000010_1000010001 //W0428_2048=+0.254866 -0.966976 0010000001_1000010001 //W0429_2048=+0.251898 -0.967754 0001111111_1000010000 //W0430_2048=+0.248928 -0.968522 0001111110_1000010000 //W0431_2048=+0.245955 -0.969281 0001111100_1000001111 //W0432_2048=+0.242980 -0.970031 000I111011_1000001111 //W0433_2048=+0.240003 -0.970772 0001111001 1000001111 // W0434 2048 = + 0.237024 -0.971504 0001111000_1000001110 //W0435_2048=+0.234042 -0.972226 0001110110_1000001110 //W0436_2048=+0.231058 -0.972940 0001110101_1000001101 //W0437_2048=+0.228072 -0.973644 0001110011_1000001101 //W0438_2048=+0.225084 -0.974339 0001110010_1000001101 //W0439_2048=+0.222094 -0.975025 0001110000_1000001100 //W0440_2048=+0.219101 -0.975702 0001101111_1000001100 //W0441_2048=+0.216107 -0.976370 0001101101_1000001100 //W0442_2048=+0.213110 -0.977028 0001101100_1000001011 //W0443_2048=+0.210112 -0.977677 0001101010_1000001011 //W0444_2048=+0.207111 -0.978317 0001101001_1000001011 //W0445_2048=+0.204109 -0.978948 0001100111_1000001010 //W0446_2048=+0.201105 -0.979570 0001100101_1000001010 //W0447_2048=+0.198098 -0.980182 0001100100_1000001010 //W0448_2048=+0.195090 -0.980785 0001100010_1000001010 //W0449_2048=+0.192080 -0.981379 0001100001_1000001001 //W0450_2048=+0.189069 -0.981964 0001011111_1000001001 //W0451_2048=+0.186055 -0.982539 0001011110_1000001001 //W0452_2048=+0.183040 -0.983105 0001011100_1000001000 //W0453_2048=+0.180023 -0.983662 0001011011_1000001000 //W0454_2048=+0.177004 -0.984210 0001011001_1000001000 //W0455_2048=+0.173984 -0.9749 0001011000_1000001000 //W0456_2048=+0.170962 -0.985278 0001010110_1000000111 //W0457_2048=+0.167938 -0.985798 0001010100_1000000111 //W0458_2048=+0.164913 -0.986308 0001010011 1000000111 // W0459 2048 = + 0.161886 -0.986809 0001010001_1000000111 //W0460_2048=+0.158858 -0.987301 0001010000_1000000110 //W0461_2048=+0.155828 -0.987784 0001001110_1000000110 //W0462_2048=+0.152797 -0.988258 0001001101_1000000110 //W0463_2048=+0.149765 -0.988722 0001001011_1000000110 //W0464_2048=+0.146730 -0.989177 0001001010_1000000101 //W0465_2048=+0.143695 -0.989622 0001001000_1000000101 //W0466_2048=+0.140658 -0.990058 0001000110_1000000101 //W0467_2048=+0.137620 -0.990485 0001000101_1000000101 //W0468_2048=+0.134581 -0.990903 0001000011_1000000100 //W0469_2048=+0.131540 -0.991311 0001000010_1000000100 //W0470_2048=+0.128498 -0.991710 0001000000_1000000100 //W0471_2048=+0.125455 -0.992099 0000111111_1000000100 //W0472_2048=+0.122411 -0.992480 0000111101_1000000100 //W0473_2048=+0.119365 -0.992850 0000111100_1000000011 //W0474_2048=+0.116319 -0.993212 0000111010_1000000011 //W0475_2048=+0.113271 -0.993564 0000111000_1000000011 //W0476_2048=+0.110222 -0.993907 0000110111_1000000011 //W0477_2048=+0.107172 -0.994240 0000110101_1000000011 // W0478_2048 = + 0104122 -0.994565 0000110100_1000000011 //W0479_2048=+0.101070 -0.994879 0000110010_1000000010 //W0480_2048=+0.098017 -0.995185 0000110001_1000000010 //W0481_2048=+0.094963 -0.995481 0000101111_1000000010 //W0482_2048=+0.091909 -0.995767 0000101101_1000000010 //W0483_2048=+0.088854 -0.996045 0000101100 1000000010 // W0484 2048 = + 0.085797 -0.996313 0000101010_1000000010 //W0485_2048=+0.082740 -0.996571 0000101001_1000000010 //W0486_2048=+0.079682 -0.996820 0000100111_1000000010 //W0487_2048=+0.076624 -0.997060 0000100110_1000000001 //W0488_2048=+0.073565 -0 997290 0000100100_1000000001 //W0489_2048=+0.070505 -0.997511 0000100011_1000000001 //W0490_2048=+0.067444 -0.997723 0000100001_1000000001 //W0491_2048=+0.064383 -0.997925 0000011111_1000000001 //W0492_2048=+0.061321 -0.998118 0000011110_1000000001 //W0493_2048=+0.058258 -0.998302 0000011100_1000000001 //W0494_2048=+0.055195 -0.998476 0000011011_1000000001 //W0495_2048=+0.052132 -0.998640 0000011001_1000000001 //W0496_2048=+0.049068 -0.998795 0000011000_1000000001 //W0497_2048=+0.046003 -0.998941 0000010110_1000000000 //W0498_2048=+0.042938 -0.999078 0000010100_1000000000 //W0499_2048=+0.039873 -0.999205 0000010011_1000000000 //W0500_2048=+0.036807 -0.999322 0000010001_1000000000 //W0501_2048=+0.033741 -0.999431 0000010000_1000000000 //W0502_2048=+0.030675 -0.999529 0000001110_1000000000 //W0503_2048=+0.027608 -0.999619 0000001101_1000000000 //W0504_2048=+0.024541 -0.999699 0000001011_1000000000 //W0505_2048=+0.021474 -0.999769 00Q0001001_1000000000 //W0506_2048=+0.018407 -0.999831 0000001000_1000000000 //W0507_2048=+0.015339 -0.999882 0000000110_1000000000 //W0508_2048=+0.012272 -0.999925 0000000101 1000000000 // W0509 2048 = + 0.009204 -0.999958 0000000011_1000000000 //W0510_2048=+0.006136 -0.999981 0000000010_1000000000 //W0511_2048=+0.003068 -0.999995 0000000000_1000000000 //W0512_2048=+0.000000 -1.000000 1111111110_1000000000 //W0513_2048=-0.003068 -0.999995 1111111101_1000000000 //W0514_2048=-0.006136 -0.999981 1111111010_1000000000 //W0516_2048=-0.012272 -0.999925 1111110111_1000000000 //W0518_2048=-0.018407 -0.999831 1111110101_1000000000 //W0519_2048=-0.021474 -0.999769 1111110011_1000000000 //W0520_2048=-0.024541 -0.999699 1111110000_1000000000 //W0522_2048=-0.030675 -0.999529 1111101101_1000000000 //W0524_2048=-0.036807 -0.999322 1111101100_1000000000 //W0525_2048=-0.039873 -0.999205 1111101010_1000000000 //W0526_2048=-0.042938 -0.999078 1111100111_1000000001 //W0528_2048=-0.049068 -0.998795 1111100100_1000000001 //W0530_2048=-0.055195 -0.998476 1111100010_1000000001 //W0531_2048=-0.058258 -0.998302 1111100001_1000000001 //W0532_2048=-0.061321 -0.998118 1111011101_1000000001 //W0534_2048=-0.067444 -0.997723 1111011010_1000000001 //W0536_2048=-0.073565 -0.997290 1111011001_1000000010 //W0537_2048=-0.076624 -0.997060 1111010111_1000000010 //W0538_2048=-0.079682 -0.996820 1111010100_1000000010 //W0540_2048=-0.085797 -0.996313 1111010001_1000000010 //W0542_2048=-0.091909 -0.995767 1111001111_1000000010 //W0543_2048=-0.094963 -0.995481 1111001110 1000000010 // W0544 2048 = -0.098017 -0.995185 1111001011_1000000011 //W0546_2048=-0.104122 -0.994565 1111001000_1000000011 //W0548_2048=-0.110222 -0.993907 1111000110_1000000011 //W0549_2048=-0.113271 -0.993564 1111000100_1000000011 //W0550_2048=-0.116319 -0.993212 1111000001_1000000100 //W0552_2048=-0.122411 -0.992480 1110111110_1000000100 //W0554_2048=-0.128498 -0.991710 1110111101_1000000100 //W0555_2048=-0.131540 -0.991311 1110111011_1000000101 //W0556_2048=-0.134581 -0.990903 1110111000_1000000101 //W0558_2048=-0.140658 -0.990058 1110110101_1000000110 //W0560_2048=-0.146730 -0.989177 1110110011_1000000110 //W0561_2048=-0.149765 -0.988722 1110110010_1000000110 //W0562_2048=-0.152797 -0.988258 1110101111_1000000111 //W0564_2048=-0.158858 -0.987301 1110101100_1000000111 //W0566_2048=-0.164913 -0.98638 1110101010_1000000111 //W0567_2048=-0.167938 -0.985798 1110101000_1000001000 //W0568_2048=-0.170962 -0.985278 1110100101_1000001000 //W0570_2048=-0.177004 -0.984210 1110100010_1000001001 //W0572_2048=-0.183040 -0.983105 1110100001_1000001001 //W0573_2048=-0.186055 -0.982539 1110011111_1000001001 //W0574_2048=-0.189069 -0.981964 1110011100_1000001010 //W0576_2048=-0.195090 -0.980785 1110011001_1000001010 //W0578_2048=-0.201105 -0.979570 1110010111_1000001011 //W0579_2048=-0.204109 -0.978948 1110010110_1000001011 //W0580_2048=-0.207111 -0.978317 1110010011 1000001100 // W0582 2048 = -0.213110 -0.977028 1110010000_1000001100 //W0584_2048=-0.219101 -0.975702 1110001110_1000001101 //W0585_2048=-0.222094 -0.975025 1110001101_1000001101 //W0586_2048=-0.225084 -0.974339 1110001010_1000001110 //W0588_2048=-0.231058 -0.972940 1110000111_1000001111 //W0590_2048=-0.237024 -0.971504 1110000101_1000001111 //W0591_2048=-0.240003 -0.970772 1110000100_1000001111 //W0592_2048=-0.242980 -0.970031 1110000001_1000010000 //W0594_2048=-0.248928 -0.968522 1101111110_1000010001 //W0596_2048=-0.254866 -0.966976 1101111100_1000010001 //W0597_2048=-0.257831 -0.966190 1101111010_1000010010 //W0598_2048=-0.260794 -0.965394 1101110111_1000010011 //W0600_2048=-0.266713 -0.963776 1101110100_1000010011 //W0602_2048=-0.272621 -0.962121 1101110011_1000010100 //W0603_2048=-0.275572 -0.961280 1101110001_1000010100 //W0604_2048=-0.278520 -0.960431 1101101110_1000010101 //W0606_2048=-0.284408 -0.958703 1101101011_1000010110 //W0608_2048=-0.290285 -0.956940 1101101010_1000010111 //W0609_2048=-0.293219 -0.956045 1101101000_1000010111 //W0610_2048=-0.296151 -0.955141 1101100101_1000011000 //W0612_2048=-0.302006 -0.953306 1101100010_1000011001 //W0614_2048=-0.307850 -0.951435 1101100001_1000011001 //W0615_2048=-0.310767 -0.950486 1101011111_1000011010 //W0616_2048=-0.313682 -0.949528 1101011100_1000011011 //W0618_2048=-0.319502 -0.947586 1101011001 1000011100 // W0620 2048 = -0.325310 -0.945607 1101011000_1000011100 //W0621_2048=-0.328210 -0.944605 1101010110_1000011101 //W0622_248=-0.331106 -0.943593 1101010100_1000011110 //W0624_2048=-0.336890 -0.941544 1101010001_1000011111 //W0626_2048=-0.342661 -0.939459 1101001111_1000100000 //W0627_2048=-0.345541 -0.938404 1101001110_1000100000 //W0628_2048=-0.348419 -0.937339 1101001011_1000100001 //W0630_2048=-0.354164 -0.935184 1101001000_1000100010 //W0632_2048=-0.359895 -0.932993 1101000110_1000100011 //W0633_2048=-0.362756 -0.931884 1101000101_1000100011 //W0634_2048=-0.365613 -0.930767 1101000010_1000100101 //W0636_2048=-0.371317 -0.928506 1100111111_1000100110 //W0638_2048=-0.377007 -0.926210 1100111110_1000100110 //W0639_2048=-0.379847 -0.925049 1100111100_1000100111 //W0640_2048=-0.382683 -0.923880 1100111001_1000101000 //W0642_2048=-0.388345 -0.921514 1100110110_1000101001 //W0644_2048=-0.393992 -0.919114 1100110101_1000101010 //W0645_2048=-0.396810 -0.917901 1100110011_1000101011 //W0646_2048=-0.399624 -0.916679 1100110001_1000101100 //W0648_2048=-0.405241 -0.914210 1100101110_1000101101 //W0650_2048=-0.410843 -0.911706 1100101100_1000101110 //W0651_2048=-0.413638 -0.910441 1100101011_1000101111 //W0652_2048=-0.416430 -0.909168 1100101000_1000110000 //W0654_2048=-0.422000 -0.906596 1100100101_1000110001 //W0656_2048=-0.427555 -0.903989 1100100100 1000110010 // W0657 2048 = -0.430326 -0.902673 1100100010_1000110011 //W0658_2048=-0.433094 -0.901349 1100011111_1000110100 //W0660_2048=-0.438616 -0.898674 1100011101_? 000110101 //W0662_2048=-0.444122 -0.895966 1100011011_1000110110 //W0663_2048=-0.446869 -0.894599 1100011010_1000110111 //W0664_2048=-0.449611 -0.893224 1100010111_1000111000 //W0666_2048=-0.455084 -0.890449 1100010100_1000111010 //W0668_2048=-0.460539 -0.887640 1100010011_1000111010 //W0669_2048=-0.463260 -0.886223 1100010001_1000111011 //W0670_2048=-0.465976 -0.884797 110? P? Llll_1000111100 //W0672_2048=-0.471397 -0.881921 1100001100_1000111110 //W0674_2048=-0.476799 -0.879012 1100001010_1000111111 //W0675_2048=-0.479494 -0.877545 1100001001_1000111111 //W0676_2048=-0.482184 -0.876070 1100000110_1001000001 //W0678_2048=-0.487550 -0.873095 1100000100_1001000011 //W0680_2048=-0.492898 -0.870087 1100000010_1001000011 //W0681_2048=-0.495565 -0.868571 1100000001_1001000100 //W0682_2048=-0.498228 -0.867046 1011111110_1001000110 //W0684_2048=-0.503538 -0.863973 1011111011_1001000111 //W0686_2048=-0.508830 -0.860867 1011111010_1001001000 //W0687_2048=-0.511469 -0.859302 1011111001_1001001001 //W0688_2048=-0.514103 -0.857729 1011110110_1001001010 //W0690_2048=-0.519356 -0.854558 1011110011_1001001100 //W0692_2048=-0.524590 -0.851355 1011110010_1001001101 //W0693_2048=-0.527199 -0.849742 1011110001 1001001110 // W0694 2048 = -0.529804 -0.848120 1011101110_1001001111 //W0696_2048=-0.534998 -0.844854 1011101011_1001010001 //W0698_2048=-0.540171 -0.841555 1011101010_1001010010 //W0699_2048=-0.542751 -0.839894 1011101001_1001010011 //W0700_2048=-0.545325 -0.838225 1011100110_1001010101 //W0702_2048=-0.550458 -0.834863 1011100100_1001010110 //W0704_2048=-0.555570 -0.831470 1011100010_1001010111 //W0705_2048=-0.558119 -0.829761 1011100001_1001011000 //W0706_2048=-0.560662 -0.828045 1011011110_1001011010 //W0708_2048=-0.565732 -0.824589 1011011100_1001011100 //W0710_2048=-0.570781 -0.821103 1011011010_1001011100 //W0711_2048=-0.573297 -0.819348 1011011001_1001011101 //W0712_2048=-0.575808 -0.817585 1011010111_1001011111 //W0714_2048=-0.580814 -0.814036 1011010100_1001100001 //W0716_2048=-0.585798 -0.810457 1011010011_1001100010 //W0717_2048=-0.588282 -0.808656 1011010010_1001100011 //W0718_2048=-0.590760 -0.806848 1011001111_1001100101 //W0720_2048=-0.595699 -0.803208 1011001100_1001100111 //W0722_2048=-0.600616 -0.799537 1011001011_1001101000 //W0723_2048=-0.603067 -0.797691 1011001010_1001101001 //W0724_2048=-0.605511 -0.795837 1011000111_1001101010 //W0726_2048=-0.610383 -0.792107 1011000101_1001101100 //W0728_2048=-0.615232 -0.788346 1011000100_1001101101 //W0729_2048=-0.617647 -0.786455 1011000011_1001101110 //W0730_2048=-0.620057 -0.784557 1011000000 1001110000 // W0732 2048 = -0.624859 -0.780737 1010111110_1001110010 //W0734_2048=-0.629638 -0.776888 1010111100_1001110011 //W0735_2048=-0.632019 -0.774953 1010111011_1001110100 //W0736_2048=-0.634393 -0.773010 1010111001_1001110110 //W0738_2048=-0.639124 -0.769103 1010110110_1001111000 //W0740_2048=-0.643832 -0.765167 1010110101_1001111001 //W0741_2048=-0.646176 -0.763188 1010110100_1001111010 //W0742_2048=-0.648514 -0.761202 1010110010_1001111100 //W0744_2048=-0.653173 -0.757209 1010101111_1001111110 //W0746_2048=-0.657807 -0.753187 1010101110_1001111111 //W0747_2048=-0.660114 -0.751165 1010101101_1010000000 //W0748_2048=-0.662416 -0.749136 1010101010_1010000011 //W0750_2048=-0.667000 -0.745058 1100010100_1000111010 //W0668_2048=-0.460539 -0.887640 1100010011_1000111010 //W0669_2048=-0.463260 -0.886223 1100010001_1000111011 //W0670_2048=-0.465976 -0.884797 1100001111_1000111100 //W0672_2048=-0.471397 -0.881921 1100001100_1000111110 //W0674_2048=-0.476799 -0.879012 1100001010_1000111111 // W0675_2048 = -0. 79494 -0.877545 1100001001_1000111111 //W0676_2048=-0.482184 -0.876070 1100000110_1001000001 //W0678_2048=-0.487550 -0.873095 1100000100_1001000011 //W0680_2048=-0.492898 -0.870087 1100000010_1001000011 //W0681_2048=-0.495565 -0.868571 1100000001_1001000100 //W0682_2048=-0.498228 -0.867046 1011111110_1001000110 //W0684_2048=-0.503538 -0.863973 1011111011 1001000111 // W0686 2048 = -0.508830 -0.860867 1011111010_1001001000 //W0687_2048=-0.511469 -0.859302 1011111001_1001001001 //W0688_2048=-0.514103 -0.857729 10111Í0110_1001001010 //W0690_2048=-0.519356 -0.854558 1011110011_1001001100 //W0692_2048=-0.524590 -0.851355 1011110010_1001001101 //W0693_2048=-0.527199 -0.849742 1011110001_1001001110 //W0694_2048=-0.529804 -0.848120 1011101110_1001001111 //W0696_2048=-0.534998 -0.844854 1011101011 1001010001 //W0698_2048=-0.540171 -0.841555 1011101010_1001010010 //W0699_2048=-0.542751 -0.839894 1011101001_1001010011 //W0700_2048=-0.545325 -0.838225 1011100110_1001010101 //W0702_2048=-0.550458 -0.834863 1011100100_1001010110 //W0704_2048=-0.555570 -0.831470 1011100010_1001010111 //W0705_2048=-0.558119 -0.829761 1011100001_1001011000 //W0706_2048=-0.560662 -0.828045 1011011110_1001011010 //W0708_2048=-0.565732 -0.824589 1011011100_1001011100 //W0710_2048=-0.570781 -0.821103 1011011010_1001011100 //W0711_2048=-0.573297 -0.819348 1011011001_1001011101 //W0712_2048=-0.575808 -0.817585 1011010111_1001011111 //W0714_2048=-0.580814 -0.814036 1011010100_1001100001 //W0716_2048=-0.585798 -0.810457 1011010011_1001100010 //W0717_2048=-0.588282 -0.808656 1011010010_1001100011 //W0718_2048=-0.590760 -0.806848 1011001111_1001100101 //W0720_2048=-0.595699 -0.803208 1011001100_1001100111 //W0722_2048=-0.600616 -0.799537 1011001011 1001101000 // W0723 2048 = -0.603067 -0.797691 1011001010_1001101001 //W0724_2048=-0.605511 -0.795837 1011000111_1001101010 //W0726_2048=-0.610383 -0.792107 1011000101AL001101100 //W0728_2048=-0.615232 -0.788346 1011000100_1001101101 //W0729_2048=-0.617647 -0.786455 1011000011_1001101110 //W0730_2048=-0.620057 -0.784557 1011000000_1001110000 //W0732_2048=-0.624859 -0.780737 1010111110_1001110010 //W0734_2048=-0.629638 -0.776888 1010111100_1001110011 //W0735_2048=-0.632019 -0.774953 1010111011_1001110100 //WQ736_2048=-0.634393 -0.773010 1010111001_1001110110 //W0738_2048=-0.639124 -0.769103 1010110110_1001111000 //W0740_2048=-0.643832 -0.765167 1010110101_1001111001 //W0741_2048=-0.646176 -0.763188 1010110100_1001111010 //W0742_2048=-0.648514 -0.761202 1010110010_1001111100 //W0744_2048=-0.653173 -0.757209 1010101111_1001111110 //W0746_2048=-0.657807 -0.753187 1010101110_1001111111 //W0747_2048=-0.660114 -0.751165 1010101101_1010000000 //W0748_2048=-0.662416 -0.749136 1010101010_1010000011 //W0750_2048=-0.667000 -0.745058 1010101000_1010000101 //W0752_2048=-0.671559 -0.740951 1010100111_1010000110 //W0753_2048=-0.673829 -0.738887 1010100110_1010000111 //W0754_2048=-0.676093 -0.736817 1010100100_1010001001 //W0756_2048=-0.680601 -0.732654 1010100001_1010001011 //W0758_2048=-0.685084 -0.728464 1010100000_1010001100 //W0759_2048=-0.687315 -0.726359 1010011111 1010001101 // W0760 2048 = -0.689541 -0.724247 1010011101_1010001111 //W0762_2048=-0.693971 -0.720003 1010011010_1010010010 //W0764_2048=-0.698376 -0.715731 1010011001_1010010011 //W0765_2048=-0.700569 -0.713585 1010011000_1010010100 //W0766_2048=-0.702755 -0.711432 1010010110_1010010110 //W0768_2048=-0.707107 -0.707107 1010010100_1010011000 //W0770_2048=-0.711432 -0.702755 1010010011_1010011001 //W0771_2048=-0.713585 -0.700569 1010010010_1010011010 //W0772_2048=-0.715731 -0.698376 1010001111_1010011101 //W0774_2048=-0.720003 -0.693971 1010001101_1010011111 //W0776_2048=-0.724247 -0.689541 1010001100_1010100000 //W0777_2048=-0.726359 -0.687315 1010001011_1010100001 //W0778_2048=-0.728464 -0.685084 1010001001_1010100100 //W0780_2048=-0.732654 -0.680601 1010000111_1010100110 //W0782_2048=-0.736817 -C.676093 101000011Q_1010100111 //W0783_204=-0.738887 -0.673829 1010000101_1010101000 //W0784_2048=-0.740951 -0.671559 1010000011_1010101010 //W0786_2048=-0.745058 -0.667000 1010000000_1010101101 //W0788_2048=-0.749136 -0.662416 1001111111_1010101110 //W0789_2048=-0.751165 -0.660114 1001111110_1010101111 //W0790_2048=-0.753187 -0.657807 1001111100_1010110010 //W0792_2048=-0.757209 -0.653173 1001111010_1010110100 //W0794_2048=-0.761202 -0.648514 1001111001_1010110101 //W0795_2048=-0.763188 -0.646176 1001111000_1010110110 //W0796_2048=-0.765167 -0.643832 1001110110 1010111001 // W0798 2048 = -0.769103 -0.639124 1001110100_1010111011 //W0800_2048=-0.773010 -0.634393 1001110011_1010111100 //W0801_2048=-0.774953 -0.632019 1001110010_1010111110 //W0802_2048=-0.776888 -0.629638 1001110000_1011000000 //W0804_2048=-0.780737 -0.624859 1001101110_1011000011 //W0806_2048=-0.784557 -0.620057 1. 001101101_1011000100 //W0807_2048=-0.786455 -0.617647 1001101100_1011000101 //W0808_2048=-0.788346 -0.615232 1001101010_1011000111 //W0810_2048=-0.792107 -0.610383 1001101001_1011001010 //W0812_2048=-0.795837 -0.605511 1001101000_1011001011 //W0813_2048=-0.797691 -0.603067 1001100111_1011001100 //W0814_2048=-0.799537 -0.600616 1001100101_1011001111 //W0816_2048=-0.803208 -0.595699 1001100011_1011010010 //W0818_2048=-0.806848 -0.590760 1001100010_1011010011 //W0819_2048=-0.808656 -0.588282 1001100001_1011010100 //W0820_2048=-0.810457 -0.585798 1001011111_1011010111 //W0822_2048=-0.814036 -0.580814 1001011101_1011011001 //W0824_2048=-0.817585 -0.575808 1001011100_1011011010 //W0825_2048=-0.819348 -0.573297 1001011100_1011011100 //W0826_2048=-0.821103 -0.570781 1001011010_1011011110 //W0828_2048=-0.824589 -0.565732 1001011000_1011100001 //W0830_2048=-0.828045 -0.560662 1001010111_1011100010 //W0831_2048=-0.829761 -0.558119 1001010110_1011100100 //W0832_2048=-0.831470 -0.555570 1001010101_1011100110 //W0834_2048=-0.834863 -0.550458 1001010011 1011101001 // W0836 2048 = -0.838225 -0.545325 1001010010_1011101010 //W0837_2048=-0.839894 -0.542751 1001010001_1011101011 //W0838_2048=-0.841555 -0.540171 1001001111_1011101110 //W0840_2048=-0.844854 -0.534998 1001001110_1011110001 //W0842_2048=-0.848120 -0.529804 1001001101_1011110010 //W0843_2048=-0.849742 -0.527199 1001001100_1011110011 //W0844_2048=-0.851355 -0.524590 1001001010_1011110110 //W0846_2048=-0.854558 -0.519356 1001001001_1011111001 //W0848_2048=-0.857729 -0.514103 1001001000_1011111010 //W0849_2048=-0.859302 -0.511469 1001000111_1011111011 //W0850_2048=-0.860867 -0.508830 1001000110_1011111110 //W0852_2048=-0.863973 -0.503538 1001000100_1100000001 //W0854_2048=-0.867046 -0.498228 1001000011_1100000010 //W0855_2048=-0.868571 -0.495565 1001000011_1100000100 //W0856_2048=-0.870087 -0.492898 1001000001_1100000110 //W0858_2048=-0.873095 -0.487550 1000111111_1100001001 //W0860_2048=-0.876070 -0.482184 1000111111_1100001010 //W0861_2048=-0.877545 -0.479494 1000111110_1100001100 //W0862_2048=-0.879012 -0.476799 1000111100_1100001111 //W0864_2048=-0.881921 -0.471397 1000111011 1100010001 //W0866_2048=-0.884797 -0.465976 1000111010_1100010011 //W0867_2048=-0.886223 -0.463260 1000111010_1100010100 //W0868_2048=-0.887640 -0.460539 1000111000_1100010111 //W0870_2048=-0.890449 -0.455084 1000110111_1100011010 //W0872_2048=-0.893224 -0.449611 1000110110 1100011011 // W0873 2048 = -0.894599 -0.446869 1000110101_1100011101 //W0874_2048=-0.895966 -0.444122 1000110100_1100011111 //W0876_2048=-0.898674 -0.438616 1000110011_1100100010 //W0878_2048=-0.901349 -0.433094 1000110010_1100100100 //W0879_2048=-0.902673 -0.430326 1000110001_1100100101 //W0880_2048=-0.903989 -0.427555 1000110000_1100101000 //W0882_2048=-0.906596 -0.422000 1000101111_1100101011 //W0884_2048=-0.909168 -0.416430 1000101110_1100101100 //W0885_2048=-0.910441 -0.413638 1000101101_1100101110 //W0886_2048=-0.911706 -0.410843 1000101100_1100110001 //W0888_2048=-0.914210 -0.405241 1000101011_1100110011 //W0890_2048=-0.916679 -0.399624 1000101010_1100110101 //W0891_2048=-0.917901 -0.396810 1000101001_1100110110 //W0892_2048=-0.919114 -0.393992 1000101000_1100111001 //W0894_2048=-0.921514 -0.388345 1000100111_1100111100 //W0896_2048=-0.923880 -0.382683 1000100110_1100111110 //W0897_2048=-0.925049 -0.379847 1000100110_1100111111 //W0898_2048=-0.926210 -0.377007 1000100101_1101000010 //W0900_2048=-0.928506 -0.371317 1000100011_1101000101 //W0902_2048=-0.930767 -0.365613 1000100011_1101000110 //W0903_2048=-0.931884 -0.362756 1000100010_1101001000 //W0904_2048=-0.932993 -0.359895 1000100001_1101001011 //W0906_2048=-0.935184 -0.354164 1000100000_1101001110 //W0908_2048=-0.937339 -0.348419 1000100000_1101001111 //W0909_2048=-0.938404 -0.345541 1000011111 1101010001 // W0910 2048 = -0.939459 -0.342661 1000011110_1101010100 //W0912_2048=-0.941544 -0.336890 1000011101_1101010110 //W0914_2048=-0.943593 -0.331106 1000011100_1101011000 //W0915_2048=-0.944605 -0.328210 1000011100_1101011001 //W0916_2048=-0.945607 -0.325310 1000011011_1101011100 //W0918_2048=-0.947586 -0.319502 000011010_1101011111 //W0920_2048=-0.949528 -0.313682 1000011001_1101100001 //W0921_2048=-0.950486 -0.310767 1000011001_1101100010 //W0922_2048=-0.951435 -0.307850 1000011000_1101100101 //W0924_2048=-0.953306 -0.302006 1000010111_1101101000 //W0926_2048=-0.955141 -0.296151 1000010111_1101101010 //W0927_2048=-0.956045 -0.293219 1000010110_1101101011 //W0928_2048=-0.956940 -0.290285 1000010101_1101101110 //W0930_2048=-0.958703 -0.284408 1000010100_1101110001 //W0932_2048=-0.960431 -0.278520 1000010100_1101110011 //W0933_2048=-0.961280 -0.275572 1000010011_1101110100 //W0934_2048=-0.962121 -0.272621 1000010011_1101110111 //W0936_2048=-0.963776 -0.266713 1000010010_1101111010 //W0938_2048=-0.965394 -0.260794 1000010001_1101111100 //W0939_2048=-0.966190 -0.257831 1000010001_1101111110 //W0940_2048=-0.966976 -0.254866 1000010000_1110000001 //W0942_2048=-0.968522 -0.248928 1000001111_1110000100 //W0944_2048=-0.970031 -0.242980 1000001111_1110000101 //W0945_2048=-0.970772 -0.240003 1000001111_1110000111 //W0946_2048=-0.971504 -0.237024 1000001110 1110001010 // W0948 2048 = -0.972940 -0.231058 1000001101_1110001101 //W0950_2048=-0.974339 -0.225084 1000001101_1110001110 //W0951_2048=-0.975025 -0.222094 1000001100_1110010000 //W0952_2048=-0.975702 -0.219101 1000001100_1110010011 //W0954_2048=-0.977028 -0.213110 1000001011_1110010110 //W0956_2048=-0.978317 -0.207111 1000001011_1110010111 //W0957_2048=-0.978948 -0.204109 1000001010_1110011001 //W0958_2048=-0.979570 -0.201105 1000001010_1110011100 //W0960_2048=-0.980785 -0.195090 1000001001_1110011111 //W0962_2048=-0.981964 -0.189069 1000001001_1110100001 //W0963_2048=-0.982539 -0.186055 1000001001_1110100010 //W0964_2048=-0.983105 -0.183040 1000001000_1110100101 //W0966_2048=-0.984210 -0.177004 1000001000_1110101000 //W0968_2048=-0.985278 -0.170962 1000000111_1110101010 //W0969_2048=-0.985798 -0.167938 1000000111_1110101100 //W0970_2048=-0.986308 -0.164913 1000000111_1110101111 //W0972_2048=-0.987301 -0.158858 1000000110_1110110010 //W0974_2048=-0.988258 -0.152797 1000000110_1110110011 //W0975_2048=-0.988722 -0.149765 1000000110_1110110101 // W0976_2048 = -0. 89177 -0.146730 1000000101_1110111000 //W0978_2048=-0.990058 -0.140658 1000000101_1110111011 //W0980_2048=-0.990903 -0.134581 1000000100_1110111101 //W0981_2048=-0.991311 -0.131540 1000000100_1110111110 //W0982_2048=-0.991710 -0.128498 1000000100_1111000001 //W0984_2048=-0.992480 -0.122411 1000000011 1111000100 // W0986 2048 = -0.993212 -0.116319 1000000011_1111000110 //W0987_2048=-0.993564 -0.113271 1000000011_1111001000 //W0988_2048=-0.993907 -0.110222 1000000011_1111001011 //W0990_2048=-0.994565 -0.104122 1000000010_1111001110 //W0992_2048=-0.995185 -0.098017 1000000010_1111001111 //W0993_2048=-0.995481 -0.094963 1000000010_1111010001 //W0994_2048=-0.995767 -0.091909 1000000010_1111010100 //W0996_2048=-0.996313 -0.085797 1000000010_1111010111 //W0998_2048=-0.996820 -0.079682 1000000010_1111011001 //W0999_2048=-0.997060 -0.076624 1000000001_1111011010 //W1000_2048=-0.997290 -0.073565 1000000001_1111011101 // W1002_2048=-0.997723 -0.067444 1000000001_1111100001 // W1004_2048=-0.998118 -0.061321 1000000001_1111100010 // W1005_2048 = -0. 98302 -0.058258 1000000001_1111100100 //W1006_2048=-0.998476 -0.055195 1000000001_1111100111 //W1008_2048=-0.998795 -0.049068 1000000000_1111101010 //W1010_2048=-0.999078 -0.042938 1000000000_1111101100 // W1011_2048=-0.999205 -0.039873 1000000000_1111101101 //W1012_2048=-0.999322 -0.036807 1000000000_1111110000 //W1014_2048=-0.999529 -0.030675 1000000000_1111110011 //W1016_2048=-0.999699 -0.024541 1000000000_1111110101 //W1017_2048=-0.999769 -0.021474 1000000000_1111110111 //W1018_2048=-0.999831 -0.018407 1000000000_1111111010 //W1020_2048=-0.999925 -0.012272 1000000000_1111111101 //W1022_2048=-0.999981 -0.006136 1000000000 1111111110 // W1023 2048 = -0.999995 -0.003068 1000000000_0000000011 //W1026_2048=-0.999981 +0.006136 1000000000_0000001000 //W1029_2048=-0.999882 +0.015339 1000000000_0000001101 //W1032_2048=-0.999699 +0.024541 1000000000_0000010001 //W1035_2048=-0.999431 +0.033741 1000000000_0000010110 //W1038_2048=-0.999078 +0.042938 1000000001_0000011011 //W1041_2048=-0.998640 +0.052132 1000000001_0000011111 //W1044_2048=-0.998118 +0.061321 1000000001_0000100100 //W1047_2048=-0.997511 +0.070505 1000000010_0000101001 //W1050_2048=-0.996820 +0.079682 1000000010_0000101101 //W1053_2048=-0.996045 +0.088854 1000000010_0000110010 //W1056_2048=-0.995185 +0.098017 1000000011_0000110111 //W1059_2048=-0.994240 +0.107172 1000000011_0000111100 //W1062_2048=-0.993212 +0.116319 1000000100_0001000000 //W1065_2048=-0.992099 +0.125455 1000000101_0001000101 //W1068_2048=-0.990903 +0.134581 1000000101_0001001010 //W1071_2048=-0.989622 +0.143695 1000000110_0001001110 //W1074_2048=-0.988258 +0.152797 1000000111_0001010011 //W1077_2048=-0.986809 +0.161886 1000001000_0001011000 //W1080_2048=-0.985278 +0.170962 1000001000_0001011100 //W1083_2048=-0.983662 +0.180023 1000001001_0001100001 //W1086_2048=-0.981964 +0.189069 1000001010_0001100101 //W1089_2048=-0.980182 +0.198098 1000001011_0001101010 //W1092_2048=-0.978317 +0.207111 1000001100_0001101111 //W1095_2048=-0.976370 +0.216107 1000001101 0001110011 // W1098 2048 = -0.974339 +0.225084 1000001110_0001111000 //W1101_2048=-0.972226 +0.234042 1000001111_0001111100 //W1104_2048=-0.970031 +0.242980 1000010001_0010000001 //W1107_2048=-0.967754 +0.251898 1000010010_0010000110 //W1110_2048=-0.965394 +0.260794 1000010011_0010001010 //W1113_2048=-0.962953 +0.269668 1000010100_0010001111 //W1116_2048=-0.960431 +0.278520 1000010110_0010010011 //W1119_2048=-0.957826 +0.287347 1000010111_0010011000 //W1122_2048=-0.955141 +0.296151 1000011000_0010011100 //W1125_2048=-0.952375 +0.304929 1000011010_0010100001 //W1128_2048=-0.949528 +0.313682 1000011011_0010100101 //W1131_2048=-0.946601 +0.322408 1000011101_0010101010 // W1134_2048 = -0. 43593 +0.331106 1000011110_0010101110 //W1137_2048=-0.940506 +0.339777 1000100000_0010110010 //W1140_2048=-0.937339 +0.348419 1000100010_0010110111 //W1143_2048=-0.934093 +0.357031 1000100011_0010111011 //W1146_2048=-0.930767 +0.365613 1000100101_0011000000 //W1149_2048=-0.927363 +0.374164 1000100111_0011000100 //W1152_2048=-0.923880 +0.382683 1000101001_0011001000 //W1155_2048=-0.920318 +0.391170 1000101011_0011001101 //W1158_2048=-0.916679 +0.399624 1000101101_0011010001 //W1161_2048=-0.912962 +0.408044 1000101111_0011010101 //W1164_2048=-0.909168 +0.416430 1000110000_0011011001 //W1167_2048=-0.905297 +0.424780 1000110011_0011011110 //W1170_2048=-0.901349 +0.433094 1000110101 0011100010 // W1173 2048 = -0.897325 +0.441371 1000110111_0011100110 //W1176_2048=-0.893224 +0.449611 1000111001_0011101010 //W1179_2048=-0.889048 +0.457813 1000111011_0011101111 //W1182_2048=-0.884797 +0.465976 1000111101_0011110011 //W1185_2048=-0.880471 +0.474100 • 1000111111_0011110111 //W1188_2048=-0.876070 +0.482184 1001000010_0011111011 //W1191_2048=-0.871595 +0.490226 1001000100_0011111111 //W1194_2048=-0.867046 +0.498228 1001000110_0100000011 //W1197_2048=-0.862424 +0.506187 1001001001_0100000111 //W1200_2048=-0.857729 +0.514103 1001001011_0100001011 //W1203_2048=-0.852961 +0.521975 1001001110_0100001111 //W1206_2048=-0.848120 +0.529804 1001010000_0100010011 //W1209_2048=-0.843208 +0.537587 1001010011_0100010111 //W1212_2048=-0.838225 +0.545325 1001010101_0100011011 //W1215_2048=-0.833170 +0.553017 1001011000_0100011111 //W1218_2048=-0.828045 +0.560662 1001011011_0100100011 //W1221_2048=-0.822850 +0.568259 1001011101_0100100111 //W1224_2048=-0.817585 +0.575808 1001100000_0100101011 //W1227_2048=-0.812251 +0.583309 1001100011_0100101110 //W1230_2048=-0.806848 +0.590760 1001100110_0100110010 //W1233_2048=-0.801376 +0.598161 1001101001_0100110110 //W1236_2048=-0.795837 +0.605511 1001101011_0100111010 //W1239_2048=-0.790230 +0.612810 1001101110_0100111101 //W1242_2048=-0.784557 +0.620057 1001110001_0101000001 //W1245_2048=-0.778817 +0.627252 1001110100 0101000101 // W1248 2048 = -0.773010 +0.634393 1001110111_0101001000 //W1251_2048=-0.767139 +0.641481 1001111010_0101001100 //W1254_2048=-0.761202 +0.648514 1001111101_0101010000 //W1257_2048=-0.755201 +0.655493 1010000000_0101010011 //W1260_2048=-0.749136 +0.662416 1010000100_0101010111 //W1263_2048=-0.743008 +0.669283 1010000111_0101011010 //W1266_2048=-0.736817 +0.676093 1010001010_0101011110 //W1269_2048=-0.730563 +0.682846 1010001101_0101100001 //W1272_2048=-0.724247 +0.689541 1010010000_0101100100 //W1275_2048=-0.717870 +0.696177 1010010100_0101101000 //W1278_2048=-0.711432 +0.702755 1010010111_0101101011 //W1281_2048=-0.704934 +0.709273 1010011010_0101101110 //W1284_2048=-0.698376 +0.715731 1010011110_0101110010 //W1287_2048=-0.691759 +0.722128 1010100001_0101110101 //W1290_2048=-0.685084 +0.728464 1010100101_0101111000 //W1293_2048=-0.678350 +0.734739 1010101000_0101111011 //W1296_2048=-0.671559 +0.740951 1010101100_0101111111 //W1299_2048=-0.664711 +0.747101 1010101111_0110000010 //W1302_2048=-0.657807 +0.753187 1010110011_0110000101 //W1305_2048=-0.650847 +0.759209 1010110110_0110001000 //W1308_2048=-0.643832 +0.765167 1010111010_0110001011 //W1311_2048=-0.636762 +0.771061 1010111110_0110001110 //W1314_2048=-0.629638 +0.776888 1011000001_0110010001 //W1317_2048=-0.622461 +0.782651 1011000101_0110010100 //W1320_2048=-0.615232 +0.788346 1011001001 0110010111 // W1323 2048 = -0.607950 +0.793975 1011001100_0110011001 //W1326_2048=-0.600616 +0.799537 1011010000_0110011100 //W1329_2048=-0.593232 +0.805031 1011010100_0110011111 //W1332_2048=-0.585798 +0.810457 1011011000_0110100010 //W1335_2048=-0.578314 +0.815814 1011011100_0110100100 //W1338_2048=-0.570781 +0.821103 1011100000_0110100111 //W1341_2048=-0.563199 +0.826321 1011100100_0110101010 //W1344_2048=-0.555570 +0.831470 1011100111_0110101100 //W1347_2048=-0.547894 +0.836548 1011101011_0110101111 //W1350_2048=-0.540171 +0.841555 1011101111_0110110001 //W1353_2048=-0.532403 +0.846491 1011110011_0110110100 //W1356_2048=-0.524590 +0.851355 1011110111_0110110110 //W1359_2048=-0.516732 +0.856147 1011111011_0110111001 //W1362_2048=-0.508830 +0.860867 1100000000_0110111011 //W1365_2048=-0.500885 +0.865514 1100000100_0110111101 //W1368_2048=-0.492898 +0.870087 1100001000_0111000000 //W1371_2048=-0.484869 +0.874587 1100001100_0111000010 //W1374_2048=-0.476799 +0.879012 1100010000_0111000100 //W1377_2048=-0.468689 +0.883363 1100010100_0111000110 //W1380_2048=-0.460539 +0.887640 1100011000_Q111001001 //W1383_2048=-0.452350 +0.891841 1100011101_0111001011 //W1386_2048=-0.444122 +0.895966 1100100001_0111001101 //W1389_2048=-0.435857 +0.900016 1100100101_0111001111 //W1392_2048=-0.427555 +0.903989 1100101001_0111010001 // W1395_2048 = -0. 19217 +0.907886 1100101110 0111010011 // W1398 2048 = -0.410843 +0.911706 1100110010_0111010101 //W1401_2048=-0.402435 +0.915449 1100110110_0111010111 //W1404_2048=-0.393992 +0.919114 1100111011_0111011000 //W1407_2048=-0.385516 +0.922701 1100111111_0111011010 //W1410_2048=-0.377007 +0.926210 1101000011_0111011100 //W1413_2048=-0.368467 +0.929641 1101001000_0111011110 //W1416_2048=-0.359895 +0.932993 1101001100_0111011111 //W1419_2048=-0.351293 +0.936266 1101010001_0111100001 //W1422_2048=-0.342661 +0.939459 1101010101_0111100011 //W1425_2048=-0.334000 +0.942573 1101011001_0111100100 //W1428_2048=-0.325310 +0.945607 1101011110_0111100110 //W1431_2048=-0.316593 +0.948561 1101100010_0111100111 // W1434 2048 = -0.307850 +0.951435 1101100111_0111101001 //W1437_2048=-0.299080 +0.954228 1101101011_0111101010 //W1440_2048=-0.290285 +0.956940 1101110000_0111101011 //W1443_2048=-0.281465 +0.959572 1101110100_0111101101 //W1446_2048=-0.272621 +0.962121 1101111001_0111101110 //W1449_2048=-0.263755 +0.964590 1101111110_0111101111 //W1452_2048=-0.254866 +0.966976 1110000010_0111110000 //W1455_2048=-0.245955 +0.969281 1110000111_0111110001 //W1458_2048=-0.237024 +0.971504 1110001011_0111110011 //W1461_2048=-0.228072 +0.973644 1110010000_0111110100 //W1464_2048=-0.219101 +0.975702 1110010100_0111110101 //W1467_2048=-0.210112 +0.977677 1110011001_0111110110 //W1470_2048=-0.201105 +0.979570 1110011110 0111110110 // W1473 2048 = -0.192080 +0.981379 1110100010_0111110111 //W1476_2048=-0.183040 +0.983105 1110100111_0111111000 //W1479_2048=-0.173984 +0.984749 1110101100_0111111001 //W1482_2048=-0.164913 +0.986308 1110110000_0111111010 //W1485_2048=-0.155828 +0.987784 1110110101_0111111010 //W1488_2048=-0.146730 +0.989177 1110111010_0111111011 //W1491_2048=-0.137620 +0.990485 1110111110_0111111100 //W1494_2048=-0.128498 +0.991710 1111000011_0111111100 //W1497_2048=-0.119365 +0.992850 1111001000_0111111101 //W1500_2048=-0.110222 +0.993907 lllip01100_0111111101 //W1503_2048=-0.101070 +0.994879 1111010001_0111111110 //W1506_2048=-0.091909 +0.995767 1111010110_0111111110 //W1509_2048=-0.082740 +0.996571 1111011010_0111111111 //W1512_2048=-0.073565 +0.997290 1111011111_0111111111 //W1515_2048=-0.064383 +0.997925 1111100100_0111111111 //W1518_2048=-0.055195 +0.998476 1111101000_0111111111 //W1521_2048=-0.046003 +0.998941 1111101101_0111111111 //W1524_2048=-0.036807 +0.999322 1111110010_0111111111 //W1527_2048=-0.027608 +0.999619 1111110111_0111111111 // W1530_2048=-0.018407 +0.999831 1111111011_0111111111 //W1533_2048=-0.009204 +0.999958 Listing 17 // 512 point FFT twiddle factor coefficients (Radix 4 + 2). // Coefficients stored as non-fractional 10 bit integers (scale l). // Real Coefficient (cosine valué) is coefficient high-byte.

// Imaginary Coefficient (sine valué) is coefficient low-byte. 0111111111_0000000000 //W0000_0512=+l.000000 -0.000000 0111111111_1111111010 //W0001_0512=+0.999925 -0.012272 0111111111_1111110011 //W0002_0512=+0.999699 -0.024541 0111111111_1111101101 //W0003_0512=+0.999322 -0.036807 0111111111_1111100111 //W0004_0512=+0.998795 -0.049068 0111111111_1111100001 //W0005_0512=+0.998118 -0.061321 0111111111_1111011010 //W0006_0512=+0.997290 -0.073565 0111111110_1111010100 //W0007_0512=+0.996313 -0.085797 0111111110_1111001110 //W0008_0512=+0.995185 -0.098017 0111111101_1111001000 //W0009_0512=+0.993907 -0.110222 0111111100_1111000001 //W0010_0512=+0.992480 -0.122411 0111111011_1110111011 //W0011_0512=+0.990903 -0.134581 0111111010_1110110101 //W0012_0512=+0.989177 -0.146730 0111111001_1110101111 //W0013_0512=+0.987301 -0.158858 0111111000_1110101000 //W0014_0512=+0.985278 -0.170962 0111110111_1110100010 //W0015_0512=+0.983105 -0.183040 0111110110_1110011100 //W0016_0512=+0.980785 -0.195090 0111110101_1110010110 //W0017_0512=+0.978317 -0.207111 0111110100_1110010000 //W0018_0512=+0.975702 -0.219101 0111110010_1110001010 //W0019_0512=+0.972940 -0.231058 0111110001_1110000100 //W0020_0512=+0.970031 -0.242980 0111101111_1101111110 //W0021_0512=+0.966976 -0.2866 0111101101_1101110111 //W0022_0512=+0.963776 -0.266713 0111101100 1101110001 // W0023 0512 = + 0.960431 -0.278520 01111010l '? _ 1101101011 //W0024_0512=+0.956940 -0.290285 0111101000_1101100101 //W0025_0512=+0.953306 -0.302006 0111100110_1101011111 //W0026_0512=+0.949528 -0.313682 0111100100_1101011001 //W0027_0512=+0.945607 -0.325310 0111100010_1101010100 //W0028_0512=+0.941544 -0.336890 0111100000_1101001110 //W0029_0512=+0.937339 -0.348419 0111011110_1101001000 //W0030_0512=+0.932993 -0.359895 0111011011 1101000010 //W0031_0512=+0.928506 -0.371317 0111011001_1100111100 //W0032_0512=+0.923880 -0.382683 0111010111_1100110110 //W0033_0512=+0.919114 -0.393992 0111010100_1100110001 //W0034_0512=+0.914210 -0.405241 0111010001_1100101011 //W0035_0512=+0.909168 -0.416430 0111001111_1100100101 //W0036_0512=+0.903989 -0.427555 0111001100_1100011111 //W0037_0512=+0.898674 -0.438616 0111001001_1100011010 //W0038_0512=+0.893224 -0.449611 0111000110_1100010100 //W0039_0512=+0.887640 -0.460539 0111000100_1100001111 //W0040_0512=+0.881921 -0.471397 0111000001_1100001001 //W0041_0512=+0.876070 -0.482184 0110111101_1100000100 //W0042_0512=+0.870087 -0.492898 0110111010_1011111110 //W0043_0512=+0.863973 -0.503538 0110110111_1011111001 //W0044_0512=+0.857729 -0.514103 0110110100_1011110011 //W0045_0512=+0.851355 -0.524590 0110110001_1011101110 //W0046_0512=+0.844854 -0.534998 0110101101_1011101001 //W0047_0512=+0.838225 -0.545325 0110101010 1011100100 // W0048 0512 = + 0.831470 -0.555570 0110100110_1011011110 //W0049_0512=+0.824589 -0.565732 0110100011_1011011001 //W0050_0512=+0.817585 -0.575808 0110Ó11111_1011010100 //W0051_0512=+0.810457 -0.585798 0110011011_1011001111 //W0052_0512=+0.803208 -0.595699 0110010111_1011001010 //W0053_0512=+0.795837 -0.605511 0110010100_1011000101 //W0054_0512=+0.788346 -0.615232 0110010000_1011000000 //W0055_0512=+0.780737 -0.624859 0110001100_1010111011 //W0056_0512=+0.773010 -0.634393 0110001000_1010110110 //W0057_0512=+0.765167 -0.643832 0110000100_1010110010 //W0058_0512=+0.757209 -0.653173 0110000000_1010101101 //W0059_0512=+0.749136 -0.662416 0101111011_1010101000 //W0060_0512=+0.740951 -0.671559 0101110111_1010100100 //W0061_0512=+0.732654 -0.680601 0101110011_1010011111 //W0062_0512=+0.724247 -0.689541 0101101110_1010011010 //W0063_0512=+0.715731 -0.698376 0101101010_1010010110 //W0064_0512=+0.707107 -0.707107 0101100110_1010010010 //W0065_0512=+0.698376 -0.715731 0101100001_1010001101 //W0066_0512=+0.689541 -0.724247 0101011100_1010001001 //W0067_0512=+0.680601 -0.732654 0101011000_1010000101 //W0068_0512=+0.671559 -0.740951 0101010011_1010000000 //W0069_0512=+0.662416 -0.749136 0101001110_1001111100 //W0070_0512=+0.653173 -0.757209 0101001010_1001111000 //W0071_0512=+0.643832 -0.765167 0101000101_1001110100 //W0072_0512=+0.634393 -0.773010 0101000000 1001110000 // W0073 0512 = + 0.624859 -0.780737 0100111011_1001101100 //W0074_0512=+0.615232 -0.788346 0100110110_1001101001 //W0075_0512=+0.605511 -0.795837 0100110001_1001100101 //W0076_0512=+0.595699 -0.803208 0100101100_1001100001 //W0077_0512=+0.585798 -0.810457 0100100111_1001011101 //W0078_0512=+0.575808 -0.817585 0100100010_1001011010 //W0079_0512=+0.565732 -0.824589 0100011100_1001010110 //W0080_0512=+0.555570 -0.831470 0100010111_1001010011 //W0081_0512=+0.545325 -0.838225 0100010010_1001001111 //W0082_0512=+0.534998 -0.844854 0100001101_1001001100 //W0083_0512=+0.524590 -0.851355 0100000111_1001001001 //W0084_0512=+0.514103 -0.857729 0100000010_1001000110 //W0085_0512=+0.503538 -0.863973 0011111100_1001000011 //W0086_.0512=+0.492898 -0.870087 0011110111_1000111111 //W0087_0512=+0.482184 -0.876070 0011110001_1000111100 //W0088_0512=+0.471397 -0.881921 0011101100_1000111010 //W0089_0512=+0.460539 -0.887640 0011100110_1000110111 //W0090_0512=+0.449611 -0.893224 0011100001_1000110100 //W0091_0512=+0.438616 -0.898674 0011011011_1000110001 //W0092_0512=+0.427555 -0.903989 0011010101_1000101111 //W0093_0512=+0.416430 -0.909168 0011001111_1000101100 //W0094_0512=+0.405241 -0.914210 0011001010_1000101001 //W0095_0512=+0.393992 -0.919114 0011000100_1000100111 //W0096_0512=+0.382683 -0.923880 0010111110_1000100101 //W0097_0512=+0.371317 -0.928506 0010111000 1000100010 // W0098 0512 = + 0.359895 -0.932993 0010110010_1000100000 //W0099_0512=+0.348419 -0.937339 0010101100_1000011110 //W0100_0512=+0.336890 -0.941544 0010100111_1000011100 //W0101_0512=+0.325310 -0.945607 0010100001_1000011010 //W0102_0512=+0.313682 -0.949528 0010011011_1000011000 //W0103_0512=+0.302006 -0.953306 0010010101_1000010110 //W0104_0512=+0.290285 -0.956940 0010001111_1000010100 //W0105_0512=+0.278520 -0.960431 0010001001_1000010011 //W0106_0512=+0.266713 -0.963776 0010000010_1000010001 //W0107_0512=+0.254866 -0.966976 0001111100_1000001111 //W0108_0512=+0.242980 -0.970031 0001110110_1000001110 //W0109_0512=+0.231058 -0.972940 0001110000_1000001100 //W0110_0512=+0.219101 -0.975702 0001101010_1000001011 //W0111_0512=+0.207111 -0.978317 0001100100_1000001010 //W0112_0512=+0.195090 -0.980785 0001011110_1000001001 //W0113_0512=+0.183040 -0.983105 0001011000_1000001000 //W0114_0512=+0.170962 -0.985278 0001010001_1000000111 //W0115_0512=+0.158858 -0.987301 0001001011_1000000110 //W0116_0512=+0.146730 -0.989177 0001000101_1000000101 //W0117_0512=+0.134581 -0.990903 0000111111_1000000100 //W0118_0512=+0.122411 -0.992480 0000111000_1000000011 //W0119_0512=+0.110222 -0.993907 0000110010_1000000010 //W0120_0512=+0.098017 -0.995185 0000101100_1000000010 //W0121_0512=+0.085797 -0.996313 0000100110_1000000001 //W0122_0512=+0.073565 -0.997290 0000011111 1000000001 // W0123 0512 = + 0.061321 -0.998118 0000011001_1000000001 //W0124_0512=+0.049068 -0.998795 0000010011_1000000000 //W0125_0512=+0.036807 -0.999322 0000001101_1000000000 //W0126_0512=+0.024541 -0.999699 0000000110_1000000000 //W0127_0512=+0.012272 -0.999925 0000000000_1000000000 // W0128_0512 = + 0000000 -1.000000 1111111010_1000000000 //W0129_0512=-0.012272 -0.999925 1111110011_1000000000 //W0130_0512=-0.024541 -0.999699 1111100111_1000000001 //W0132_0512=-0.049068 -0.998795 1111011010_1000000001 //W0134_0512=-0.073565 -0.997290 1111010100_1000000010 //W0135_0512=-0.085797 -0.996313 1111001110_1000000010 //W0136_0512=-0.098017 -0.995185 111100O001_1000000100 //W0138_0512=-0.122411 -0.992480 1110110101_1000000110 //W0140_0512=-0.146730 -0.989177 1110101111_1000000111 //W0141_0512=-0.158858 -0.987301 1110101000_1000001000 //W0142_0512=-0.170962 -0.985278 1110011100_1000001010 //W0144_0512=-0.195090 -0.980785 1110010000_1000001100 //W0146_0512=-0.219101 -0.975702 1110001010_1000001110 //W0147_0512=-0.231058 -0.972940 1110000100_1000001111 //W0148_0512=-0.242980 -0.970031 1101110111_1000010011 //W0150_0512=-0.266713 -0.963776 1101101011_1000010110 //W0152_0512=-0.290285 -0.956940 1101100101_1000011000 //W0153_0512=-0.302006 -0.953306 1101011111_1000011010 //W0154_0512=-0.313682 -0.949528 1101010100_1000011110 //W0156_0512=-0.336890 -0.941544 1101001000 1000100010 // W0158 0512 = -0.359895 -0.932993 1101000010_1000100101 //W0159_0512=-0.371317 -0.928506 1100111100_1000100111 //W0160_0512=-0.382683 -0.923880 1100110001_1000101100 //W0162_0512=-0.405241 -0.914210 1100100101_1000110001 //W0164_0512=-0.427555 -0.903989 1100011111_1000110100 //W0165_0512=-0.438616 -0.898674 1100011010_1000110111 //W0166_0512=-0.449611 -0.893224 1100001111_1000111100 //W0168_0512=-0.471397 -0.881921 1100000100_1001000011 //W0170_0512=-0.492898 -0.870087 1011111110_1001000110 //W0171_0512=-0.503538 -0.863973 1011111001_1001001001 //W0172_0512=-0.514103 -0.857729 1011101110_1001001111 //W0174_0512=-0.534998 -0.844854 1011100100_1001010110 //W0176_0512=-0.555570 -0.831470 1011011110_1001011010 //W0177_0512=-0.565732 -0.824589 1011011001_1001011101 //W0178_0512=-0.575808 -0.817585 1011001111_1001100101 //W0180_0512=-0.595699 -0.803208 1011000101_1001101100 //W0182_0512=-0.615232 -0.788346 1011000000_1001110000 //W0183_0512=-0.624859 -0.780737 1010111011_1001110100 //W0184_0512=-0.634393 -0.773010 1010110010_1001111100 //W0186_0512=-0.653173 -0.757209 1010101000_1010000101 //W0188_0512=-0.671559 -0.740951 1010100100_1010001001 //W0189_0512=-0.680601 -0.732654 1010011111_1010001101 //W0190_0512=-0.689541 -0.724247 1010010110_1010010110 //W0192_0512=-0.707107 -0.707107 1010001101_1010011111 //W0194_0512=-0.724247 -0.689541 A010001001 1010100100 // W0195 0512 = -0.732654 -0.680601 1010000101_1010101000 //W0196_0512=-0.740951 -0.671559 1001111100_1010110010 //W0198_0512=-0.757209 -0.653173 1001110100_1010111011 //W0200_0512=-0.773010 -0.634393 1001110000_1011000000 //W0201_0512=-0.780737 -0.624859 1001101100_1011000101 //W0202_0512=-0.788346 -0.615232 1001100101_1011001111 //W0204_0512=-0.803208 -0.595699 1001011101_1011011001 //W0206_0512=-0.817585 -0.575808 1001011010_1011011110 //W0207_0512=-0.824589 -0.565732 1001010110_1011100100 // W0208_0512 = -0.831470 -0.555570 1001001111_1011101110 //W0210_0512=-0.844854 -0.534998 1001001001_1011111001 //W0212_0512=-0.857729 -0.514103 1001000110_1011111110 //W0213_0512=-0.863973 -0.503538 1001000011_1100000100 //W0214_0512=-0.870087 -0.492898 1000111100_1100001111 //W0216_0512=-0.881921 -0.471397 1000110111_1100011010 //W0218_0512=-0.893224 -0.449611 1000110100_1100011111 //W0219_0512=-0.898674 -0.438616 1000110001_1100100101 //W0220_0512=-0.903989 -0.427555 1000101100_1100110001 //W0222_0512=-0.914210 -0.405241 1000100111_1100111100 //W0224_0512=-0.923880 -0.382683 1000100101_1101000010 //W0225_0512=-0.928506 -0.371317 1000100010_1101001000 //W0226_0512=-0.932993 -0.359895 1000011110_1101010100 //W0228_0512=-0.941544 -0.336890 1000011010_1101011111 //W0230_0512=-0.949528 -0.313682 1000011000_1101100101 //W0231_0512=-0.953306 -0.302006 1000010110 1101101011 // W0232 0512 = -0.956940 -0.290285 1000010011_1101110111 // W0234 0512 = -0.963776 -0.266713 1000001111_1110000100 //W0236_0512=-0.970031 -0.242980 1000001110_1110001010 //W0237_0512=-0.972940 -0.231058 1000001100_1110010000 //W0238_0512=-0.975702 -0.219101 1000001010_1110011100 //W0240_0512=-0.980785 -0.195090 1000001000_1110101000 //W0242_0512=-0.985278 -0.170962 1000000111_1110101111 //W0243_0512=-0.987301 -0.158858 1000000110_1110110101 //W0244_0512=-0.989177 -0.146730 1000000100_1111000001 //W0246_0512=-0.992480 -0.122411 1000000010_1111001110 //W0248_0512=-0.995185 -0.098017 1000000010_1111010100 //W0249_0512=-0.996313 -0.085797 1000000001_1111011010 //W0250_0512=-0.997290 -0.073565 1000000001_1111100111 //W0252_0512=-0.998795 -0.049068 1000000000_1111110011 //W0254_0512=-0.999699 -0.024541 1000000000_1111111010 //W0255_0512=-0.999925 -0.012272 1000000000_0000001101 //W0258_0512=-0.999699 +0.024541 1000000001_0000011111 //W0261_0512=-0.998118 +0.061321 1000000010_0000110010 //W0264_0512=-0.995185 +0.098017 1000000101_0001000101 //W0267_0512=-0.990903 +0.134581 1000001000_0001011000 //W0270_0512=-0.985278 +0.170962 1000001011_0001101010 // W0273_0512 = -0. 78317 +0.207111 1000001111_0001111100 //W0276_0512=-0.970031 +0.242980 1000010100 0010001111 //W0279_0512=-0.960431 +0.278520 1000011010_0010100001 //W0282_0512=-0.949528 +0.313682 1000100000 0010110010 // W0285 0512 = -0.937339 +0.348419 1000100111_0011000100 //W0288_0512=-0.923880 +0.382683 1000101111_0011010101 //W0291_05l2=-0.909168 +0.416430 10001Í0111_0011100110 //W0294_0512=-0.893224 +0.449611 1000111111_0011110111 //W0297_0512=-0.876070 +0.482184 1001001001_0100000111 //W0300_0512=-0.857729 +0.514103 1001010011_0100010111 //W0303_0512=-0.838225 +0.545325 1001011101_0100100111 //W0306_0512=-0.817585 +0.575808 1001101001_0100110110 //W0309_0512=-0.795837 +0.605511 1001110100_0101000101 //W0312_0512=-0.773010 +0.634393 1010000000_0101010011 //W0315_0512=-0.749136 +0.662416 1010001101_0101100001 //W0318_0512=-0.724247 +0.689541 1010011010_0101101110 //W0321_0512=-0.698376 +0.715731 1010101000_0101111011 //W0324_0512=-0.671559 +0.740951 1010110110_0110001000 //W0327_0512=-0.643832 +0.765167 1011000101_0110010100 //W0330_0512=-0.615232 +0.788346 1011010100_0110011111 //W0333_0512=-0.585798 +0.810457 1011100100_0110101010 //W0336_0512=-0.555570 +0.831470 1011110011_0110110100 //W0339_0512=-0.524590 +0.851355 1100000100_0110111101 //W0342_0512=-0.492898 +0.870087 1100010100_0111000110 //W0345_0512=-0.460539 +0.887640 1100100101_0111001111 //W0348_0512=-0.427555 +0.903989 1100110110_0111010111 //W0351_0512=-0.393992 +0.919114 1101001000_0111011110 //W0354_0512=-0.359895 +0.932993 1101011001_0111100100 //W0357_0512=-0.325310 +0.945607 1101101011 0111101010 // W0360 0512 = - 0.290285 +0.956940 1101111110_0111101111 //W0363_0512=-0.254866 +0.966976 1110010000_0111110100 //W0366_0512=-0.219101 +0.975702 1110100010_0111110111 //W0369_0512=-0.183040 +0.983105 1110110101_0111111010 //W0372_0512=-0.146730 +0.989177 1111001000_0111111101 //W0375_0512=-0.110222 +0.993907 1111011010_0111111111 //W0378_0512=-0.073565 +0.997290 1111101101_0111111111 //W0381_0512=-0.036807 +0.999322 Listing 18 / * FOLDBEGINS 0 0"Copyright" * / ***************************** Copyright (c) Pioneer Digital Design Center Limited ÑAME: pilloc_rtl.v PURPOSE: Pilot location CREATED: June 1997 BY: T. Foxcroft MODIFIED: USED IN PROJECTS: cofdm only.

? FOLDENDS * / FOLDBEGINS 0 0"Defines" * / 'define FFTS AZE 2048' define DATABINS 1705 'define SCATNUM 45' define SCALEFACTOR640. 3792 // 3x8192 / sqrt (42) 'define SCALEFACT0R16Q 3886 // 3x8192 / sqrt (10) * 2' define SCALEFACTORQPS 2172 // 3x8192 / sqrt (2) * 8 'define AVERAGESF 12'hc49 // O .04x4096x32768 / 1705 = 3145 / * FOLDENDS * / module chanest (clk, resync, in_valid, in_data, constellation, u_symbol, us_pilots, uc_pilots, ct_pilots, out_tps, tps_valid, uncorrected_iq, out_valid, outi, outq, c_symbol, incfreq, wrstrb, ramindata, ramoutdata, ramaddr); / * FOLDBEGINS 0 0"i / o" * / input clk, resync, in_valid; input [23: 0] in_data; input [1: 0] constellation; output u_symbol; output us_pilots, uc_pilots, ct_pilots; output out_tps, tps_valid; output [23: 0] uncorrected_iq; output out_valid; output [7: 0] outi; output [7: 0] OUtq; output c_symbol; output incfreq; output wrstrb; output [23: 0] ramindata; input [23: 0] ramoutdata; output [10: 0] ramaddr; / * FOLDENDS * / / * FOLDBEGINS 0 0"TPS location" * / reg [10: 0] tpsloc; reg [4: 0] tpscount; always © (tpscount) begin case (tpscount) 5'bOOOOO: tpsloc = 34; 5'bO0001: tpsloc = 50; 5'bO0010: tpsloc = 209 5'bO0011: tpsloc = 346, 5'bO0100: tpsloc = 413- 5'bO0101: tpsloc = 569, 5'bO0110: tpsloc = 595 5'bO0111: tpsloc = 688, 5'bO1000: tpsloc = 790; 5'bO1001: tpsloc = 901 5'bOlOlO: tpsloc = 1073, 5'b? L? Ll: tpsloc = 1219, 5'bO1100: tpsloc = 1262, 5'b? Ll?: Tpsloc = 1286, 5'bO1110 : tpsloc = 1469, 5'b? llll: tpsloc = 1594 default: tpsloc = 1687; endcase end / * FOLDENDS / / * FOLDBEGINS O O "continuous pilot location" * / reg [10: 0] contloc; reg [5: 0] contloccount; always © (contloccount) begin case (contloccount) 6'bOOOOOO: contloc = O; 6'bOOOOl: contloc = 48, 6'bO00010: contloc = 54, 6'bO00011: contloc = 87, 6'bO00100: contloc = 141 6'bO00101: contloc = 156 6'bO00110: contloc = 192 6'bOOOlll: contloc = 201 6'bO01000: contloc = 255 6'bO01001: contloc - 279 6'bO01010: contloc = 282 6'bO01011: contloc = 333 6'bO01100: contloc = 432 6'bO01101: contloc = 450- 6'bOOlllO: contloc = 483 A'bOOllll: contloc = 525 6 'bOlOOOO: contloc = 531 6 'bOlOOOl: contloc = 618 6 'bOlOOlO: contloc = 636 6 'bOlOOll: contloc = 714 6 • bOlOlOO: contloc = 759 6 'bOlOlOl: contloc = 765 6 'bOlOUO: contloc = 780 6 'bOlOlll: contloc = 804 6 'bOHOOO: contloc = 873 6 'bOHOOl: contloc = 888 6 'BOTH: contloc = 918 6 bOHOll: contloc = 939; 6 bOlllOO: contloc = 942; 6 bOlllOl: contloc = 969; 6 bOllllO: contloc = 984; 6 bOlllll: contloc = 1050 6 blOOOOO: contloc = 1101 6 blOOOOl: contloc = 1107 6 blOOOlO: contloc = 1110 6 blOOOll: contloc = 1137 6 blOOlOO: contloc = 1140 6 blOOlOl: contloc = 1146 6 blOOHO: contloc = 1206 6 blOOlll: contloc = 1269 6 blOlOOO: contloc = 1323 6'bl01001: contloc = 1377, 6'bl01010: contloc = 1491, 6'bl01011: contloc = 1683, default: contloc = 1704; endcase end / * F0LDENDS / / FOLDBEGINS * / 0 0"continuous pilot location" * / / * reg [10: 0] contloc [44: 0]; reg [5: 0] contloccount; initial begin contloc [0] = 0; contloc [1] = 48; contloc [2] = 54; contloc [3] = 87; contloc [4] = 141; contloc [5] = 156; contloc [6] = 192; contloc [7] = 201; contloc [8] = 255; contloc [9] = 279 contloc [10] = 282; contloc [11] = 333; contloc [12] = 432; contloc [13] = 450; contloc [14] = 483; contloc [15] = 525; contloc [16] = 531; contloc [17] = 618; contloc [18] = 636; contloc [19] = 714; contloc [20] = 759; contloc [21] = 765; contloc [22] = 780; contloc [23] = 804; contloc [24] = 873; contloc [25] = 888; contloc [26] = 918; contloc [27] = 939; contloc [28] = 942; contloc [29] = 969 contloc [30] = 984; contloc [31] = 1050; contloc [32] = 1101; contloc [33] = 1107; contloc [34] = 1110 contloc [35] = 1137; contloc [36] = 1140; contloc [37] = 1146; contloc [38] = 1206; contloc [39] = 1269; contloc [40] = 1323; contloc [41] = 1377; contloc [42] = 1491; contloc [43] = 1683; contloc [44] = 1704; end * t / * F0LDENDS * / / * FOLDBEGINS 00"Control vars * / reg [1: 0] constell; reg resynch; r e g valid, valid, validl, valid2, valid3, valid4, valid5, validd, valid 7, validd; reg [1: 0] whichsymbol; reg [1: 0] pwhichsymbol; reg incwhichsymbol; reg [23: 0] fftdata; reg [10: 0] fftcount; reg [10: 0] tapcount; reg [3: 0] countl2; reg [3:01 dcountl2; regdadavalid; reg tapinit; reg tapinitl, tapinit2; reg [7: 0] nscat; reg pilot; reg tapload; // controls when the taps are loaded reg tapload2; reg shiftinnewtap; reg filgo; / * FOLDENDS * / / * FOLDBEGINS 0 0"Channel Est vars" * / reg [11: 0] tapi [5: 0]; reg [11: 0] tapq [5: 0]; reg [27: 0] sumi, -reg [27: 0] sumq; reg [11: 0] chani; reg [11: 0] chanq; wire [27: 0] chani_; wire [27: 0] chanq_; reg [1 1: 0] idata; reg [11: 0] qdata; / * FOLDENDS * / / * FOLDBEGINS 0 0"RAM vars" * / reg [10: 0] ramaddr; reg [10: 0] pilotaddr; wire [10: 0] ramaddr_; wire [10: 0] ramaddrrev_; reg [23: 0] ramindata; wire [23: 0] ramoutdata; reg [23: 0] ramout; reg. [23: 0] ramot; reg wrstrb; reg rwtoggle; reg framedata, framedataO; reg frav, firsffrav; reg [23: 0] avchannel; reg [11: 0] avchan; reg avlow; wire [23: 0] avchan_; / * FOLDENDS * / / * FOLDBEGINS 0 0"Channel cale vars" * / reg chan_val; r e g chan_valO, chan_vall, chan_val2, chan_val3, chan_val4, out_valid; reg [23: 0] sum; reg [11: 0] sumsq; reg [1 1: 0] sumsqtemp; reg [11: 0] topreal; reg [11: 0] topimag; reg [7: 0] outi; reg [7: 0] outitemp; reg [5: 0] outitem; reg [7 0] outq; reg [10: 0] prbs; // integer intsumi, intsumq, intsumsq, intouti, intoutq; / * FOLDENDS * / / * FOLDBEGINS OR "uncorrected pilot vars" / reg u_symbol; reg us_pilots; reg uc_pilots; reg [23: 0] uncorrected_iq; reg [2: 0] tps_pilots; reg [5: 0] tpsmaj count; wire [5: 0] tpsmaj count_; reg ct_pilots; reg out_tps, tps_valid; reg [1: 0] pilotdata; / * FOLDENDS * / / * FOLDBEGINS OR "pilot looses vars" * / wire [1: 0] which_symbol; 'wire [10: 0] cpoffset; wire [10: 0] pilotramaddr_; wire [23: 0] pilotramin_; wire pilotwrstrb wire found_pilots; reg pilotlocated; / * F0LDENDS * / / * FOLDBEGINS 0 OR "sync function arrays" * / reg [11: 0] syncO; reg [11: 0] syncl; reg [1 1: 0] sync2; reg [3: 0] syncoffset; always @ (dcountl2 or validl or valid2) begin if (validl I valid2) syncoffset = 4 'c-dcountl2; else syncsffset = dcountl2; / * FOLDBEGINS O 2"" * / case (syncoffset) 4'hl: begin syncO = 4046; syncl = 272; sync2 = 95; end 4 'h2: begln syncO = 3899; syncl = 476; sync2 = 168; end 4 'h3:' begin syncO = 3661; syncl = 614; sync2 = 217; end 4 'h4: begin syncO = 3344; syncl = 687; sync2 = 243; end 4'h5: begin syncO = 2963; syncl = 701; sync2 = 248; end 4'h6: begin syncO = 2534; syncl = 665; sync2 = 234; end 4 'h7: begin syncO = 2076; syncl = 590; sync2 = 205; end 4'h8: begin syncO = 1609; syncl = 486; sync2 = 167; end 4 * h9: begin syncO = 1152; syncl = 364; sync2 = 123; end 4 'ha: begin syncO = 722; syncl = 237; sync2 = 78; end default begin syncO = 334; syncl = 113; sync2 = 36; end endcase / * FOLDENDS * / end / * FOLDENDS / always © (posedge clk) begin / * FOLDBEGINS02"Control" / constell < = constellation; resynch < = resync; if (resynch) begin / * FOLDBEGINS O 2"" * / vaiid < = l'bO; valid < = 1'bO; validl < = l'bO; valid2 < = l'bO; valid3 < = l'bOj valid4 < = l'bO; valid5 < = l'bO; validate < = l'bOj valid7 < = l'bOj validd < = l'bO; fftcount < = 11 'bO; ramdatavalid < = l'bO; chan_val < = l'bO; tapinit < = l'bO; tapinitl < = l'bO, tapinit2 < = l'bO; rwtoggle < = l'bO; / * FOLDENDS * / end else begin / * FOLDBEGINS O 2"" * / valid < = in_valid; valid < = valid _._. pilotlocated; validl < = valid; valid2 < = validl, valid3 < = valid2, valid4 < = valid3, valid5 < = valid4, validd < = valid5, valid7 < = valid6, validd < = valid7, if (valid2) fftcount < = fftcount + l'bl; chan val < = valid4 && filtgo & __ framedata; incwhichsymbol < = validl & d. (fftcount == (FFTSIZE-l)); if (incwhichsymbol) begin rwtoggle < = ¡Rwtoggle; tapinit < = l'bl; ramdatavalid < = l'bl; end else if (valid6) tapinit < = l'bO; tapinitl < = tapinit; tapinit2 < = tapinitl; / * FOLDENDS * / end fftdata < = in_data; / * FOLDBEGINS OR "frame averager" / if (resynch) begin frav < = l'bO; firstfrav < = l'bO; end else begin if (chan_val && framedata) frav < = l'bl; else if (! framedata && framedataO) frav < = l'bO; if (chan_val £ --- framedata && frav) firstfrav < = l'bl; else if (chan_val) firstfrav < = l'bO; / * FOLDBEGINS O 2"calculate 0.2 x mean channel amplitude" * / if (chan_valO) begin if (firstfrav) begin avchannel < = avmult (sumsqtemp); avenan c = avchan_ [ll: 0]; end else avchannel < = avmult (sumsqtemp) + avchannel; end / * FOLDENDS * / if (chan_vall) avlow < = (sumsqtemp <avchan)? 1: 0; end / FOLDENDS * / if (resynch) begin framedata < = l'bO; framedataO < = l'bO; tapload < = l'bO; end else begin framedataO < = framedata; if (incwhichsymbolS.-. (epoffset == 0)) framedata < = 1 else if (ramdatavalid &S.valid2 & __ (fftcount == (epoffset - 1) framedata < = 1; else if (valid2d. & (fftcount == (epoffset + DATABINS))) framedata < = O; tapload < = framedata; end filtgo = ramdatavalid &S. (valid2? tapload: filtgo); tapload2 < = valid & .-. tapload &&(countl2 == ll) & _. (fftcount = 0 ); pilot < = (countl2 == 0); dcountl2 < = countl2; shift'innewtap < = ¡((Nscat == 139) (nscat == 140) // (nscat == 141)); if (incwhichsymbol) begin if (! ramdatavalid) begin whichsymbol = pwhichsymbol; tapcount < = pwhichsymbol2 'bll + epoffset; end else begin whichsymbol < = whichsymbol + l'bl; t a p c o u n t < =. { whichsymbol [1] "whichsymbol [0], whichsymbol [0].}. 2 'bll + epoffset; end end else if (framedata) begin if (fftcount == cpoffset) begin / FOLDBEGINS O 4" set up the counters " / // countl2 = ((4-whichsymbol) &4 'bOOll) * 3; countl2 < =. { whichsymbol [1] "whichsymbol [O], hichsymbol [0].}. 2 'bll; if (valid) nscat < = 8'bO; / * FOLDENDS * / end else begin / * FOLDBEGINS OR 4"" * / if (valid) begin countl2 < = (countl2 == ll)? 4 'bO: countl2 + l'bl; tapcount < = tapcount + l'bl; 'if (countl2 == ll) nscat < = nscat + l'bl; end / * FOLDENDS * / end end else begin if (tapinit2 & valid5) nscat < = 8'bO; if (tapinit) begin if (valid3 \, valid4 [valid5 & (whichsymbol == 2 'bO)) tapcount < = tapcount + 4 'he; else if (validd) tapcount < = tapcount +. { whichsymbol [1] "whichsymbol [O], whichsymbol [0].}. 2 'bll + l'bl; end end / * F0LDENDS * / / * FOLDBEGINS 0 2" Channel Estimation "* / if (tapinit2) begin / * FOLDBEGINS 0 4"Read in first 3 or 4 taps" * / if (validd) prbs c = alphal 2 (alpha (whichsymbol)) else else (valid6 1 I valid7 1 1 (valid8__. (Whichsymbol == 2 'bO) )) prbs < = alphal2 (prbs); if (valid5) begin tapi [O] < = pseudo (ramout [23: 12], l'bl) tapi [1] < = pseudo (ramout [23: 12 ], l'bl) tapi [2] < = pseudo (ramout [23: 12], l'bl) tapi [3] < = pseudo (ramout [23: 12], l'bl) * tapq [0 ] < = pseudo (ramout [11: 0], l'bl) tapq [l] < = pseudo (ramout [1 1: 0], 1 'b 1); tapq [2] = pseudo (ramout [11: 0], l'bl); tapq [3] < = pseudo (ramout [1 1: 0], 1 'bl); end else if (! ((whichsymbol! = 2 'bO) S_S_valid8)) begin tapi [5] < = tapi [4] tapi [4] < = tapi [3] tapi [3] < = tapi [2] tapi [2] < = tapi [1] tapi.fl] < = tapi [0] tapi [0] < = pseudo (ramout [23: 12], prbs [0]); tapq [5] '< = tapq [4] tapq [4] < = tapq [3] tapq [3] < = tapq [2] tapq [2] < = tapq [l] tapq [l] < = tapq [0] tapq [0] < = pseudo (ramout [11: 0], prbs [0]); end / * FOLDENDS * / end else if (framedata) begin / * FOLDBEGINS 0 4"update taps in normal op." / if (tapload2) begin prbs < = alphal2 (prbs); tapi [5] < = tapi [4] tapi [4] < = tapi [3] tapi [3] < = tapi [2] tapi [2] < = tapi [1] tapi [1] < = tapi [0] if (shiftinnewtap) tapi [0] < = pseudo (ramout [23: 12], prbs [0]); tapq [5] < = tapq [4] tapq [4] < = tapq [3] tapq [3] < = tapq [2] tapq [2] < = tapq [l] tapq [l] < = tapq [0] if (shif innewtap) tapq [0] < = pseudo (ramout [11: 0], prbs [0]); end / FOLDENDS / / FOLDBEGINS0 4"Channel interpolate" / if (pilot) begin if (valid4) begin chani < = tapi [3]; chanq < = tapq [3]; 'end if (valid3) begin idata < = ramot [23: 12]; qdata < = ramot [11: 0]; end end else begin if (valid 1) beg in sumí < = mult (tapi [0], sync2) - mult (tapi [1], syncl); sumq < = mult (tapq [0], sync2); end else if (valid2) begin sumi < = sumí + mult (tapi [2], syncO); sumq < = sumq + mult (tapq [2], syncO) - mult (tapq [1], syncl); end else if (valid3) begin sumi < = sumi + mult (tapi [3], syncO) - mult (tapi [4, syncl); sumq < = sumq + mult (tapq [3], syncO) + 12'h800; 112048 forfinal round-ing idata < = ramot [23: 12]; qdata < = ramot [11: 0]; end else if (valid4) begin chani < = chani_ [23: 12]; chanq < = chanq_ [23: 12]; end end // intsumi = (chani [11])? . { 20 'hfffff, chani [11: 0]} : chani; // intsumq = (chanq [ll])? . { 20 'hffhY, chanq [11: 0]} : chanq; // if (chan_val) $ display (intsumiintsumi + intsumq * intsumq); / * FOLDENDS * / end end assign chani_ = sumi + mult (tapi [5], sync2) + 12'h800; assign chanq_ = sumq + mult (tapq [5], sync2) mult (tapq [4], syncl); assign avchan_ = avchannel + 24'hO00800; ? FOLDENDSt / FOLDBEGINS02"Calcúlate channel" / always © (posedge clk) begin if (resynch) begin chan valO < = l'bO; chan_vall = l'bO chan_val2 < = l'bO, chan_val3 < = l'bO chan_val4 < = l'bO, out_valid < = l'bO; end else begin chan_valO < = chan_val; chan_vall < = chan_valO¡ chan_val2 < = chan_vall, chan_val3 < = chan_val2, chan_val4 < = chan_val3 llout_valid < = chan_val4; out_valid < = chan_val4 &_ramdatavalid -. &: pilotdata [1]; end if (chan_val) sumsqtemp < = sum [22: 11]; if (chan_valO) topreal < = sum [23: 12]; if (chan_vall) topimag < = sum [23: 12]; if (chan_val2) sumsq < = sum [23: 12]; if (chan val3) begin outitemp < = divider (topreal, sumsq, (constell == 0)); outitem < = divplussoft (topreal, sumsq, constell); end if (chan_val4) begin outq < = divider (topimag, sumsq, (constell == 0)); outi < = outitemp; end // intouti = (outi [7])? . { 24 'hmrrr, outi [7: 0]} : outi; // intoutq = (outq [7])? . { 24 'hfffff, outq [7: 0]} : outq; // if (chan_val _. & ramdatavalid) $ display (intsumi); // if (chan_val4 & __ ramdatavalid) $ displayb (outitemp'Outitem); end always @ (chan_val or chan_valO or chan_vall or chani or chanq or constell or idata or qdata or sumsqtemp) beg in if (chan_val) sum = smult (chani, chani, 1) + smult (chanq, chanq, 1) + 24 ' HO00400; else if (chan_valO) sum = smult (idata, chani, 1) + smult (qdata, chanq, 1) + 24'hO00800; else if (chan_vall) sum = smult (qdata, chani, 1) - smult (idata, chanq, 1) + 24'hO00800; else // chan val2 begin case (constell) 2 'bOO: sum = smult (sumsqtemp, SCALEFACTORQPS, 0) + 24'hO00800; 2'bO 1: sum = smult (sumsqtemp, SCALEFACT0R16Q, 0) + 24'hO00800; default: sum = smult (sumsqtemp, SCALEFACTOR64Q, 0) + 24'hO00800; endcase end end / FOLDENDS / / FOLDBEGINS O 2"Extract Continual and scattered pilots for Freq + Sampling Error Block "* / always © (posedge clk) begin if (resynch) contloccount c = 6'bO; else if (ramdatavalidS -_. Valid2S ._- (pilotaddr == contloc)) contloccount < = (contloccount == 44)? 6'bO: contloccount + l'bl; if (ramdatavalidS-S.valid2S .__ ((pilotaddr == contloc) 1 1 pilot)) uncorrected_iq < = ramot; uc_pilots < = ramdatavalid &S-framedataS-S. (pilotaddr == contloc) & _. valid2 _._.! resy nch; us_pilots < = ramdatavalidS_.framedata _-_. pilot _._. valid2 _._. J resynch; u_symbol < =! resynch _._. ramdatavalids_ £. (valid2? (pilotaddr == 0): u_symbol); // $ display (pilotaddr "ramot [23: 12]" valid2"contloccount" uncorr ected_iq [23: 12] "uneorrected_iq [ll: 0]" uc_pilots "us_pilots); end / * FOLDENDS * / / * FOLDBEGINS O 2" Extract TPS pilots "* / always © (posedge clk) begin if (resynch) begin tpscount < = 5'bO; tps_pilots c = 3'bO; tps_valid < = l'bO; ct_pilots < = l'bO; end else begin if (ramdatavalidS.S_valid2S.S- (pilotaddr == tpsloc)) tpscount < = (tpscount [4])? 5'bO: tpscount + l'bl; t p s _ p i l t s [0] < = v a l i d 2? ramdatavalid & amp; amp; amp. & (pilotaddr == tpsloc): tps_pilots [O]; tps_pilots [1] < = (chan_val? tps_pilots [O]: tps_pilots [1]); tps_pilots [2] < = tps_pilots [1] S_S_chan_val3; tps_valid < = (tpscount == 0) S_S.tps_piiots [2]; ct_pilots c = tps_pilots [2]; end if (resynch) tpsmajcount < = 6'bO; else begin if (tps_pilots [2]) begin if (tpscount == 0) begin tpsmaj count c = 6'bO; out_tps c = tpsmaj count_ [5]; end else tpsmaj count c = tpsmaj count_; end end if (resynch) pilotdata c = 2'bO; else begin if (valid2) pilotdata [O] c = ramdatavalidSSframedataS-S. ((pilotaddr == tpsloc) (pilotaddr == contloe) pilot); pilotdata [1] c = chan_valO? pilotdata [O]: pilotdata [1]; end / / $ d i s p l a y (p i l o t a d d r r a m o t [2 3: 12] "valid2" contloccount "uncorrected_iq [2 3: 12]" uncorrected_iq [1 1: 0] "uc_pilots" us_pilots); // $ display (valid2"pilotdata [0]" pilotdata [1] "pilotdata [2]" ct_ pilots, ... "out_valid" pilotaddr); end assign tpsmajcount_ = tps (topreal [1 1], tpscount, tpsmaj count); / * FOLDENDS * / / * FOLDBEGINS 1 2"pilot reach control" * / always tposedge clk) begin if (resynch) pilotlocated < = l'bO; else if (foundilots) begin pilotlocated < = l'bl; pwhichsymbol < = which_symbol + 2'blO; end end / * FOLDENDS * / / * FOLDBEGINS 0 2"RAM" * / always @ (posedge clk) begin if (pilotlocated) begin wrstrb < =! valid; if (valid) ramindata < = fftdata; pilotaddr < = ramaddr_- epoffset; ramaddr < = rwtoggle? ramaddr_: ramaddrrev_; if (valid5) ramot < = ramout; end else begln / * FOLDBEGINS 0 4"" * / wrstrb < = pilotwrstrb_; ramindata < = pilotramin_; ramaddr < = pilotramaddr / * FOLDENDS * / end ramout < = ramoutdata; end assig n ramadd r_ = (tapin it I framed ataS_ & (valid2 & __. (countl 2 == 1 1)))? tapcou nt: fftcount; assign ramaddrrev. { ramaddr _ [0], ramaddr 1], ramaddr_ [2], ramaddr_ [3], ramaddr_ [4], ramaddr_ [5], ramaddr_ [6], ramaddrl7], ramaddr_ [8], ramaddr_ [9], ramaddr_ [ 1 0]}; / * F0LDENDS * / assign c_symbol = whichsymbol [0]; / * FOLDBEGINS 00"" * / aiways © (posedge clk) begin // $ display (chan_val "framedata" frav "f irsf frav" "valid2" valid4"out_valid" avchannel "avchan" sumsqtemp ", avlow" chan_vall "); // $ display (tps_valid" out_tps "tpscount" tps_pilots [2]); // $ display (in_data "filtgo,, valid4" apload ", nscat" count 12"fft count" incw hichsymbol ", // tapcount" ramaddr "wrstrb" rwtoggle 11); // (resynch "valid" ff tcount "ramaddr" ramindata [23: 12"ramoutdata [23:12]" t apinit "tapinit2" tapcount "ramout [23: 12]" // tapi [0] "tapi [1] "tapi [2]" tapi [3] "tapi [4]" tapi [5]); // $ display (tapcount "tapinit2" valid4"valid "valid2" wrstrb "fftcount" fram edata "count 12" tapi [0] "tapi [1]" tapi [2] "tapi [3]" tapi [4] "tapi [5]); // $ display ("" intouti "intoutq" out_val id " "val id4" val id2"chan_val" fi 11 go "framedata" ff tcount "ramindata [23: 12]); // if (whichsymbol == 1) $ display (tapinit" tapcount "fftcount" ramindata [23: 12] " "tapcount" tapi [O] "tapi [1]" tapi [2] "tapi [3]" tapi [4] "tapi [5]" intsumi "intsumq" gone ta "qda ta); // $ display (framedata "pilotaddr" fftcoun "tapcoun" ramaddr "ram out [23: 12], ramindata [2 3: 12] "prbs" us_pilots "uc_pilots" ct_pilots "out_valid", contl occount "// tps_pilots [O]" tps_pilots [1] "tps_pilots [2]); end / * FOLDENDS * / pilloc pilloc (.clk (clk), resync (resync), .in_valid (in_valid), .in_data (in data),. found_pilots (found_pilots), .which_symbol (which_symbol), .epoffset (epoffset), .incfreq (incfreq), .ramaddr (pilotramaddr,. ramin (pilotramin, .ramout (ramout), .wrstrb (pilotwrstrb); / FOLDBEGINS 0 2"functions" * / / FOLDBEGINS OO "tps demod" * / function [5: 0] tps; input tpssign; input [4: 0 ] tpscount; input [5: 0] tpsmaj count; reg tpsflip; begin case (tpscount) 5'bO0001,5'bO0011,5'bO0100,5'bO0110,5'bO1011,5'bO1110: tpsflip = O; // added tpscount already incremented default: tpsflip = 1; endease tps = (tpsflipAtpssign)? tpsmaj count - l'bl: tpsmaj count + l'bl; end 'endfunction / * FOLDENDS / / FOLDBEGINS OO "pseudo function" / function [11 : 0] pseudo; input [11: 0] data; input flip, begln pseudo = flip? -data + l'bl: data; end endfunction / * FOLDENDS * / / * FOLDBEGINS OR O "averager multiplier" * / function [11: 0] avmult; input [11: 0] i; reg [23: 0] res; begin res = (i * AVEiRAGESF) + 23'hO00800; // multiply and round avmult = res [23: 12]; end endfunction / * FOLDENDS * / / * FOLDBEGINS 0 0"filter tap multiplier" * / function [27: 0] mult; input [11: 0] i; input [11: 0] j; reg [23: 0] res; reg [11: 0] modi; reg [11: 0] invi; begin invi = ~ i + l'bl; modi = i [11]? invi: i; res = (modi * j); // multiply and round mult = i [ll]? . { 4'hf, res} + l'bl: res; end endfunction * FOLDENDS * / / * FOLDBEGlNS00"signed multiplier, '* / function [23: 0] smult; input [1 1: 0] i; input [11: 0] j; input signedj; reg [23: 0] res; reg [11: 0] modi; reg [11: 0] modj; beg in modi = i [11]? ~ i + l'bl: i; modj = (j [1 1] SS-signedj)? ~ j + l'bl: j; res = (modi * modj); smult = (i [ll] A (j [1 1] S &signedj))? res + l'bl: res; end endfunction / * F0LDENDS * / / * FOLDBEGINS00"divider funetion" * / function [7: 0] divider; input [11: 0] dividend; input [11: 0J splitter; input qpsk; reg [11: 0] moddividend; reg signresult; reg [12: 0] intval; reg [12: 0] carry; reg [7: 0] divides; reg [8: 0] signeddivide; integer i; begin signresult = dividend [11]; moddividend = dividend [11]? -dividend + l'bl: dividend; divide = O; carry = qpsk? . { l 'bO, moddividend} : { moddividend, 1 'b ?}; / * FOLDBEGINS O 2"" * / for (i = 0; i &8; i = i + l) begin intval = carry - divisor; divide [7-i] =! intval [12]; carry = (intval [12])? . { carry [11: 0], 1 'b ?} : { intval [11: 0], 1 • bO}; end / * FOLDENDS * / // signeddivide = signresult? ~ divide + 2'blO: divide + l'bl; signeddivide = signresult? . { l 'bl, ~ divide} + 2'blO: . { l'bO, divide} + l'bl; // $ displayb (signeddivide "divide" signresult "constellation"); divider = signeddivide [8: 1]; end endfunction * FOLDENDS * / / * FOLDBEGINS00"divider function with soft decisions added" * / function [5: 0] divplussoft; input [11: 0] dividend; input [11: 0] divisor; input [1: 0] constellation; reg [11: 0] moddividend; reg signresult; reg [12: 0] intval; reg [12: 0] carry; reg [8: 0] divides; reg [10: 0] signeddivide; reg [11: 0] fracdivide; integer i; beg in signresult = dividend [11]; moddividend = dividend [11]? ~ dividend + l'bl: dividend; divide = O; carry = (constellat ion = = 0)? . { 1 'bO, moddividend} . { moddividend, 1 'b ?}; / * FOLDBEGINS O 2"" * / for (i = 0; i <9; i = i + l) beg in intval = carry - divisor; divide [8-i] =! intval [12]; carry = (intval [12])? . { carry [11: 0], 1 'b ?} : { intval [11: 0], 1 'b ?}; end / * FOLDENDS * / signeddivide = signresult? . { 2 'bll, -divide} + l'bl: . { 2 'bO, divide}; // $ displayb (signeddivide "divide" signresult "constellation"); / * FOLDBEGINS OR 2"qpsk" * / if (constellation == 2 'bO) begin // $ writeh ("signeddivide" ") signeddivide = signeddivide + 8'h80; // $ writeh (signeddivide" "); if (signeddivide [10]) fracdivide = 9'hO; else if (signeddivide [9] 1 1 signeddivide [8]) fracdivide = 12'h700; else begin fracdivide = signeddivide [7: 0] +. { signeddivide [7: 0], 1 'b ?} + . { signeddivide [7: 0], 2'b ?}; 11 * 7 fracdivide = fracdivide + 8'h80; end divplussoft =. { 3 'bO, fracdivide [10: 8]}; end else / * FOLDENDS * / / * FOLDBEGINS O 2"16qam" * / if (constellation == 2 'bOl) begin $ writeh ("signeddivide" ") signeddivide = signeddivide + 8'hcO; $ writeh (" signeddivide " "); if (signeddivide [10]) begin signeddivide = 10 'bO; fracdivide = 9'hO; end else if (signeddivide [9] 1 (signeddivide [8: 7] == 2 'bll)) begin Aracdivide = 12' 1.380; signeddivide = 10 'hlOO; end else begln fracdivide = signeddivide [6: 0] +. { signeddivide [6: 0], 1 'b ?} + . { signeddivide [6: 0], 2 'b ?}; I 1 * 1 fracdivide = fracdivide + 8'h40; end divplussoft =. { l 'bO, signeddivide [8: 7], fracdivide [9: 7]}; end / * FOLDENDS * / / * FOLDBEGINS O 2"32qam" * / else beg in signeddivide = signeddivide + 8'heO; if (signeddivide [10]) begin signeddivide = 10 'bO; fracdivide = 9'hO; end else if (signeddivide [9] "I (signeddivide [8: 6] == 3 'blll)) begin signeddivide = 10' h 180; fracdivide = 9'hlcO; end else begin fracdivide = signeddivide [5: 0] +. { signeddivide [5: 0], 1 'b ?} +. { signeddivide [5: 0], 2 'b ?}; 117 fracdivide = fracdivide + 8'h20; end divplussoft =. { signeddivide [8: 6], fracdivide [8: 6]} , end / * FOLDENDS * / end endfunction / * FOLDENDS * / / * FOLDBEGINS OR O "PRBS alpha3 / 6/9 / l2 multiplier" * / function [10: 0] alpha; input [1: 0] which_symbol; begin case (which_symbol) 2'bO: alpha = 11 2 'bO 1: alpha = 11 2' blO: alpha = 11 'bOOOOOOlllll; 2'bll: alpha = ll'bOOOOOOOOOll; endcase end endfunction / * FOLDENDS * / / * FOLDBEGINS00"PRBS alphal2 multiplier". * / function [10: 0] alphal2; input [10: 0] prbsin; reg [10: 0] prbsO; reg [10: 0] prbsl; reg [10: 0] prbs2; reg [10: 0] prbs3; reg [10: 0] prbs4: reg [10: 0] prbs5; reg [10: 0] prbs6; reg [10: 0] prbs7; reg [10: 0] prbsd; reg [10: 0] prbs9; reg [10: 0] prbslO; begin prbsO =. { prbsinfO] A prbsin [2], prbsin [10: 1]}; prbsl =. { prbsO [0] A prbsO [2], prbsO [10: 1]} prbs2 =. { prbsl [0] A prbsl [2], prbsl [10: 1]} prbs3 =. { prbs2 [0] A prbs2 [2], prbs2 [10: 1]} prbs4 =. { prbs3 [0] A prbs3 [2], prbs3 [10: 1]} prbs5 =. { prbs4 [0] A prbs4 [2], prbs4 [10: 1]}; prbs6 =. { prbs5 [0] A prbs5 [2], prbs5 [10: 1]}; prbs7 =. { prbs6 [0] A prbsd [2], prbs6 [10: 1]}; prbsd =. { prbs7 [0] A prbs7 [2], prbs7 [10: 1]}; prbs9 =. { prbs8 [0] A prbsd [2], prbs8 [10: 1]}; prbslO =. { prbs9 [0] A prbs9 [2], prbs9 [10: 1]}; alphal2 =. { prbslO [0] To prbslO [2], prbslO [10: 1]}; end endfunction / * FOLDENDS * / / * FOLDEN DS * / endmodule Listing 19 / * FOLDBEGINS 0 0"Copyright" * / ************************ ******** Copyright (c) Pioneer Digital Design Center Limited ÑAME: pilloc_rtl v PURPOSE: Pilot location CREATED: June 1997 BY: J. Parker (C code) MODIFIED: BY: T. Foxcroft USED IN PROJECTS: cofdm only **************************** / * FOLDENDS * / 'define FFTSIZE 2048' define SCATNUM 45 module pilloc (clk , resync, in_valid, in_data, found_pilots, which_symbol, epoffset, incfreq, ramaddr, ramin, ramout, wrstrb); / * FOLDBEGINS 0 0"i / o" * l input clk, resync, in_valid; input [23: 0] in_data; output found_pilots; output [1: 0] which_symbol; output [10: 0] epoffset; output incfreq; / * FOLDENDS * / / * FOLDBEGINS 0 0"ram i / o" * / output [10: 0] ramaddr; reg [10: 0] ramaddr_; output [23: 0] ramin; input [23: 0] ramout; output wrstrb: reg [10: 0] ramaddr; reg [23: 0] ramin; reg wrstrb; / * F0LDENDS * / / * FOLDBEGINS 0 0"vars" * / reg found_pilots; reg [1: 0] which_symbol; reg [1: 0] which_symbolcount; reg [1: 0] which_symbol_; reg [10: 0] epoffset; reg incfreq; reg found_ilot; reg [19: 0] v; reg [19: 0] sum; reg [3: 0] splocoffset; wire [10: 0] carrier_number; reg [10: 0] continual_pilot_of f set; reg resynch; reg [3: 0] valid; reg [23: 0] fftdata; reg [10: 0] f f tcount; reg contcomplete; reg f irsteontsearch; reg ñnishedsearch; reg [4: 0] f irstscatcomplete; reg [4: 0] f ailedtolock; reg [2: 0] spmax; reg [2: 0] spmaxfirst; reg [10: 0] pilot_of f set; reg [1: 0] splocl zero; reg [10: 0] splocO; reg [5: 0] splocl; reg [10: 0] splocmaxcount; reg [3: 0] spoffset; reg [19: 0] sumscat [11: 0]; reg [19: 0] sumscatmax; reg [3: 0] sumscatmaxnoO; reg [3: 0] sumscatmaxnol; wire [19: 0] sumscatl; wire [19: 0] sumscat3; wire [19: 0] sumscat5; reg [11: 0] sumscatfirst; reg [4: 0] fftfinished; reg ramwritestop; // botch for development purposes wire [3: 0] modl2fftcount; / * FOLDENDS * / / * FOLDBEGINS O O "continuous pilot location" * / reg [10: 0] contloc; always © (splocl) begin case (splocl) 6'bOOOOOO: contloc = O; 6'bO00001: contloc = 48, 6'bO00010: contloc = 54, 6'bO00011: contloc = 87, 6'bO00100: contl? C = 141, 6'bO00101: contloc = 156; 6 'bOOOHO: contloc = 192 6 • bOOOlll: contloc = 201 6 bO0Í000: contloc = 255 6 bOOlOOl: contloc = 279 6 bOOlOlO: contloc = 282 6 bOOlOll: contloc = 333 6 bOOHOO: contloc = 432 6 bOOllOl: contloc = 450 6 bOOlllO: contloc = 483 6 bOOllll: contloc = 525 6 bOlOOOO: contloc = 531 6 bOlOOOl: contloc = 618 6 bOlOOlO: contloc = 636 6 bOlOOll: contloc = 714 6 bOlOlOO: contloc = 759 6 bOlOlOl: contloc = 765 6 'bOlOllO: contloc = 780 6 'bOlOlll: contloc = 804 6 'bOllOOO: contloc = 873 6 'bOllOOl: contloc = 868 6 'bOllOlO: contloc = 918 6 'bOllOll: contloc = 939 6 'bOlllOO: contloc = 942 6 'bOlllOl: contloc = 969 6 'bOllllO: contloc = 984 6'b? Lllll: contloc = 1050 6'bl00000: contloc = 1101 6'bl00001: contloc = 1107 6'bl00010: contloc = 11 10 6'bl00011: contloc = 1137 6'bl00100: contloc = 1140 6'bl00101: contloc = 1146 6'blOOllO: contloc = 1206 6'blOOlll: contloc = 1269 6'bl01000: contloc = 1323 6'bl01001: contloc = 1377 6'blOlOlO: contloc = 1491 6'bl? L? ll contloc = 1683 default: contloc = 1704; endcase end / * FOLDENDS * / always © (posedge clk) begln resynch < = resync; if (resynch) beg in valid < = 4'bO; fftcount < = 1 1 'bO; firstscatcomplete < = 5 sum < = 20 'bO; splocO < = 11 'bO; splocl < = 6'bO, contcomplete < = l'bO; failedtolock < = 5'bO; spmax < = l'bO; spmaxfirst < = l'bO; ramwritestop < = l'bO; found_pilots < = l'bO; found_pilot < = 1'bO; firstcontsearch < = 1'bO; finishedsearch < = l'bO; which_symbolcount < = 2'bO; incfreq < = l'bO; end else begin incfreq < =! failedtolock [1] _.s.failedtolock [0] S.S.fftfinished [4]; found_pilots < =! found_pilotS.S.finishedsearch; found_pilot < = hnishedsearch; valid [O] < = in_valid; valid [1] < = valid [O]; valid [2] < = valid [1]; valid [3] < = valid [2]; fftdata < = in data; - if (valid [O] S-S-Ifinishedsearch) fftcount < = fftcount + l'bl; // if (fftfinished [O]) // $ display ("frame" "fftcount); // if (incfreq) 11 $ display (" tweek "); / * FOLDBEGINS OR 4" get continual pilots "* / spmax [ 1] < = spmax [0]; spmax [2] < = spmax [1]; spmaxfirst [1] < = spmaxfirst [0]; spmaxfirst [2] < = spmaxfirst [1]; // if ( fftfinished [3]) // $ display (spoffset "which_syrnbol); if (fftfinished [3]) begin failedtolock [1] < = failedtolock [O]; failedtolock [2] < = failedtolock [1], -failedtolock [3] < = failedtolock [2]; ailedtolock [4] < = failedtolock [3], -if (failedtolock [O]) begin / * FOLDBEGINS O 2"" * / if (failedtolock [4]) failedtolock [O] < = 1'bO; firstscatcomplete < = 5'bO; ramwritestop < = l'bO; firstcontsearch < = l'bO; / * FOLDENDS * / end else begin / * FOLDBEGINS OR 4"" * / firstscatcomplete [O] < = l'bl; firstcontsearch < =! firstscatcomplete [O]; ramwritestop < = Ramwritestop finishedsearch; contcomplete < = ramwritestop; if (! finishedsearchs.s.firstscatcomplete [O] S.S-ramwritestop) begin f inishedsearch < = f irstcontsearch? 1 'bO: (cpof f set == continual_pilot_of f set); epoffset < = continual_pilot_of f set, -f a i l e d t o l or c k [0] < ! f irstcontsearchScS. (epoffset! = continual_pilot_of f set); end XFOLDENDS * / end end else begin f irstscatcomplete [1] < = f irstscatcomplete [O] SS. ! contcomplete; firstscatcomplete [2] < = firstscatcomplete [1; if (firstscatcomplete [O] £ .-.! finishedsearch &S!! contcomplete -.-.! fi nishedsearch SaSc (splocl == 44) Scí (splocO == splocmaxcount)) contcomplete < = l 'bl; end if (found_pilots) $ display (which_symbol "epoffset" spoffset); // $ display. { sum "contcomplete" ramwritestop "which_symbol" spoffset ", splo cO" splocmaxcount,, v,,,,,, fftfinished [3] "finishedsearch); // $ display (fftcount" firstscatcomplete [O],, ramwritestop,, ,, spoffset,, umsca tmaxno 1"" finishedsearch "found_pilots" // "// pilot_offset" which_symbol "" epoffse "failedtolock); sploclzero [0] < = (splocl == 0); sploclzero [1] < = sploclzero [0]; if (firstscatcomplete [0] ScSd finishedsearch -...! contcomplete _- &! fi nishedsearch) begi'n if (splocl == 44) begin / * FOLDBEGINS 0 4"" * / // $ display (splocO "splocmaxcount); pilot_offset < = splocO + splocoffset; which_symbol < = which_symbol_- which_symbolcount; if (splocO == splocmaxcount) begin splocO < = 11 'bO; // contcomplete < = l'bl; which_symbolcount < = 2'bO; end else begin splocO < = splocO + 2 'bll; which_symbolcount < = which_symbolcount + l'bl; end íf (splocO == 0) spmaxfirs [O] < = l'bl; splocl < = 6'bO; spmax [O] < = l'bl; / * FOLDENDS * / end else begin / * FOLDBEGINS OR 4"" * / splocl < = splocl + l'bl; spmax [0] < = l'bO; spmaxfirst [O] < = l'bO; / * FOLDENDS * / end - end if (firstscatcomplete [2]) begin if (splocl zero [l]) sum < = modulus (ramout [23: 12], ramout [11: 0]); else sum < = modulus (ramout [23: 12], ramout [11: 0]) + sum; end? FOLDENDS * / end? FOLDBEGINS O 2"search for largest 'continous pilot correlation" * / if (spmax [2]) begin if (spmaxfirst [2]) begin v < = sum; continual_pilot_offset < = pilot_offset; end else begin if (sum > v) begin v < = sum; continual_pilot_offset < = pilot_offset; end end // $ display (sum "continual_pilot_offset" contcomplete "ramwrites top" which symbol "spoffset", splocO "splocmaxcount" v); // $ display (sum); end / * F0LDENDS * / end assign carrier_number = contloc + splocO + splocoffset; XFOLDBEGINS O O "scattered pilot offset mod 3" * / always © (spoffset) begin splocoffset = 2'bO; splocmaxcount = 342; which_symbol_ = 2'bO; case (spoffset) 4 'bO000,4' bO011,4 'bO 110, 4'b 1001: begin splocoffset = 2'bO; splocmaxcount = 342; end 4 'bO001,4' bOlOO, 4 'bOlll, 4' bl010: 'begin splocoffset = 2'b? l; splocmaxcount = 339; end // 4'bOOlO, 4'bO 101, 4'blOOO.4'bl? ll: default: begin splocoffset = 2'bl ?; splocmaxcount = 339; end endcase case (spoffset) 4 'bO000,4' bOOOl-4 'bO010: which_symbol_ = 2'bO; 4 * bO011,4 'bO100,4' bOlOl: which_symbol_ = 2'b? L; 4 'bOllO, 4' b0111,4 'blOOO: which_symbol_ = 2'blO; // 4 'bl001,4' bl010,4 'blOll: default: which_symbol_ = 2'bll; endcase end / * F0LDENDS * / / * FOLDBEGINS 10"Search for scattered pilots" * / always © (posedge clk) begin if (resynch) sumscatfirst < = 12'hfff; else begin if (valid [0] _. £.! finishedsearch) / * FOLDBEGINS 12"do the accumulations" * / case (12fftcount mod) 4'hO: begin sumscat [O] < = (sumscatfirst [O])? modulus (fftdata [23: 12], fftdata [11: 0]): sumscat [O] + modulus (fftdata [23: 12], fftdata [11: 0]); sumscatfirst [O] < = l'bO; end 4 'hl: begin sumscat [1] < = (sumscatfirs [1]? modulus (f ftdata [23: 12], f ftdata [11: 0]): sumsca [1] + modulus (f ftdata [23: 12], f ftdata [11: 0]); sumscatf irst [1] < - l 'bO; end 4' h2: begin sumscat [2] < = (sumscatf irst [2])? modulus (f ftdata [23: 12], f ftdata [11: 0] ): sumscat [2] + modulus (f ftdata [23: 12], f ftdata [11: 0]); sumscatf irst [2] < = l'bO; end 4 'h3.-begin sumscat [3] < = (sumscatfirst [3])? modulus (f ftdata [23: 12], f ftdata [11: 0]): sumscat [3] + modulus (f ftdata [23: 12], f ftdata [11: 0] ); sumscatf irst [3] < = l'bO; end 4 'h4: begin sumscat [4]' < = (sumscatf irst [4])? modulus (f ftdata [23: 12], f ftdata [11 : 0]): sumscat [4] + modulus (f ftdata [23: 12], f ftdata [11: 0]); sumscatf irst [4] < = l'bO; end 4'h5: begi'n sumscat [5] < = (sumscatfirst [5])? Modulus (f ftdata [23: 12], f ftdata [11: 0]): sumscat [5] + modulus (f ftdata [ 23: 12], f ftdata [11: 0]); sumscatf irst [5] < = l'bO; end 4 'h6: begin s u m s.c a t [6] < = (s u m s c a t f i r s t [6])? • modulus (f ftdata [23: 12], f ftdata [11: 0]): sumscat [6] + modulus (fftdata [23: 12], fftdata [11: 0]); sumscatfirst [6] < = l'bO; end 4, h7: begin s u m s c a t [7] < = (s u m s c a t f i r s t [7])? modulus (f ftdata [23: 12], f ftdata [11: 0]): sumscat [7] + modulus (f ftdata [23: 12], f ftdata [11: 0]), - sumscatf irst [7] < = l'bO; end 4 'h8: begin s u m s c a t [8] < = (s u m s c a t f i r s t [8])? modulus (f ftdata [23: 12], f ftdata [11: 0]): sumscat [8] + modulus (f ftdata [23: 12], f ftdata [11: 0]); sumscatf irs [8] < = l'bO; end 4 'h9: begin sumscat [9] < = (sumscatf irs [9])? modulus (fftdata [23: 12], fftdata [11: 0]): sumsca [9] + modulus (fftdata [23: 12], fftdata [11: 0]); • sumscatfirst [9] < = l'bO; end 4 'a: begin sumscat [10] < = (sumscatfirst [10])? modulus (fftdata [23] 12], fftdata [11: 0]): sumscat [10] + modulus (fftdata [23: 12], fftdata [11: 0]); sumscatfirst [10] < = l'bO; end default: begln sumscat [11] < = (sumscatfirst [11])? modulus (fftdata [23: 12], fftdata [11: 0]): sumscat [11] + modulus (fftdata [23.- 12], fftdata [11: 0]); sumscatfirst [11] < = l'bO; end endcase XFOLDENDS * / else if (fftf inished [O]) sumscatfirst < = 12'hfff; end / * FOLDBEGINS10"Find offset" * / if (resynch) fftfinished < = 5'bO; else begin fftfinished [0] < = valid [O] S.S.! finishedsearchS_S- (fftcount == 2047); ffttinishedfl] < = fftfinished [0]; fftfinished [2] < = fftfinished [1]; fftfinished [3] < = fftfinished [2], - fftíinished [4] < = fftfinished [3]; end if (! ramwritestop) begin if (f ftf inished [0]) begin sumsca [0 < = (sumscat [0] sumscat [1])? sumscat [0]: sumscat [1 sumscat [1 < = (sumscat [0] > sumscat [1])? 0: 1; sumscat [2 < = (sumscat [2] > sumscat [3])? sumscat [2] sumscat [3. sumscat [3 < = (sumscat [2] > sumscat [3])? 2. 3; sumsca [4 < = (sumscat [4] > sumscat [5])? sumscat [4] sumscat [5 sumscat [5 < = (sumscat [4] > sumscat [5])? Four. Five; sumscat [6 < = (sumscat [6] > sumscat [7])? sumscat [6] sumscat [7 sumscat [7 < = (sumscat [6] > sumscat [7])? 6: 7; sumscat [8] < = (sumscat [8] > sumscat [9])? sumscat [8] sumscat [9]; sumscat [9] < = (sumscat [8] > sumscat [9])? 8: 9; sumscat [10] < = (sumscat [10] > sumscat [11])? sumscat [10]: sumscat [11]; sumscat [11] < = (sumscat [10] > sumscat [11])? 1 0: 1 1; end if (fftf inished [1]) begin sumscat [0 (sumscat [0] > sumscat [2])? sumscat [0]: sumscat [2 sumscat [1 (sumscat [0] > sumscat [2])? sumscat [1] sumscat [3 sumsca [2 (sumscat [4] > sumscat [6])? sumscat [4] sumscat [6 sumscat [3: sumscat [4] > sumscat [6])? sumscat [5] sumscat [7 sumscat [4 < = (sumsca [8] > sumscat [10])? sumscat [8] sumsca [10]; sumscat [5] < = (sumscat [8] > sumscat [10])? sumscat [9] sumscat [11], -end if (fftfinished [2] S.S.! ramwritestop) spoffset < = sumscatmaxnol; end if (fftfinished [0]) begin $ display (sumscat [0]); $ display (sumscat [1]); $ display (sumscat [2]) $ display (sumscat [3]) $ display (sumscat [4]) $ display (sumscat [5]) $ display (sumscat [6]) $ display (sumscat [7]) $ display (sumscat [8]) $ display (sumscat [9]) $ display (sumsca [10]); $ display (sumscat [11]), - $ display (); end end always © (sumscat [O] or sumscat [1] or sumscat [2] or sumscat [3] or sumscat [4] or sumscat [5] or sumscatl or sumscat3 or sumscat5) begin sumscatmax = (sumscat [O] > sumscat [2])? sumscat [O]: sumscat [2]; sumscatmaxnoO = (sumscat [O] > sumscat [2])? sumscatl [3: 0]: sumscat3 [3: 0]; sumscatmaxnol = (sumscatmax > sumscat [4])? sumscatmaxnoO: sumscat5 [3: 0]; end assign modl2fftcount = modl2 (fftcount); assign sumscatl = sumscat [1]; assign sumscat3 = sumscat [3]; assign sumscat5 = sumscat [5]; / * FOLDENDS * / / * FOLDENDS * / / * FOLDBEGINS00"ram" * / always © (posedge clk) ramaddr_ < = ramaddr; always © (ramwritestop or valid or finishedsearch or fftcount or carrier_number or ramwritestdp or ramaddr_or fftdata) begin ramaddr = ramaddr_; if (! ramwritestop) begin if (valid [O] S-S_! finishedsearch) r 'a m a d d r = . { fftcount [O], ff count [1], fftcount [2], fftcount [3], fftcount [4], fftcount [5], fftcount [6], fftcount [7], fftcount [8], ffcount [9] ], fftcount [10]}; end else ramaddr = carrier_number; ramin = fftdata; - wrstrb =! (! ramwritestop_.S.valid [1]); end / * FOLDENDS * / / * FOLDBEGINS00"modulus approximation function *" / function [11: 0] modulus; input [11: 0] i; input [11: 0] j; reg [11: 0] modi; reg [1 1: 0] modj, - begin modi = (i [11]? A: i) + i [11]; modj = (j [11]? ~ j: j) + j [11]; modulus = modi + modj; end endfunction XFOLDENDS * / / * FOLDBEGINS 0 0"modl2" * / function [3: 0] modl2; input [10: 0] count; reg [14: 0] onetwelfth; reg [7: 0] modulusl2: parameter TWELFTH = 12'haab; begin onetwelfth =. { count [0], count [1], count [2], count [3], count [4], count [5], count [6], coun [7], count [8], count [9], count [10]} * TWELFTH; modulusl2 =. { onetwelf th [14: 9], 1 'b ?} + onetwelFth [14: 9] + 4 'hd; // * 12 modl2 = modulusl2 [7: 4]; end? FOLDENDS * / endfunction endmodule Listing 20 // Sccsld: @ (#) bch_decode.v 1.2 d / 22/97 / * FOLDBEGINS 0 0"copyright" * / // ************ ********************** Copyright (c) 1997 Pioneer Digital Design Center Limited // // PURPOSE: BCH decoder for TPS pilots. Flags up to two error // positions using search technique. // // ********************************* XFOLDENDS * / define DATA0_SIZE 7 'bOllOlOO defines DATA1 _SIZE 7'b? ll? lll module bch_decode (clk, resync, in_data, in_valid, in_finalwrite, out_valid, out_data); / * FOLDBEGINS 0 0"I / Os" * / input clk, resync; input in_data, in_valid, in_finalwrite; output out_valid; output out_data; reg out_data; reg out_valid; / * FOLDENDS * / / * FOLDBEGINS 0 0"variables" * / reg resynch; reg valid; reg finalwrite; reg indata; reg [6: 0] S 0; reg [6: 0] YES; reg [6: 0] S2; reg [6: 0] count; reg searchlerror, found2error, oneerror, twoerror; wire twoerror_; reg noerrors; reg delayO, delayl, delay2; reg [6: 0] GsO, reg [6: 0] Gsl, reg [6: 0] Gs2, / * FOLDENDS * / always © (posedge clk) begin / * FOLDBEGINS O 2"read in data and calculate syndromes" * / resynch < = resync; if (resynch) begin valid < = 1'bO; 50 < = 7'bO; 51 < = 7'bO; 52 < = 7'bO; end else begin valid < = in_valid; if (delayl ___. twoerror_) begin / * FOLDBEGINS OR 4"update after one in two errors found" * / 50 < = SOAGsO j 51 < = SXGsl 52 < = S2AGs2 / * FOLDENDS * / end else if (valid) begin SO < = indata "MULTA1 (SO) SI <Indata" MULTA2 (SI) S2 < = indata "MULTA3 (S2) end end indata < = in_data; / * FOLDENDS * / / * FOLDBEGINS O 2" out_valid control "* / if (resynch) begin delayO < = l'bO; delayl < = l ' bO; delay2 < = l'bO; out_valid < = l'bO; finalwrite < = l'bO; end else begin finalwrite < = in_finalwrite; if (validS &finalwrite) delayO < = l'bl; else if (count == DATA1 _SIZE4) delayO < = l'bO; delayl < = delayO; delay2 < = delayl; out_valid < = delay2; end? FOLDENDS * / / * FOLDBEGINS O 2"error search algorithm" * / if (delayOS.Sc! delayl) begin noerrors, < = (SO == 7'bO); searchlerror < = (GFULL (SO, SI) == S2); found2error < = l'bO; twoerror < = l'bO; count < = 7'bO; GsO < = 7'h50; Gsl < = 7'h20; Gs2 < = 7'h3d; end else if (delayl) begin oneerror < = ( (SO "GsO) == 7 'bO) SS-searchlerror; twoerror < = twoerror_; if (twoerror) begin searchlerror < = l'bl; found2error < = l'bl; end - GsO < = DIVI (GsO); Gsl < = D1V2 (Gsl); Gs2 < = D1V3 (Gs2); count < = count + l'bl; end out_data < = (twoerror // oneerror) S.S.! noerrors; / FOLDENDS * / end assign twoerror_ = (GFULL ((SO "GsO), (Sl" Gsl)) == (S2"Gs2)) &! F ound2error & &two; XFOLDBEGINS OO" functions "* /? FOLDBEGINS OO "GFULL function" * / function [6: 0] GFULL; input [6: 0] X; input [6: 0] Y; reg [6: 0] AO, Al, A2, A3, A4, A5, A6; integer i; begin A0 = X; A1 = {A0 [5], A0 [4], A0 [3], A0 [2] "A0 [6], A0 [1], AO [0] ], A0 [6]}; A2 =. { A1 [5], A1 [4], Al [3], A1 [2] "Al [6], Al [1], Al [0], Al [6].}; A3 =. { A2 [5], A2 [4], A2 [3], A2 [2] "A2 [6], A2 [1], A2 [0], A2 [6].}.

A4 =. { A3 [5], A3 [4], A3 [3], A3 [2] A3 [6], A3 [1], A3 [0], A3 [6]} • A5 =. { A4 [5], A4 [4], A4 [3], A4 [2] A4 [6], A4 [1], A4 [0], A4 [6]} A6 =. { A5 [5], A5 [4], A5 [3], A5 [2] A5 [6], A5 [1], A5 [0], A5 [6]} for (i = 0; i &7; i = i + l) begin A0 [i] = A0 [i] £. £. Y [0] Al [i] = Al [i] &-. Y [l] A2 [i] = A2 [i] & & Y [2] A3 [i] = A3 [i] S.S. And [3]; A4 [i] = A4 [i] S_¿- Y [4]; A5 [Í] = A5 [i] & & And [5]; A6 [i] = A6 [i] _. & And [6]; end GFULL = A0"A1" A2"A3" A4"A5" A6; end endfunction / * F0LDENDS * / / * FOLDBEGINS 0 0"MULTAl function" / function [6: 0] MULTAl; input [6: 0] X; begin MULTAl =. { X [5], X [4], X [3], X [2] "X [6], X [1], X [0], X [6].}.; End endfunction / * FOLDENDS * / / * FOLDBEGINS OO "MULTA2 function" * / function [6: 0] FINE2; input [6: 0] X; begin FINE2 = {X [4], X [3], X [2] "X [6 ], X [1] X [5], X [0], X [6], X [5]}; end endfunction? FOLDENDS * / / * FOLDBEGINS 0 0"MULTA3 function" * / function [6: 0] MULTA3; input [6: 0] X; begin MULTA3 =. { X [3], X [2] "X [6], X [1]" X [5], X [0] "X [4], X [6], X [5], X [4]};; end endfunction? FOLDENDS * /? FOLDBEGINS 0 0"DIVl function" * / function [6: 0] DIVl; input [6: 0] X; begin DIVl = {X [0], X [6] , X [5], X [4], X [3] "X [0], X [2], X [1]}; end endfunction? FOLDENDS * / '/ * FOLDBEGINS 0 0"DIV2 function" * / function [6: 0] DIV2; input [6: 0] X; begin DIV2 =. { X [l], X [0], X [6], X [5], X [4] "X [1], X [3] AX [0], X [2].}.; End endfu nction ? FOLDENDS * / / * FOLDBEGINS 0 0"DIV3 function" * / function [6: 0] DIV3; input [6: 0] X; begin DIV3 = {X [2], X [1], X [ 0], X [6], X [5] "X [2], X [4]" X [l], X [3] "X [0]}; end endfunction? FOLDENDS * / / FOLDENDS * /? FOLDBEGINS 0 0"" * / // always (posedge clk) // $ display (in_valid "in_data" in_f inalwrite,,,, out_valid,, out_data,,, S0, , S1,, S2,,); // always © (psedge clk) // $ display (resynch,, in_valid,, in_data,, out_valid,, SO,, SI,,,, count,,, delayO,, delayl,, delay2,,,, / / , ,, delay2,, noerrors,, oneerror,, twoerror,, out_data,, out_valid); // always © (posedge clk) / / $ display (in_valid,, in_data,,,, out_valid,, out_data,,, SO,, YES,, ^^, i i I // // always © (posedge clk) / '/ $ display (in_valid,, in_data,,,, out_valid,, out_data,,, SO,, YES,, S2,,,); ? FOLDENDS * / endmodule Listing 21 // Sccsld: @ (#) tps.v 1.29 / 15/97 /? FOLDBEGINS OO ,, copyright, * / // ************** ********************** Copyright (c) 1997 Pioneer Digital Design Center Limited // ÑAME: tps_rtl.v // PURPOSE: Demodulates TPS pilots using DPSK. Finds sync bits. // Corrects up to two errors using BCH. // (DPSK produces two errors for each transmission error) // HISTORY: 11519191 PK Added sean 10 ports, you, tdin, tdout // // ************************** **********? FOLDENDS * / define SYNCSEQO 16 'bOlllOllllOlOllOO define SYNCSEQl 16' blOOOlOOOOlOlOOll module tps (resync, clk, tps_valid, tps_pilot, tps_sync, tps_data, upsel, upaddr, uprstr, lupdata, te, tdin , tdout); ? FOLDBEGINS O O ,, i / os ,, * / input resync, clk, tps_valid, tps_pilot, upsel, uprstr, te, tdin; input [1: 0] upaddr; inout [7.-0] lupdata; output tps_sync, tdout; output [30: 0] tps_data; * FOLDENDS * / / * FOLDBEGINS0 0 ,, registers ,, * / reg resynch; reg [1: 0] foundsync; reg [66: 0] tpsreg; reg [15: 0] syncreg; reg [1: 0] tpsvalid; reg [1: 0] pilot; reg tps_sync, -reg [7: 0] bch_count; reg [2: 0] bch go; reg bch_finalwrite; wire bch_data; wire bch valid; wire bch_error; • integer i; wire upselOj wire upsell, wire upsel2, wire upsel3, / * FOLDENDS * / always © (posedge clk) begin? FOLDBEGINS O 2,, Synchronize to TPS '' * // resynch < = resync; if (tpsvalid [0] ScSc! (f oundsync [0] I I f oundsync [1] I I tps_sync)) begin tpsreg [66] < = pilot [1] "pilot [O]; for (i = 0; i <66; i = i + l) tpsreg [i] < = tpsreg [i + l], - end else if (bch_valid_-S_bch_error ) tpsreg [bch_count] < =! tpsreg [bch_count]; if (tpsvalid [O] Ss (f oundsync [O] // foundsync [l])) begin syncreg [15] < = pilot [1] "pilot [ 0]; for (i = 0; i < l 5; i = i + l) syncreg [i] < = syncreg [i + 1]; end pilot [0] < = tps_pilot; pilot [1] < = pilot [0]; if (resynch) begin tpsvalid < = 2'bO; tps_sync < = l'bO; bch_go < = 3 'bO; bch_f inalwrite < = l'bO; bch_count < = 8'bO; foundsync < = 2'bO; end else begin tpsvalid [O] < = tps_valid; tpsvalid [l] < = tpsvalid [O]; bch_go [l] < = bch_go [O]; bch_go [2] < = bch_go [1] bch_finalwrite < = (bch_count == 65) S.S.bch_go [2]; íf ((bch_count == 52) S.S_bch_valid) tps_sync < = l'bl; ? FOLDBEGINS O 2,, counter, * / if (bch_count == 66) bch_count < = 8'bO; else if (tpsvalid [1] & _.! (foundsync [0] // foundsync [1])) begin if (tpsreg [15: 0] == SYNCSEQl) bch_csunt < = 8'hfe; // - 2 if (tpsreg [15: 0] == SYNCSEQO) bch_count < - 8'hfe; // -2 end else if. { tpsvalid [1] &S. (bch_count = = 15) S.S. (foundsync [0] // foundsync [1])) bch_count < = 8'hfe; / / -2 else begin if (bch_valid bch_go [O] // ((foundsync [O] // foundsync [1]) __S.tpsva lid [0] bch_count < = bch_count + l'bl; end? FOLDENDS * / ? FOLDBEGINS O 2,, BCH + second SYNC reg control, * / if (bch_count == 66) begin bch_go < = 3'bO; end else if (tpsvalid [1]) begin if (foundsync [0] foundsync [ 1]) begin if (bch_count == 1 5) begin if (((syncreg [15: 0] ==. SYNCSEQO) & f oundsync [1]) // ((syncreg [15: 0] == 'SYNCSEQ 1) __ & f oundsync [O])) bch_go [0] < = l'bl; else foundsync < = 2'bO; end end else begin if (tpsreg [15: 0] == .SYNCSEQl) f oundsync [1] = l'bl; if (tpsreg [15: 0] == SYNCSEQO) foundsync [0] < = l'bl; end end / FOLDENDS * / end / * FOLDENDS * / end assign bch_data = tpsreg [bch_count]; ? FOLDBEGINS O O,,,, * / // always © (posedge clk) // begin / / $ write (tps_valid,, tps_sync,, tps_pilot,, tpsvalid [1],, pilot, // bch_finalwrite,,,,,, bch_go [2],, bch_data,, bch_valid,, bch_err,, bch_count,, tps sync ,,,,,); // $ displayb (tpsreg,, syncreg,, foundsync); // end / * FOLDENDS * /? FOLDBEGINS00,. micro access ,, * / assign upselO = upselS.S-uprstr_.S-! upaddr [1] £ _ £.! upaddr [0] assign upsell = upselS ._- uprstrS.S_! upaddr [1] S.S. upaddr [O] assign upsel2 = upsel ___- uprstr _-_- upaddr [1] __S.¡ upaddr [0] assign upsel3 = upsel _._- uprstr _.__ upaddr [1] ____ upaddr [O] assign lupdata = upselO? . { l 'bO, tps_data [30: 24]} : 8'bz, lupdata = upsell? tps_data [23: 16]: 8'bz, lupdata = upsel2? tps_data [15: 8]: 8'bz, lupdata = upsel3? tps_data [7: 0]: d'bz; / * FOLDENDS * / assign tps_data = tpsreg [52: 22]; bch_decode bchl (. clk (clk), .resync (resync), .in_valid (bch_go [2]), .in_finalwrite (bch_finalwrite), .in_data (bch_data), .out_valid (bch_valid),. out_data (bch_error)); endmodule Listing 22 // SccslD =% W%% G% // FOLDBEGINS 0 O,, Copyright (c) 1997 Pioneer Digital Design Center Limited ... "Copyright (c) 1997 Pioneer Digital Design Center Limited ÑAME: sydint_rtl. v PURPOSE: < a one line description > CREATED: Thu 14 Aug 1997 BY: Paul (Paul McCloy) MODIFICATION HISTORY: 9/15/97 PK Increased width to 13 to allow for bad_carrier flag // // FOLDENDS '// FOLDBEGINS 0 O, module symdint ... < - top level ,, // module symdint // FOLDBEGINS O O,, pins (out_data, valid, d_symbol, valid_in, demap_data,. odd_symbol, symbol, carrierO, constellation, - // FOLDBEGINS O 3"ram pins ..." ram_a, ram_d i, ram_do, ram_wreq, // FOLDENDS // FOLDBEGINS O 3,, sean pins ... "tdin, tdout, you, // FOLDENDS nrst, clk // FOLDENDS parameterWlDTH = 13; // Modified by PK 15/9/97; 12-> 13 parameter ADDR_WI DTH = 11; // FOLDBEGINS 0 2"outputs ..." output tdout; output valid; output [17: 0] out_data; output d_symbol; output [ADDR WIDTH- 1: 0] ram_a; output [WIDTH-1: 0] ram_di; output ram_wreq; // FOLDENDS // FOLDBEGINS 02"inputs ..." input valid_in; input [WIDTH-1: 0] demap_data; input odd_symbol; input symbol; carrierO input; input [WIDTH-1: 0] ram_do; input [1: 0] constellation; input tdin, te; input nrst, clk; // FOLDENDS // FOLDBEGINS 0 2,, regs / wires. , // FOLDBEGINS 0 0 ,, inputs regs ... "reg valid_in_reg; reg [WlDTH-1: 0] demap_data_reg; reg odd_symbol_reg; reg symbol_reg; reg] WlDTH-1.-0] ram_do_reg; reg [1: 0] constellation_reg; // FOLDENDS // FOLDBEGINS00,, output regs ... "reg valid; reg [17: 0] out_data; reg d_symboi; reg [ADDR_WIDTH-1: 0] ram_a; - reg WIDTH-1: 0] ram_di; reg ram_wreq; // FOLDENDS // FOLDBEGINS 0 0 ,, instate_reg ...,, parameter INSTATE_WAIT_SYMBOL = 2'dO; parameter INSTATE_WAIT_VALID = 2 'di; parameter INSTATE_WRITE = 2 'd2; parameter INSTATE_WRITE_RAM = 2 'd3; reg [1: 0] instate_reg; // FOLDENDS // FOLDBEGINS 0 0,, outstate_reg ... "parameter OUTSTATE_WAIT_WRITEFINISHED = 3'dO; parameter OUTSTATE_WAIT0 = 3 'd 1; parameter 0UTSTATE_WAIT1 = 3' d2; parameter OUTSTATE_READRAM = 3 'd3; parameter OUTSTATE_WAIT2 = 3' d4; parameter OUTSTATE_OUTPUTDATA = 3 'd5; parameter OUTSTATE_WAIT3 = 3' d6; reg [2: 0] outstate_reg, - // FOLDENDS reg [ADDR_WIDTH-1: 0] read_addr_reg; • reg [WlDTH-1: 0] data_reg; reg next_read_reg, next_write_reg; reg frist_data_reg; reg odd_read_reg, odd_write_reg; reg sym_rst_read_reg, sym_rst_write_reg; reg [17: 0] demapped; reg [3: 0] iminus; reg [3: 0] g inus; reg [8: 0] outi; reg [8: 0] outq; reg [5: 0] demap; // FOLDBEGINS 0 0 ,, ires ... "wire [ADDR_WIDTH-1: 0] address_read, address_write; wire finished_read, finished_write; wire valid_read, write_valid; wire [5: 0] ini, inq; // FOLDENDS // FOLDENDS ag # (ADDR_WIDTH) r // FOLDBEGINS 0 2 ,, pins ... ".address (address_read),. finished (finished_read), .next (next_read_reg),. random (odd_read_reg),. sym_rst (sym_rst_read_reg), .nrst (nrst), .clk (clk) // FOLDENDS ag # (ADDR_WIDTH) w // FOLDBEGINS 0 2 ,, pins ... "(. address (address_write),. finished (finished_write), . next (next_write_reg),. random (-odd_write_reg),. sym_rst (sym_rst write_reg), .nrst (nrst), .clk (clk)); // FOLDENDS // FOLDBEGINS 0 2,, latch inputs ... always © (posedge clk) begin valid_in_reg < = valid_in; demap_data_reg < = demap_da to; odd_symbol_reg < = odd_symbol; symbol_reg < = symbol; ram_do_reg < = ram_do, -constellation_reg < = constellation; end // FOLDENDS always © ( posedge clk) begin if (-nrst) // FOLDBEGINS 0 4 ,, reset ... "begln instate_reg < = INSTATE_WAIT_SYMBOL outstate_reg < = OUTSTATE_WAIT_WRITEFINISHED; next_read_reg < = 0; end // FOLDENDS else begin // FOLDBEGINS 0 4,, input state machine ... "// $ write (" DB% Od% m): instate_reg =% Od fw =% b \ n ", // $ time, instate_reg, finished_write); case (instate_reg) INSTATE_WAIT_SYMBOL: begin sym_rst_write_reg < = 1; next_write_reg < = 0; ram_wreq < = 0; if (symbol_reg) begin // $ write ("DB% Od% Om): GOT = % x (NEW SYMBOL) \ n ", $ time, demap_data_reg), - $ write (" DB (% Od% Om): START WRlTE \ n ", $ time); odd_write_reg < = odd_symbol_reg; data_reg < = demap_data_reg; instate_reg < = INSTATE_WRITE; end end INSTATE_WAIT_VALID: begin ram_wreq < = 0; next_write_reg < = 0? F (finished_write) begin $ write ("DB% Od% m): END (l) WRlTE \ n", $ time); mstate_reg < = INSTATE_WAIT_SYMBOL; end else begin íf (valid_in_reg) begin data_reg < = demap_data_reg; mstate_reg < = INSTATE_WRITE; end end end INSTATE_WRITE: begm sym_rst_write_reg < = 0; next_write_reg < = 1; ram_a < = address write; // $ write ("DB% Od% 0m): RWrite [% x] =% x \ n", $ time, address_write, data_reg); ram_di < = data_reg; ram_wreq < = 1 if (finished_write) begin $ write ("DB% Od% m): END (2) WRlTE \ n", $ time); instate_reg < = INSTATE_WAIT_SYMBOL; ram_wreq < = 0; end else instate_reg < = INSTATE_WAIT_VALID; end endcase // FOLDENDS // FOLDBEGINS 0 4,, output state machine .. ,, // $ write ("DB% 0d% m): outstate_reg =% Od nr:% br:% b \ n", // $ time, outstate_reg, next_read_reg, odd_symbol_reg); case (outstate_reg) OUTSTATE_WAIT_WRITEFINISHED: begin sym_rst_read_reg < = 1; frist_data_reg < = 1; valid < = 0; if (finished_write) begin odd_read_reg < = odd_write_reg; outstate_reg < = OUTSTATE WAITO; $ write ("DB% Od% m): START READ \ n", $ time); // $ write ("DB% Od% m): Read (NEW SYMBOL) \ n", $ time, address_read); end end OUTSTATE_WAIT0: begin sym_rst_read_reg < = 0; outstate_reg = OUTSTATE_WAITl; end OUTSTATE_WAITl: begin outstate_reg < = OUTSTATE_READRAM; end OUTSTATE_READRAM: begin // $ write ("DB% Od% m): Read [% x] \ n", $ time, address_read); ram_a < = address_read; ram_wreq < = 0; next_read_reg < = 1; outstate_reg < = OUTSTATE_WAIT2; end OUTSTATE_WAIT2: begin next_read_reg < = 0; outstate_reg < = OUTSTATE_OUTPUTDATA; end OUTSTATE_OUTPUTDATA: begin out_data =. { outi [8: 6], outq [8: 6], outi [5: 3], outq [5: 3], outi [2: 0],? Utq [2:]}; valid < = 1; d_symbol < = frist_data_reg; frist_data_reg < = 0; outstate_reg < = OUTSTATE_WAIT3; end OUTSTATE_WAIT3: begin valid < = 0; if (finished_read) begin outstate_reg < = OUTSTATE_WAIT_WRITEFINISHED; $ write ("DB% 0d% m): END READ \ n", $ time); end else outstate_reg < = OUTSTATE_WAIT0; end endcase // FOLDENDS end end always © (constellation_reg or ini or inq) // FOLDBEGINS 0 2 ,, demapper ... "begin // FOLDBEGINS 0 2,, coarse demapping,, iminus = { ini [5: 3 ], l'b ?.}. -2 'd3; qminus = { inq [5: 3], 1' b.}. -2 '3; if (constellation_reg == 2' bOl) begin demap = {2 'bO, iminus [2], qminus [2],! (Iminus [2] "iminus [1]),! (qminus [2] "qminus [1]) // $ writeb (demap,,); // $ display (iminus,, ini [5: 3]); end else if (constellation_reg == 2 'blO) begin iminus = { ini [5: 3], l'b ?.}. -3 'd7; qminus = { inq [5: 3], 1' b ?.}. -3'd7; demap = { iminus [3], qminus [3],! (iminus [3] "iminus [2]),! (qminus [3] "qminus [2]), (iminus [2]" iminus [1]), (qminus [2] "qminus [1]).};; end else demap =. 6 'bO; // FOLDENDS if (constellation_reg == 2 'bOl) begin // FOLDBEGINS OR 4,, 16QAM,, if (1 iminus [1] SS-iminus [O]) begin outi [8: 6] = 3' bO; outi [5 : 3] = demap [3]? 3'blll: 3'bO; outi [2: 0] = iminus [2]? Ini [2: 0]: ~ ini [2: 0]; end else begin outi [8 : 6] = 3 'bO; outi [5: 3] = ~ ini [2: 0]; outi [2: 0] = 3' blll; end if ('¡qminus [1] S._qminus [O]) begin outq [8: 6] = 3 'bO; outq [5: 3] = demap [2]? 3'blll: 3'bO; outq [2: 0] = qminus [2]? inq [2: 0] : ~ inq [2: 0]; end else begin outq [8: 6] = 3'bO; outq [5: 3] = ~ inq [2: 0]; outq [2: 0] = 3 'blll; end // FOLDENDS end else if (constellation_reg == 2 'blO) begin // FOLDBEGINS 0 4 ,, 64QAM,, if (! iminus [1]) begin outi [8: 6] = demap [5]? 3'blll: 3'bO; outi [5: 3] = demap [3]? 3 'blll: 3'bO; outi [2: 0] = iminus [2]? ~ ini [2: 0]: ini [2.-0]; end else if (! iminus [2]) begin outi [8: 6] = demap [5]? 3'blll: 3'bO; outi [5: 3] = iminus [3]? ini [2: 0]: -ini [2: 0]; outi [2: 0] = demap [1]? 3'blll: 3'bO; end else begin outi [8: 6] = ~ ini [2: 0]; outi [5: 3] = demap [3]? 3'blll: 3'bO; outi [2: 0] = demap [1]? 3'blll: 3'bO; end if (! minus [1]) begin outq [8: 6] = demap [4]? 3'blll: 3'bO; outq [5: 3] = demap [2]? 3'blll: 3"b0; outq [2: 0] = qminus [2]? -inq [2: 0]: inq [2: 0]; end else if (qminus [2]) begin outq [8. -6] = demap [4]? 3'blll: 3'bO outq [5: 3] = qminus [3]? Inq [2: 0]: ~ inq [2: 0]; outq [2: 0] = demap [O]? 3'blll: 3'bO; end else begin outq [8: 6] = -inq [2: 0], -outq [5: 3] = demap [2]? 3'blll: 3 ' bO; outq [2: 0] = dema [O]? 3'blll: 3'bO; end // FOLDENDS end else begin // FOLDBEGINS 0 4 ,, QPSK,, outi = { 6'bO, -ini [2: 0].}.; • outq = {6 * bO, ~ inq [2: 0].};; // FOLDENDS end end // FOLDENDS assign ini = ram_do_reg [11: 6], - assign inq = ram_do_reg [5: 0]; endmodule // FOLDENDS // FOLDBEGINS 0 0,, module ag (address gereration). module ag // FOLDBEGINS 0 0,, pins ... "(address, finished, next, random, sym_rst, nrst, clk); // FOLDENDS - parameterADDR_WlDTH = 12; // FOLDBEGINS 0 2" outputs ... " . output [ADDR_WIDTH-1: 0] address; output finished; // FOLDENDS // FOLDBEGINS 0 2 ,, inputs ... "input next; random input; input sym_rst; input nrst, clk; // FOLDENDS // FOLDBEGINS 0 2,, regs .. ,, integer i; reg finished; reg [9: 0] prsr_reg; reg [11: 0] count_reg; wire address_valid; // FOLDENDS always © (posedge clk) begin if (~ nrst) begin count_reg < = 0; prsr_reg < = 10 'dO; end else begin if (sym_rst) begin finished < = 0; count_reg < = O; end else if (next (! address_valid &random)) begin // $ write ("DB% Od% m): Next (r:% d) \ n", $ time, random); ? f (random) // FOLDBEGINS 0 8,, do the random stuff .. ,, begin if (! address_valid) begin // FOLDBEGINS O 4 ,, drive the prsr ... "if (count_reg == 11 'dO) prsr_reg < = 10 'dO; else if (count_reg == 1 1' di prsr_reg < = 10'dl; else begin for (i = 0, i < 9, i = i + l) prsr_reg [i] < = prsr_reg [i + 1]; prsr_reg [9] < = prsr_reg [O] prsr_reg [3]; end // FOLDENDS count_reg < = count_reg + 1; // $ write ("DB% Od% m): count =% Od Rand (Retry) \ n ", $ time, count_reg); end else begin if (count_reg == ll'd2047) begin // $ write (" D'B% Od% m): *** FINISHED Rand \ n ", $ time); finished <= 1; count_reg < = OR; prsr_reg < = 10 'dO; end else begi'n // FOLDBEGINS O 6,, drive the prsr if (count_reg == 11 'dO) prsr_reg < = 10' dO; else if (count_reg == 11 'd 1) prsr_reg < = 10' d 1; else begin for (i = 0; ic9; i = i + l) prsr_reg [i ] < = prsr_reg [i + 1]; prsr_reg [9] < = prsr_reg [O] "prsr_reg [3]; end // FOLDENDS count_reg < = count_reg + 1; // $ write ("DB%? d% m): count =% Od Rand \ n", $ time, count_reg); finished < = 0; end end end // FOLDENDS else // FOLDBEGINS08,, do the sequential stuff ... "begin if (count_reg! = ll'dlSll) begin // $ write (" DB% Od% m): count = 0d Sequ \ n ", $ time, count_reg); count_reg < = count_reg +1; finished < = 0; end else begin // $ write (" DB% Od% m): * FINISHED Sequ \ n ", $ time); finished < = 1; count_reg < = 0; end end // FOLDENDS end end end // FOLDBEGINS 0 2 ,, assign address .. ,, assign address = (random)? ( { count_reg [0], // lO prsr_reg [2, // 9 prsr_reg [5, II 8 prsr_reg [8, // 7 prsr_reg [3, // 6 prsr_reg [7, // 5 prsr_reg [0 / // 4 prsr_reg [1, // 3 prsr_reg [4, // 2 prsr_reg [6, // 1 prsr_reg [9.}.): // 0 count_reg; // FOLDENDS assign address_valid = (address <ll'dl512); endmodule // FOLDENDS Listing 23 - // SccslD:,, @ (#) bitdeint .v 1.49 / 14/97 ,, // FOLDBEGINS 0 0 ,, Copyright (c) 1997 Pioneer Digital Design Center Limited,, *********************** Copyright (c) 1997 Pioneer Digital Design Center Limited AME: bitdeint_rtl. v PURPOSE: bit deinterleaver CREATED: Wed 23 Jul 1997 BY: Paul (Paul McCloy) MODIFICATION HISTORY: ***************************** ** // FOLDENDS module bitdeint // FOLDBEGINS O 2,, pins ... "i_data, q_data discard i, discard_q, valid, // output // FOLDBEGINS O 2" ramO pins ... "ramO_a, ramO di, ramO_do , ramO_wreq, • ramO_ce, // FOLDENDS // FOLDBEGINS OR 2"raml pins ..." ram 1 _a, raml _ di, ram 1 _do, ram 1 _wreq, raml ce, // FOLbENDS // FOLDBEGINS O 2"ram2 pins,, ram2_a, ram2_di, ram2_do, ram2_wreq, ram2_ce, // FOLDENDS bad_carrier, valid in, data_in, symbol, constellation, // constellation alpha, // does not do anything yet // FOLDBEGINS O 2,, sean pins .. . "tdin, tdout, you, // FOLDENDS nrst, clk); // FOLDENDS parameter SBW = 3; // soft bit width // FOLDBEGINS 0 2" outputs ... " // FOLDBEGINS 0 0"ramO outputs ..." output [6: 0] ramO_a; output [((SBW + 1) < 1) -1: 0] ramO_di; output ramO_ce; output ramO_wreq; // FOLDENDS // FOLDBEGINS 0 0"raml outputs ..." output [6: 0] raml_a; output [((SBW + 1) < 1) -1: 0] raml_di; output raml_ce; output raml_wreq; // FOLDENDS // FOLDBEGINS 0 0"ram2 outputs ..." output [6: 0] ram2_a; output [((SBW + 1) < < < 1) -l: 0] ram2 di; output ram2_ce; output ram2_wreq; // FOLDENDS output tdout; output [SBW-1: 0] i_data; output [SBW-1: 0] q_data; output discard_i; output discard_q; output valid; // FOLDENDS // FOLDBEGINS 0 2 ,, inputs ... "input [((SBW + 1) <1) -1: 0] ramO_do; input [((SBW + 1) < < 1) -1: 0] raml_do; input [((SBW + 1) < < -ll: 0] ram2_do; input bad_c'arrier; input valid_in; input [((SBW <2) + (SBW < < 1) -1: 0] data_in; // 6 * SBW input bits sy bol; input [1: 0] constellation; input [2: 0] alpha; inpu't tdin, te; input nrst, clk; / / FOLDENDS // FOLDBEGINS 0 2,, reg / wire .. ,, // FOLDBEGINS 0 0"outputs ..,, // FOLDBEGINS OO" ramO regs ... "reg [6: 0] ramO_a; reg [(( SBW + 1) <1) -1: 0] ramO_di; reg ramOce; reg ramO_wreq; // FOLDENDS // FOLDBEGINS OO "raml regs ..." reg [6: 0] raml_a; reg [((SBW +1) <1) -1: 0] raml_di; reg raml_ce; reg raml _wreq; // FOLDENDS // FOLDBEGINS OO "ram2 regs ..." reg [6: 0] ram2_a; reg [((SBW +1) < < 1) -1: 0] ram2_di; reg ram2_ce; reg ram2_wreq; // FOLDENDS reg [SBW- 1: 0] i_data; reg [SBW- 1: 0] q_data; reg discard_i; reg discard_q; reg va fight; // FOLDENDS // FOLDBEGINS OO ,, inputs ... "reg valid_in_reg; reg [((SBW <2) + (SBW <1)) -1: 0] data_in_reg; // 6 * SBW bits reg symbol_reg,, bad_carrier_reg; reg [1: 0] constellation_reg; reg [2: 0] alpha_reg; reg [((SBW + 1) <1: -1] ramO_do_reg; reg [((SBW + 1) <1) -1: 0] raml_do_reg; reg [((SBW + 1) <1: -1] -1: 0] ram2_do_reg; // FOLDENDS reg [6: 0] iO_adr_reg; reg [6 : 0] il_adr_reg; reg [6: 0] i2_adr_reg; reg [6: 0] Í3_adr_reg; reg [6: 0] i4_adr_reg; reg [6: 0] i5_adr_reg; reg [2: 0] mode_reg; reg [(SBW < < 2) + (SBW <1) -1: 0] data_reg; 1/6 * (SBW) bits reg [((SBW + 1) <1) + SBW: 0] i_out_buf_reg, q_out_buf_reg, - // 3 * (SBW + 1) bits reg ram_filled_reg, out_buf_full_reg, bad_car_reg; wire [SBW: O] iO_in, qO_in, il_in, ql_in, i2_in, q2_in; wire [SBW.-O] iO_ram, qO_ram, il_ram , ql_ram, i2_ram, q2_ram; // FOLDENDS // FOLDBEGINS O 2,, latch inputs ... "always © (posedge clk) begin bad_carrier_reg < = bad_carrier; valid_in_reg < = valid_in data_in_reg < = data_in; symbol_reg < = symbol; constellation_reg < = constellation; alpha_reg < = alpha; ramO_do_reg < = ramO_do raml_do_reg < = raml_do, ram2_do_reg < = ram2_d ?; end // FOLDENDS always © (posedge clk) begin if ("nrst) // FOLDBEGINS O 4,, reset ... "begin mode_reg < = 2'bOO; valid < = O; iO_adr_reg < = O il_adr_reg < = 63;? 2_adr_reg < = 105; i3_adr_reg < = 42? 4_adr_reg < = 21, i5_adr_reg < = 84; i_out_buf_reg < = O; q_out_buf_reg < = O; - ram_filled_reg < = O; out_buf_full_reg < = O; end // FOLDENDS else begin if (valid_in_reg) // FOLDBEGINS O 6 ,, start cycle ... ,, begin data_reg < = data_in_reg; bad_car_reg < = bad_carrier_reg; // $ write ("DB% Od% m): data_reg =% X (% b.% b.% b) \ n", $ time, data_in_reg, // bad_carrier, bad_carrier_reg, bad_car_reg); // FOLDBEGINS O 2 ,, logic to read i0, l, 2 ... "ramO_a < = ¡0_adr_reg; ramO_wreq < = O; raml_a < = il_adr_reg; raml_wreq < = 0; ram2_a < = i2_adr_reg; ram2_wreq < = 0; // FOLDENDS ramO ce < = 1; raml_ce < = (constellation_reg == 2'bl0) (constellation_reg == 2'b? l); ram2_ce < = (constellation_reg == 2'blO); // FOLDBEGINS O 2 ,, output il and ql ... "if (out_buf_full_reg S (constellation_reg! = 2'bOO)) begin valid < = 1; i_data < = i_out_buf_reg [((SBW + l) < <; 1) -2: (SBW + l)]; discard_i < - i_out_buf_reg [((SBW + l) < < < 1) -1]; q_data < = q_out_buf_reg [((SBW + l); 1) -2: (SBW + l)]; discard_q < - q_out buf_reg [((SBW + l) < <1) -1]; // $ write ("DB% Od% m): OUT (l):% x% x \ n ", $ time, // i_out_buf_reg [((SBW + l) < < 1) -2: (SBW + l)], // q_out_buf_reg [((SBW + l ) <1) -2: (SBW + l)]); end // FOLDENDS mode_reg < = 3'bO01; end // FOLDENDS else begin // $ write ("DB% Od% m): m =% b \ n ", $ time, mode_reg); case (mode_reg) // FOLDBEGINS O 8,, 3'bOOl: .. ,, 3'bO01: begin // FOLDBEGINS O 4,, logic to read q ?. 1,2 .. ,, ramO_a <; = i3_adr_reg; ramO_wreq < = O; raml_a < = Í4_adr_reg; raml_wreq < = 0; ram2_a < = i5_adr_reg; ram2_wreq < = 0; // FOLDENDS valid < = O; mode_reg < = 3'bO10; end // FOLDENDS // FOLDBEGINS O 8 ,, 3'bO10: .. ,, 3'bO10: begin mode_reg < = 3'b? Ll; // FOLDBEGINS O 4,, output i2 and q2 ... "if (out_buf_full_reg _ (constellation_reg == 2'blO)) begin valid < = 1; i_data < = i_out_buf_reg [SBW-1: 0]; discard_i < - i_out_buf_reg [SBW]; q_data < = q_out_buf_reg [SBW-1: 0]; discard_q < = q_out_buf_reg [SBW1; // $ write ("DB% Od% m): OUT (2):% x% x \ n ", $ time, // i_out_buf reg [SBW-l: 0], // q_out_buf_reg [SBW-1: 0]); end // FOLDENDS end // FOLDENDS // FOLDBEGINS 0 8, 3 'bOll: 3'b? Ll: begin valid < = O; // $ write ("DB% Od% m): ram read i0:% x il:% x i2:% x \ n", // $ time, / / ramO_do_reg [((SBW + l) <1) -1: SBW + l], // raml_do_reg [((SBW + l) < < 1) -1: SBW + l], // ram2_do_reg [((SBW + l) < < < 1) -1: SBW + 1]); i_out_buf_reg < = { RamO_do_reg [((SBW + l) < < < < 1) -1: SBW + 1] , raml _do_reg [((SBW + l) < < < < 1) -1: SBW + 1], ram2_do_reg [((SBW + l) < < 1) -1: SBW + l].};; / / FOLDBEGINS O 4 ,, logic to write new i0, l, 2 ... "ramO_a < = iO_adr_reg; ramO_wreq < = 1; ramO_di < =. { iO_in, qO_ram}; raml_a < = il_adr_reg; raml_wreq < - 1 raml_di < =. { il_in, ql_ram}; ram2_a < = i2_adr_reg; ram2_wreq < = 1; ram2_di < =. { i2_in, q2_ram}; // FOLDENDS mode_reg < = 3'bl00; end // FOLDENDS // FOLDBEGINS O 8 ,, 3'blOO: ... "3'blOO: begin // $ write (" DB% Od% m): ram read qO:% x ql:% x q2:% x \ n ", // $ time, // ramO_do_reg [SBW: 0], // raml_do_reg [SBW: 0], // ram2_do_reg [SBW: 0]); q_out_buf_reg < =. { ramO_do_reg [SBW: O], ram 1 _do_reg [SBW: O], ram2_do_reg [SB: O]}; out_buf_full_reg < = ram_filled_reg; // FOLDBEGINS O 4 ,, logic to write new qO, l, 2 .. ,, ramO_a < = i3_adr_reg; ramO_wreq < = 1; ramO_di < =. {; 0_ram, qO_in); raml_a < = i4_adr_reg; raml_wreq < = 1; raml_di < =. { il_ram, ql_in }; ram2_a < = i5_adr_reg; ram2_wreq < = 1; ram2_di < =. { i2_ram, q2_in }; // FOLDENDS // FOLDBEGINS O 4 ,, output iO and qO ... "if (out_buf_full_reg) • begin valid < = 1; i_data < = i_out_buf _reg [((SBW + l) < < 1) + SBW-1: ((SBW + l) Al)]; discard_i < = i_out_buf_reg [((SBW + l) < < 1) + SBW1; q_data < = q_out_buf_reg [((SBW + l) < <; 1) + SBW-1: ((SBW + l) '< 1)]; discard_q < = q_out_buf_reg [((SBW + l) < < 1) + SBW]; // $ write ("DB % Od% m): OUT (0):% x% x \ n ", $ time, // i_out_buf_reg [((SBW + l) c < 1) + SBW-1: ((SBW + l) '• 1)], // q_out_buf_reg [((SBW + l) <1) + SBW-1: ((SBW + l) <1)]); end // FOLDENDS mode_reg < = 3 ' bl? l; end // FOLDENDS // FOLDBEGINS O 8 ,, 3'bl? l: .. ,, 3'bl? l: begin valid < = O; I / FOLDBEGINS O 4,, increment ram address .. . "if (0_adr_reg == 7'dl25) begin; 0_adr_reg < = O; // FOLDBEGINS O 2,, do il_adr_reg (63 offset). il_adr_reg < = (il_adr_reg == 7'd20)? 7'd84: (il_adr_reg == 7'd41)? 7'dl05: (il_adr_reg == 7'd62)? 7'dO: (il_adr_reg == 7'd83)? 7'd21: (il_adr_reg == 7'dl04)? 7'd42: 7 'd63; // FOLDENDS // FOLDBEGINS O 2,, do i2_adr_reg (105 offset). i2_adr_reg < = (i2_adr_reg == 7'd20)? 7'd42: (i2_adr_reg == 7 * d41)? 7'd63: (i2_adr_reg == 7'd62)? 7'd84: (i2_adr_reg == 7'd83)? 7'dl05: (i2_adr_reg == 7'dl04)? 7'dO: 7'd21; // FOLDENDS // FOLDBEGINS 0 2,, do i3_adr_reg (42 offset) .. i3_adr_reg < = (i3_adr_reg == 7'd20)? 7'dl05: (i3_adr_reg == 7'd41)? 7 'dO: (i3_adr_reg == 7'd62)? 7'd21: (i3_adr_reg == 7'dd3)? 7'd42: (i3_adr_reg == 7'dl04)? 7'd63: 7 'd84; // FOLDENDS // FOLDBEGINS O 2,, do i4_adr_reg (21 offset) .. Í4_adr_reg < = (i4_adr_reg == 7'd20)? 7'dO: (i4_adr_reg == 7'd4l)? 7'd21: (i4_adr_reg == 7'd62)? 7'd42: (i4_adr_reg == 7'd83)? 7'd63: (i4_adr_reg == 7 'di04)? 7 * d84: 7'd 105; // FOLDENDS // FOLDBEGINS 0 2,, do i5_adr_reg (84 offset) ... "i5_adr_reg = (i5_adr_reg == 7'd20)? 7'd63: (i5_adr_reg == 7'd41)? 7'd84: (i5_adr_reg == 7'd62)? 7'dl05: (i5_adr_reg == 7'd83)? 7'dO: (i5_adr_reg == 7'dl04)? 7'd21: 7'd42; // FOLDENDS ram_filled_reg < = 1; end else begin; 0_adr_reg < = jO_adr_reg + 1; il_adr_reg < = (il_adr_reg == 7'dl25)? 0: il_adr_reg +1; i2_adr_reg < = (i2_adr_reg == 7'dl25)? 0: i2_adr_reg +1; i3_adr_reg < = (i3_adr_reg == 7 'di25)? 0: i3_adr_reg +1; i4_adr_reg < = (i4_adr_reg == 7'dl25)? 0: i4_adr_reg +1; i5_adr_reg < = (Í5_adr reg == 7'dl25 )? 0: i5_adr_reg +1; end // FOLDENDS end // FOLDENDS endcase end end end assign iO_in =. { bad_car_reg, data_reg [(SBW < < 2) + (SBW < < 1) -1: (SBW < 2) + SBW 'j}; assign qO_in =. { bad_car_reg, data_reg [(SBWc < 2) + SBW-1: SBW2]}; assign il_in =. { bad_car_reg, data_reg [(SBW < < 2) -1: (SBW1) + SBW}; assign ql_in =. { bad_car_reg, data_reg [(SBW < < 1) + SBW-1: SBW1]}; assign i2_in =. { bad_car_reg, data_reg [(SBW < < 1) -1: SB}; assign q2_in =. { bad_car_reg, data_reg [SBW-l: 0]} , -assign iO_ram = i_out_buf_reg [((SBW + l) <1) + SBW: ((SBW + l) < < < < < 1)]; assign qO_ram = q_out_buf_reg [((SBW + l) < < < < 1) + SBW: ((SBW + l) <1)]; assign il_ram = i_out_buf_reg [((SBW + l) < < < < < 1) -1: SBW + l], -assign ql_ram = q out_buf_reg ((SBW + l) 1) -1.-SBW + 1]; assign i2_ram = i_out_buf_reg [SBW: 0]; 'assign q2_ram = q_out_buf_reg [SBW: 0]; endmodule Listing 24 // Sccsld: ********************************* Copyright (c) 1997 Pioneer Digital Design Center Limited ***************************************** module acc_prod (clk, resync, load, symbol, newhase, old_phase, xcount, acc_out); input clk, resync, load, symbol; input [10: 0] xcount; input [13: 0] new_phase, oldhase; output [29: 0] acc_? ut; reg [29: 0] acc_out; reg [29: 0] acc_int; reg [14: 0] díff; reg [25: 0] xdiff; reg sign; reg [14: 0] mod_diff; reg [25: 0] mod_xdiff; always © (posedge clk) begin if (resync) begin acc_? Ut < = 0; acc_int < = 0; end else begin if (load) acc_int < = acc_int +. { xdiff [25], xdiff [25], // sign extend xdiff [25], xdiff [25], xdiff}; if (symbol) begin acc_out < = acc_int; acc_int < = 0; end end always © (new_phase or old_phase or xcount) begin diff =. { new_phase [13], new_phase} // sign extend up to allow -. { old_phase [13], old_phase}; // differences up to 360 sign = diff [14]; mod_diff = sign? ("diff + 1): diff; mod_xdiff = mod_diff * {4'bO, xcount.}.; xdiff = sign? (~ mod_xdiff + 1): mod_xdiff; end endmodule Listing 25 // Sccsld: W%% G% ******************************** Copyright (c) 1997 Pioneer Digital Design Center Limited * **************************** module acc_simple (clk, resync, load, symbol, new_phase, old_phase, acc_out ); input clk, resync, load, symbol; input [13: 0] new_phase, old_phase; output [20: 0] acc_out; reg [20: 0] acc_out; reg [20: 0] acc_in; reg [14: 0 ] diff; always © (posedge clk) begin if (resync) begin acc_out < = O; acc_int < = O; end else 'begin if (load) acc int < = acc_int + { diff [14], difft4], // sign extend diff [14], diff [14], diff [14], diff [14], diff, if (symbol) • begin acc_out < = acc_int; acc_int < = O; end end end always © (new_phase or old_phase) diff = { new_phase [13], new_phase.}. // sign extend up to allow - { old_phase [13], old_phase.}.; // difference s up to 360 always © (diff or load) begin: display reg [14: 0] real_diff; if (load) begin if (diff [14]) beg in real_diff = (-diff + 1); $ display (,, diff = -% Od,,, real diff); end else $ display (,, diff =% Od,,, diff); end end // display endmodule Listing 26 // Sccsld:% W%% G% *************************** **** Copyright (c) 1997 Pioneer Digital Design Center Limited ******************************* ** module addr_gen (clk, resync, u_symbol, uc_pilot, got_phase, en, load, guard, addr, xcount, guard_reg, symbol); input clk, resync, u_symbol, uc_pilot, got_phase; input [1: 0] guard; output in, load, symbol; output [1: 0] guard_reg; output [9: 0] addr; output [10: 0] xcount; reg on ,, load, load_p, inc_count2, symbol; reg [1: 0] guard_reg; reg [5: 0] count45; reg [10: 0] xcount; reg [9: 0] addr; always © (posedge clk) beg in if (resync) begin count45 < = 0; load_p < = 0; load < = 0; inc_count2 < = 0; symbol < = 0; guard_reg < = 0; end else begin if (u_symbol) begin inc_count2 < = 1; guard_reg < = guard; end if (inc_count2 & uc_pilot) begin inc_count2 < = 0; count45 < = 0; end if (got_phase) count45 < = count45 + 1; load_p < = in; load = load_p; symbol < = (inc_count2 S.S. ucilot); addr < = count45 in < = got_phase - & Resync S.S. (count45 < 45); // !! Four. Five ? end end always @ (count45 case (count45) 1: xcount = 1; 2: xcount = 49, 3: xcount = 55, 4: xcount = 8í 5: xcount = 142; 6: xcount = 157; 7: xcount = 193; 8: xcount = 202; 9: xcount = 256; 10: xcount = 280 11: xcount = 283 12: xcount = 334 13: xcount = 433 14: xcount = 451 15: xcount = 484 16: xcount = 526 17: xcount = 532 18: xcount = 619 19: xcount = 637 20: xcount = 715 21: xcount = 760 22: xcount = 766 23: xcount = 781 24: xcount = 805 25: xcount = 874; 26: xcount = 8d9; 27: xcount = 919; 28: xcount = 940; 29: xcount = 943; 30: xcount = 970; 31: xcount = 985; 32: xcount = 1051 33: xcount = 1102, 34: xcount = 1108 35: xcoun = 1111; 36: xcount = 1138 37: xcount = 1141 38: xcount = 1147 39: xcount = 1207 40: xcount = 1270, 41: xcount = 1324 42: xcount = 1378 43: xcount = 1492 44: xcount = 1684 45: xcount = 1705 default: xcount = O; endcase Endmodule Listing 27 // Sccsld:% W%% G% ****************************** Copyright (c) 1997 Pioneer Digital Design Center Limited ************************** module avg_8 (clk,, resync, symbol, in_data, avg_out); parameter phase_width = 12; input clk, resync, symbol; input [phase_width-2: 0] in_data; output [phase_width-2: 0] avg_out; reg [phase_width-2: 0] avg_out; reg [phase_width-2: 0] store [7: 0]; wire [phase_width-2: 0 store7 = store [7]; wire [phase_width-2: 0 storeß = store [6]; wire [phase_width-2: 0 store5 = store [5]; wire [phase_width- 2: 0 store4 = store [4]; wire [phase_width-2: 0 store3 = store [3]; wire [phase_width-2: 0 store2 = store [2]; wire [phase_width-2: 0 storel = store [1]; wire [phase_width-2: 0 storeO = store [O]; wire [phase_width-1] sum = ( { store7 [phase_width-2], store7 [phase_width-2] store7 [phase_width-2] store7.}. + { stored [phase_width- 2], store6 [phase_width - 2], store6 [phase_width-2], store ..}. + { Store5 [phase_wid h-2], store5 [phase_width- 2], store5 [phase_width-2], store5.}. + { store4 [phase_width- 2], store4 [phase_width- 2], store4 [phase_width-2], store4.}. + { store3 [phase_width- 2], store3 [phase_widt h- 2], store3 [phase_width-2] , store3.}. + { store2 [phase_width- 2], store2 [phase_width- 2], store2 [phase_width-2], store2.}. + { storel [phase_width-2], storel [phase_width-2 ], storel [phase_width-2], storel.}. + { storeO [phase_width- 2], st oreO [phase_width- 2], storeO [phase_width-2], storeO.}.); always © (posedge clk) begin if (resync) begin store [7] < = D; store [6] = O; store [5] < = O; store [4] < = O; store [3] < = O; store [2] < = O; store [1] < = 0; store [O] < = O; avg_out < = 0; end else if (symbol) begin store [7] < = store [6 store [6] < = store [] store [5] < = store [4 store [4] < = store [3 store [3] < = store [2 store [2] < = store [1 store [1] < = store [O store [O] < = in_data avg_out < = sum > > 3; end end end mod u Listing 28 // Sccsld:% W%% G% *********************** Copyright (c) 1997 Pioneer Digital Design Center Limited ***************************** module twowire26 (clk, rst, in_valid, din, out_accept, out_valid, in_accept, dout, set); input clk, rst, set, in_valid, out_accept; input [25: 0] din; output in_accept, out _valid; output [25: 0] dout; reg_in_accept, out_valid, acc_int, acc_int_reg, in_valid_reg, val_int; reg [25: 0] dout, din_reg; always © (posedge clk) beg in if (rst) out_valid < = o; else if (acc_int 1 1 set) out_valid < = val_int; if (in_accept) begin in_valid_reg < = in_valid; din_reg < = din; end 'if (acc_int) dout < = in_accept? din: din_reg; • if (set) acc_int_reg < = 1; else acc_int_reg < = acc_int; end always @ (out_accept or out_valid or acc_int_reg or in_valid or in_valid_reg) beg in acc int = out_accept 1 1! out_valid in_accept = acc_int_reg! In_valid_reg; val_int = in_accept? in_valid: in_valid_reg; end endmodule module buffer (clk, nrst, resync, u_symbol_in, uc_pilot_in, ui_data_in, uq_data_in, u_symbol_out, uc_pilot_out, ui_data_out, uq_data_out, got_phase); input clk, nrst, resync, u_symbol_in, uc_pilot_in, got_phase; input [11: 0] ui_data_in, uq_data_in; output u_symbol_out, uc_pilot_out; output [11: 0] ui_data_out, uq_data_out; reg u_symbol_out, uc_pilot_out, accept; wire u_symbol or, ucilot o; reg [11: 0] ui_data_out, uq_data_out; wire [11: 0] ui_data_o, uq_data_o; wire a, v; wire [25: 0] d; wire in_valid = u_symbol_in 1 1 uc_pilot_in; wire rst =! nrst 1 1 resync; twowire26 twl (.clk (clk), .rst (rst), .in_valid (in_valid),. din ( { u_symbol_in, uc_pilot_in, ui_data_in, uq_data_in.}.), .out_accept (a),. out_valid (v) ,. in_accept (),. dout (d),. set (l * b0)); twowire26 tw2 (.clk (clk), .rst (rst), .in_valid (v),. din (d), .out_accept (accept),. out_valid (out_valid),. in_accept (a),. dout (. { . u_symbol_o, uc_pilot_o, ui_data_o, uq data_o.}.), .set (1 'bO)); always @ (u_symbol_o or uc_pilot_o or ui_data_o or uq_data_o or out_valid or accept) beg in if (out_valid _. £ - accept) begin u_symbol out = u_sytnbol_o uc_pilot_out = uc_pilot_o; ui_data_out = ui_data_o; uq_data_out = uq_data_o, -end else begin u_symbol_out = O; uc_pilot_out = O; ui_data_out = O; uq_data_out = O; end end always (posedge clk) begin if (rst I! got_phase) accept < = 1; else if (uc_pilot_out) accept < = O; end endmodule Listing 29 // Sccsld:% W%% G% ******************************* * Copyright (c) 1997 Pioneer Digital Design Center Limited ****************************************** divide (clk, go, numer, denom, answ, got); ********************************************** * this divider is optimized on the main that the answer will always be less than 1 - ie denom > numer *********************************************** **** input clk, go; input [10: 0] numer, denom; output got; output [10: 0] answ; reg got; reg [10: 0] answ; reg [20: 0] sub, internal; reg [3: 0] dcount; always @ (posedge clk) begin if (go) begin dcount = 0; internal < = numer < < 10; sub < = name < < 9; end if (dcount < 11) begin if (internal > sub) begin internal < = internal - sub; answ [10 - dcount] < = 1; end else begin internal < = infernal; answ [10 - dcount] < = 0; end sub < = sub > > 1; dcount < = dcount + 1; end got < = (dcount == 10); end endmodule Listing 30 // Sccsld:% W%% G% ******************************* * Copyright (c) 1997 Pioneer Digital Design Center Limited ******************************* module fserr_str (clk, nrst, resync, u_symbol, uc_pilot, ui_data, uqXlata, guard, freq_sweep, sr_sweep, lupdata, upaddr, upwstr, uprstr, upsell, upsel2, ram_di, te, tdin, freq_err, samp_err, ram_rnw, ram_addr, ram_do, tdout); input olk, nrst, resync, u_symbol, uc_pilot, upwstr, uprstr, te, tdin, upsell, upsel2; mput [1: 0] guard; input [3: 0] freq_sweep, sr_sweep, upaddr; input [11: 0] ui_data, uq_data; input [13: 0] ram_do; output ram_rnw, tdout; - output [9: 0] ram_addr; output [12: 0] freq_err, samp_err; output [13: 0] ram_di; inout [7: 0] lupdata; wire got_phase, en, load, symbol, u_symbol_buf, ucilot_buf; wire freq_open, sample_open; wire [1: 0] guard_reg; wire [10: 0] xcount; wire [1 1: 0] ui_data_buf, uq_data_buf; wire [13: 0] phase_in, phase_out, wire [20: 0] acc_out_simple; wire [29: 0] acc_out_prod wire [12: 0] freq_err_uf, samp_err_uf; wire [12: 0] freq_err_fil, samp_err_fil, freq_twiddle, sample_twiddle; buffer buffer (.clk (clk), .nrst (nrst), .resync (resync), . u_symbol_in (u_symbol),. uc_pilot_in (uc_pilot),. ui_data_in (ui_data),. uq_data_in (uq_data),. u_symbol_out (u_symbol_buf) .uc_pilot_out (uc_pilot_buf), .ui_data_ou (ui_data_buf),. uq_data__out (uq_data_buf), .got_phase (got_phase)), - tan_taylor phase_extr (. clk (clk),. nrst (nrst),. resync (resync), .uc_pilot (uc_pilot_buf), .ui_data (ui_data_buf), -. uq_data (uq_data_buf), .phase (phase_in),. got_phase (got_phase)); addr_gen addr_gen (. c lk (clk),. re sync (re sync), . u_symbol (u_symbol_buf 1,. uc_pilot (uc_pilot_buf1, .gothase (got_phase), .en (en), .load (load), .guard (guard), .addr (ram_addr), .xcount (xcount), .guard_reg (guard_reg),. symbol (symbol)); pilot_store pilot_store (.clk (clk), .en (en),. ram_do (ram_do), . phase_in (phase_in),. ram_rnw (ram_rnw),. ram_di (ram_di), .phase_out (phase_out)); acc_simple acc_simple (.clk (clk), .resync (resync), .load (load), .symbol (symbol), .new_phase (phase_in),. old_phase (phase_out),. acc_out (acc_out_simple)); acc_prod acc_prod (.cl (clk),. resync (resync), .load (load), . symbol (symbol),. new_phase (phase_in), .old_phase (phase_out), .xcount (xcount),. acc_out (acc out_prod)); slow_arith slow_arith (. acc_simple (acc_out_simple), . acc_prod (acc_out_prod),. guard (guard_reg),. freq_err_uf (freq_err_uf),. samp_err_uf (samp_err_uf1), - avg_8 # (14) Ipf_freq (.clk (clk), .resync (resync),. symbol (symbol), .in_data (freq_err_uf),. avg_ou (freq_err_fil)); avg_8 # (14) Ipf_samp (.clk (clk), .resync (resync),. symbol (symbol), .in_data (samp_err_uf1,. avg_out (samp_err_fil)); / * median_filter # (14) Ipf_freq (.clk (clk ), .nrst (nrst), .in_valid (symbol),. din (freq_err_uf), .dout (freq_err_fil)); media_hlter # (14) Ipf_samp (.clk (clk), .nrst (nrst),. in_valid (symbol ), .din (samp_err_uf), .dout (samp_err_fil)); * / sweep_twiddle sweep_twiddle (. freq_err_fil (freq_err_fil), . samp_err_fil (samp_err_fil),. freq_sweep (freq_sweep),. sr_sweep (sr_sweep),. freq_open (freq_open), .sample_open (sample_open),. freq_twiddle (freq_twiddle). sample_twiddle (sample_twiddle),. freq_err_out (freq_err),,. samp_err_out (samp_err)); lupidec lupidec (.clk (clk), .nrst (nrst), .resync (resync), .upaddr (upaddr), .upwstr (upwstr), .uprstr (uprstr),. lupdata (lupdata),. freq_open (freq_open),. sample_open (sample_open),. freq_twiddle (freq_twiddle),. sample_twiddle (sample_twiddle),. sample_loop_bw (),. freq_loop_bw (),. freq_err (freq err),. samp_err (samp_err),. f_err_update (),. s_err_update ()); endmodule Listing 31 // Sccsld:% W%% G% i ****** * ************************* ****************** Copyright (c) 1997 Pioneer Digital Design Center Limited *************************** lupidec module (clk, nrst, resync , upaddr, upwstr, uprstr, lupdata, freq_open, sample_open, freq_twiddle, sample_twiddle, sample_loop_bw, freq_loop_bw, freq_err, samp_err, f_err_update, s_err_update); mput clk, nrst, resync, upwstr, uprstr, f_err_update, s_err_update; input [3: 0] upaddr; mput [12: 0] freq_err, samp_err, -mout [7: 0] lupdata; output freq_open, sample_open; output [12: 0] freq_twiddle, sample_twiddle, sample_loop_bw, freq_loop_bw; reg freq_open, sample_open; reg [12: 0] freq_twiddle, sample_twiddle, sample_loop_bw, freq_loop_bw; wire wr_str; wire [3: 0] wr addr; wire [7: 0] wr_data; / * FOLDBEGINS 0 2 ,, address decode ,, * / ? FOLDBEGINS 0 0,, read decode ,, * / wire f_err_h_ren = (upaddr == 4 'he); wire f_err_I_ren = (upaddr == 4'hf) wire s_err_h_ren = (upaddr == 4'hc); wire s_err_l_ren = (upaddr == 4'hd); wire f_twd_h_ren = (upaddr == 4'h4) wire f_twd_l_ren = (upaddr == 4'h5); wire s_twd_h_ren = (upaddr == 4'h8); wire s_twd_I_ren = (upaddr == 4'h9) wire f_lbw_h_ren = (upaddr == 4'h6), wire f_lbw_l_ren = (upaddr == 4'h7); wire s_Ibw_h_ren = (upaddr == 4 'ha) wire s_lbw_l_ren = (upaddr == 4'hb); / * FOLDENDS * /? FOLDBEG1NS00,, write decode ,, * / wire f_twd_h_wen = (wr_addr == 4'h4); wire f_twd_l_wen = (wr_addr == 4'h5); wire s_twd_h_wen = (wr_addr == 4'hd); wire s_twd_I_wen = (wr_addr == 4'h9); wire f_lbw_h_wen = (wr_addr == 4'h6); wire f_lbw_l_wen = (wr_addr == 4'h7); wire s_lbw_h_wen = (wr_addr == 4 'ha); wire s_lbw_l_wen = (wr_addr == 4'hb); / * FOLDENDS * / / * FOLDENDS * /? FOLDBEGINS 0 2,, upi regs ,, * /? FOLDBEGINS 0 0,, f req error status reg,, * / upi_status_reg2 fr_err (.clk (clk), .nrst (nrst ), . status_value ( {3 'bO, freq_err.}.),. capture_strobe (f_err_update),. read_strobe (uprstr),. reg_select_l (f_err _l_ren),. reg_select_h (f_err_h_ren),. lupdata (lupdata)); / * FOLDENDS * /? FOLDBEGINS 0 0,, sample error status reg ,, * / upi_status_reg2 sr_err (.clk (clk), .nrst (nrst), . status_value ( {3 'bO, samp_err.}.),. capture_strobe (s_err_update),. read_strobe (uprstr),. reg_select_l (s_err_l_ren),. reg_select_h (s_err_h_ren),. lupdata (lupdata)); / * FOLDENDS * /? FOLDBEGINS O O,, control regs write latch,, / upi_write_latch # (3) write_lat (.clk (clk), .nrst (nrst),. Lupdata (lupdata), . upaddr (upaddr), .write_strobe (upwstr),. write_data (wr_data),. write_address (wr_addr), .write_sync (wr_str)); / * FOLDENDS * /? FOLDBEGINS OO,, freq twiddle etc rdbk regs ,, * / upi_rdbk_reg freq_r_upper (. Control_value ( { Freq_open, 2 'bO, freq_twiddle [12: 8].}.), .read_strobe (uprstr) , .reg_select (f_twd_h_ren),. lupdata (lupdata)); upi_rdbk_reg freq_r_lower (. control_value (freq_twiddle [7: 0]), .read_strobe (uprstr),. reg_select (f_twd_I_ren),. lupdata (lupdata)); / FOLDENDS /? FOLDBEGINS OO,, samp twiddle etc rdbk regs ,, * / upi_rdbk_reg samp_r_upper (. Control_value ( { Sample_open, 2'bO, sample_twiddle [12: 8].}.),. Read_strobe (uprstr),. reg_select (s_twd_h_ren),. lupdata (lupdata)); upi_rdbk_reg samp_r_lower (. control_value (sample_twiddle [7: 0]),. read_strobe (uprstr),. reg_select (s_twd_I_ren), .lupdata (lupdata)); / * FOLDENDS * / / * FOLDBEGINS OO,, freq loop bw rdbk regs ,, * / upi_rdbk_reg f r_lp_r_upper (. Control_value ( {3 'bO, freq_loop_bw [12: 8].}.),. Read_strobe (uprstr) , .reg_select (f_lbw_h_ren),. lupdata (lupdata)); upi_rdbk_reg fr_lp_r_lower (. control_value (freq_loop_bw [7: 0]), . read_strobe (uprstr),. reg__select (f_lbw_l_ren),. lupdata (lupdata)); / * FOLDENDS /? FOLDBEGINS OO,, samp loop bw rdbk regs ,, * / - upi_rdbk_reg sr_lp_r_upper (. Control_value ( { 3 'bO, sample_loop_bw [12 8].}.),.. Read_strobe (uprstr),. reg_select (s_lbw_h_ren),. lupdata (lupdata)); u p i _ r d b k _ r e g s r _ l p _ r _ l o w e r (. control_value (sample_loop_bw [7: 0]),. read_strobe (uprstr),. reg_select (s_lbw_l_ren),. lupdata (lupdata)); / FOLDENDS / / * FOLDENDS / / FOLDBEGINS02 ,, control regs ,, * / always @ (posedge clk) begin if (! Nrst) begin freq_open < = O; sample_open < = O; freq_twiddle < = 0 sample_twiddle c- O; sample_loop_bw < = 0; / / lili freq_loop_bw < = 0; 1/1111 end else begin if (wr_str) begin i f (f _ t wd_h_we n) begin freq_open < = wr_data [7]; freq_twiddle [12: d] < = wr_data [4: 0]; end i f (f _twd_I_wen) freq_twiddle [7: 0] < = wr_data [7: 0]; i f (s_t wd_h_wen) begin sample_open < = wr_data [7]; sample_twiddle [12: 8] < = wr_data [4: 0]; end if (s_twd_I_wen) sample_twiddle [7: 0] < = wr_data [7: 0], -i f (f _Ibw_h_wen) freq_loop_bw [l2: 8] < = wr_data [4: 0]; i f (f _1 bw_l_wen) freq_loop_bw [7: 0] < = wr_data [7: 0]; if (s_lbw_h_wen) sample_loop_bw [12: 8] < = wr_data [4: 0]; if (s_lbw_l_wen) sample_loop_bw [7: 0] < = wr_data [7: 0]; end end end / * FOLDENDS * / endmodule Listing 32 // Sccsld:% W%% G% ************************* ****** Copyright (c) 1997 Pioneer Digital Design Center Limited ***************************** **** module pilot_store (clk, en, ram_do, phase_in, ram_rnw, ram_di, phase_out); input clk, in; // input [9: 0] addr; input [13: 0] phase_in; input [13: 0] ram_d ?; output ram_rnw; output [13: 0] ram_di, phase_out; wire r am_rnw; // reg en_dl; // reg [9: 0] addr_reg; // reg [13: 0] mem [579: 0]; reg [13: 0] phase_out; II, phase_in_reg; wire [13: 0] ram_di; always © (posedge clk) begin // en_d 1 < = in; if (en) begin // phase_in_reg < = phase_in; // addr_reg < = addr; phase_out < = ram_do; // phase_out < = mem [addr]; end // if (en_dl) // me [addr_reg] < = phase_in_reg; end assign ram_di = phase_in; assign ram_rnw = ¡en; endmodule Listing 33 // Sccsld:% W%% G% ****************************** Copyright (c) 1997 Pioneer Digital Design Center Limited **************************** module slow_arith (acc_simple, acc_prod, guard, freq_err_uf, samp_err_uf); input [1: 0] guard; input [20: 0] acc_simple; input [29: 0] acc_prod; output [12: 0] freq_err_uf, samp_err_uf; reg [12: 0] freq_err_uf, samp_err_uf; reg [20: 0] freq_scale; reg [38: 0] inter_freq; reg sign; reg [20: 0] mod_acc; reg [38: 0] mod_trunc_sat reg [41: 0] mod, reg sign_a, sign_b, sign_inter_sr, -reg [20: 0] mod_acc_s; reg [29: 0] mod_acc_p; reg [35: 0] a, mod_a; reg [35: 0] b, mod_b; reg [36: 0] mod_diff, diff; reg [46: 0] inter_sr, mod_inter_sr; parameter sp = 45, acc_x = 33927, samp_scale = 11 'blOlOOlOOllO; always (guard) case (guard) 2'bOO: freq_scale = 21 'bOllllOlOOlllllOOOlOll; // guard == 64 2'b? l: freq_scale = 21 'bOlllOllOlllOOOlOOOOll; // guard == 128 2'blO: freq_scale = 21 'bOlllOOOOOlOOOlllOlOlO; // guard == 256 2 'bll: freq_scale = 21' bOllOOlOlOOOOllOOlllll; // guard == 512 endcase always © (acc_simple or freq_scale) begin sign = acc_simple [20]; mod_acc = sign? (~ acc_simple + 1) .- acc_simple; mod = (freq_scale mod_acc); // inter_freq - sign? (~ mod + 1): mod; if (mod [41:38] > 0) begin mod_trunc_sat = 39h3Ffrrrrrrr; $ display (,, freq_err saturated,,); end else mod_trunc_sat = mod [38: 0], • inter_freq = sign? (~ mod_trunc_sat + 1): mod_trunc_sat; freq_err_uf = inter_freq > 26; end always © (acc_simple or acc_prod) begin sign_a = acc_prod [29]; mod_acc_p = sign_a? (-acc_prod + 1): acc_prod; mod_a = sp * mod_acc_p; a = sign_a? (~ mod_a + 1) .- mod_a; sign_b = acc_simple [20]; mod_acc_s = sign_b? (-acc_simple + 1): acc_simple; mod_b = acc_x mod_acc_s, -b = sign_b? (~ mod_b + 1): mod_b; diff =. { a [35], a} -. { b [35], b}; // sign extend sign_inter_sr = diff [36] mod_diff - sign_inter_sr? (~ diff + 1): diff; - mod_inter_sr = (mod_diff * samp_scale); inter_sr = sign_inter_sr? (~ mod_inter_sr + 1): mod_inter_sr; - samp_err_uf = inter_sr > > 3. 4; //! Scaling! ! end endmodule Listing 34 // Sccsld:% W%% G% / ij - ***************************** **** **** ***************** Copyright (c) 1997 Pioneer Digital Design Center Limited *********************************** module sweep_twiddle (freq_err_fil, samp_err_fil, freq_sweep, sr_sweep, freq_open, sample_open, freq_twiddle, sample_twiddle, freq_err_out, samp_err_out), - input freq_open, sample_open; input [3: 0] freq_sweep, sr_sweep; input [12: 0] freq_err_fil, samp_err_fil, freq_twiddle, sample_twiddle; output [12: 0] freq_err_out, samp_err_out; reg [12: 0] freq_err_ou, samp_err_out; reg [12: 0] freq_err_swept, samp_err_swept; always @ (freq_sweep or freq_err_fil) case (freq_sweep) 4'b0000: freq_err_swept = freq_err_fil; 4'bO001: freq_err_swept = freq_err_fil + 500 4'bO010: freq_err_swept = freq_err_fil + 1000; 4'bOOll: freq_err_swept = freq_err_fil + 1500; 4'bO100: freq_err_swept = freq_err_fil + 2000; 4'bO101: freq__err_swept = freq_err_fil + 2500; 4'bO110: freq_err_swept = freq_err_fil + 3000; 4'b? Lll: freq_err_swept = freq_err_fil + 3500; default: freq_err_swept = freq_err_fil; endcase always @ (sr_sweep or samp_err_fil) case (sr_sweep) 4'bOOOO: samp_err_swept = samp_err_fil; 4'bO00l: samp_err_swept = samp_err_fil + 500; 4'BOOlO: samp_err_swept = samp_err_fil - 500; 4'bO0ll: samp_err_swept = samp_err_fil + 1000; 4'bOlOO: samp_err_swept = samp_err_fil - 1000; 4'bO101: samp_err_swept = samp_err_fil + 1500; 4 'bOllO. • samp_err_swept = samp_err_fil- 1500; 4'b? Lll: samp_err_swept = samp_err_fil + 2000; 4'bl000: samp_err_swept = samp_err_fil - 2000; default: samp_err_swept = samp_err_fil; endcase always © (freq_err_swept or freq_open or freq_twiddle) if (freq_open) freq_err_out = freq_twiddle; else freq_err_out = freq_err_swept + freq_twiddle; always. © (samp_err_swept or sample_open or sample_twiddle) if (sample_open) samp_err_out = sample_twiddle; else samp_err_out = samp_err_swept + sample_twiddle; endmodule Listing 35 // Sccsld:% W%% G% / ******************************* ******************** Copyright (c) 1997 Pioneer Digital Design Center Limited ****************************** module tan_taylor (clk, nrst, resync, uc_pilot, ui_data , uq_data, phase, got_phase); input clk, nrst, resync, uc_pilot; input [11: 0] ui_data, uq_data; output got_phase; output [13: 0] phase; reg got_phase; reg [13: 0] phase; reg add, qgti, odqeqi, i_zero_reg, q_zero_reg, go; reg [1: 0] quadrant, - reg [6: 0] count, count_dl; reg [10: 0] mod_i, mod_q, coeff, numer, denom; reg [21: 0] x_sqd, x_pow, next_term, sum, flip, next_term_unshift, prev_sum, x_sqd_unshift, x_pow_unshift; wire got; wire [10: 0] div; parameter pi = 6434, pi_over2 = 3217, minus_pi_o2 = 13167, pi_over4 = 1609; divide divl (clk, go, numer, denom, div, got); always © (posedge clk) begin if (nrst 1 1 resync) count < = else begin if (uc_pilot) begin mod_i < = ui_data [ll]? (~ ui_data [10: 0] + 1): ui_data [10: 0], mod_q < = uq_data [11]? (~ uq_data [10: 0] + 1): uq_data [10: 0]; quadrant < =. { uq_data [11], ui_data [11]}; count < = 0; go < = 0; end else begin if (count == 0) begin qgti < = (mod_q> mod_i) modqeqi < = (mod_q = - mod_i); i_zero_reg < = (mod_i == 0); q_zero_reg < = (mod_q == 0); add < = 0; go < = 1; count < =; end if ((count > = 3) S.S. (count < 71)) count < = count + 2; ? f (count == 1) begin 90 < = 0; if (got) begln sum < = div; x_pow < = div; x_sqd < = x_sqd_unshift > eleven; count < = 3; end end if ((count > 1) ScS. (count < 69)) x_pow < = x_pow_unshift > > eleven; if ((count > 3) ScSc (count < 69)) next_term < = next_term_unshift > > 12; if ((count &5) & S_ (count < 69)) - begin prev_sum < = sum; sum = add? (sum + next_term): (sum - next_term); add < = Add; end end if. { count == 67) sum < = (prev_sum + sum) > > 1; if (count == 69) casex ( { i_zero_reg, q_zero_reg, qgti, modqeqi, quadrant.}.) 6'blxx0_0x: phase < = pi_over2; 6'blxx0_lx: phase < = minus_pi_o2; 6'b01xO_xO: phase < = O 6 'b01xO_xl: phase < = pi; 6'bO010_00: phase < =. { 2 'bOO, f lip [11: 0]}; 6'bO010_01: phase < = pi -. { 2 'bOO, f lip [11: 0]}; 6'bO010_10: phase < = 0 -. { 2 'bOO, f li [11: 0]}; 6'bO010_ll: phase < =. { 2 'bOO, f lip [11: 0]} -pi; 6'bOOOO_00: phase < =. { 2 'bOO, sum [11: 0]}; 6'bO000_01: phase < = pi -. { 2 'bOO, sum [11: 0]}; 6'bO000 _10: phase < = O -. { 2 'bOO, sum [11: 0]}; 6'bOOOO ll: phase < =. { 2 'bOO, sum [11: 0]} -pi; 6'bxxxl_00: phase < = pi_over4; 6'bxxxl_01: phase < = pi - pi_over4; 6'bxxxl_10: phase < = O - pi_over4 6'bxxxl_11: phase < = pi_over4 - pi; endcase count_dl < = count; got_phase < = (count == 69); end end always © (div) x_sqd_unshift = div div; // had to do this in order to stop synthesis throwing away! always (x_pow or coeff) next_term_unshift = (x_pow coeff); // compass dp_cell mult_booth_csum always © (x_pow or x_sqd) x_pow_unshift = (x_pow x_sqd); // compass dp_cell mult_booth_csum always © (count_dl) case (count_d 1) 3: coeff = 11 'bl0101010101; 5: coeff = 11'bOllOOllOOll; 7: coeff = 11 'bOlOOlOOlOOl; 9: coeff = 11 'bOOlllOOOlll; • totoootooooq.tt = ggaoo: 6_ 53 txxoootooooq. xt = ggaoo: 5 oxotootooooq. tt = ggaoo: ss tottootooooq. tt = ggaoo: is • oooototooooq. tt = ggaoo: tg • Atooxoxooooq.xx = ggaoo - 6 03 • txtototooooq. tt = ggaoo • L? 7 • ttottotooooq.tt = ggaoo: t -Atttxoxooooq.tt = ggaoo: zt ootoottooooq. tt = ggaoo • - tt tootottooooq. tt = ggaoo - ez st otttottooooq. tt = ggaoo - L Z tototttooooq. tt = ggaoo: it is ootttttooooq. tt = ggaoo: ee • ootooootoooq.tt = ggaoo = te • Aottoootoooq.tt: = ggaoo = 63 ot • ttxotootoooq. tt = ggaoo A3 • ttooototoooq. tt = ggaoo: _3 • otoottotoooq.tt = = ggaoo A3 • Atoooottoooq. tt = ggaoo • A3 -tttotottoooq.tt = = ggaoo • - 61 • 'tooottttoooq. tt = ggaoo xt 'toootoootooq. tt = ggaoo: st • ttotttootooq.tt = = ggaoo •• et • Oototttotooq.tt = = ggaoo = tt 6S-_ 61: coeff - 1 1'bOOOOlOOOOll; 63: coeff = 1 1'bOOOOlOOOOOl; // 65: coeff = // 67: coeff = 11 'bOOOOOllllOl; 1169: coeff = 11'bOOOOOlllOll; // 71: coeff = 11 'bOOOOOlllOOl, // 73: coeff = 11' bOOOOOlllOOO, // 75: coeff = 11 'bOOOOOllOllO, // 77: coeff = 11' bOOOOOllOlOl, default: coeff = 11 'bx; endcase always © (mod_q or mod_i or qgti) beg in numer = qgti? mod_i: mod_q; denom = qgti? mod_q: mod_i; end always © (sum) flip = pi_over2 - sum; // always © (got) // if (got) // $ display (,, numer was% d, name was% d, div then% d,,, numer, denom, div); // always © (count) // if (count < 68) $ display (,, as far as x to the% Od term, approx =% d,,, (count -6), sum); always @ (got_phase) begin: display reg [i3: 0] real_phase; if (phase [13]) begin real_phase = (-phase + 1); if (got_phase) $ display (,,% t: got phase, phase = -% 0d,,, $ time, real_phase), -end else begin if (got_phase) $ display (,,% t: got phase, phase = % 0d,,, $ time, phase); end end // display endmodule Although this invention has been explained with reference to the structure described herein, it is not confined to the details that are established, and it is intended that this application cover any modification and change that may be within the scope of the following claims: state that in relation to this date, the best method known by the applicant to carry out the aforementioned invention, is the conventional one for the manufacture of the objects or products to which it refers.

Claims (35)

1. CLAIMS Having described the invention as above, the property is claimed as contained in the following: 1. A digital receiver for multiple carrier signals, comprising: an amplifier that accepts a multiple carrier analog signal, wherein the multiple carrier signal comprises a stream of data symbols having a symbol period Ts, wherein the symbols comprise an active interval, a guard interval and a boundary between them, the guard interval is a replication of a portion of the active interval; an analog to digital converter coupled to the amplifier; an I / Q demodulator to recover the in-phase and quadrature components of the data sampled by the analog-to-digital converter; an automatic gain control circuit coupled to the digital analog converter to provide a gain control signal for the amplifier; a low-pass filter circuit that accepts I and Q data from the I / Q demodulator, where the I and Q data are decimated; a resampling circuit that receives the decimated data I and Q at a first rate and which transmits the resampled I and Q data at a second speed; an FFT interval synchronization circuit coupled to the resampling circuit to locate a limit of the guard interval; a real-time channelized FFT processor operationally associated with the FFT interval synchronization circuit, wherein the FFT processor comprises at least one stage, the stage comprising: a complex coefficient multiplier; and a memory that has a search table defined therein for multiplicands that are multiplied by a multiplier of the complex coefficient, a value of each multiplicand is unique in the search table; and a monitor circuit responding to the FFT interval synchronization circuit to detect a predetermined event, whereby the event indicates that it has been located at a boundary between an active symbol and a guard interval.
2. 2. The receiver according to claim 1, characterized in that the interval synchronization circuit FFT comprises: a first delay element that accepts the resampled I and Q data currently arriving, and transmits delayed resampled I and Q data; a subtracter, to produce a difference signal representative of the difference between the resampled I and Q data arriving at that time and the delayed resampled I and Q data; a first circuit for producing an output signal having a unipolar magnitude that is representative of the difference signal of the subtracter; a second delay element for storing the output signal of the first circuit; a third delay element receiving the delayed output of the second delay element; and a second circuit for computing a statistical relationship between the data stored in the second delay element and the data stored in the third delay element and having an output representative of the statistical relationship.
3. The receiver according to claim 2, characterized in that the statistical relation comprises a proportion F.
4. 4. The receiver according to claim 1, characterized in that the FFT processor operates in an 8K mode.
5. 5. The receiver according to claim 1, characterized in that the FFT processor further comprises an address generator for the memory, the address generator accepts a signal representing a dependency order of a currently required multiply and transmits an address of the memory in which is stored multiplying currently required.
6. The receiver according to claim 5, characterized in that each multiplier is stored in the search table in the order of its respective order dependence for multiplication by the complex coefficient multiplier, the order dependencies of the multiples define a sequence of increment and the address generator comprises: an accumulator to store a previous address that is generated by the address generator; a circuit for calculating an increment value of the multiplier currently required; and an adder to add the increment value to the previous directions.
7. The receiver according to claim 6, characterized in that the search table comprises a plurality of rows, and the increment sequence comprises a plurality of increment sequences, the multiplicands are stored in row order, wherein in a first row a first increment sequence is 0; in a second row, a second increment sequence is 1; in a third row, a first and second breakpoints Bl, B2 of a third increment sequence are determined respectively by the relationships B1WM = 4WB1M "" __. 4" 232, = S 4p n = 0 ; and in a fourth row a third breakpoint B3 of a third increment sequence is determined, by the ratio B3M = 2 x 4W + 2 where MN represents the memory of the nth stage of the FFT processor.
8. 8. The receiver according to claim 1, characterized in that it also comprises channel estimation and correction circuits comprising: pilot signal location circuits that receive a digital transformed signal representing a frame from the FFT processor to locate pilot carriers in them , where the pilot carriers are separated into a carrier spectrum of the digital signal transformed at K intervals and have predetermined magnitudes, the location circuits of the pilot signal comprise: a first circuit to calculate an order of carriers in the K module of the digital signal transformed; Accumulated K is coupled to the second circuit to accumulate magnitudes of the carriers in the transformed digital signal, the accumulated magnitudes define a set; and a correlation circuit for correlating the sets K of accumulated magnitude values with the predetermined magnitudes, wherein the first member has a calculated position of modulus K in each of the sets K is uniquely offset from the start position of the framework.
9. The receiver according to claim 8, characterized in that the location circuits of the pilot signal further comprise a bit inversion circuit for inverting the order of the bits of the transformed digital signal.
10. The receiver according to claim 7, characterized in that the magnitudes of the carriers and the predetermined magnitudes are amplitudes.
11. The receiver according to claim 7, characterized in that the magnitudes of the carriers and the predetermined magnitudes are absolute values.
12. The receiver according to claim 7, characterized in that the correlation circuits further comprise a peak tracking circuit for determining a separation between a first peak and a second peak of the K sets of accumulated magnitudes.
13. The receiver according to claim 7, characterized in that the channel estimation and correction circuit further comprises: an interpolation filter for estimating a channel response between the pilot carriers; and a multiplication circuit for multiplying data carriers transmitted by the FFT processor with a correction coefficient produced by the interpolation filter.
14. 14. The receiver according to claim 7, characterized in that the channel estimation and correction circuits further comprise: a phase extraction circuit that accepts a data stream of the I and Q data not corrected in phase from the FFT processor, and produces a signal representative of the phase angle of the uncorrected data, the phase extraction circuit includes an accumulator for accumulating the data phase angles I and Q without correction in the successive phase.
15. The receiver according to claim 14, characterized in that the channel estimation and correction circuits further comprise: an automatic frequency control circuit coupled to the phase extraction circuit and to the accumulator, comprising; a memory for storing a phase error as a cumulative of a first symbol conveyed in the data I and Q of uncorrected phase; wherein the accumulator is coupled to the memory and accumulates a difference between a common phase error of a plurality of pilot carriers in a second symbol and a common phase error of the corresponding pilot carriers in the first symbol; an output or transmission of the accumulator is coupled to the I / Q demodulator.
16. The receiver according to claim 15, characterized in that the coupled output of the accumulator is activated by the I / Q demodulator only during the reception of a guard interval therein.
17. 17. The receiver according to claim 14, characterized in that the channel estimation and correction circuits further comprise an automatic sampling rate control circuit coupled to the phase extraction circuit, comprising: a memory for storing accumulated phase errors of pilot carriers in a first symbol transported in Phase I and Q data uncorrected; wherein the accumulator is coupled to the memory and accumulates the differences between the phase errors of the pilot carriers and a second symbol and the phase errors of the corresponding pilot carriers in the first symbol to define a plurality of phase error differentials. carrier between accumulated symbols, a phase slope is defined by a difference between a first accumulated carrier-to-symbol phase differential and a second cumulative intersymbol carrier-phase differential; an output of the accumulator is coupled to the I / Q demodulator.
18. 18. The receiver according to claim 17, characterized in that the sampling rate control circuit stores a plurality of cumulative intersymbol carrier phase error differentials and calculates a line of best fit between them.
19. 19. The receiver according to claim 17, characterized in that the output signal coupled from the accumulator is activated in the resampling circuit only during the reception of a guard interval in it.
20. The receiver according to claim 17, characterized in that a common memory is coupled to store the output of the phase extraction circuit, to the automatic frequency control circuit to the automatic sampling speed control circuit.
21. The receiver according to claim 14, characterized in that the phase extraction circuit further comprises: a channeled circuit for interactively calculating the tangent arc of a rotation angle according to the series tan 1 (x) = x - x = X '~ 3 ~ T x \ 1 ~ 9 ~ where x is a proportion of the uncorrected phase I and Q data.
22. 22. The receiver according to claim 21, characterized in that the channelized circuit comprises: a constant coefficient multiplier; and a multiplexer for selecting one of a plurality of constant coefficients of a series, an output of the multiplexer is connected to an input of the constant coefficient multiplier.
23. 23. The receiver according to claim 21, characterized in that the channelized circuit comprises: a multiplier; a first memory for storing the quantity x2, the first memory is coupled to a first input of the multiplier; a second memory for retaining an output of the multiplier; and a feedback connection between the second memory and the second input of the multiplier.
24. The receiver according to claim 21, characterized in that the channelized circuit further comprises: a third memory for storing a value of the series; a control circuit coupled to the third memory, wherein the channelization circuit calculates N terms of the series, and the channelization circuit calculates N + l terms of the series, where N is an integer; an averaging circuit coupled to the third memory to calculate an average of the N terms and the N + l terms of the series.
25. The receiver according to claim 1, characterized in that the data transmitted on a pilot carrier of the multiple carrier signal is encoded BCH according to a polynomial h (x), code generator, characterized in that it also comprises: a demodulator operative in the data encoded by BCH; an interactive channelized BCH decoder circuit comprising: a circuit coupled to the demodulator to form a Galois field of the polynomial, and calculating a plurality of syndromes thereof; a plurality of storage registers, each of the storage registers stores one of the respective syndromes; a plurality of feedback shift registers, each of the feedback shift registers accepts data from one of the respective storage registers and has an output; a plurality of field multipliers of Galois, each of the multipliers is connected to a feedback loop through one of the respective feedback shift registers and multiplies the output of its associated feedback shift register by an alpha value of the Galois field, - a multiplier field output Galois to multiply the output of two of the feedback displacement records; an error detection circuit connected to the feedback shift registers and the output Galois field multiplier, wherein the output signal of the error detection circuit indicates an error in a stream of data bits; and a feedback line enabled by the error detection circuit and connected to the storage registers, where the outputs of the feedback shift registers are written to the storage registers.
26. 26. The receiver according to claim 25, characterized in that the Galois field multiplier comprises: a first register that initially stores a first multiplier A; a constant coefficient multiplier connected to the register for multiplication by a value, an output of the constant coefficient multiplier is connected to the first register to define a first feedback circuit, so that the katesimo cycle of the synchronized operation or clock of the first record contains the field product of Galois A k; a second record to store a second multiplying B; an AND gate (Y) connected to the second register and to the output of the constant coefficient multiplier; an adder that has a first input connected to an output of the AND gate; an accumulator connected to the second inlet of the adder, wherein the outlet of the adder is connected to the accumulator to define a second feedback circuit; where the field product of Galois AB is transmitted by the adder.
27. 27. A method for estimating a frequency responsible for a channel, comprising the steps of: receiving from a channel a multiple carrier signal having a plurality of scattered pilot carrier and data carriers, the scattered pilot carriers are separated in a first interval N and are transmitted at a power that differs from the transmitted power of the data carriers; convert the signal of the multiple carrier to a digital representation thereof; performing a Fourier transformation on the digital representation of the multiple carrier signal to generate a transformed digital signal; inverting the bit order of the transformed digital signal to generate a signal with an inverted order of bits; accumulate cyclically magnitudes of carriers on the inverted signal in the order of bits in N accumulators; correlate the accumulated magnitudes with the power of the dispersed pilot carriers; in response to the correlation step, generate a synchronizing signal that identifies a carrier of the multiple carrier signal.
28. 28. The method according to claim 27, characterized in that the step of accumulating magnitudes comprises the steps of: adding absolute values of a real component of the inverted signal in order of bits to the respective absolute values of imaginary components thereof to generate sums; store the sums in the accumulators respectively.
29. 29. The method according to claim 27, characterized in that the step of correlating the accumulated magnitudes further comprises the step of: identifying a first accumulator having the highest value stored in it that represents a first carrier position.
30. 30. The method according to claim 29, characterized in that the step of correlating the accumulated magnitudes further comprises the steps of: identifying a second accumulator having the second highest value stored thereon representing a second carrier position; and determining an interval between the first carrier position and the second carrier position.
31. 31. The method according to claim 27, characterized in that it further comprises the steps of: comparing a position of a carrier of a first symbol in the inverted signal in order of bits with a position of a carrier of a second symbol therein.
32. 32. The method according to claim 27, characterized in that it further comprises the steps of: interpolating between the pilot carriers to determine correction factors for respective intermediate data carriers placed between them; and respectively adjust the magnitudes of the intermediate data carriers according to the correction factors.
33. The method according to claim 27, characterized in that it further comprises the steps of: determining a mean phase difference between the corresponding pilot carriers of successive symbols that are transmitted in the transformed digital signal; and generating a first control signal in response to the middle phase difference; and in response to the first control signal adjust a frequency of reception of the multiple carrier signal.
34. 34. The method according to claim 33, characterized in that it further comprises the steps of: determining a first phase difference between a first data carrier of a first symbol in the transmitted data carrier, and the first data carrier of a second symbol in it; determining a second phase difference between the second data carrier of the first symbol and the second data carrier of the second symbol; and determining a difference between the first phase difference and the second phase difference to define a phase slope between the first data carrier and the second data carrier; generate a second control signal in response to the phase slope; and in response to the second control signal, adjust a sampling frequency of the multiple carrier signal.,
35. 35. The method according to claim 34, characterized in that the step of determining a difference between the first phase difference and the second phase difference comprises calculating a line of best fit.