AU727726B2 - Single chip VLSI implementation of a digital receiver employing orthogonal frequency division multiplexing - Google Patents

Description

WO 98/19410 PCTIUS97/18911 1 SINGLE CHIP VLSI IMPLEMENTATION OF A DIGITAL RECEIVER EMPLOYING ORTHOGONAL FREQUENCY DIVISION MULTIPLEXING This invention relates to receivers of electromagnetic signals employing multicarrier modulation. More particularly this invention relates to a digital receiver which is implemented on a single VLSI chip for receiving transmissions employing orthogonal frequency division multiplexing, and which is suitable for the reception of digital video broadcasts.

Coded orthogonal frequency division multiplexing ("COFDM") has been proposed for digital audio and digital video broadcasting, both of which require efficient use of limited bandwidth, and a method of transmission which is reliable in the face of several effects. For example the impulse response of a typical channel can be modeled as the sum of a plurality of Dirac pulses having different delays. Each pulse is subject to a multiplication factor, in which the amplitude generally follows a Rayleigh law. Such a pulse train can extend over several microseconds, making unencoded transmission at high bit rates unreliable. In addition to random noise, impulse noise, and fading, other major difficulties in digital terrestrial transmissions at high data rates include multipath propagation, and adjacent channel interference, where the nearby frequencies have highly correlated signal variations. COFDM is particularly suitable for these applications.

In practical COFDM arrangements, relatively small amounts of data are modulated onto each of a large number of carriers that are closely spaced in frequency. The duration of a data symbol is increased in the same ratio as the number of carriers or subchannels, so that inter-symbol interference is markedly reduced.

Multiplexing according to COFDM is illustrated in Figs. 1 and 2, wherein the spectrum of a single COFDM carrier or subchannel is indicated by line 2. A set of carrier frequencies is indicated by the superimposed waveforms in Fig. 2, where orthogonality conditions are satisfied. In general two real-valued functions are orthogonal if b f jp(t)l Kq(t)dt (1) a where K is a constant, and K 0 if p q; K ;0 if p q. Practical encoding and decoding of signals according to COFDM relies heavily on the fast Fourier transform as can be appreciated from the following equations.

The signal of a carrier c is given by Sc(t Ac(t)e J[lt (2) WO 98/19410 PCTIS97/18911 2 where A c is the data at time t, w) is the frequency of the carrier, and c, is the phase. N carriers in the COFDM signal is given by

N

Ss(t) 1 A (t)e i [nt*" 1 0 (3) n 0 (0n nAw (4) Sampling over one symbol period, then n(t) n Ac(t)=A. (6) With a sampling frequency of 1/T, the resulting signal is represented by

N

s(t) (1 IN) E An(t)el +nAw)kT+, (7) n=0 Sampling over the period of one data symbol T NT, with co 0, N-1 s,(kT) 1 AneJ'nei(nw)kT (8) n =0 which compares with the general form of the inverse discrete Fourier transform: N -1 g(kT) G(n/(kT))e jn n k N (9) n=o In the above equations Ane' n is the input signal in the sampled frequency domain, and ss(kT) is the time domain representation. It is known that increasing the size of the FFT provides longer symbol durations and improves ruggedness of the system as regards echoes which exceed the length of the guard interval. However computational complexity increases according to Nlog 2 N, and is a practical limitation.

In the presence of intersymbol interference caused by the transmission channel, orthogonality between the signals is not maintained. One approach to this problem has been to deliberately sacrifice some of the emitted energy by preceding each symbol in the time domain by an interval which exceeds the memory of the channel, and any multipath delay. The "guard interval" so chosen -is large enough to absorb any intersymbol interference, and is established by preceding each symbol by a replication of a portion of itself. The replication is typically a cyclic extension of the terminal portion WO 98/19410 PCT/US97/18911 3 of the symbol. Referring to Fig. 3, a data symbol 4 has an active interval 6 which contains all the data transmitted in the symbol. The terminal portion 8 of the active interval 6 is repeated at the beginning of the symbol as the guard interval 10. The COFDM signal is represented by the solid line 12. It is possible to cyclically repeat the initial portion of the active interval 6 at the end of the symbol.

Transmission of COFDM data can be accomplished according to the known general scheme shown in Fig. 4. A serial data stream 14 is converted to a series of parallel streams 16 in a serial-to-parallel converter 18. Each of the parallel streams 16 is grouped into x bits each to form a complex number, where x determines the signal constellation of its associated parallel stream. After outer coding and interleaving in block 20 pilot carriers are inserted via a signal mapper 22 for use in synchronization and channel estimation in the receiver. The pilot carriers are typically of two types. Continual pilot carriers are transmitted in the same location in each symbol, with the same phase and amplitude. In the receiver, these are utilized for phase noise cancellation, automatic frequency control, and time/sampling synchronization. Scattered pilot carriers are distributed throughout the symbol, and their location typically changes from symbol to symbol. They are primarily useful in channel estimation. Next the complex numbers are modulated at baseband by the inverse fast fourier transform ("IFFT") in block 24. A guard interval is then inserted at block 26. The discrete symbols are then converted to analog, typically low-pass filtered, and then upconverted to radiofrequency in block 28.

The signal is then transmitted through a channel 30 and received in a receiver 32. As is well known in the art, the receiver applies an inverse of the transmission process to obtain the transmitted information. In particular an FFT is applied to demodulate the signal.

A modern application of COFDM has been proposed in the European Telecommunications Standard ETS 300 744 (March 1997), which specifies the framing structure, channel coding, and modulation for digital terrestrial television. The specification was designed to accommodate digital terrestrial television within the existing spectrum allocation for analog transmissions, yet provide adequate protection against high levels of co-channel interference and adjacent channel interference. A flexible guard interval is specified, so that the system can support diverse network configurations, while maintaining high spectral efficiency, and sufficient protection against co-channel interference and adjacent channel interference from existing PAL/SECAM services. The noted European Telecommunications Standard defines two modes of operation. A "2K mode", suitable for single transmitter operation and for small single frequency networks with limited transmitter distances. An "8K mode" can be used for either single transmitter operation or for large single frequency networks. Various levels of quadrature amplitude modulation are supported, as are different inner code rates, in order to balance bit rate against ruggedness. The system is intended to accommodate a transport layer according to the Moving Picture Experts Group and is directly compatiblewith MPEG-2 coded TV signals (ISO/IEC 13818).

In the noted European Telecommunications Standard data carriers in a COFDM frame can be either quadrature phase shift keyed 16-QAM, 64-QAM, nonuniform 16-QAM, or non-uniform 64-QAM using Gray mapping.

An important problem in the reception of COFDM transmission is difficulty in maintaining synchronization due to phase noise and jitter which arise from upconversion prior to transmission, downconversion in the receiver, and the front end oscillator in the tuner, which is typically a voltage controlled oscillator. Except for provision of pilot carriers to aid in synchronization during demodulation, these issues are not specifically addressed in the noted European Telecommunications Standard, but are left for the implementer to solve.

Basically phase disturbances are of two types. First, noisy components which disturb neighbor carriers in a multicarrier system are called the "foreign noise contribution" Second, a noisy component which disturbs its own carrier is referred to as the "own noise contribution".

:I Referring to Fig. 5, the position of ideal constellation samples are indicated by "x" 2 0 symbols 34. The effect of foreign noise contribution is stochastic, resulting in Gaussian- S like noise. Samples perturbed in this manner are indicated on Fig. 5 as circles 36. The effects of the own noise contribution is a common rotation of all constellation points, ol indicated as a displacement between each symbol 34 and its associated circle 36.

This is referred to as the "common phase error", which notably changes from symbol to ?25 symbol, and must therefore be recalculated each symbol period T s The common phase error may also be interpreted as a mean phase deviation during the symbol period T s In order for the receiver 32 to process the data symbols in a practical system, a mathematical operation is performed on the complex signal representing each data symbol. Generally this is an FFT. For valid results to be obtained, a particular form of timing synchronization is required in order to align the FFT interval with the received data symbol.

In accordance with the present invention, there is provided a digital receiver for multicarrier signals comprising: an amplifier accepting an analog multicarrier signal, wherein said multicarrier signal comprises a stream of data symbols having a symbol period wherein the symbols comprise an active interval, a guard interval, and a boundary therebetween, ,Z1(d guard interval being a replication of a portion of said active interval; P:%OPER\DBW 1471-98 speci.doc-19 October. 2000 an analog to digital converter coupled to said amplifier; an I/Q demodulator for recovering in phase and quadrature components from data sampled by said analog to digital converter; an automatic gain control circuit coupled to said analog to digital converter for providing a gain control signal for said amplifier; a low pass filter circuit accepting I and Q data from said I/Q demodulator wherein said I and Q data are decimated; a resampling circuit receiving said decimated I and Q data at a first rate and outputting resampled I and Q data at a second rate; an FFT window synchronization circuit coupled to said resampling circuit for locating a boundary of said guard interval; a real-time pipelined FFT processor operationally associated with said FFT window synchronization circuit, wherein said FFT processor comprises at least one stage, said stage comprising: 5 a complex coefficient multiplier; and a memory having a lookup table defined therein for multiplicands being multiplied in said complex coefficient multiplier, a value of each said multiplicand being unique in said lookup table; and a monitor circuit responsive to said FFT window synchronization 20 circuit for detecting a predetermined event, whereby said event indicates that a boundary between an active symbol and a guard

S..

interval has been located.

The present invention also provides a method for estimation of a frequency response of a channel, comprising the steps of: receiving from a channel a multicarrier signal having a plurality of data carriers and scattered pilot carriers, said scattered pilot carriers being spaced apart at a first interval N and being transmitted at a power that differs from a transmitted power of said data carriers; converting said multicarrier signal to a digital representation thereof; performing a Fourier transform on said digital representation of said multicarrier signal to generate a transformed digital signal; P:\OPER\DBW\51471-98 spooi.doc-19 October. 2000 6 reversing a bit order of said transformed digital signal to generate a bitorder reversed signal; cyclically accumulating magnitudes of carriers in said bit-order reversed signal in N accumulators; correlating said accumulated magnitudes with said power of said scattered pilot carriers; responsive to said step of correlating, generating a synchronizing signal that identifies a carrier of said multicarrier signal.

The present invention also provides a modulated multicarrier receiver comprising: a demodulator accepting digitized data representing modulated multicarrier symbols; carrier recovery circuitry; •a microprocessor interface; 15 a Viterbi decoder; channel estimation circuitry; an FFT processor; wherein the multicarrier receiver produces an output comprising demodulated video data; and 20 wherein the multicarrier receiver is implemented in a single chip.

The present invention also provides a receiver for receiving modulated *.0 symbols that have an active interval and a guard interval separated by a boundary, the receiver having a guard interval detector comprising: a measurement block; a delay block, the delay being approximately equal to the active interval; a subtractor generating a difference sample corresponding to the difference in measured signal strength between a first symbol and a second delayed symbol; a storage block storing N difference samples; a processing block applying a mathematical operation to the stored N 3,0 difference samples.

P:\OPERf)BW147-98 psm.dc-19OctobCF, 2000 7 The present invention also provides a method of processing a modulated multicarrier signal comprising: receiving digitized data representing modulated multicarrier symbols comprising an active interval and a guard interval; passing the received data through an I/Q demodulator; synchronising an FFT window to the active interval; performing an FFT on the active interval; estimating the channel characteristics; producing an output comprising unmodulated digitized video data corresponding to the received modulated multicarrier signal; and wherein the passing, synchronising, performing, applying, estimating, and producing are performed within a single chip.

The present invention also provides a method for synchronizing an FFT Si window to a modulated multicarrier signal having symbols comprising: 15 choosing a pair of blocks of symbols; measuring a characteristic of a first symbol of a first block of the pair; measuring a characteristic of a first symbol of a second block of the pair; determining the difference between the first symbol of the first block and the first symbol of the second block; 20 repeating the measuring steps and the determination step for successive ooe..i symbols in each block; and applying a statistical test to the determined differences between the first S"and second blocks.

The present invention also provides a method for synchronizing an FFT window to a modulated multicarrier signal having symbols comprising: receiving a digital signal corresponding to the multicarrier signal; producing a delayed signal by delaying the received signal by L symbols; determining the difference between the delayed signal and the received signal and producing a difference signal; delaying the difference signal by N symbols; .,inputting the difference signal and the delayed difference signal into an P:kOPER\lBWVS1471-98 spwci.do-19 Octobc. 8 adder/subtractor; delaying the output of the adder/subtractor; feeding back the delayed output of the adder/subtractor as an additional input into the adder/subtractor.

The present invention also provides a method for synchronizing an FFT window to a modulated multicarrier signal having symbols comprising: receiving a digital signal corresponding to the multicarrier signal; delaying the digital signal producing a delayed; correlating the delayed signal to the received signal; accessing data in a lookup table stored in memory as a function of the correlating.

The present invention also provides a method for synchronizing an FFT window to a modulated multicarrier signal having symbols comprising: receiving a digital signal corresponding to the multicarrier signal; 15 measuring the signal to noise ratio of the digital signal; choosing a synchronization technique of a plurality of synchronization techniques as a function of the measured signal to noise ratio.

A preferred embodiment of the present invention is hereinafter described, with reference to the following drawings, wherein: 20 Fig. 1 illustrates the spectrum of a COFDM subchannel; Fig. 2 shows a frequency spectrum for multiple carriers in a COFDM signal; Fig. 3. is a diagram of a signal according to COFDM and shows a data symbol format; Fig. 4 is a block diagram illustrating an FFT based COFDM system; Fig. 5 illustrates certain perturbations in a COFDM signal constellation; Fig. 6 is a flow diagram of a method of timing synchronization according to a preferred embodiment of the invention.

(The next page is page 11) WO 98/19410 PCT/US97/18911 11 Fig. 7 is a plot of an F ratio test performed on several data symbols for coarse timing synchronization; Fig. 8 is a plot of an incomplete beta function for different degrees of freedom; Fig. 9 is a plot helpful in understanding a test of statistical significance according to the invention; Fig. 10 is an electrical schematic of a synchronization circuit according to an alternate embodiment of the invention; Fig. 11 is an electrical schematic of a synchronization circuit according to another alternate embodiment of the invention; Fig. 12 is a block diagram of a single-chip embodiment of a digital receiver in accordance with the invention; Fig. 13 is a block diagram illustrating the front end of the digital receiver shown in Fig. 12 in further detail; Fig. 14 is a block diagram illustrating the FFT circuitry, channel estimation and correction circuitry of the digital receiver shown in Fig. 12; Fig. 15 is a block diagram illustrating another portion of the digital receiver shown in Fig. 12; Fig. 16 is a more detailed block diagram of the channel estimation and correction circuitry shown in Fig. 14; Fig. 17 is a schematic of the automatic gain control circuitry of the digital receiver shown in Fig. 12; Fig. 18 is a schematic of the I/Q demodulator of the digital receiver shown in Fig.

12; Fig. 19 illustrates in greater detail a low pass filter shown in Fig. 13; Fig. 20 shows the response of the low pass filter shown in Fig. 19, Fig. 21 shows the resampling circuitry of the digital receiver shown in Fig. 12; Fig. 22 illustrates a portion of an interpolator in the resampling circuitry of Fig. 21; Fig. 23 is a more detailed block diagram of the FFT window circuitry shown in Fig.

14; Fig. 24 is a schematic of a butterfly unit in the FFT calculation circuitry shown in Fig.14; Figs. 25 and 26 are schematics of butterfly units in accordance with the prior art; Fig. 27 is a schematic of a radix 22 2 FFT processor in accordance with the invention; Fig. 28 is 32 point flow graph of the FFT processor shown in Fig. 27; Fig. 29 is a schematic of a configurable 2K/8K radix 22+2 single path, -delay feedback pipelined FFT-processor in accordance with the invention; WO 98/19410 PCTIS97/18911 12 Fig. 30 is a detailed schematic of a complex multiplier used in the circuitry shown in Fig. 29; Fig. 31 is a detailed schematicof an alternate embodiment of a complex multipliers used in the circuitry shown in Fig. 29; Fig. 32 is another diagram illustrating the organization of the twiddle factors for each of the multipliers in the circuitry shown in Fig. 29; Fig. 33 illustrates the organization of the twiddle factors for each of the multipliers in the circuitry shown in Fig. 29; Fig. 34 is a schematic of address generator used in the circuitry shown in Fig. 29; Fig. 35 is a schematic of a generalization of the address generator shown in Fig.

34; Fig. 36 is a flow chart illustrating the process of pilot location conducted by the channel estimation and correction circuitry shown in Fig. 16; Fig. 37 is a flow chart of an embodiment of the pilot localization procedure according to the invention.

Fig. 38 is a more detailed block diagram of the tps sequence block of the circuitry shown in Fig. 14; Fig. 39 is a schematic of a BCH decoder used in the tps processing circuitry shown in Fig. 38; Fig. 40 is a more detailed schematic of a Galois field multiplier shown in Fig. 39; Fig. 41 is a block diagram generically illustrating the automatic sampling control and automatic frequency control loops of the digital receiver shown in Fig. 12; Fig. 42 is a more detailed block diagram of the automatic sampling control and automatic frequency control loops shown in Fig. 41 Fig. 43 is a more detailed block diagram of the phase extract block of the circuitry shown in Fig. 42; Fig. 44 is a schematic of thecircuitry employed to calculate an arctangent in the block diagram shown in Fig. 43; Fig. 45 is a plot of the square error at different values of ca of the Taylor expansion to 32 terms; Fig. 46 is a plot of the square error at different values of c of the Taylor expansion to 31 terms; Fig. 47 is a plot of the square error at different values of a of the average of the Taylor expansion to 31 and 32 terms; Fig. 48 is a plot of the phase differences of pilot carriers with a line of best fit shown; WO 98/19410 PCT/US97/18911 13 Fig. 49 is a more detailed block diagram an alternate embodiment of the automatic sampling control and automatic frequency control loops shown in Fig. 41; Fig. 50 illustrates a coded constellation format used in the demapping circuitry of Fig. Fig. 51 illustratesthe conversion of I,Q data to binary data value using the format shown in Fig. Fig. 52 is a more detailed block diagram of the symbol deinterleaving circuitry shown in Fig. Fig. 53 is a more detailed block diagram of the bit deinterleaving circuitry shown in Fig. Fig. 54 illustrates the conversion from a coded constellation format to a 24 bit soft I/Q format by the bit deinterleaving circuitry shown in Fig. 53; Fig. 55 is a more detailed block diagram of the microprocessor interface of the receiver shown in Fig. 12; Fig. 56 is a more detailed block diagram of the system controller of the receiver shown in Fig. 12; and Fig. 57 is a state diagram relating to channel acquisition in the system controller of the receiver shown in Fig. 56.

Alignment of The FFT Window Referring again to Figs. 3 and 4, according to the invention a statistical method is applied to COFDM signals to find the end of the guard interval 10. This method is explained with reference to the above noted European Telecommunications Standard, but is applicable to many forms of frequency division multiplexing having prefixed or postfixed guard intervals. It allows the receiver 32 to find the end of the guard interval given only the received sampled complex signal (solid line 12) and the size of the active interval 6. The method relies on the fact that the guard interval 10 is a copy of the last part of the data symbol 4. In the receiver 32, due to echoes and noise from the channel and errors in the local oscillator, the guard interval 10 and the last part of the data symbol 4 will differ. If the errors introduced are random then a statistical method can be applied. According to the invention, the received complex signal is sampled at a rate which is nearly identical to that used in the transmitter. A difference signal is found for a pair of received samples which are separated by a period of time which is as close as possible to the active interval 6. This period should be equal to the size of the fast fourier transform being applied 2048 or 8192 samples). Let I 0i S i i i-fftsize 114l WO 98/19410 PCT/US97/18911 14 where Si is the difference signal; and §-fftsize are the current and previous complex input samples of which the modulus is taken. That is, the subscript indexes a linear time sequence of input values. Assuming that the input signal is random, then S i is also random. Within the guard interval s i and si-ffsizewill be similar, although not identical, due to the effects of the channel. Sj will be therefore a random signal with a small dispersion.

As used herein the term "dispersion" means generally the spread of values, and is not restricted to a particular mathematical definition. In general the active part of one symbol is not related to the active part of the next symbol. Outside of the guard interval S i will be random with a much larger dispersion. In order to find the end of the guard interval, the dispersion of the difference signal Si is monitored to look for a significant increase which will occur at the boundary of the guard interval 10 and the active interval 6. The inventors have also observed that a large decrease in dispersion is seen at the start of the guard interval According to a preferred embodiment of the invention samples of the input signal are stored over an interval which includes at least one symbol period T s The dispersion of the difference signal S i is calculated over a block of samples. The block is moved back in time over a number of samples, n, and the dispersion is recalculated. These two blocks are referred to herein as "comparison blocks". The ratio of a current dispersion in a first comparison block to the dispersion in a previous comparison block is found.

Then, the F ratio significance test is used to find significant differences in the dispersions of the two comparison blocks. The F ratio is defined as VAR(i) VAR(i-n) where n is a positive integer, i indexes the input samples, and VAR(i) is the variance of a block of values of length N samples. Variance can be defined as VAR(i) (Si_j 1 S ij (16) N jo Nj=o While the F ratio significance test is used in the preferred embodiment, other functions of the two dispersion values which give a signal relating to the change in dispersion could be used. There are many such functions. An advantage of the F ratio is that for a random input signal it has a known probability distribution, allowing convenient statistical analysis for purposes of performance analysis and system design. Also the F ratio intrinsically normalizes the signal, making the result independent of the signal level.

WO 98/19410 PCT/US97/18911 The method is disclosed with reference to Fig. 6, in which a first member of a sample pair in a current evaluation block is measured at step 38. A delay of one active interval 6 Fig. 3) is experienced in step 40. This may be accomplished with a digital delay such as a FIFO, or equivalently by buffering samples for an active interval in a memory and accessing appropriate cells of the memory. A second member of the sample pair is measured in step 42, and the difference between the first and second member is determined and stored in step 44. The end of the current block is tested at decision step 46. The size of the evaluation block should not exceed the length of a guard interval, and may be considerably smaller. In the event the end of the current block has not yet been reached, another sample is acquired at step 48, and control returns to step 38.

If the end of the current block has been reached, the dispersion of the current block is measured in step 50, and is treated as one of two comparison blocks of data.

A test is made at decision step 52 to determine if a group of two comparison blocks have been evaluated. If this test is negative, then another block of data is acquired in step 54, after which control returns to step 38. The other block of data need not be contiguous with the block just completed.

In the event the test at.decision step 52 is positive, the F ratio is computed for the group of two comparison blocks at step 56. The results obtained in step 56 are submitted to peak detection in step 60. Peak detection optionally includes statistical tests of significance, as is explained hereinbelow.

If peaks are detected, then the boundary of a guard interval is established in step 62 for purposes of synchronization of the FFT window which is necessary for further signal reconstruction. If peaks are not detected, the above process is repeated with a block of samples taken from another portion of the data stream.

Example 1: Referring now to Fig. 7 a complex signal was generated according to the above noted European Telecommunicationsstandard using a random number generator, and transmitted across a Ricean channel model together with added white Gaussian noise (SNR Data symbols were then analyzed according to the above described method. The results 6 data symbols are shown in Fig. 7, wherein the F ratio is plotted for convenience of presentation on a logarithmic axis as line 64, because the spikes 66, 68, at the beginning and end of the guard intervals respectively, are very large.

Although it is quite evident from Figure 7 that the ends of the guard intervals are easy to find using any of several well known peak detectors, it is possible to apply a statistical test to more accurately answer the question: do the two blocks of samples have the same dispersion? This is the null hypothesis, H 0 i.e. the dispersion is the WO 98/19410 PCT/US97/18911 16 same and the observed spike in F is due to random fluctuations only. If H 0 has very low probability it can be rejected, which would correspond to detection of the start or end of the guard interval. From the way the COFDM symbol is-constructed H 0 is expected to be true for comparison blocks lying entirely within the guard interval or within the active interval, but false when the comparison blocks straddle a boundary at the start or end of the guard interval. If comparison blocks of random samples are drawn from the same population then the probability of F is given by Q(F V 1 ,v 2

=I,(V

v 2 (17) 2 2 where 10 is the incomplete Beta function,

V

2 x V 2 (18)

V

2 VlF and v 1 and v 2 are the number of degrees of freedom with which the first and second dispersions are estimated. In this example v1 v2 if n N. The shape of the function is shown in Fig. 8. From a statistical point of view n should be sufficiently large so that the two blocks do not overlap, i.e. n N. If the blocks do overlap, then the calculation of the second dispersion will use samples used for the calculation of the first dispersion. This effectively reduces the number of degrees of freedom and hence the significance of the result. It has been determined that setting n=N works well.

The function Q0 in equation (13) actually gives the one-tailed probability. H 0 could be rejected if F is either very large or very small, and so the two-tailed test is required.

Actually the two tails are identical, so for a two-tailed test the probability is double that given in equation However, this results in values of probability greater than one for F<1. The probability, p, is therefore calculated as follows: V V 2 v (19) 2 2 and then, if (p p 2 p. This probability reflects the viability of H 0 Thus if p is small, H 0 can be rejected and it can be stated, with a specified degree of certainty, that the comparison blocks come from sample populations with different dispersion. The noted European Telecommunications Standard specification states that the block size, N, should be 32 for a correlation algorithm. N={32,64} have been successfully tried. The probability functions obtained are shown in Fig. 9 using these values for N. In the preferred embodiment p 0.05 has been set for the rejection of H o WO 98/19410 PCT/US97/18911 17 A precise implementation would be to calculate F, then x, then the incomplete Beta function, then p and then apply the threshold test. This algorithm would be very difficult to realize in hardware since the Beta function is very complicated. In the preferred embodiment it is much simpler, and gives the same results, to set the acceptance threshold and N parameter, and thus define an upper and lower limit for F. It is then only necessary to calculate F and compare it with the limits. In order to simply find the end of the guard interval it may be safely assumed that F>1. Only the upper limit on F is needed. To calculate the limits on F accurately, a suitable root-finding method, such as Newton-Raphson may be utilized. Typical values are given in Table 1.

Table 1 p threshold v1 v2 31 vl v2 63 F lower F_upper F lower F_upper 0.2 0.627419 1.593832 0.722591 1.383909 0.1 0.548808 1.822132 0.658620 1.518326 0.05 0.488143 2.048582 0.607525 1.646022 0.01 0.386894 2.584689 0.518205 1.929738 0.005 0.354055 2.824422 0.487936 2.049448 0.001 0.293234 3.410251 0.429794 2.326695 4 4.337235 10- 5 5.393528 6 6.605896 7 8.002969 8 9.616664 This method has been successfully tested using the specified channel model with additive white Gaussian noise (SNR=3.7).

The formula for dispersion given in Equation (12) would require a multiplier for implementation in silicon. The calculation of F is a division in which the (N-1) normalisation constants cancel out as long as the two blocks have the same size.

Accurate multiplication and division can be expensive in silicon. In the preferred embodiment simplifications have been implemented which give less accurate, but still viable, values for F. Si can be assumed to have zero mean so it is not necessary to calculate the mean from the block of samples. This also increases the number of degrees of freedom from to N. Instead of calculating variance using the standard WO 98/19410 PCT/US97/18911 18 sum of squares formula, the dispersion can be estimated by the mean absolute deviation. The formula for VAR(i) becomes N-1 2 IS N j=o The factor divides out in the calculation of F if the two blocks have the same size.

But there still remains the division of the two dispersions and the squaring required.

These can be tackled using logarithms to the base 2. Substituting from Equation (16) into Equation (11) gives N-1 F= j- o a (21) N-1 Sb E ISi-n-j Taking logs to the base 2 gives log F 2 (log s log s b y (22) It is then only necessary to calculate y and compare it with the logarithm to the base 2 of the F upper limit. The comparison can be made by subtracting the log of the limit from 2(log2sa-log2sb) and comparing with zero. The factor of 2 can be absorbed into the limit.

Calculation of the logs to base two is relatively straightforward in hardware if the numbers are stored as fixed point fractions. The fractions can be split into an exponent and a fractional mantissa: x A2

B

Taking log base 2 gives logx logA B. Since A is fractional it is practical to find its logarithm using a lookup table. The exponent B can be found from the position of the MSB (since s a and s b will both be positive numbers).

The calculation can thus be reduced to require only addition and subtraction arithmetic operations. The limit should also be recalculated using v1=v2=N if using this method. In practice, the significance level may be set empirically for a particular application, preferably p 0.05.

It will be appreciated by those skilled in the art that various measures of dispersion may be utilized without departing from the spirit of the invention, for example the WO 98/19410 PCT/US97/18911 19 standard deviation, skew, various moments, histograms, and other calculations known in the art.

In a first alternate embodiment of the invention, the above described method is employed using either the real or the imaginary parts of the signal instead of the modulus. This embodiment achieves economy in hardware.

In a second alternate embodiment of the invention, the n parameter of equation (11) has been optimized. At the end of the guard interval, the two blocks straddle more of the transition to the active interval, giving a well-defined increase in the dispersion.

Using any value n>2 has the drawback that several successive points will give significant increases as the later block travels up to the boundary. This small problem is easily overcome by introducing a dead period after detection of the boundary. That is, once a spike has been detected a set of samples equal to the size of the FFT window is accepted before further attempts are made to locate another spike. The dead period has the added benefit of not introducing false spikes. When using larger values of n the spikes 66, 68 Fig. 7) increase, whilst the H 0 noisy F signal remain much the same.

Example 2: The maximum F-spike height as a function of n has been measured systematically together with the background variation in F. The results are shown in Table 2.

Table 2 n F.d Fm 3 1.0009 0.07 7.5 107 1.0012 0.10 10.7 107 10 1.0011 0.14 12.9 92 1.0014 0.17 16.7 98 1.0014 0.19 19.3 102 1.0012 0.23 20.9 91 0.9975 0.24 22.0 92 50 0.9926 0.25 20.4 81.6 Table 2 was developed using the first 5 frames of the signal analyzed in Fig. 7.

The statistics in columns and of Table 2 were made by excluding any points where F>=3.0 to exclude spikes from the calculations. The spikes would otherwise affect the values of mean and standard deviation even though they are from a different statistical population.

WO 98/19410 PCT/US97/18911 The results indicate that the background variation in F, Fs.d was affected by n, increasing asymptotically to a value of approximately 0.28. It is likely that this is the effect of overlapping blocks. For example, for N=64 and n<64, the blocks over which the dispersions are calculated will contain some of the same values and therefore be correlated. To test this theory Fs.d. was evaluated for n>N, and the results are shown in Table 3.

Table 3 n I Fsd.

0.258 70 0.266 0.270 0.278 100 0.285 128 0.297 256 0.366 The dependence becomes linear at n N12. If F is calculated every n samples, rather than every sample, then this dependence may be reduced. However, this creates a risk for small guard intervals of not having the first block wholly within the guard interval and the second wholly within the active interval.

A third alternate embodiment of the invention is disclosed with reference to Fig. which schematically illustrates a timing synchronization circuit 70. The circuit accepts a complex input signal 72, and includes a circuit module 74 which develops the modulus of its input, which is taken from node 83. The circuit module 74 insures that the value being subsequently processed is an unsigned number. The input to the circuit module 74 is a difference signal which is developed by a subtracter75 which takes as inputs the input signal 72 and a delayed version of the input signal 72 which has been processed through a delay circuit 79, preferably realized as a FIFO 77 of length L, where L is the size of the FFT window. As explained above, it is also possible to operate this circuit where the input signal 72 is real, imaginary, or complex, or even the modulus of a complex number. In the case where the input signal 72 is real, or imaginary, the circuit module 74 can be modified, and can be any known circuit that removes the sign of the output of the subtracter75, or equivalently sets the sign so that the outputs accumulate monotonically; i.e. the circuit has a unipolar output. The output of the circuit module 74 is ultimately clocked into a digital delay, which is preferably implemented as a FIFO 78.

When the FIFO 78 is full, a signal SIG1 80 is asserted, and the output of the FIFO 78 WO 98/19410 PCT/US97/18911 21 becomes available, as indicated by the AND gate 82. An adder/subtracter circuit 84 is also connected to the node 76, and its output is stored in a register 86. A delayed version of the output of the adder/subtractercircuit 84 is taken from the register 86 and fed back as a second input to the adder/subtractercircuit 84 on line 88. In the event the signal SIG1 80 has been asserted, a version of the output of the circuit module 74, delayed by a first predetermined interval N, where N is the number of samples in the comparison blocks, is subtracted from the signal on node 76.

The signal on line 88 is an index into a lookup table, preferably implemented as a read-only-memory and shown as ROM 90. The address of the ROM contains the logarithm to the base 2 of the magnitude of the signal on line 88, which then appears at node 92. The node 92 is connected to a subtracter 94, and to a delay circuit, shown as FIFO 98, which is used to develop the denominatorof the middle term of equation (17).

The subtracter 94 produces a signal which is compared against the log 2 of a predetermined threshold value FLIMIT in a comparison circuit 106, shown for simplicity as an adder 108 connected to a comparator 110. The output signal SYNC 112 is asserted when the boundary of a guard interval has been located.

Although not implemented in the presently preferred embodiment, It is also possible to configure the size of the FIFO 77 dynamically, so that the size of the interval being evaluated can be adjusted according to operating conditions. This may conveniently be done by storing the values on the node 92 in a RAM 114 for computation of their dispersion.

In a fourth alternate embodiment of the invention, explained with reference to Fig.

11, components similar to those of the embodiment shown in Fig. 10 have the same reference numerals. A timing synchronization circuit 116 is similar to the timing synchronization circuit 70, except now the delay circuit 79 is realized as the FIFO 77, and another FIFO 100, one of which is selected by a multiplexer 102. Both of the FIFOs 77, 100 provide the same delay; however the capacities of the two are different. The FIFO 100 provides for storage of samples taken in an interval equal to the size of the FFT window, and is normally selected in a first mode of operation, for example during channel acquisition, when it is necessary to evaluate an entire symbol in order to locate a boundary of a guard interval. In the noted European Telecommunications standard, up to 8K of data storage is required, with commensurate resource requirements. During subsequent operation, the approximate location of the guard interval boundaries will be known from the history of the previous symbols. In a second mode of operation, It is therefore only necessary to evaluate a much smaller interval in order to verify the exact location of the guard interval boundary. The number of samples used in the computation WO 98/19410 PCT/US97/18911 22 of the dispersion can be kept to a small number, preferably 32 or 64, and the much smaller FIFO 77 accordingly selected to hold the computed values. The resources saved thereby can be utilized for other functions in the demodulator, and memory utilized by the larger FIFO 100 may also be reallocated for other purposes.

A control block 81 optionally advances the evaluation interval relative to symbol boundaries in the data stream in successive symbols, and can also be used to delay for the dead period. Eventually the moving evaluation interval straddles the boundary of the current symbol's guard interval, and synchronization is then determined. The size of the evaluation interval is chosen to minimize the use of memory, yet to be large enough to achieve statistical significance in the evaluation interval. The size of the evaluation interval, and the FIFO 77 may be statically or dynamically configured.

Single Chip Implementation of a COFDM Demodulator Overview Referring initially to Fig. 12, there is shown a high level block diagram of a multicarrier digital receiver 126 in accordance with the invention. The embodiment described hereinbelow conforms to the ETS 300 744 telecommunications standard (2K mode), but can be adapted by those skilled in the art to operate with other standards without departing from the spirit of the invention. A radio frequency signal is received from a channel such as an antenna 128, into a tuner 130, which is conventional, and preferably has first and second intermediate frequency amplifiers. The output of the second intermediate frequency amplifier (not shown), is conducted on line 132 to an analog to digital converter 134. The digitized output of the analog to digital converter 134 is provided to block 136 in which I/Q demodulation, FFT, channel estimation and correction, inner and outer deinterleaving, and forward error correction are conducted.

Carrier and timing recovery are performed in block 136 entirely in the digital domain, and the only feedback to the tuner 130 is the automatic gain control signal which is provided on line 138. A steady 20 MHz clock on line 140 is provided for use as a sampling clock for the external analog to digital converter 134. A host microprocessor interface 142 can be either parallel or serial. The system has been arranged to operate with a minimum of host processor support. In particular channel acquisition can be achieved without any host processor intervention.

The functions performed within the block 136 are grouped for convenience of presentation into a front end (Fig. 13), FFT and channel correction group (Fig. 14), and a back end (Fig. As shown in Fig. 13, I/Q samples at are received by an IQ demodulator 144 from the analog to digital converter 134 (Fig. 12) on a bus 146 at a rate of 20 megasamples per second. An AGC circuit 148 also takes its input from the bus 146. A frequency rate WO 98/19410 PCTIUJS97/18911 23 control loop is implemented using a numerically controlled oscillator 150, which receives frequency error signals on line 152, and frequency error update information on line 154.

Frequency and sampling rate control are achieved in the frequency domain, based on the pilot carrier information. The frequency error signals, which are derived from the pilot carriers, and the frequency error update information will both be disclosed in further detail shortly. The I and Q data output from the IQ demodulator 144 are both passed through identical low pass filters 156, decimated to 10 megasamples per second, and provided to a sinc interpolator 158. Sample rate control is achieved using a numerically controlled oscillator 160 which receives sample rate control information derived from the pilot signals on line 162, and receives sample error update timing information on line 164.

As shown in Fig. 14, acquisition and control of the FFT window are performed in block 166, which receives signals from the sinc interpolator 158 (Fig. 13). The FFT, computations are performed in FFT calculation circuitry 168. Channel estimation and correction are performed in channel estimation and correction block 170, and involves localization of the pilot carriers, as will be described below in greater detail. The tps information obtained during pilot localization is processed in tps sequence extract block 172. Uncorrected pilot carriers are provided by the circuitry of channel estimation and correction block 170 to correction circuitry 174, which develops sampling rate error and frequency error signals that are fed back to the numerically controlled oscillators 150, 160 (Fig. 13).

Referring to Fig. 15, corrected I and Q data output from channel estimation and correction block 170 are provided to demapping circuitry 176. The current constellation and hierarchical constellation parameters, derived from the tps data, are also input on lines 178, 180. The resulting symbols are deinterleaved in symbol deinterleaver 182, utilizing a 1512 x 13 memory store. One bit of each cell in the memory store is used to flag carriers having insufficient signal strength for reliable channel correction. Bit deinterleaver 184 then provides deinterleaved I and Q data to a Viterbi Decoder 186, which discards the flagged carriers, so that unreliable carriers do not influence traceback metrics. A Forney deinterleaver 188 accepts the output of the Viterbi Decoder 186 and is coupled to a Reed-Solomon decoder 190. The forward error correction provided by the Viterbi and Reed-Solomon decoders is relied upon to recover lost data in the case of flagged carriers.

Referring to Fig. 16, in the presently preferred embodiment a mean value is calculated in block 192 for uncorrected carriers with-reference to the previous symbol.

Data carriers whose interpolated channel response falls below some fraction, preferably 0.2, of this mean will be marked with a bad_carrier flag 194. The bad_carrier flag 194 WO 98/19410 PCT/US97/18911 24 is carried through the demapping circuitry 176, symbol deinterleaver 182, and bit deinterleaver 184, to the Viterbi Decoder 186 where it is used to discard data relating to the unreliable carriers. The parameters used to set the bad_carrier flag 194 can be varied by the microprocessor interface 142.

An output interface 196 produces an output which can be an MPEG-2 transport stream. The symbol deinterleaver 182, and the bit deinterleaver 184 are conventional.

The Viterbi decoder 186, Forney deinterleaver 188, Reed-Solomon decoder 190, and the output interface 196 are conventional. They can be the components disclosed in copending Application No. 638,273, entitled "An Error Detection and Correction System for a Stream of Encoded Data", filed April 26, 1996, Application No. 480,976, entitled "Signal Processing System", filed June 7, 1995, and Application No. 481,107, entitled "Signal Processing Apparatus and Method", filed June 7, 1995, all of which are commonly assigned herewith, and are incorporated herein by reference. The operation of the multicarrierdigital receiver 126 (Fig. 12) is controlled by a system controller 198.

Optionally the hierarchical constellation parameters can be programmed to speed up channel acquisition, rather than derived from the tps data.

The input and output signals and the register map of the multicarrier digital receiver 126 are described in tables 4, and 5 respectively.

Automatic Gain Control The purpose of the AGC circuit 148 (Fig. 13)is to generate a control signal to vary the gain of the COFDM input signal to the device before it is analog-to-digitalconverted.

As shown in greater detail in Fig. 17, a Sigma-Delta modulator 200 is used to provide a signal which can be used as a gain control to a tuner, once it has been low-pass filtered by an external R-C network.

The magnitude of the control voltage signal 202 is given by: control_voltage control_voltage error (23) where error K(Idatal mean) (24) where K is a constant (normally which determines the gain in the AGC control loop. The mean value can be determined from the statistics of Gaussian noise, which is a close approximation to the properties of the COFDM input signal, where the input data is scaled to The control voltage signal 202 is set back to its initial value when the signal resync 204 is set low, indicating a channel change or some other event requiring resynchronization.

The input and output signals and the registers for the microprocessorinterface 142 of the AGC circuit 148 are described in tables 6, 7, and 8 respectively.

WO 98/19410 PCT/US97/18911 IQ Demodulator The function of the IQ demodulator 144 (Fig. 13) is to recover in-phase and quadrature components of the received sampled data. It is shown in further detail in Fig.

18.

The numerically controlled oscillator 150 generates in-phase and quadrature sinusoids at a rate of (32/17) MHz, which are multiplied with data samples in multipliers 206. The address generator 208 advances the phase linearly. The frequency error input 210 increments or decrements the phase advance value. The samples are multiplied with the sinusoids in the multipliers 206using 10 bit x 10 bit multiply operations. In one embodiment the IQ demodulator 144 is operated at 20 MHZ and then retimed to in retiming block 212. In a preferred embodiment the IQ demodulator 144 is operated at 40MHz, in which case the retiming block 212 is omitted.

Sinusoids are generated by the address generator 208 on lines 214, 216. The phase value is employed as an address into a lookup table ROM 218. Only quarter cycles are stored in the lookup table ROM 218 to save area. Full cycles can be generated from the stored quarter cycles by manipulating the data from the ROM 218 and inverting the data in the case of negative cycles. Two values are read from the lookup table ROM 218 for every input sample a cosine and a sine, which differ in phase by 90 degrees.

The input and output signals of the IQ demodulator 144 are described in tables 9 and 10 respectively.

Low Pass Filter The purpose of the low pass filters 156 (Fig. 1 3) is to remove aliased frequencies after IQ demodulation frequencies above the 32/7 MHz second IF are suppressed by 40dB. I and Q data are filtered separately. The output data is decimated to megasamples per second ("Msps") because the filter removes any frequencies above 1/4 of the original 20 Msps sampling rate. The filter is constructed with approximately taps which are symmetrical about the center, allowing the filter structure to be optimized to reduce the number of multipliers 220. Fig. 19 is a block diagram of one of the low pass filters 156, the other being identical. Fig. 19 shows a representative symmetrical tap 222, and a center tap 224. The required filter response of the low pass filters 156 is shown in Fig. The input and output signals of the low pass filters 156 are described in tables 11 and 12 respectively.

Resampling Referring to Fig. 13, the purpose of resampling is to reduce the 10 Msps-data stream output from the low pass filters 156 down to a rate of (64/7) Msps, which is the WO 98/19410 PCT/US97/18911 26 nominal sample rate of the terrestrial digital video broadcasting modulator at the transmitter.

Resampling is accomplished in the sinc interpolator 158, and the numerically controlled oscillator 160. The latter generates a nominal 64/7 MHZ signal. The resampling circuitry is shown in further detail in Fig. 21. The numerically controlled oscillator 160 generates a valid pulse on line 226 and a signal 228 representing the interpolation distance for each 40MHz clock cycle in which a 64/7MHz sample should be produced. The interpolation distance is used to select the appropriate set of interpolating filter coefficients which are stored in coefficient ROMs 230. It should be noted that only the sinc interpolatorfor I data is illustrated in Fig. 21. The structures for Q data are identical.

Fig. 22 illustrates the generation of the interpolation distance and the valid pulse.

Nominally T s 1/10 Msps, and T 1/ (64/7) Msps. The sinc interpolation circuit disclosed in our noted Application No. 08/638,273 is suitable, with appropriate adjustment of the operating frequencies.

The input and output signals of the sinc interpolator 158 and the numerically controlled oscillator 160 are described in tables 13 and 14 respectively.

FFT Window As has been explained in detail above, the function of the FFT Window function is to locate the "active interval" of the COFDM symbol, as distinct from the "guard interval". This function is referred to herein for convenience as "FFT Window". In this embodiment the active interval contains the time domain representation of the 2048 carriers which will be recovered by the FFT itself.

The FFT window operates in two modes; Acquisition and Tracking. In Acquisition mode the entire incoming sample stream is searched for the guard interval/active interval boundary. This is indicated when the F-ratio reaches a peak, as discussed above. Once this boundary hasbeen located, window timing is triggered and the incoming sample stream is searched again for the next guard interval/active interval boundary. When this has been located the length of the guard interval is known and the expected position of the next guard/active boundary can be predicted. The FFT window function then switches to tracking mode.

This embodiment is similar to the fourth alternate embodiment discussed above in respect of the tracking mode. In tracking mode only a small section of the incoming sample stream around the point where the guard/active boundary is expected to be is searched. The position of the active interval drifts slightly in response to IF frequency and sampling rate offsets in the front-end before the FFT is calculated. This drift is WO 98/19410 PCT/US97/18911 27 tracked and FFT window timing corrected, the corrections being inserted only during the guard interval.

It will be appreciated by those skilled in the art that in a practical single chip implementation as is disclosed herein, memory is an expensive resource in terms of chip area, and therefore must be minimized. Referring to Fig. 23, during Acquisition mode the FFT calculation process is not active so hardware can be shared between the FFT Window and the FFT calculation, most notably a 1024x22 RAM 232 used as a FIFO by the FFT Window, and selected for receipt of FFT data on line 234 by a multiplexer 236. Once in Tracking mode the FFT calculation process is active so that other control loops to recover sampling rate and frequency which depend on FFT data pilots in the COFDM symbol) can initialize. Therefore tracking mode requires adedicated tracking FIFO 238, which is selected by a multiplexer 240.

The input and output signals, and signals relating to the microprocessor interface 142 of the FFT Window circuitry shown in Fig. 23 are described in tables 15, 16, and 17 respectively.

In one embodiment a threshold level, set from statistical considerations, is applied to the F-ratio signal (see Fig. 7) to detect the negative and positive spikes which occur at the start and end of the guard interval respectively. The distance between the spikes is used to estimate the guard interval size. Repeated detection of the positive spikes is used to confirm correct synchronization. However with this method under noisy conditions the F-ratio signal becomes noisy and the spikes are not always reliably detectable.

In another embodiment peak detection is used to find the spikes in the F-ratios.

It has been found that a fixed threshold is reliable only at or exceeding about a carrierto-noise ratio of 12 dB. Peak detection is generally more sensitive and more specific, with generally reliable operation generally at 6 7 dB. The maxima should occur at the end of the guard interval. The difference in time between the two maxima is checked against the possible guard interval sizes. With an allowance for noise, the difference in time indicates the most likely guard interval size and the maxima themselves provide a good indication of the start of the active part of the symbol.

Preferably this process is iterated for several symbols to confirm detection, and is expected to improve performance when the C/N ratio is low.

The data stream is passed to accumulators 242, 244, each holding 64 moduli.

Conversion to logarithms and subtraction of the logarithms is performed in block 246.

The peaks are detected in peak detector block 248. Averaging of the symbol peaks is performed in block 250.

WO 98/19410 PCT/US97/18911 28 In noisy conditions, the maxima may be due to noise giving possibly inaccurate indications of the guard interval length and the start of the active symbol. The general strategy to cope with this is to perform a limited number of retries.

Currently, calculation of the F-ratio is done "on thefly" i.e. only once at each point.

The variance estimates are calculated from 64 values only. Under noisy conditions, the variance estimates become very noisy and the spikes can become obscured. In an optional variation this problem is solved by obtaining more values for the variance estimate, by storing the varianceestimate during acquisition for each of the possible T+Gmax, points in the storage block 256. The variance estimates themselves may be formed by accumulating variances for each point, and then filtering in time over a number of symbols. A moving average filter or an infinite impulse response filter is suitable. A moving run of symbols, preferably between 16 and 32, are integrated in block 252, which increases the reliability of peak detection under noisy conditions. The storage block 256 holding the integrated F-ratio values is searched to find the maximum value. This is of length T+Gmax, where Gmax is the maximum guard interval size, T/4.

Preferably the memory for storage block 256 is dynamically allocated, depending on whether acquisition mode or tracking mode is operative. Any unused memory is released to other processes. Similarly in tracking mode the integrated data stream is stored in tracking integration buffer 254.

This method has been tested with up to 4 symbols, without an IIR filter, and it has been found that the spikes can be recovered. However this approach does require increased memory.

FFT Processor The discrete Fourier transform has the well known formula L-1 x(k) E x(n)Wnk k L n=o where N the number of points in the DFT; x(k) the kth output in the frequency domain; x(n) the nth input in the time domain and W Lnk e -j(2TrnkL) (26) W is also known as a "twiddle factor".

For N 1000 the DFT imposes a heavy computational burden and becomes impractical. Instead the continuous Fourier transform is used, given by WO 98/19410 PCT/US97/18911 29 t f x(t)e -j dt (27) The continuous Fourier transform, when computed according to the well known FFT algorithm, breaks the original N-point sequence into two shorter sequences. In the present invention the FFT is implemented using the basic butterfly unit 258 as shown in Fig. 24. The outputs C and D represent equations of the form C A B, and D (A

B)W

k The butterfly unit 258 exploits the fact that the powers of W are really just complex additions or subtractions.

A real-time FFT processor, realized as the FFT calculation circuitry 168 (Fig. 14) is a key component in the implementation of the multicarrier digital receiver 126 (Fig.

12). Known 8K pipeline FFT chips have been implemented with 1.5M transistors, requiring an area of 100 mm 2 in 0.5p technology, based on the architecture of Bi and Jones. Even using a memory implementation with 3-transistor digital delay line techniques, over 1M transistors are needed. This has been further reduced with alternative architecture to 0.6M, as reported in the document A New Approach to Pipeline FFT Processor. Shousheng He and Mats Torkelson, Teracom Svensk RundRadio. DTTV-SA 180, TM 1547. This document proposes a hardware-oriented radix-2 2 algorithm, having radix-4 multiplicative complexity. However the requirements of the FFT computation in the present invention require the implementation of a radix 22+2 FFT processor.

Referring to Fig. 25 and Fig. 26 the butterfly structures BF21 260 and BF211 262, known from the noted Torkelson publication, are shown. The butterfly structure BF211 262 differs from the butterfly structure BF21 260 in that it has logic 264 and has a crossover 266 for crossing the real and imaginary inputs to facilitate multiplication by -j.

Fig. 27 illustrates the retimed architecture of a radix 22 2 FFT processor 268 in accordance with the invention, which is fully pipelined, and comprises a plurality of stages, stage-0 270 through stage-6 272. Except for stage-0 270, the stages each comprise one butterfly structure BF2I 260 and one butterfly structure BF211 262, and storage RAMS 274, 276 associated therewith, stage-0 270 only has a single butterfly structure BF21 260. This architecture performs a straight-forward 32-point FFT. stage-6 272 has control logic associated therewith, including demultiplexer 278 and multiplexer 280, allowing stage-6 272 to be bypassed, thus providing a 2K implementation of the FFT. Counters 282 configure the butterfly structures BF2I 260 and BF2II 262 to select one of the two possible diagonal computations, during which data is being simultaneously written to and read from the storage RAMS 274, 276.

WO 98/19410 PCTI/US97/18911 Fig. 28 illustrates a 32 point flow graph of the FFT processor 268 using radix 22+2 pipeline architecture. Computations are performed using eight 4-point FFTs and four 8point FFTs. These are decomposed in turn into two 4-point FFTs and four 2-point FFTs.

Fig. 29 illustrates the retimed architecture of a configurable 2K/8K radix 22+2 single path, delay feedback pipelined FFT processor 284, in which like elements in Fig.

27 are given the same reference numerals. The stages have a plurality of pipeline registers 286 which are required for proper timing of the butterfly structures BF21 260 and BF211 262 in the various stages. As can be seen, the addition of each pipelined stage multiplies the range of the FFT by a factor of 4. There are 6 complex multipliers 288, 290, 292, 294, 296, 298 which operate in parallel. This processor computes one pair of I/Q data points every four fast clock cycles, which is equivalentto the sample rate clock. Using 0.35pm technology the worst case throughput is 140ps for the 2K mode of operation, and 550ps for the 8K mode, exceeding the requirements of the ETS 300 744 telecommunicationsstandard. Data enters the pipeline from the left side of Fig. 29, and emerges on the right. The intermediate storage requirements are 2K/8K for I data and 2K/8K for Q data, and is mode dependent. In practice the radix-4 stage is implemented as a cascade of two adapted radix-2 stages that exploit the radix-4 algorithms to reduce the number of required complex multipliers.

Fig. 30 is a schematic of one embodiment of the multipliers 288, 290, 292, 294, 296, 298 for performing the complex multiplication C A x B, where A is data, and B is a coefficient. Because the FFT processor 284 has 6 complex multipliers, each requiring 3 hardware multipliers 300, a total of 18 hardware multipliers 300 would be required. It is preferable to use the embodiment of Fig. 31 in which some of the hardware multipliers 300 are replaced by multiplexers 302, 304.

Turning again to Fig. 29 there are a plurality of RAMS 306, 308, 310, 312, 314, 316 which are preferably realized as ROMs and contain lookup tables containing complex coefficients comprising cosines for the multipliers 288, 290,292, 294, 296, 298 respectively. It has been discovered that by addressing the RAMS 306, 308, 310, 312, 314, 316 according to a particular addressing scheme, the size of these RAMS can be markedly reduced. The tradeoff between the complexity of the addressing circuitry and the reduction in RAM size becomes favorable beginning at stage-3 318. Referring again to Fig. 28 there are two columns 320, 322. Column 320 holds values W 2

W

14 followed by W 1

W

7 and then W 3

W

21 These coefficients are stored in the RAM 308, required by the particular multiplier 290. Column 322 contains values W 8

W

4

W

1 2 which repeat 3 times. Note furtherthat between the values W 8

W

4 and W 4

W

12 are connections 324, 326 to the preceding butterfly unit located in column 328. In practice the connections 324, 326 are implemented as multiplications by In moving from multiplier to WO 98/19410 PCT/US97/18911 31 multipliertoward the left in Fig. 29, the lookup table space is multiplied by a power of 4 at each stage. In Fig. 32 table 330, the lookup table for multiplier M 3 contains 512 entries. It can be deduced by extrapolation that multiplier M 5 must contain 8192 twiddle factors, and corresponds to the size of the FFT being performed by the FFT processor 284 (Fig. 29).

Before examining the look-up table space in more detail it is helpful to considerthe plurality of horizontal lines 332. Moving downward from the top of Fig. 28, the line beginning at x(3) extends to W 8 which is the first twiddle factor required, and is at the third effective step in the flow diagram. Figs. 33 and 32 show the organization of the twiddle factors for each of the multipliers, wherein the terminology Mk represents the multiplier associated with the kth stage. Thus table 334 relates to multiplier M 0 The notation for the W values (twiddle factors) is shown in box 336. The subscript at the bottom right represents a time stamp, that is an order dependency in which the twiddle factors are required by the pipeline. The superscript represents the address of the twiddle factor in its lookup table. The superscript is the index of the twiddle factor.

Thus in table 334 it may be seen that WO is required at time 0, W 1 at time 1, and WO is again required at time 2. Further inspection of the other tables in Figs. 33, 32 reveals that half of the entries in each table are redundant. The storage requirementfor the lookup tables can be decreased by 50% by eliminating redundant entries. This has been accomplished by organizing the W values in ascending order by index, so that the values can be stored in memory in ascending order. Thus in the case of table 338 the index values range from 0 to 21, with gaps at 11, 13, 16, 17, 19, and The procedure for organizing the lookup table and the addressing scheme for accessing the twiddle factors is explained with reference to table 338, but is applicable to the other tables in Fig. 33. Each row is assigned a line number as illustrated. (2) Each twiddle factor is assigned an order dependency which is noted in the lower right of its respective cell in table 338. It is assumed that table 338 in its reduced form will contain only unique twiddle factors in ascending order by index within the memory address space. Consequently-each twiddle factor is assigned a memory address as shown in the upper left of its respective cell.

During address generation, for line 3 of table 338 the address is simply held at 0.

For line 1 the address is incremented by 1 to the end of the line. However lines 0 and 2 contain non-trivial address sequences. For line 0, looking at table 340, which contains 64 values, it will be observed that the address sequence changes according to the intervals 2,2,2,2, and then later For line 2, the address first increments by 3, then by 2, and finally by 1. The locations at which the address increments change are WO 98/19410 PCTIUS97/18911 32 referred to herein as the "break-points".These values of the break points range between 0, corresponding to the first point in line 2, to the last position in the line.

By inspection it can be seen that the occurrence of the first break point changes from table to table following the recurrence relationship B1MN 4B1MN (28) with the initial condition B 1 (29) where MN is the multiplier of the Nth stage of the FFT processor 284.

Expanding the recurrence relationship gives: BlM, 4 B1M -1)x4-1)x4 B1N 4NB1 -3 4 3 -4 N 2 -40 (31) N-1 B1 M 4NB1M 4n (32) n=0 Similarly the second break point B2 for line 2 is determined from the recurrence relation B2N 4B2MN +1 (33) with the initial condition 2B25 1 (34) or

B

2 N 4

B

2 M+1)x 4 +1)x 4

N

B

2 M 4 n (36) n=O Break point B3 for line 0 at which the sequence changes from increments of 2,2,2,2 to the pattern can be located by inspecting tables 338, 340, and 330. In table 338 the break point B3 occurs very late in the line, such that the second sequence only presents its first two elements. By examining the address locations in the larger noted tables, it can be deduced that the location of break point B3 is related to the number of entries in a particular table as WO 98/19410 PCT/US97/18911 33

K

B3 +2 (37) 4 where K is the number of table entries. In the tables in Fig. 29 K 8, 32, 128, 2048, 8192. Therefore, in terms of the N'th complex multiplier, break point B3 can be expressed as 83, 2 x 4N 2 (38) where N 2 0.

Address generators 342, 344, 346, 348 are operative for the lookup tables in RAMS 310, 312, 314, 316. Silicon area savings for the smaller tables 308, 306 are too small to make this scheme worthwhile.

Fig. 34 schematically illustrates an address generator 342 for the above described address generation scheme, and is specific for the table 340 and multiplier M 2 128 possible input states are accepted in lines inAddr 350, and a multiplexer 352 selects the two most significant bits to decode 1 of 4 values. The output of the multiplexer 352 relates to the line number of the input state. Actually the output is the address increment applicable to the line number of the input state, and is used to control a counter 354 whose incremental address changes according to value on line 356. Thus, the increment for line 3 of table 340 is provided to the multiplexer 352 on line 358, and has a value of zero, as was explained above. Similarly the increment for line 1 of table 340 is provided to the multiplexer 352 on line 360, and has a value of 1.

The situations of line 0 and line 2 are more complicated. For line 0 the output of decoding logic 362 is provided by multiplexer 364, and has either an incremental value of 2, or the output of multiplexer 366. The latter could be either 1 or 2, depending on the state of a two bit counter 368, which feeds back a value of 0 or 1 as signal count 370.

Decoding logic 372 decodesthe states for line 2 of table 340. The relationship of the current input state to the two break points of line 2 are tested by comparators 374, 376. The break point is actually set one sample earlier than the comparator output to allow for retiming. The outputs of the comparators 374, 376 are selectors for the multiplexers 378, 380 respectively.

The current address, held in accumulator 382 is incremented by the output of the multiplexer 352 by the adder 384. A simple logic circuit 386 resets the outgoing address, which is contained in register ACC 388, by asserting the signal rst 390 upon completion of each line of table 340. This insures that at the start of the next line the address points to twiddle factor W. The new address is output on the 6 bit bus out_Address 392, which is one bit smaller than the input in_Addr 350.

WO 98/19410 PCT/US97/18911 34 Fig. 35 is a generalization of address generator 342 (Fig. 34), in which the incoming address has a path of B bits. Like elements in Figs. 34 and 35 are given the same reference numerals. The structure of address generator 394 is similar to that of the address generator 342, except now the various lines of the input in_addr 396 and the output outaddr[B-2:0] 398 are denoted in terms of B. Thus the multiplexer 352 in Fig. 35 is selected by input in_addr 400 Similarly one of the inputs of comparator 374 and of comparator 376 is inaddr 402. Outaddr[B-2:0] 398 forms the output. The advantage of this structure is a reduction in the size of the lookup table RAM of The FFT calculation circuitry 168 (Fig. 14) is disclosed in Verilog code listings 1 17. The Verilog code for the address generator 394 is generic, enabling any power-offour table to be implemented.

Channel Estimation and Correction The function of the Channel estimation and correction circuitry shown in channel estimation and correction block 170 (Fig. 14) is to estimate the frequency response of the channel based on the received values of the continuous and scattered pilots specified in the ETS 300 744 telecommunicationsstandard, and generate compensation coefficients which correct for the channel effects and thus reconstruct the transmitted spectrum. A more detailed block diagram of the chan nel estimation and correction block 170 is shown in Fig. 16.

In acquisition mode, the channel estimation and correction block 170 needs to locate the pilots before any channel estimation can take place. The circuitry performs a convolution across the 2048 carriers to locate the positions of the scattered pilots, which are always evenly spaced, 12 carriers apart. Having found the scattered pilots.

the continual pilots can be located; once this is done the exact position of the 1705 active carriers within the 2048 outputs of the FFT calculation circuitry 168 (Fig. 14) is known. A timing generator 404 within the block can then be initialized, which then generates reference timing pulses to locate pilots for channel estimation calculation and for use in other functions of the demodulator as well.

Channel estimation is performed by using the evenly spaced scattered pilots, and then interpolating between them to generate the frequency response of the channel.

The received carriers (pilots and data) are complex divided by the interpolated channel response to produced a corrected spectrum. A complete symbol is held in a buffer 406.

This corrects for the bit-reversed order of the data received from the FFT calculation circuitry 168. It should be noted that raw, uncorrected data is required by the frequency and sampling rate error circuitry.

WO 98/19410 PCT/US97/18911 The task of synchronizing to the OFDM symbol in the frequency domain data received from the FFT calculation circuitry 168 (Fig. 14) begins with the localization of the scattered and continual pilots, which occurs in pilot locate block 408. Scattered pilots, which according to the ETS 300 744 telecommunications standard, occur every 12 data samples, offset by 3 samples with respect to the start of the frame in each succeeding frame. As the power of the pilot carriers is 4/3 the maximum power of any data carrier, a succession of correlations are performed using sets of carriers spaced at intervals of 12. One of the 12 possible sets is correlates highly with the boosted pilot carrier power.

A first embodiment of the pilot search procedure is now disclosed with reference to Figs. 36 and 16. It should be noted that the scattered pilot search procedure is done on the fly, and storage is only required in so far as is necessary to perform the subsequent step of continual pilot location discussed below. At step 410, after the assertion of the signal resync 204, generally occurring after a channel change or on power up, the signal pilot_lock 412 is set low. Then, at step 414 the process awaits the first symbol pulse from the FFT calculation circuitry 168 (Fig. 14) on line 416 indicating the start of the first symbol. The first symbol is received and stored. In one embodiment of the pilot search procedure each point from 0 to 2047 is read in turn, accumulating each value (II! IQ1) in one of 12 accumulators (not shown). The accumulators are selected in turn in a cycle of 12, thus convolving possible scattered pilot positions. Two well known peak trackers indicate the accumulator with highest value (Peak1) and the accumulator having the second highest value (Peak2). The accumulator having the highest value corresponds to the scattered pilot orientation. The second highest value is tracked so that the difference between the highest peak and the second highest peak can be used as a "quality" measure. At decision step 418, if the two peaks are not far enough apart, a test for completion of a full range frequency sweep is made at decision step 420. If the test fails, failure of the scattered pilot search is reported at step 422.

Otherwise, at step 424 the IQ Demodulator LO frequency is incremented by +1/8 carrier spacing by incrementing the magnitude of the control signal freq_sweep 426. Then the search for scattered pilots is repeated after delaying 3 symbols at step 428 to allow time for the effect of the change to propagate through the FFT calculation circuitry 168 and buffers. The peak difference threshold can be altered by the control microprocessor via the microprocessor interface 142 and block 430.

In a variation of the first embodiment there is only a single peak tracker which indicates the accumulator with highest value, which corresponds to the scattered pilot orientation. The true scattered pilot orientation thus found is one of 12 possible orientations.

WO 98/19410 PCT/US97/18911 36 If the test at decision step 418 is successful, the search for continual pilots is begun at step 432 by establishing an initial pilot offset from the 0 location in the RAM, storing the FFT data, according to the formula pilot offset (accumulator mod 3) (39) Thus, if the scattered pilot peak is in accumulator 0, 3, 6 or 9 the pilot offset is 0. If the scattered pilot peak is in accumulator 1, 4, 7, or 10 then pilot offset is 1, etc. Then carrier positions expected for continual pilots are read, adding the pilot offset value to the address, and accumulating (Ill Iql) values. This procedure is repeated until first 115 continual pilot start positions have been searched. From the ETS 300 744 telecommunications standard the number of possible first carrier positions among the active carriers lying in a contiguous block between carrier 0 and carrier 2047 is easily calculated as (2048-1705) 3 115, as explained below. It is thus guaranteed that the active interval begins within the first (2048-1705) carrier positions. The carrier corresponding to the peak value stored is the first active carrier in the symbol.

Upon completion of the continual pilot search, at step 434 the timing generator404 is reset to synchronize to the first active carrier and scattered pilot phase. The signal pilot_lock412 is then set high at step 436, indicating that the pilots have been located successfully, then at step 436 the timing generator 404 is reset to synchronize to the first active carrier and scattered pilot phase.

In a tracking mode of operation, shown as step 438, the scattered pilot search is repeated periodically, and evaluated at decision step 440. This can be done at each symbol, or less frequently, depending upon propagation conditions. The predicted movement of the scattered pilot correlation peak is reflected by appropriate timing in the timing generator404, and can be used as a test that timing has remained synchronized.

Failure of the test at decision step 440 is reported at step 442, and the signal pilot_lock 412 is set low.

A second embodiment of the pilot search procedure is now disclosed with reference to Figs. 16 and 37. At step 444 the assertion of the signal resync 204, generally occurring after a channel change or on power up, the signal pilotlock 412 is set low. Then, at step 446 a symbol is accepted for evaluation. A search for scattered pilots, conducted according to any of the procedures explained above, is performed at step 448. Then a search for continual pilots is performed as described above at step 450. At decision step 452 it is determined whether two symbols have been processed.

If the test fails, control returns to step 446 and another symbol is processed. If the test succeeds at step 454 another test is made for consistency in the positions of the scattered and continual pilots in the two symbols. If the test at step 454 fails, then the WO 98/19410 PCT/US97/18911 37 procedure beginning with decision step 420 is performed in the same manner as previously described with reference to Fig. 36. If the test at step 454 succeeds at step 456 the timing generator 404 is reset to synchronize to the first active carrier and scattered pilot phase. The signal pilotlock 412 is then set high at step 458, indicating that the pilots have been located successfully.

In a tracking mode of operation, shown as step 460, the scattered pilot search is repeated periodically, and evaluated at decision step 462. This can be done at each cycle of operation, or less frequently, depending upon propagation conditions. The predicted movement of the scattered pilot correlation peak is reflected by appropriate timing in the timing generator404, and can be used as a test that timing has remained synchronized. Failure of the test at decision step 462 is reported at step 464, and the signal pilot lock 412 is set low.

It will be appreciated that after the scattered pilots have been located, the task of locating the continual pilots is simplified considerably. As the continual pilots are inserted at a known sequence of positions, the first of which is offset by a multiple of 3 positions with respect to start of the frame, as specified by the ETS 300 744 telecommunications standard. Two of three possible location sets in the data space can therefore be immediately excluded, and it is only necessary to search the third set. Accordingly the continual pilot search is repeated, each iteration beginning at a location 3 carriers higher. New accumulated values and the current start location are stored if they are larger than the previous accumulated value. This is repeated until all continual pilot start positions have been searched. The carrier corresponding to the largest peak value stored will be the first active carrier in the symbol. It is unnecessary to evaluate the "quality" of the continual pilot correlation peak. The scattered pilot search represents a correlation of 142 samples, and has higher noise immunity that of the search for continual pilots. The continual pilot search is almost certain to be succeed if scattered pilot search completed successfully.

The above sequences locate scattered pilot positions within 1/4 symbol period, assuming accumulation at 40MHz, and locate continual pilots in less than 1 symbol period (45 x 115 clock cycles assuming 40MHz operation).

The I and Q data is provided to the pilot locate block 408 by the FFT calculation circuitry 168 (Fig. 14) in bit-reversed order on line 416. This complicatesthe problem of utilizing a minimum amount of RAM while computing the correlations during pilot localization. Incoming addresses are therefore bit reversed, and computed modulo 12 in order to determine which of 12 possible bins is to store the data. In order to avoid the square root function needed to approximate the carrier amplitude, the absolute values of the data are summed instead as a practical approximation. The scattered pilots are WO 98/19410 PCT/US97/18911 38 determined "on the fly". The continual pilots are located on frames which succeed the frames in which the scattered pilots were located.

The operation of the timing generator 404 is now disclosed in further detail. The addressing sequence for the RAM buffer 406 is synchronized by a symbol pulse from the FFT calculation circuitry 168 (Fig. 14). The FFT calculation process runs continuously once the first symbol from has been received following FFT Window acquisition.

Addressing alternates between bit-reversed and linear addressing for successive symbols. The timing generator 404 also generates all read-write timing pulses.

Signals u_symbol 466 and csymbol 468 are symbol timing pulses indicating the start of a new uncorrected symbol or corrected symbol. The signal u_symbol 466 is delayed by latency of the interpolating filter 470 and the complex multiplier 472, which are synchronized to RAM Address Sequence Timing.

For carrier timing the signals c_carrier0 474, pilot timing signals us_pilot(+) 476, uc_pilot(+) 478, c_tps_pilot(*) 480 and odd_symbol pulse 482 are referenced to a common start pulse sequence. A base timing counter (not shown) is synchronized by the pilot locate sync timing pulse 484, and is therefore offset from symbol timing. Pilot timing outputs are also synchronized to uncorrected symbol output from the buffer 406 or the corrected symbol output delayed by the interpolating filter 470 and the complex multiplier 472. On assertion of the signal resync 204 all timing output is set to inactive states until the first symbol is received. Let the transmitted pilot at carrier k be Pk and the received pilot be P'k" Pk Hk "Wk Pk where Pk is described below, and Ik jQk (41) where k indexes pilot carriers, Hk is the channel response and wk is the reference sequence. We interpolate Hk to generate compensation values for the received data carriers, D'k: Dk Ik jQk (42) Dk D k D (43) Hk where k indexes data carriers. Received pilots can be demodulated using a locally generated reference sequence and are then passed to the interpolating filter.

WO 98/19410 PCT/US97/18911 39 The interpolating filter 470, realized in this embodiment with 6 taps and 12 coefficients, is utilized to estimate the portion of the channel between the scattered pilots. As explained above pilots are transmitted at known power levels relative to the data carriers and are modulated by a known reference sequence according to the ETS 300 744 telecommunicationsstandard. The transmitted pilot carrier amplitudes are 4/3 of nominal data carrier power for reference bit of 1, -4/3 for the reference bit of 0; quadrature component 0 in both cases). Interpolation coefficients are selected from the 0-11 cyclic count in the timing generator 404 synchronized to data availability.

Appropriate correction factors may be selected for data points to provide on-the-fly correction. The coefficients vary depending on scattered pilot phase. Since the positions of reference pilots vary, therefore coefficients to compensate a given data carrier also vary.

The input and output signals, and signals relating to the microprocessor interface 142 of the channel estimation and correction block 170 are described in tables 18, 19 and 20 respectively. The circuitry of the channel estimation and correction block 170 is disclosed in Verilog code listings 18 and 19.

TPS Sequence Extract The tps sequence extract block 172 (Fig. 14), although set out as a separate block for clarity of presentation, is in actuality partially included in the channel estimation and correction block 170. It recovers the 68-bit TPS data carried in a 68-symbol OFDM frame, and is shown in further detail in Fig. 38. Each bit is repeated on 17 differential binary phase shift keyed ("DBPSK") modulated carriers, the tps pilots, within a COFDM symbol to provide a highly robust transport channel. The 68-bit tps sequence includes 14 parity bits generated by a BCH code, which is specified in the ETS 300 744 telecommunications standard. Of course appropriate modifications can be made by those skilled in the art for other standards having different BCH encoding, and for modes other than 2K mode.

A clipper 486 clips incoming corrected spectrum data to The sign bit can be optionally evaluated to obtain the clipped result. In comparison block 488 clipped received tps pilot symbols are compared against a reference sequence input. In the described embodiment a value of 0 in the reference sequence matches -1 in the pilot, and a value of 1 in the reference sequence matches +1 in the pilot. Majority vote comparisons are used to provide an overall +1 or -1 result. A result of +1 implies the same modulation as the reference sequence, and a result of -1 implies inverse modulation.

The DBPSK demodulator 490 converts the sequence from the majority-vote form to a binary form. The sequence converts to a value of 0 if the modulation in current WO 98/19410 PCTIS97/18911 and previous symbols was the same, and to 1 if modulation between successive symbols is inverted.

From an uninitialized condition a search for either of two sync words in 68-bit tps sequence (4 x 68-bit 1 superframe) is conducted in the frame synchronizer block 492.

The synchronization words of a superframe are as follows: 0011010111101110 sync word for frames 1 and 3 1100101000010001 sync word for frames 2 and 4 Having acquired either sync word, a search for the other is conducted in the appropriate position in the next OFDM frame. On finding the second sync word synchronization is declared by raising the signal tps_sync 494. Data is then passed to the BCH decoder 496, which operates on 14 parity bits at the end of an OFDM frame against received data in the frame. Errors are corrected as necessary.

Decoded data is provided to output store block 498, which stores tps data that is found in a full OFDM frame. The output store block 498 is updated only at the end of an OFDM frame. Only 30 bits of interest are made available. Presently some of these bits are reserved for future use. The length indicator is not retained.

The BCH decoder 496 has been implemented in a manner that avoids the necessity of performing the Berlekamp Algorithm and Chien Search which are conventional in BCH decoding. The Galois Field Multiplier used in the BCH decoder496 is an improvementof the Galois Field Multiplierwhich is disclosed in our copending U.S.

Application No. 08/801,544.

The particular BCH code protecting the tps sequence is specified in the ETS 300 744 telecommunications standard as BCH (67,53,t=2), having a code generator polynomial 25 h(x) x' +x9 +X6+x5+x 4+X2 +x+1 (44) or equivalently h(x) (x +x3+1) (X 7

+X

3

+X

2 The left factor is used to generate the Galois Field which is needed for error detection.

Referring to Fig. 39, this is calculated in syndrome calculation block 500 which can be implemented using a conventional feedback shift register to generate the a values. The first three syndromes are then computed by dividing the received signal R(x) by the values a 1 a 2 and a 3 again using a conventional feedback shift register implementation, as is well known in the art of BCH decoding. It can be shown that the syndromes are WO 98/19410 PCT/US97/18911 41 So (aC)eo (a 1)e1 (46)

S

1 (a 2 )eo (a 2 (47)

S

2 (a 3 (a 3 )el (48) During the syndrome computation the syndromes are stored in storage registers 502.

In the event S o is 0, then it can be immediately concluded that there are no errors in the current tps sequence, and a signal is asserted on line 504 which is provided to error detect block 506, and the data of the received signal R(x) either output unchanged or toggled according to the output of the error detect block 506 on line 508. As explained below, if S1 0 So 2 (49) then exactly one error is present, a condition which is communicated to the error detect block 506 on line 510. Otherwise it is assumed that two errors are present. More than two errors cannot be detected in the present implementation.

In order to solve the system of three non-linear equations shown above, data flow from the registers R[2:0] 502 into search block 512 is enabled by a signal EOF 514, indicating the end of a frame. Three feedback shift registers 516, 518, 520 having respective Galois Field multipliers 522, 524, 526 for acc ac 3 in the feedback loop are initialized to 50H, 20H, and 3dH (wherein the notation refers to hexadecimal numbers). The feedback shift registers 516, 518, 520 are clocked each time a new data bit is available. The syndromes and outputs of the feedback shift registers 516, 518, 520 are clocked into to a search module, which performs a search for the error positions using an iterative substitution search technique, which will now be described. The outputs of feedback shift registers 516, 518 are multiplied in a Galois Field Multiplier 528.

Considering the case of one error, So is added, modulo 2, preferably using a network of XOR gates 530, to the output of the first feedback shift register 516 (a-geno).

If the relationship (S Cgeno) 0 holds, it is concluded that there is an error in the present data bit. The bit being currently output from the frame store is toggled. The search is halted, and the data is output from the frame store.

WO 98/19410 PCT/US97/18911 42 Considering the case of two errors, if the following relationship holds, there is an error in the current bit being output from the frame store:

(S

0 +a(geno) 0 (S 1 +Ogen (S2 +.agen2) (51) It is now necessary to store the three terms calculated in the immediately preceding equation into the registers R[2:0] 502 which previously stored the syndromes S o

S

2 This is represented by line 532.

The process continues, now looking for the second error, and reusing the data in registers R[2:0] 502, which now contains the syndromes as adjusted by the previous iteration. The adjusted syndromes are denoted SO' S 2 So (S O +ageno) ,etc. (52) Now, if agen) 0 (53) the second error has been found, and the bit being currently output from the frame store is toggled by XOR gate 534. If the search fails, more than two errors may be present and an error signal (not shown) is set.

the Galois Field Multiplier 528 is a clocked digital circuit and is disclosed with reference to Fig. 40. The tps data is received very slowly, relative to the other processes occurring in the multicarrier digital receiver 126. It is thus possible to execute the iterative substitution search slowly, and the Galois Field Multipliers are designed for minimum space utilization. They do not require alpha generators, but rely on small constant coefficient multipliers, with iterative feedback to produce the required alpha values. The arrangementtakes advantage of the relationship in Galois Field arithmetic (n a1 a n-1 (54) After initialization by a signal init 536 which selects multiplexers 538, 540, the multiplicand A 542 is accumulated in register 544 and repeatedly multiplied by the value a 1 in multiplier 546. The output on line 548 is repeatedly ANDed bitwise with the multiplicand B held in a shift register 550. The output of the shift register is provided on a one bit line 552 to the gate 554. The output of the gate 554 is accumulated in register 556 using the adder 558.

The input and output signals and signals relating to the microprocessor interface 142 of the- tps sequence extract block 172 are described in tables 21, 22, and 23.

Circuitry of the tps sequence extract block 172 and the BCH decoder 496 is disclosed in Verilog code listings 20 and 21.

WO 98/19410 PCT/US97/18911 43 Automatic Fine Frequency Control and Automatic Sampling Rate Control A non ideal oscillator present in the transmission chain of an orthogonal frequency division multiplexed ("OFDM") signal affects all carriers in the OFDM symbols. The OFDM carriers adopt the same phase and frequency disturbances resulting from the noisy local oscillator. Variations in the frequency of the Local Oscillator lead to phase shifts, and consequent loss of orthogonality within the OFDM symbol. Therefore competent automatic frequency control is required in the receiver to track the frequency offsets relative to the transmitter in order to minimize these phase shifts and hence maintain orthogonality.

All the carriers within an OFDM-symbol are equally affected by the phase shifts.

This is similar to the common phase error caused by phase noise. The common phase error present on all carriers is used to generate an Automatic Frequency Control ("AFC") signal, which is completely in the digital domain, since I/Q demodulation is performed in the digital domain. The approach taken is the calculation of the common phase error for every OFDM symbol. This is achieved by using the reference pilots. The change in the common phase error is measured over time to detect a frequency offset and is used to derive the AFC control signal. The generic approach for the AFC control loop and the automatic sampling rate control loop disclosed below is illustrated in Fig. 41.

Automatic sampling rate control is required when the receiver's master clock is not aligned with that of the transmitter. The misalignment causes two problems: the demodulating carriers have incorrect spacing; and the interval of the FFT calculation is also wrong.

The effect of this timing error is to introduce a phase slope onto the demodulated OFDM data. This phase slope is proportional to the timing error. The phase slope can be determined by calculating the phase difference between successive OFDM symbols, using reference pilots, and estimating the slope of these phase differences. A least squares approach is used for line fitting. The ASC signal is low-pass filtered and fed back to the sinc interpolator 158 (Fig. 13).

The mean phase difference between the reference pilots in subsequent OFDM symbols is used to calculate the frequency deviation. Assuming that the frequency deviations of the local oscillator are constant, then the phase rotates with a, where a 2rrfdmT t rads. Here fd is frequency deviation, m is the number of symbols between repetitions of identical pilot positions, and T t is the period comprising the sum of the active interval and the guard interval. The AFC signal is generated over time by low pass filtering a. The value of the frequency deviation is then used to control the IQ demodulator 144 (Fig. 13).

WO 98/19410 PCT/US97/18911 44 The AFC and ASC control signals are effective only when a guard interval is passing indicated by the assertion of signal IQGI on line 154 (Fig. 13). This prevents a symbol from being processed under two different conditions.

The correction circuitry 174 (Fig. 14) is shown in greater detail in Fig. 42.

Frequency error values output on line 560 are calculated by determining the average of the differences of phase values of corresponding pilots in a current symbol and the previous symbol. The resulting frequency error value is filtered in low pass filter 562 before being fed-back to the IQ demodulator 144 (Fig. 13). It is optional to also evaluate continual pilots in order to cope with larger frequency errors. Sampling rate error, output on line 564 is determined by looking at the phase difference between pilots in a symbol and the same pilots in a previous symbol. The differences vary across the symbol, giving a number of points through which a line can be fitted using the well known method of least squares regression. The slope of this line is indicative of the magnitude and direction of the sampling rate error. The sampling rate error derived in this way is filtered in low pass filter 566 before being fed back to the sinc interpolator 158 (Fig. 13).

A separate store 568 for the scattered pilots contained in 4 symbols is shared by the frequency error section 570 and the sampling rate error section 572. Direct comparison of scattered pilot symbols is thereby facilitated, since the scattered pilot phase repeats every four symbols. In an alternate embodiment where scattered pilots are used to provide control information, storage must be provided for four symbols. In the preferred embodiment, wherein control information is derived from continual pilots, storage for only one symbol is needed.

Recovery of the angle of rotation a from the I and Q data is accomplished in the phase extract block 574, where c tan 1 In the presently preferred embodiment, the computations are done at a resolution of 14 bits. The phase extract block 574 is illustrated in greater detail in Fig. 43. The quadrant of a is first determined in block 576. The special cases where I or Q have a zero magnitude or I Q is dealt with by the assertion of signals on lines 578. If the magnitude of Q exceeds that of I, quotient inversion is accomplished in block 580, utilizing a control signal 582. A positive integer division operation is performed in division block 584.

Although this operation requires 11 clock cycles, there is more than enough time allocated for phase extraction to afford it. The calculation of the arctangent of the quotient is accomplished by a pipelined, truncated iterative calculation in block 586of the Taylor Series WO 98/19410 PCT/US97/18911 X3 X5 X7 9 tan-'(x) X-x Ixl<1 (56) 3 5 79 Block 586 is shown in greater detail in the schematic of Fig. 44. The value x 2 is calculated once in block 588 and stored for use in subsequent iterations. Powers of x are then iteratively computed using feedback line 590 and a multiplier592. The divisions are calculated using a constant multiplier 594 in which the coefficients are hardwired.

The sum is accumulated using adder/subtractor 596. The entire computation requires 47 48 clock cycles at 40 MHz.

Turning again to Fig. 43, quadrant mapping, and the output of special cases is handled in block 598 under control of block 576. It may be noted that the square error of the result of the Taylor Expansion rises rapidly as cx approaches 45 degrees, as shown in Fig. 45 and Fig. 46, which are plots of the -square error at different values of a of the Taylor expansion to 32 and 31 terms respectively. The Taylor expansions to 31 and 32 terms are averaged, with the result that the square error drops dramatically, as shown in Fig. 47. A memory (not shown) for holding intermediate values for the averaging calculation is provided in block 598.

Constant Phase Error across all scattered Pilots is due to frequency offset at IQ Demodulator. Frequency Error can be defined as: ferr (57) 2TmT t where c, m and T, have the same meanings as given above. c is determined by taking the average of the difference of phase values of corresponding pilots between the current symbol and a symbol delayed for m symbol periods. In the above equation, m 1 in the case of continual pilots. This computation uses accumulation block 600 which accumulates the sum of the current symbol minus the symbol that preceded it by 4.

Accumulation block 602 has an x multiplier, wherein x varies from 1 to a minimum of 142 (in 2K mode according to the ETS 300 744 telecommunicationsstandard). The low pass filters 562, 566 can be implemented as moving average filters having 10 20 taps. The data available from the accumulation block 602 is the accumulated total of pilot phases each sampled m symbols apart. The frequency error can be calculated from ferr Acc{new-old} (58) (2)nTmT, N 142 in the case of scattered pilots, and 45 for continual pilots, assuming 2K mode of operation according to the ETS 300 744 telecommunications standard. The WO 98/19410 PCTIUS9718911 46 technique for determining sampling rate error is illustrated in Fig. 48, in which the phase differences of pilot carriers, computed from differences of every fourth symbol (Sn Sn-4 are plotted against frequency of the carriers. The line of best fit 604 is indicated. A slope of 0 would indicate no sampling rate error.

Upon receipt of control signal 606 from the pilot locate block 408 (Fig. 14), a frequency sweep is initiated by block 608, which inserts an offset into the low-pass filtered frequency error output using adder 610. Similarly a frequency sweep is initiated by block 612, which inserts an offset into the low-pass filtered sampling rate error output using adder 614. The frequency sweeps are linear in increments of 1/8 of the carrier spacing steps, from 0 3.5kHz corresponding to control signal values of 0x0-0x7.

A preferred embodiment of the correction circuitry 174 (Fig. 14) is shown in greater detail in Fig. 49. Continual pilots rather than scattered pilots are held in a memory-store 616 at a resolution of 14 bits. The generation of the multiplier x for the computation in the accumulation block 618 is more complicated, since in accordance with the noted ETS 300 744 telecommunicationsstandard, the continual pilots are not evenly spaced as are the scattered pilots. However, it is now only necessary to evaluate 45 continual pilots (in 2K mode according to the ETS 300 744 telecommunicationsstandard). In this embodiment only the continual pilots of one symbol need be stored in the store 616.

Inclusion of the guard interval size, is necessary to calculate the total duration of the symbol T t is received from the FFT window circuitry (block 166, Fig. 14) on line 620.

The input and output signals and signals relating to the microprocessor interface 142 of the circuitry illustrated in Fig. 42 are described in tables 24, 25, 26, and Table 27 respectively. The circuitry is further disclosed in Verilog code listings 24 Demapper The demapping circuitry 176 (Fig. 15) is shown as a separate block for clarity, but in practice is integrated into-the channel estimation and correction circuitry. It converts I and Q data, each at 12-bit resolution into a demapped 12-bit coded constellation format (3-bit I, I soft-bit, 3-bit Q, Q soft-bit). The coded constellation is illustrated in Fig.

and Fig. 51. For 64-QAM the 3 bits are used for the I and Q values, 2 bits for 16-QAM 2-bits and 1 bit for QPSK.

For example in Fig. 51 values of 1= 6.2, Q= -3.7 would be demapped to: I-data 001; I soft-bit=011; Q-data=101; Q soft-bit=101.

The input and output signals of the demapping circuitry 176 are described in tables 28 and 29 respectively.

Symbol Deinterleaver The symbol deinterleaver 182 (Fig. 15) reverses the process of symbol interleaving of the transmitted signal. As shown in Fig. 52 the deinterleaver requires a 1512 x 13 WO 98/19410 PCT/US97/18911 47 memory store, indicated as block 622. The address generator624 generates addresses to write in interleaved data and read out data in linear sequence. In practice the address generator 624 is realized as a read address generator and a separate write address generator. Reading and writing occur at different instantaneous rates in order to reduce the burstiness of the data flow. The address generator 624 is resynchronized for each new COFDM symbol by a symbol timing pulse 626. Carrier of index 0 is marked by carrier0 pulse 628. Addresses should be generated relative to the address in which this carrier is stored.

The input and output signals of the symbol deinterleaver 182 are described in tables 30 and 31 respectively. Circuitry of the symbol deinterleaver 182 is disclosed in Verilog code listing 22.

Bit Deinterleaver Referring to Fig. 54, the bit deinterleaver 184 (Fig. 15) reverses the process of bitwise interleaving of the transmitted signal, and is shown further detail in Fig. 53. In soft encoding circuitry 630 input data is reformatted from the coded constellation format to a 24 bit soft I/Q format. The soft encoding circuitry 630 is disclosed for clarity with the bit deinterleaver 184, but is realized as part of the symbol deinterleaver discussed above. The deinterleave address generator 632 generates addresses to read the 6 appropriate soft-bits from the 126 x 24 memory store 634, following the address algorithm in the ETS 300 744 telecommunications standard. The deinterleave address generator 632 is resynchronized for each new COFDM symbol by the symbol timing pulse 626.

The output interface 636 assembles I and Q output data streams from soft-bits read from the memory store 634. Three I soft bits and three Q soft bits are extracted from the memory store 634 at each deinterleave operation, and are parallel-serial converted to provide the input data stream to the Viterbi Decoder 186 (Fig. The input and output signals-of the bit deinterleaver 184 are described in tables 32 and 33 respectively. Circuitry of the bit deinterleaver 184 is disclosed in Verilog code listing 23.

Host Microprocessor Interface The function of the microprocessor interface 142 is to allow a host microprocessor to access control and status information within the multicarrier digital receiver 126 (Fig.

12). The microprocessor interface 142 is shown in greater detail in Fig. 55. A serial interface 638 and a parallel interface 640 are provided, the latter being primarily of value for testing and debugging. The serial interface 638 is of known type and is 12C compatible. The microprocessor interface 142 includes a maskable interrupt capability allowing the receiver to be configured to request processor intervention depending on WO 98/19410 PCT/US97/18911 48 internal conditions. It should be noted, that the multicarrier digital receiver 126 does not depend on intervention of the microprocessor interface 142 for any part of its normal operation.

The use of interrupts from the point of view of the host processor is now described.

"Event" is the term used to describe an on-chip condition that a user might want to observe. An event could indicate an error condition or it could be informative to user software. There are two single bit registers (not shown) are associated with each interrupt or event. These are the condition event register and the condition mask register.

The condition event register is a one bit read/write register whose value is set to one by a condition occurring within the circuit. The register is set to one even if the condition only existed transiently. The condition event register is then guaranteed to remain set to one until the user's software resets it, or the entire chip is reset. The condition event register is cleared to zero by writing the value one. Writing zero to the condition event register leaves the register unaltered. The condition event register must be set to zero by user software before another occurrence of the condition can be observed.

The condition mask register is a one bit read/write register which enables the generation of an interrupt request if the corresponding condition event register is set.

If the condition event is already set when 1 is written to the condition mask register an interrupt request will be generated immediately. The value 1 enables interrupts. The condition mask register clears to zero on chip reset. Unless stated otherwise a block will stop operation after generating an interrupt request and will restart soon after either the condition event register or the condition mask register are cleared.

Event bits and mask bits are always grouped into corresponding bit positions in consecutive bytes in the register map. This allows interrupt service software to use the value read from the mask registers as a mask for the value in the event registers to identify which event generated the interrupt. There is a single global event bit that summarizes the event activity on the chip. The chip event register presents the OR of all the on-chip events that have 1 in their respective mask bit. A value of 1 in the chip mask bit allows the chip to generate interrupts. A value of 0 in the chip mask bit prevents any on-chip events from generating interrupt requests. Writing 1 or 0 to the chip event register has no effect. The chip event register only clears when all the events enabled by a 1 in their respective mask bits have been cleared.

The IRQ signal 642 is asserted if both the chip event bit and the chip event mask are set. The IRQ signal 642 is an active low, "open collector" output which requires an WO 98/19410 PCT/US97/18911 49 off-chip pull-up resistor. When active the IRQ output is pulled down by an impedance of 1000 or less. A pull-up resistor of approx. 4kQ is suitable.

The input and output signals of the microprocessor interface 142 are described in tables 34 and 35 respectively.

System Controller The system controller 198 (Fig. 15), which controls the operation of the multicarrier digital receiver 126 (Fig. 12), in particular channel acquisition and the handling of error conditions, is shown in further detail in Fig. 56.

Referring to the state diagram in Fig. 57, the channel acquisition sequence is driven by four timeouts.

AGC acquisition timeout. 20 ms (80 symbols) are allowed for the AGC to bring up the signal level, shown in step 644. Then the FFT window is enabled to start acquisition search in block 646.

Symbol acquisition timeout: 200 symbol periods, the maximum guard interval plus active symbol length, is allocated to acquire the FFT window in step 648. Another symbol periods are allocated to pilot location in step 650. Approximately 50 ms are required to process 2K OFDM symbols. An option is provided to exit step 650 as soon as the pilots have been located to save acquisition time in non-extreme situations.

Control Loop Settling timeout: A further 10 ms, representing approximately symbols is allocated to allow the control loops to settle in step 652. An option is provided to exit step 652 and return to an initial step resync 654 if pilots have been lost if control loop settling timeout occurs.

Viterbi synchronizationtimeout: In block 656 approximately 150 symbol periods are allocated for the worst case of tps synchronization, indicated by step 658 and approximately 100 symbol periods for the Viterbi Decoder 186 (Fig. 15) to synchronize to the transmitted puncture rate, shown as step 660. This is approximately 65 ms. In reasonable conditions it is unnecessaryto wait this long. As soon as Viterbi synchronization is established, then transition to the system_lock state 662. It is possible to bypass the tps synchronization requirement by setting parameters (see table below) in the receiver parameters register and setting set rx parameters to 1.

If acquisition fails at any stage, the process automatically returns to step resync 654 for retry.

Having acquired lock, the system will remain in lock unless a Reed-Solomon overload event occurs, i.e. the number of Reed-Solomon packets with uncorrectable errors exceeds a predetermined value (the rso_limit value) in any 1 second period. If any of the 4 synchronizing state machines in the acquisition sequence, FFT window (step 648), pilot locate (step 650), tps synchronization (step 658) and Viterbi synchroni- WO 98/19410 PCT/US97/18911 zation (step 660), lose synchronization once channel acquisition has occurred, no action will be taken until an event, rso_event, occurs and the step resync 654 is triggered automatically.

In poor signal conditions acquisition may be difficult, particularly the Viterbi synchronization. Therefore a bit is optionally provided in the microprocessor interface 142 Fig. 12), which when set extends the timeouts by a factor of 4.

The input and output signals, and the microprocessor interface registers of the system controller 198 are described in tables 36, 37, 38, and 39 respectively.

Tables Pin Name _I/O Description Tuner/ADC Interface SCLK O Sample clock for ADC I Input ADC data bus AGC O Automatic Gain Control to tuner(Sigma-Delta output) O External Tuner Control Outputs MPEG-2 Transport Interface O MPEG-2 Transport Stream Data bus OUTCLK O MPEG Transport Stream Output Clock SYNC O MPEG Transport Stream Sync pulse (1 per 188byte) VALID O MPEG Transport Stream Valid data flag ERROR O MPEG Transport Stream Errored data flag Serial Host Microprocessor Interface SD I/O Serial Interface Data SC I Serial Interface Clock SDT I/O Serial Data Through SCT O Serial Clock Through (40MHz clock out when DEBUG is high) I Serial Address Inputs (Hardwired external value) used as TSEL pins when DE- BUG is high Parallel Host Microprocessor Interface WO 98/19410 PCT/US97/18911 Pin Name I/O Description I Microprocessor Address Bus I/O Microprocessor Data Bus 2-bit/DEBUG data MWE I Microprocessor Write Enable MCE I Microprocessor Chip Enable NOTIRQ O Interrupt Request JTAG Test Access Port TCK I JTAG Test Clock TMS I JTAG Test Mode Select TDI I JTAG Test Data In TDO O JTAG Test Data Out NTRST I JTAG TAP Controller Reset Miscellaneous Pins NRESET I Asynchronous Reset I 40MHz Input Clock TSTRI I Transport Stream Interface tristate control TA I Test Address Bit Snooper access (Bit 7 of up address bus) DEBUG I Test Pin TSEL [2:0]/SADDR[2:0] I Internal Test Inputs (mux out internal data onto 0 normal upi, 1= fft input data (24-bit), 2 fft output data (24-bit), 3 channel correction output data (24-bit), 4 fec input data.(2 x 3-bit softbit) all data clocked out @40MHz, 24-bit data in 4 bytes. Clock brought out on SCT pin, for convenience. Symbol timing/other synch. signals indicated with market bits in data.

TLOOP Test Input Table 4 WO 98/19410 PCT/US97/18911 Ad- Bit No. Dir/Re- Register Name Description dress set (Hex) 0x00 Event Reg.

O R/W/0 chip_event OR of all events which are interrupt-enabled (unmasked) 1 R/W/0 lockfailedevent Set to 1 if channel acquisition sequence fails 2 R/W/0 rs overloadevent Set to 1 if Reed-Solomon Decoder exceeds set threshold within one 1 second period 0x01 Mask Reg.

0 RNW/0 chip_mask Set to 1 to enable IRQ output 1 R/W/0 lock_failedmask Set to 1 to enable interrupt on channel acquisition fail 2 R/W/0 rs_overload mask Set to 1 to enable interrupt on RS error threshold exceeded 0x02 Status Reg.

O R/0 system_locked Set to 1 when system acquired channel successfully 1 R/0 viterbi_sync Set to 1 when Viterbi is synchronized 2 R/0 tps_sync Set to 1 when OFDM frame carrying TPS data has been synchronized to.

3 R/0 pilotloc Set to 1 when pilots in COFDM symbol have been located and synchronized to 4 R/0 fftloc Set to 1 when guard interval has been located and synchronized to.

R/1 viterbi rate Received Viterbi Code rate 0x04- 0x05 Control Reg: change_channel When set to 1, holds device in "Reset" state. Clearing this bit initiates channel change.

WO 98/19410 PCT/US97/18911 Ad- Bit No. Dir/Re- Register Name Description dress set (Hex) RNV/W agc_invert Invert AGC Signa-Delta output. Default setting means low output associated with reduced AGC gain.

2 R/W/0 o_clk_phase Set to 1 to invert phase of output clock. Default condition: output data changes on falling edge of output clock.

3 R/W/0 set_rx_parameters Set to 1 to take Receiver Parameter Data from Receiver Parameter Register.

Default condition: settings taken from TPS data (longer channel acquisition time) 4 R/W/O extend_agc Set to 1 to hold acquisition sequence in agc_acquire state R/W/0 extend fs Set to 1 to hold acquisition sequence in fs_acquire state 6 R/W/0 extendsettle Set to 1 to hold acquisition sequence in fs_settle state R/W/0 extend_sync When set to 1 to hold acquisition sequence in vit_sync state 4 4 4 10:8 R/W0I External Tuner Control bits (external pins 11 R/W/0 i2c_gate 12C "Gate" signal; setting this to 1 enables the isolation buffer between the "processor sidel2C" bus and the "Tuner side" 12C so the processor can access a Tuner through COFDM device. Setting to 0 closes the "gate" to prevent 12C bus noise affecting delicate RF.

WO 98/19410 PCT/US97/18911 Ad- Bit No. Dir/Re- Register Name Description dress set (Hex) 12 R/W/ tstri Transport Stream Tristate (TSTRI) control set to 1 to tristate MPEG TS interface to mux a QPSK device to same MPEG demux).

Power-on state of TS output controlled by external pin TSTRI.

13 R/W/0) fast_ber Set to 1 to reduce BER counter, vit ill state counter and rso_counter, counter periods from 1 sec to 100ms.

R/W/0 soft reset Software Reset set to 1 to reset all blocks except upi.

Set to 0 to release.

0x06- Receiver Parameter Register: 0x07 15:14 R/W/2 upi_constellation Constellation Pattern for Demapper and Bit Deinterleaver (reset condition 64-QAM) 13:12 R/W/0 upi_guard Guard Interval: 00 1/32, 01 1/16, 10= 1/8, 11 1/4 11:9 R/W/0 upi_alpha Hierarchical Tranmission Mode or "alpha value" (reset condition non-hierarchical mode) R/W/0 upi_hp_rate Viterbi Code Rate for HP stream in non-hierarchical mode this is taken as the Viterbi Code Rate (reset condition 1/2 rate code) 4:2 R/W/0 upi_lp_rate Viterbi Code Rate for LP stream (reset condition 1/2 rate code) R/W/0 upi_tx_mode Tranmission mode (00=2K, 01=8K, others reserved) 0x08 7:0 R/W/0 rso limit Errored packet per second limit (for rs_overload_event bit) WO 98/19410 PCT/US97/18911 Ad- Bit No. Dir/Re- Register Name Description dress set (Hex) 0x09 7:0 R/0 rsocount Count of Uncorrectable Transport Packets per second (saturates at 255).

Write to register to latch a stable count value which can then be read back OxOa- 15:0 R/0 ber BER (before RS) deduced OxOb from RS corrections in 1 second period max correctable bit errors ~1.35M/sec for 7/8, 64-QAM, 1/32 GI (equivalent to 43.e-3 BER assuming useful bitrate of 31.67 e6). Only top 16 bits of 21 bit counter are visible resolution of ~1e-6 depending on code-rate, constellation GI length. Write to register to latch a stable count value which can then be read back.

OxOc- 15:0 R/0 agclevel AGC "Control Voltage" OxOd (msb's) OxOe- 11:0 R/0 freq_error IQ Demodulator Frequency OxOf Error (from feedback loop) 0x10- TPS Data (including future use bits) 0x13 R/0 tps_frame Number of last received cmplete OFDM frame in superframe 3:2 R/0 tps_constellation Constellation Pattern from TPS data R/0 tps_alpha Hierachical Transmission Information 10:8 R/0 tpshp_rate Viterbi Code Rate of High-Priority stream (In non-hierarchical mode this is the code rate of the entire stream) 13:11 R/0 tpslp_rate Viterbi Code Rate of Low-Priority stream 15:14 R/0 tps_guard_int Guard Interval WO 98/19410 PCT/US97/18911 k Ad- Bit No. Dir/Re- Register Name Description dress set (Hex) 17:16 R/0 tps_tx_mode Transmission Mode 31:19 R/0 tps_future Undefined bits allocated for future use Debug Access 0x20- 15 R/W/0 agc_open Set to 1 to break AGC con- 0x21 trol loop 11:0 R/W/0 agctwiddle AGC twiddle factor 0x22- R/W/0 agcloop_bw AGC Control loops parame- 0x23 ters 0x24- 15 R/W/0 freq_open Set to 1 to break freq con- 0x25 trol loop 14 R/W/0 freq_nogi Set to 1 to allow frequency update anytime, not just during Guard Interval 11:0 R/W/0 freq_twiddle IQ Demod twiddle factor 0x26- freq_loop_bw Frequency Control Loop 0x27 parameters 0x28- 15 R/W/0 sample_open Set to 1 to break sample 0x29 control loop 14 R/W/0 sample_nogi Set to 1 to allow sample update anytime, not just during Guard Interval 11:0 R/WIO sample_twiddle Sampling Rate Twiddle factor Ox2a- R/W/0 sample_loop_bw Sampling Rate Control Ox2b Loop parameters Ox2c- 11:0 R/0 sampling_rate_err Sampling Rate Error (from Ox2d feedback loop) 0x30- 0x31 R/W/0 lock fft window Set to 1 to prevent fft_window moving in Tracking mode 14 R/W/0 inc fft window Write 1 to move fft window position one sample period later (one-shot operation) 13 R/W/0 dec fft window Write 1 to move fft window position one sample period earlier (one-shot operation) 12:0 R/0 fft_window FFT Window position WO 98/19410 WO 9819410PCTIUS97/1891 1 Ad- Bit No. Dir/Re- Register Name Description dress____ set (Hex) I R/W/O fft-win-thresh FFT Window Threshold 0x34- 15 RIO/ set-carrier_0 Set to 1 to use carrier_0 0x35 value as setting 11:0 R/W/0 carrier_0 Carrier 0 position; readback value detected by Pilot Locate algorithm or force a value by writing over it 0x36 7:0 RAN! csithresh Channel State Information threshold the fraction of mean level below which data carriers are marked by a bad-carrier flag. Nomi- 0.2 (for 2/3 code rate).

0x37 0x38- 11:0 R/O vit ill-states Viterbi Illegal State Rate 0x39 (per second)Write to register to latch count which can then be read back SNOOPERS (External test address bit TA[6) 1 0x40- 15:14 RANR/ T,IQGlFreqerror[ IQ Demod Snooper (Note: 0x41 11:0 W 11:0] bitO0= lsb of highest addressed byte, 21) 0x44- 31:30 RAN T, Valid Low-Pass Filter Snooper 0x47 27:16 RAN Q-data[1 11:0 RANV 1-data[ 11:0] 0x48- 47:46 RANV T,SincGl Resampler Snooper Ox4d 43:32 RAN Sample err[1 31 RA\N Valid 27:16 RAN 11:0 RAN 1-data[1 0x50- 31:29 RN T, Valid,Resync FFT Snooper 0x53 27:16 RA\N Q-data[1 11:0 RANV I-data[1 0x54- 31:30 RAN T, Valid, Channel Estimation Cor- 0x57 29:28 RAN Symbol,Resync rection Snooper 27:16 RAN Q-data[1 11:0 RAN l-data[1 0x58- 31:30 RAN T, Resync Frequency Sampling Er- Ox~b 29:28 RAN usymbol, uc-pilot ror Snooper 27:16 RAN Q-data[1 11:0 RAN I-data[1 1:01 WO 98/19410 W098/9410PCTIUS97/18911I Ad- fBit No, Dir/Re- Register Name Description dress_____ (H ex) Ox~c- 31:30 R[W T, Resync TPS Sequence Extract 29:28 R/WV csymbo!, tps_pil. Snoopers 27:16 RAN RAN reference Jseq 11:0 RN I-data[1 0x60- 39 RAN T Demap Snooper 0x65 36:35 RAN constellation 34:32 RAN alpha 27:16 RN O-data[1 15:14 RN Valid, c-symbol 13 RAN c-carrierO 11:0 RAN l-data[1 1:01 0x68- 23:22 RAN T, valid symbol, Symbol Deinterleave Ox6a 21:20 RAN carrierO Snooper 19 RAN odd_symbol 11:0 RAN demapdata[1 1:0] Ox6c- 23:21 RAN T, valid, symbol Bit Deinterleaver Snooper Ox6e 20:19 RAN constellation 18:16 RN alpha 11:0 RAN symdidata[1 0x70- 15:13 RAN T, valid, resync Viterbi Snooper 0x71 6:4 RN RAN 1-data[2:0] 0x72- 15:14 RAN T, valid, Forney Deinterleaver 0x73 13:12 RAN resync, eop Snooper RAN vit data[7:01 0x74- 15:14 RAN T, valid, Reed Solomon Snooper 0x75 13:12 RAN resync, eop RAN 0x76- 15:14 RAN T, valid, Output Interface Snooper 0x77 13:12 RAN resynceop 11:0 RAN error val, error RAN 0x78- 31 RAN T System Controller Snooper Ox7b 30:20 RAN tpsdata [10: 01 19:18 RAN pkt err, err -val 17 RAN vit -ill -state 16 RAN vit ill-val 14 RAN rs -co rr -val 13:8 RAN rs RAN vit- sync, tps sync 4:3 RANV pilot loc, ift loc RAN vit Table WO 98/19410 PCT/US97/18911 Signal Description clk 40MHz main clock 20MHz sample clock (used as a "valid" signal to indicate when valid input samples are received) sampled data input from ADC agc_resync control input; held low on channel change on transition to high AGC should reset itself and accumulate new control voltage for new channel.

(bi-di) Internal Microprocessor Data bus Internal Microprocessor Address Bus (only 2-bits required) upwstr Internal uP write strobe uprstr Internal uP read strobe upsell Internal Address decode output (high valid for Ox0c-0x0d) upsel2 Internal Address decode output (high valid for 0x20- 0x23) te, tdin Scan inputs Table 6 Signal Description agc Signal Delta modulated output signal; when integrated by external RC it provides an analogue representation of the internal digital "control voltage" valuelnterpolated output data tdout scan outputs Table 7 Address Bit No. Dir/Re- Register Description (Hex) set__ Name OxOc- 15:0 R/0 agc_level AGC "Control Voltage" (msb's) OxOd 0x20- 15 R/W/0 agc_open Set to 1 to break AGC control 0x21 loop 11:0 R/W/0 agc_twiddle AGC twiddle factor 0x22- R/W/0 agc_loop_bw AGC Control loops parameters 0x23 Table 8 WO 98/19410 PCT/US97/18911 Signal Description clk 40MHz main clock nrst Active-low synchronous reset 20MHz sample clock (used as a "valid" signal to indicate when input data sample is valid) input data sample from ADC. (AGC should ensure that this white-noise-like signal is scaled to full dynamic range) freq_err[11:0] Frequency Error input 1Hz accurate tuning over carrier spacing IQGI Valid pulse for enable frequency error signal. The effect of the frequency control loop is held off until a guard interval is passing through the IQ Demod block. (IQGI is gener7 ated by the FFT window and indicates when a guard interval is passing).

te, tdin Scan test inputs Table 9 Signal Description I-data[11:0] I data-stream to be low-pass filtered (40 MHZ timing) Q-data[11:0] Q data-stream to be low-pass filtered (40 MHZ timing) valid Valid output data indicator; high if data is being output on this clock cycle (40 MHZ timing) tdout Scan test output Table Signal Description clk 40MHz clock (2x sample clock) nrst Active-low synchronous reset valid_in high-pulse indicating valid data from IQ-demodulator timing) i_data[11:0], input data from IQ-demodulator q_data[11:0] te, tdin Scan test inputs Table 11 Signal Description i_out[11:0], Low-Pass filtered output data q_out[11:0] WO 98/19410 PCT/US97/18911 Signal Description valid Output pulse indicating valid data output (decimated to tdout Scan test output Table 12 Signal I Description 40MHz main clock (2x sample clock) validin input data valid signal; when valid is low, input data should be ignored i data[11:0], input data from low-pass filter (decimated to q_data[11:0] sr_err[11:0] SamplingRate Error feedback fro Freq/Sampling Error block SincGI Valid pulse for Error signal; effect of Sampling Rate contol loop is held off until guard interval is passing through Sinc Interpolator. FFT Window block generates this signal at appropriate time.

te,tdin Scan test signals Table 13 Signal Description i_out[11:0], Interpolated output data q_out[11:0] valid Output pulse indicating valid data output) tdout Scan test output Table 14 Signal Description 40MHz clock (2x sample clock) validin input data valid signal; when valid is low, input data should be ignored.

i_data[11:0] input data from front-end (ignore quadrature data for this block) resync Control signal: forces Sync FSM back to acquisition mode when pulsed high Expected guard interval; programmed by Host uP to aid fft window acquisition. 00 1/32, 01 1/16, 10 1/8, 11 1/4 WO 98/19410 PCT/US97/18911 Signal Description (bi-di) Internal Microprocessor Data bus (bi-directional) upaddr[0] Internal uP address bus (only 1-bit required) upwstr Internal uP write strobe uprstr Internal uP read strobe upsel _Address decode output to select FFT window block Table Signal Description FFTWindow Timing output pulse; low for 2048 samples indicating the active interval ffitlock Output pulse indicating status of Sync FSM; 1 Symbol acquired Received Guard Interval Size: 00 1/32, 01 1/16, 10 1/8, 11 =/4 IQGI Timing pulse indicating when the guard interval should arrive at the IQ demodulator (Frequency Error only corrected in the Guard Interval) SincGI Timing pulse indicating when the guard interval should arrive at the Sinc Interpolator (Sampling Error only corrected in the Guard Interval) Sampling Rate sweep output; 4-Bit output used by Frequency and Sampling Error block to generate Sampling Rate "ping-pong" sweep during FFT window acquisition.

Table 16 Address Bit Dir/Reset Register Name Description (Hex) No.

0x30- 0x32 R/W/0 lock fft window Set to 1 to prevent fft_window moving in Tracking mode 14 R/W/0 inc fft window Write 1 to move fft window position one sample period later (one-shot operation) 13 R/W/0 dec fft window Write 1 to move fft window position one sample period earlier (one-shot operation) 12:0 R/0 fftwindow FFT Window position WO 98/19410 PCT/US97/18911 Signal Description 40MHz clock (2x sample clock) nrst Synchronous reset (active low) valid in input data valid signal; when valid is low, input data should be ignored i_data[11:0], input data from FFT q_data[11:0] symbol Symbol timing pulse from FFT; high for first valid data value of a new symbol resync Resynchronization input triggered on e.g. channel change.

Pulsed high to indicate return to acquisition mode (wait for first symbol pulse after resync before beginning pilot search) (bi-di) Internal Microprocessor Databus upaddr[0] Internal uP address bus (only 1-bit required) upwstr Internal uP write strobe uprstr Internal uP read strobe upsel Internal address decode output; high for addresses 0x032-( x033 Table 18 Signal Description ui_data[11:0], Uncorrected spectrum data, as read from RAM buffer (for uq_data[11:0] Frequency/Sampling Error block) u_symbol Uncorrected symbol start; high for first carrier of the uncorrected symbol uspilot high for any carrier which is a scattered pilot in the uncorrected symbol ci_data[11:0], Corrected spectrum data; as output from the complex cq_data[11:0] multiplier valid high for valid corrected symbol data carriers only badcarrier high if interpolated channel response for the carrier is below pre-set fraction of the mean of carriers of previous symbol viterbi will discard the data carried by this carrier WO 98/19410 PCT/US97/18911 Signal Description c_symbol high for the first carrier in the corrected symbol c_carrier0 high for the first active carrier in the corrected symbol (a continual pilot corresponding to a carrier index value of 0) c_tps_pilot high for any carrier in the corrected symbol which is a TPS pilot pilot_lock output high if pilots successfully located at the end of pilot acquisition phase.

odd_symbol high for symbol period if symbol is odd number in frame (as determined from scattered pilot phase) c_reference_seq Reference sequence output to TPS Sequence block Frequency Sweep control; incrementing 3-bit count which increments IQ Demodulator LO offset in Frequency and Sampling block. Sweeps 0-0.875 carrier spacing offset in 0.125 carrier spacing steps Table 19 Address (Hex) Bit No. Dir/Reset Register Description II IName 0x32- 15 R/W/0 setcarrier_0 Set to 1 to use 0x33 carrier_0 value as setting 11:0 R/W/0 carrier_0 Carrier 0 position 0x36 7:0 R/W/ csi thresh Channel State Information threshold the fraction of mean level below which data carriers are marked by a badcarrier flag. Nominally 0.2 (for 2/3 code rate). A value of 0 would turn CSI off for comparison testing.

0x37 Table WO 98/19410 PCT/US97/18911 Signal Description 40MHz clock (2x sample clock)ci_data[11:0] corrected pilot data from Channel Estimation and Correction (only need I data because corrected pilots should only insignificant Im component; only need sign bit) tps_pilot high for single clock cycle when data input is a tps_pilot use like a valid signal.

reference_seq Reference Sequence PRBS input from Channel Estimation Correction ignore for non-tps_pilot values c_symbol timing pulse high for 1 clock cycle for first carrier in new symbol (whether or not that carrier is active) (bi-di) Internal Microprocessor Databus Internal uP address bus (only 2-bits required) upwstr Internal uP write strobe uprstr Internal uP read strobe upsel Internal address decode output; high for addresses 0x10-0x13 Table 21 Signal Description tps_data [29:0] Output tps data (held static for 1 OFDM frame): frame number tps_data[3:2] constellation tps_data[6:4] hierarchy tps_data[9:7] code rate, HP stream tps_data[12:10] code rate, LP stream tps_data[14:13] guard interval tps_data[16:15] transmission mode tps_data[29:17] future use bits Note that parameters are transmitted for the next frame; outputs should be double-buffered so parameters appear at block outputs in the correct frame (used by Demapper and Symbol/Bit deinterleave blocks to decode incoming data) tps_sync Status output from Frame Sync FSM set to 1 when FSM is sync'd i.e when 2 valid sync words have been received in expected postions AND correct TPS data is available at the block outputs.

Table 22

I

Ox10-0x 13 I TPS Data (including future use bits) R/0 tps frame Number of last received complete OFDM frame in superframe WO 98/19410 PCT/US97/18911 Ox10-0x TPS Data (including future use bits) R/0 tps_constellation Constellation Pattern from TPS data R/0 tps_alpha Hierarchical Transmission Information 10:8 R/0 tps_hp_rate Viterbi Code Rate of High-Priority stream (In non-hierarchical mode this is the code rate of the entire stream) 13:11 R/0 tps_lp_rate Viterbi Code Rate of Low-Priority stream 15:14 R/0 tps_guard_int Guard Interval 17:16 R/0 tpstxmode Transmission Mode 31:19 tpsfuture Undefined bits allocated for future use Table 23 Signal Description 40MHz clock (2x sample clock) nrst Active low reset us_pilot input data valid signal; high when a scattered pilot is output from the Channel Estimation Correction block Guard Interval from which symbol period Tt can be deduced:00 1/32 (Tt 231us) 01 1/16 (238us), 10 1/8 (252us), 11 1/4 (280us) ui_data[11:0], input data from Channel Estimation Correction (Uncoruq_data[11:0] rected spectrum) u_symbol Symbol timing pulse from Channel Estimation Correction; high for first valid data value of a new symbol (uncorrected spectrum) resync Resynchronization input triggered on e.g. channel change. Pulsed high to indicate return to acquisition mode (wait for first symbol pulse after resync before beginning Pilot search) Sampling Rate Sweep control from FFT Window block; 0 OHz offset, 1=+500Hz, 2=-500Hz,3=+1000Hz, 4=-1000Hz,5=+1500Hz,6=-1500Hz,7=+2000Hz,8=-2000H z Frequency Sweep control from Channel Estimation Correction block; represents number n range 0-7 frequency offset nx500Hz WO 98/19410 PCT/US97/18911 Signal Description (bi-di) Internal Microprocessor Databus Internal uP address bus (only 4-bit required) upwstr Internal uP write strobe uprstr Internal uP read strobe upsell Internal address decode output; high for addresses OxOe- OxOf upsel2 Address decode for addresses in range 0x24-0x2d Table 24 Signal Description frequency_error frequecy error output (to IQ Demod) sampling_rate_error Sampling Rate Error output (to Sinc Interpolator) freq_lock status output; high if frequency error low samplelock status output; high if sampling rate error low Table Address (Hex) Bit No. Dir/Reset Register Description Name OxOe- 11:0 R/0 freq_error IQ Demodu- OxOf lator Frequency Error (from feedback loop) Table 26 Address (Hex) Bit No. Dir/Re- Register Name Description set 0x24- 15 R/W/0 freq_open Set to 1 to break freq 0x25 control loop 14 R/W/0 freq_nogi Set to 1 to allow frequency update anytime, not just during Guard Interval 11:0 R/W/O freq_twiddle IQ Demod twiddle factor 0x26- freq_loop_bw Frequency Control Loop 0x27 parameters 0x28- 0x29 R/W/O sample_open Set to 1 to break sample control loop WO 98/19410 PCT/US97/18911 Address (Hex) Bit No. Dir/Re- Register Name Description _set 14 R/W/0 sample_nogi Set to 1 to allow sample update anythime, not just during Guard Interval 11:0 R/W/0 sample_twiddle Sampling Rate Twiddle factor Ox2a- R/W/0 sample_loopbw Sampling Rate Control Ox2b Loop parameters Ox2c- 11:0 R/O sampling_rate_err Sampling Rate Error Ox2d (from feedback loop) -Table 27 Signal Description 40MHz clock (2x sample clock) validin input data valid signal; when valid is low, input data should be ignored i_data[11:0], q_data[11:0] input data from Channel Estimation Correction.

badcarrierin Carrier Status falg set if carrier falls below acceptable level; indicates to viterbi that data from this carrier should be discarded from error correction calculations.

c_symbol Timing synchronization signal high for the first data sample in the corrected COFDM symbol.

control signal which defines constellation: 00 QPSK, 01 16-QAM, 10 64-QAM control signal defining hierarchical transmission parameter, alpha: 000 non-hierarchical transmission, 001 =-alpha value of 1, 010 alpha value of 2, 011 alpha value of 4 (Note the first release of the chip will not support hierarchical transmission) Table 28 Signal Description outdata[11:0] deinterleaved output data 6 I, 6 Q format badcarrier badcarrier flag carried through demap process unchanged.

valid Valid output data indicator; high if data is being output on this clock cycle WO 98/19410 PCT/US97/18911 Signal Description d_symbol Symbol timing pulse re-timed to synchronize with outdata Table 29 Signal Description 40MHz clock (2x sample clock) valid_in input data valid signal; when valid is low, input data should be ignored demap_data[11:0] input data from Demapper. Data is in 6-bit I, 6-bit Q format (for 64_QAM) badcarrier in Carrier status signal set if carrier falls below limits; indicates to viterbi that data should be ignored. Carried with data as extra bit through deinterleaver store.

symbol Timing synchronization signal high for the first data sample in a COFDM symbol. Used to resynchronize address generation carrier0 Timing pulse high for the first active carrier (corresponding to carrier index value of 0) in a symbol odd_symbol high if symbol is odd number in the frame (different interleaving pattern in odd and even symbols within 68-symbol frame) Table Signal Description outdata[11:0] deinterleaved output data coded constellation format badcarrier Bad carrier output having passed through deinterleave

RAM.

valid Valid output data indicator; high if data is being output on this clock cycle d_symbol Output timing synchronization signal high for first data sample in de-interleaved COFDM symbol.

Table 31 Signal Description 40MHz clock (2x sample clock) validin input data valid signal; when valid is low, input data should be ignored. Valid "spread out" to smooth out data rate over whole symbol average of 1 data valid every six cycles. Effective data rate at viterbi input dropped to sdi_data[11:0] input data from Symbol Deinterleaver. Data is in 6-bit I, 6-bit Q format (for 64_QAM) WO 98/19410 PCT/US97/18911 Signal Description bad_carrier Set to 1 if a carrier conveying the data fell below cceptable limits; indicates to Viterbi that this data should be ignored symbol Timing synchronization signal high for the first data sample in a COFDM symbol. Used to resynchronize address generation Constellation Type indicator:10 64-QAM01 16-QAM00

QPSK

Hierarchical transmission control:000 non-hierarchical, 001 alpha value 1, 010 alpha value 2, 011 alpha value 4(Note: in this first version of the device only non-hierarchical mode is supported) Table 32 Signal Description I soft-bit to Viterbi discard-I flag bit drived from bad_carrier signal; viterbi will ignore this soft-bit if set.(bad-carrier is repeated per soft-bit because of interleaving) Q soft-bit to Viterbi discard-Q flag-bit; Vlterbi will ignore this soft-bit if set valid Valid output data indicator; high if data is being output on this clock cycle Table 33 Signal Description (bi-di) Microprocessor Data bus (bi-directional) Microprocessor Address Bus MR/W Microprocessor Read /Write control SCL Serial Interface Clock SDA(bi-di) Serial Interface Data I/O (bi-directional same pin as MD[0]) Serial Interface Address S/P Serial/Parallel interface select Table 34 Signal Description (bi-di) Internal processor data bus (inverted) (bi-directional) WO 98/19410 PCT/US97/18911 Signal Description Internal address bus (decoded to provide individual selects for various register banks within functional blocks) upgrstr Internal read strobe upgwstr Internal write strobe IRQ Interrupt Request (Active low, open collector) Table Signal Description Uncontrolled 40MHz clock from input pad (bi-di) Internal Microprocessor Data bus (bi-directional) Internal Microprocessor Address Bus (only bits relevant to registers within System Control) uprstr Internal Microprocessor Read strobe upwstr Internal Microprocessor Write Strobe upsell block select decoded from microprocessor interface (1 access to this block enabled) valid for addresses Ox00-0x0b upsel2 address decode for 0x38-0x39 range tps_data[10:0] TPS data received in OFDM frame (1:0 tps_constellation; 4:2 tps_alpha7:5 tps_hp_rate10:8 tps_lp_rate)(Don't bother with Guard Interval these parameters only affect back end blocks) Count of bits corrected in each RS packet (accumulated over 1 second for BER value) rs_corr_val Valid pulse; high when rscorrect value is valid pkt_err Set to 1 to indicate RS packet is uncorrectable; has >64 bit errors or is corrupted in some other way.

err_val Set to 1 to indicate when pkt_err signal is valid vitillstate Viterbiillegal state pulse; (accumulate to give Viterbi illegal state count) vitillval NOW NOT REQUIRED Viterbi illegal state valid pulse vit_sync Status signal 1 if Viterbi is synchronized tps_sync Status signal 1 if TPS is synchronized pilot_loc Status signal 1 if pilot location completed successfully (found_pilots)) fftloc Status signal 1 if FFT window has located correctly Received Viterbi puncture rate.

WO 98/19410 PCT/US97/18911 Signal Description tck JTAG test clock used for control of clock in test mode njreset JTAG test reset for clock control block jshift JTAG test register shift control for clock control block j_ctrl_in JTAG test data input Table 36 Signal Description Test-controlled main clock Test-controlled sample clock (input to IQ Demod and

AGC)

(bi-di) Internal processor data bus (bi-directional) nirq Active Low interrupt request bit (derived from chip_event) Internal address bus (decoded to provide individual selects for various register banks within functional blocks) Hierarchical mode information Viterbi code rate for High Priority channel (in non-hierarchical mode this is the code rate for the complete channel) Viterbi code rate for Low Priority channel.

Transmission mode (2K or 8K) Guard Interval rxp_valid Set to 1 if Host Interface has set rx_para data used as a "valid" signal for rx_para data (in case of TPS data use tps_sync) o_clk_phase Control line; set to 1 to invert output clock phase External Tuner Control bits i2c_gate 12C "Gate" control ts_tri Transport Stream Interface tristate control soft_reset Software Reset (set to 1 to reset everything except upi) agc_invert Control line: set to 1 to invert sense of AGC sigma-delta output (default: low output equates to low AGC gain) agcresync Control line: When set low AGC held in initial condition.

Resync transitioning high commences the AGC acquisition sequence WO 98/19410 PCT/US97/18911 Signal Description fft_resync Control line: hold low to re-initialise FFT, Channel Estimation Correction, Frequency/Sampling Error and TPS blocks. Transition high commences FFT window locate, Pilot locate and TPS synchronisation.

viterbiresync Contol line; hold low to re-initiliase FEC backend. Transition high commences Viterbi synchronisation.

j_ctrl_out JTAG test data output from clock control block.

Table 37 Address Bit No. Dir/Reset Register Name Description (Hex) 0x00 Event Reg.

0 R/NV/ chip_event OR of all events which are interrupt-enabled (unmasked) 1 R/W/0 lock failed event Set to 1 if channel acquisition sequence fails 2 RN/W/ rsoverloadevent Set to 1 if Reed-Solomon Decoder exceeds set threshold within one 1 second period 0x01 Mask Reg.

0 R/W/0 chip_mask Set to 1 to enable IRQ output 1 RN/W0 lock failedmask Set to 1 to enable interrupt on channel acquisition fail 2 R/W/0 rs_overload_mask Set to 1 to enable interrupt on RS error threshold exceeded 0x02 Status Reg.

O R/O system_locked Set to 1 when system acquired channel successfully 1 R/0 viterbi_sync Set to 1 when Viterbi is synchronized R/0 tps_sync Set to 1 when OFDM frame carrying TPS data has been synchronized WO 98/19410 PCT/US97/18911 Address Bit No. Dir/Reset Register Name Description (Hex) 3 R/0 pilot_loc Set to 1 when pilots in COFDM symbol have been located and synchronized to 4 R/0 fftloc Set to 1 when guard interval has been located and synchronized to.

R/1 viterbirate Received Viterbi Code rate 0x04-0x0 Control Reg:

TI

R/W/0 change_channel When set to 1, holds device in "Reset" state.

Clearing this bit initiates channel change.

1 R/W/0 agc_invert Invert AGC Signa-Delta output. Default setting means low output associated with reduced AGC gain.

2 R/W/0 o_clk_phase Set to 1 to invert phase of output clock. Default condition: output data changes on falling edge of output clock.

3 R/W/O set_rxparameters Set to 1 to take Reciver Parameter Data from Receiver Parameter Register. Default condition: settings taken from TPS data (longer channel acquisition time) 4 R/W/0 extendagc Set to 1 to hold acquisition sequence in agc_acquire state RNV/0 extend_fs Set to 1 to hold acquisition sequence in fs_acquire state 6 R/W/0 extend_settle Set to 1 to hold acquisition sequence in fssettle state WO 98/19410 PCT/US97/18911 Address Bit No. Dir/Reset Register Name Description (Hex) 7 R/W/0 extend_syn When set to 1 to hold acquisition sequence in vit_sync state 10:8 R/W/0 xtc External Tuner Control bits (external pins R/W/0 i2c_gate 12C "Gate" signal; setting this to 1 enables the isolation buffer between the "processor side" 12C bus and the "Tuner side" 12C so the processor can acces a Tuner through COFDM device.

Setting to 0 closes the "gate" to prevent 12C bus noise affecting delicate RF.

12 R/W/0 ts_tri Transport Stream Tristate control set to 1 to tristate MPEG TS interface (eg. to mux a QPSK devce to same MPEG demux).

Power-on state of TS output controlled by external pin somehow!!! 13 R/W/0 fast ber Set to 1 to reduce BER counter, vit ill state counter and rsocounter, counter periods from 1 sec to 100ms R/W/0 softreset Software Reset set to 1 to reset all blocks except upi. Set to 0 to release.

0x06-0x0 Receiver Parameter Register: 7 15:14 R/W/2 upi_constellation Constellation Pattern for Demapper and Bit Deinterleaver (reset condition 64-QAM) 13:12 RWV/0 upi_guard Guard Interval: 00 1/32, 01 1/16, 1/8, 11 1/4 WO 98/19410 PCT/US97/18911 Address Bit No. Dir/Reset Register Name Description (Hex) 11:9 R/W/0 upi_alpha Hierarchical Tranmission Mode or "alpha value" (reset condition non-hierarchical mode) R/W/O upi_hp_rate Viterbi Code Rate for HP stream in non-hierarchical mode this is taken as the Viterbi Code Rate (reset condition 1/2 rate code) 4:2 R/W/0 upilp_rate Viterbi Code Rate for LP stream (reset condition 1/2 rate code) R/W/0 upi tx_mode Trnnsmission mode (00=2K, 01=8K, others __reserved) 0x08 7:0 R/W/0 rsolimit Errored packet per second limit (for rs_overload_event bit) 0x09 7:0 R/0 rso count Count of Uncorrectable Transport Packets per second (saturates at 255).Write to register to latch a stable count value which can then be read back.

OxOa 15:0 R/0 ber BER (before RS) de- OxOb duced from RS corrections in 1 second period max correctable bit errors -1.35M/sec for 7/8, 64-QAM, 1/32 GI (equivalent to 43.e-3 BER assuming useful bitrate of 31.67 e6).

Only top 16 bits of 21 bit counter are visible resolution of ~1e-6 depending on code-rate, constellation GI length.

Write to register to latch a stable count value which can then be read back.

Table 38 WO 98/19410 PCT/US97/1891 1 0x38-0x39 11:0 RIO vit ill states Viterbi Illegal State Rate (per second) Write to register to latch count which can then be read back Table 39- WO 98/19410 PCT/US97/18911 78 Listing 1 //Sccsld: %G% Copyright 1997 Pioneer Digital Design Centre Limited Author Dawood Alam.

Description: Verilog code for butterfly processor BF21. (RTL) Notes Computes first stage in radix 4 calculation.

'timescale 1ns 100ps module fft_bf21 (clk, enable_1, in_x r, in_x1i, in_x2r, in_x2i, in_s, outz1r, outzli, outz2r, out_z2i, out_ovf); parameter wordlength 5; Data wordlength.

input clk, //Master clock.

enable_1, I/ Enable on clock 3.

in_s; Control line.

input [wordlength-1:0] in_xlr, Input I from memory.

in_xli, I/ Input Q from memory.

in_x2r, Input I stage n-1.

in_x2i; Input Q stage n-1.

output out ovf; Overflow flag.

output [wordlength-1:0] out_z1r, //Output out_zli, //Output Q to stage n+1 out_z2r, Output I to memory.

out_z2i; Output Q to memory.

I to stage n+1 wire [wordlength-1:0] in_xlr, in_xli, in_x2r, in_x2i, out_z1r, out_zi, out_z2r, out_z2i; wire in_s, enable_l, out_ovf; reg [wordlength-1:0] zlitmpl, z2rtmp1, z2i_tmpl, zl r_tmp2, zl i_tmp2, z2rtmp2, zlr_tmpl, WO 98/19410 W09819410PCTIUS97/1891 1 z2iLtmp2; ovf-tmp, ovf-tmp0, ovf-tmpl, ovf-tmp2, ovf-tmp3, ex-reg0, ex-regi1, ex_reg2, ex-reg3; always @(in-s or in-xl r or in_xl i or in-x2r or in-x2i) begin {ex-regD,zl r tmplI= in xl r +in x2r; ovftmp0 in...xlr[wordlength-1] IOverflow check.

i n-x2 r[word length- 1] -zlrmpl [wordlength-1]I -in xl r~wordlength-1 -in_x2r[word length- 1] z1ir-tmpl [wordlength-1 if (ovf -tmp0) Saturate logic.

zlr-tmpl (ex regO) {1'bl1,{word length- 1{f1'bO}}}: 'bO,{word length- 1 {1 'bi {ex_reg,zlitmpl}= in xli in-x2i; ovf tmpl =inxli~wordlength-1] IIOverflo in x2i[word length- 1] -Z1li -tmpl1[word length-1] -in-xl i[wordlength-1 -in x2 i[word length- 1] zli-tmpl[wordength-1]; if (ovf -tmpl) Saturate logic.

zli-tmpl (ex regi) {1'bl,{word length- {1 'bO,{word length- 1 {1 'b At check.

w check.

{ex_reg2,z2r-tmpl} in xl r in_x2r; ovf-tmp2 in xlr~wordlength-1] IIOverflo' -i n x2r[word length- 1] -z2r tmpl [wordlength-1] -in -xl friword length-i1] i nx2r[word length- 1] z2 r-tmpl 1 word length-1 if (ovf -tmp2) Saturate logic.

z2r-tmpl1 (ex reg2) f1'bl 1{word length- 1 {1 'bO, {word length- 1{f1'b1})}; {ex_reg3,z2itmpl} =inxli- in-x2i; ovf-tmp3 in xl i[wordiength-1 IOverflow check.

-in_.x2i [word length- 1] -z2i -tmpljwordlength-1] inx 1li[word length- 1] in x2i[word length- 1] E2 i -tmpl [wordlength-1]; if (ovf -tmp3) Saturate logic.

z2i-tmpl (ex reg3) {1'bl1,{word length- 1{1'bO}} {l 'bQ,{wordlength-1{1'b}}}; WO098/19410 PCTJUS97/1891 1 IOutput stage with two channel mnux.

if (!in_s) begin: mux-passthru zir-tmp2 in.xlr; z1li tmp2 =in xl i; z2r-tmp2 in-x2r; z2i -tmp2 in-x2i; end else begin: mux-computing z1ir-tmp2 zlr-tmpl; z1li tmp2 z1 itmpl; z2Ftmp2 z2rtmpl; z2i -tmp2 =z2i-tmpl; end end assign out-zl r =z rtmp2; assign out zl i= z1li-tmp2; assign out-z2r =z2r-tmp2; assign out-z2i z2i-tmp2; always @(posedge cik) if (enable 1) Butterfly completes at the end of clock cycle 0.

ovf-tmp <=in-s (ovf tmp0 ovf tmpl Iovf tmp2 11 ovf-tmp3); assign out-ovf ovf-tmp; 'ifdef OVERFLOWDEBUGLOWLEVEL IDebug code to display overflow output of a particular adder.

IConcurrently monitor overflow flag and halt on overflow.

always @(ovf-tmp or ovf-tmp0 or ovf tmpl or ovf tmp2 or ovf-tmp3) if (ovf-tmp) begin if (ovf tmp0) $display("ovf tmpO on BF21 ",ovf tmp0); if (ovf tmpl) $display("ovf tmpl on BF21 ",ovf-tmpl); if (ovf tmp2) $display("ovf -tmp2 on BF21 ",ovf-tmp2); if (ovf tmp3) $display('ovf tmp3 on BF21 ",ovf-tmp3); $stop; end 'endif endmodule Listing 2 ISccsld: %G% Copyright 1997 Pioneer Digital Design Centre Limited Author Dawood Alam.

Description: Verilog code for butterfly processor BF21I1. (RTL) Notes Computes second stage in radix 4 calculation.

WO 98/19410 WO 9819410PCTIUS97/1891 1 'timescale 1 ns 1 D0ps module fft bf211 (cik, enable_1, in-xl r, in-~xl i, in-x2r, in-x2i, in-s, in-t, out-ir out-zli, out-z2r, out-z2i, out-ovf); parameter wordlength 5; Data wordlength.

input cik, enableI, in_s, in t; input [wordi-engthin-xl i, in -x2r, in__x2i; output out -o output [wordlengt[ out Zl i, out z2r, out~z2i; HI Master clock.

HI Enable on clock 3.

HI Control line.

HI Control line.

1:0] in xi r, /Input I from memory.

H/Input Q from memory.

H/Input I stage n-i.

H/Input Q stage n-i.

if; I Overflow flag.

1-1:0] out -z1ir, H/Output I to stage n+1 HI Output Q to stage n+1 HI Output I to memory.

HI Output Q-to memory.

wire [word length-1: 0] in xl r, in-xl i, in-x2r, in-x2i, out zir, ou t zii, out z2r, out~z2i; wire in_s, in-t, enable_1, out ovf, contfrol; reg [word length-i 1:0] z1 rtmpl, z1i tmpi, z2r-tmpi, z2i tmpl, z1 r imp2, zi itmp2, z2Ftmp2, z2i tmp2, x2ritImpi, x~ri tmp2; reg ovf-tmp, ovf-tmp0, ovf-tmpi, ovf tmp2, ovf-tmp3, ex-regO, ex -regi, ex_reg2, WO 98/19410 W098/9410PCTIUS97/1891 1 82 ex-reg3; assign control in-s !in t; always @(in_s or control or in-xl r or in-xl i or in-x2r or in-x2i) begin Crosspoint switch, used in computing complex j values.

if (control) begin: switch-crossed x2ri-tmpl in -x2i;I i-r.

x2ri -tmp2 in-x2r; IIr end else begin: switch-thru x2ri-tmpl in x2r;I r-r.

x2ri -tmp2 in-x2i; Ii end {ex-reg,zl rtmpl}=inxlr +x2ri-tmpl; ovf-tmp0 in xl r[wordlength-1 IOverflow check.

x2ri-tmpl1[word length- 1] -zlr tmpl[wordlength-1]t -i n_xlfr[word length- 1] -x2ri-tmpl [wordlength-1] zir-tmpl[wordlength-1]; if (ovf tmp0) Saturate logic.

zlr-tmpl (ex regO) {1'b 1,word length- {1 'bO, {word length- 1 {1 bl {ex regl,zli tmpl} (control) in xli x2ri tmp2:ir ovf-tmpl in xli[wordlength-1] /f-overflo (control A i2 ri -tmp2[word length- 11) Deals -z itmpl [wordlength-1I HI /+-input.

-in_xl i[wordlength-1] -(control A x2 ritmp2[word length- z1 i tmpl [wordlength-1 if (ovf-trpl) Saturate logic.

zl1itmpl1 (ex regi1) {1'b1,{wo rd length-1 {1 'bO, {wo rd length -1 {1 'b1 x1li x2ri -tmp2; N check.

with a w check.

a (ex reg2,z2r tmpl} in xl r -x2ri tmpl; ovFtmp2 inx1 r[wordlength-1 I Overflo, -x2ri-tmpl[wordlength-1] IIDeals with -z2rjtmplwordlength-1] H input.

-in x1 r[wordlength-1] x2iri tmpl1[word length-i] z2r tmpl [wordlength-1]; if (ovftmp2) Saturate logic.

z2r-tmpl (ex reg2) {1'b1, {word length {1 'bO, {word length- 1 {1 'bi1 {ex -reg3,z2i -tmpl} (control) in xl i x2ri-tmp2:in x1 i x2ri tmp2; ovf -tmp3 in xli[wordlength-1] Overflow-check.

-(control A x2ri -tmp2[word length- HI Deals with a -z2i-tmpl[wordlength-1] I 1-+input.

-in xl i[wordlength-1 WO 98/19410 PCTfUS97/18911 83 (control A x2ri-tmp2[word length- z2i tmnpl[wordlength-1]; if (ovf-trp3) II Saturate logic.

z2i-tmpl =(ex reg3) {1'bl1,{word length- 1{1'bOl}}: {1'bO,{Wordlength-1{1'bl}}}; HI Output stage with two channel mux.

if (!in-s) begin: mux-passthru z1ir-tmp2 =inxlr; zli tmp2 =in xli; z2r-tmp2 x2ri-tmpl; z2i-tmp2 =x2ri-tmp2; end else begin: mux computing z1ir-tmp2 =z1lr-tmpl; zl1i tmp2 =zl1i-tmpl1; z2r-tmp2 z2r-tmpl; z2i-tmp2 =z2i-tmpl; end end assign out z1ir zlr tmp2; assign out zl i z1li tmp2; assign out z2r z2r-tmp2; assign out-z2i z2L-tmp2; always @(posedge cik) if (enable 1) HI Butterfly completes at the end of clock cycle 0.

ovf-tmp in s (ovf tmp0 ovf-tmpl ovf-tmp2 11 ovf-tmp3); assign out-ovf ovf-tmp; ifdef OVERFLOW DEBUG LOW LEVEL HI Debug code to display overflow output of a particular adder.

HI Concurrently monitor overflow flag and halt on overflow.

always @(ovf-tmp or ovf-tmp0 or ovf tmpl or ovf-tmp2 or ovf-tmp3) if (ovf tmp) begin if (ovf tmpO) $display("ovf tmpO on BF211 ",ovf tmpO); if (ovf tmpl) $display("ovf tmpl on BF211 ",ovf tmpl); if (ovf -tmp2) $display( t ovf tmp2 on BF211 ",ovf-tmp2); if (ovf -tmp3) $display('ovf tmp3 on BF211 ",ovf-tmp3); $stop; end 'endif endmodule Listing 3 HI Sccsld: %G% Copyright 1997 Pioneer Digital Design Centre Limited WO 98/19410 PCT/US97/18911 84 Author Dawood Alam.

Description: Verilog code for a variable size ROM with complex data store.

(RTL)

Notes Used to store complex Twiddle factors.

'timescale 1ns 100ps module fft_rom (clk, enable_3, address, rom_data); parameter c_wordlength 1; Coeff wordlength.

parameter romAddressSize 1; Address size.

parameter FILE "../../../fft/src/lookup_tables/lu 10bit 2048ptscaleX"; I/ Lookup tab filename. (Listings 16, 17) input clk, enable_3; input [rom_AddressSize-1:0] address; output [c_wordlength-1:0] rom_data; reg [c_wordlength*2-1:0] rom rom_AddressSize)-l]; reg [c_wordlength*2-1:0] btmpl, rom_data; always @(address) b_tmpl rom[address]; always @(posedge clk) if (enable_3) rom_data b_tmpl; initial $readmemb(FILE, rom); endmodule Listing 4 I/ Sccsld: Listing 4 Copyright 1997 Pioneer Digital Design Centre Limited Author Dawood Alam.

Description: Verilog code for variable length single bit shift register.

Notes Used to delay pipeline control signals by "length" clocks.

'timescale 1ns/ 100ps WO 98/19410 PCTIUS97/18911 module fftsr_1bit (clk, enable_3, in_data, out_data); parameter length 1; Shift reg length.

input clk, Master clock; enable_3; Enable on clock 3.

input in_data; Input data.

output out_data; Output data.

reg shift_reg [length-1:0]; Shift register.

wire out_data; wire clk, enable_3; integer i; always (posedge clk) if (enable_3) begin for (i (length-1); i 0; i i 1) if (i 0) shift_reg[0] in_data; Force input to SR.

else shiftreg[i] shift_reg[i-1]; Shift data once.

end assign out_data shift_reg[length-1]; endmodule Listing Sccsld: %G% Copyright 1997 Pioneer Digital Design Centre Limited Author Dawood Alam.

Description: Verilog code for a dual-port FIFO. (RTL) Notes Used as a pipeline register to delay address into the address decoder.

'timescale 1 ns 100ps module fftsr_addr (clk, enable_3, in_data, out_data); parameter wordlength 1; Data wordlength I/Q.

parameter length 1; Shift reg length.

input clk, I/ Master clock; enable_3; Enable on clock 3.

input [wordlength-1:0] indata; SR input data.

output [wordlength-1:0] out_data; SR output data.

WO 98/19410 PCTIUS97/18911 86 reg [wordlength-l:0] shift_reg [length-1:0]; Shift register.

wire [wordlength-1:0] out_data; wire clk, enable_3; integer i; always (posedge clk) if (enable_3) begin for (i (length-1); i 0; i i- 1) if (i 0) shift_reg[0] in_data; Force input to SR.

else shift_reg[i] shiftreg[i-1]; Shift data once.

end assign out_data shift_reg[length-1]; endmodule Listing 6 //Sccsld: %G% Copyright 1997 Pioneer Digital Design Centre Ltd.

Author Dawood Alam.

Description: Verilog code for an signed twiddle factor multiplier. (RTL) Notes Single multiplexed multiplier and 2 adders employed to perform 3 multiplies and 5 additions. Pipeline depth 2.

ar/ai Complex data, br/bi Complex coefficient.

bi br could be pre-calculated in the ROM lookup, however in this implementation it is NOT an overhead as this path is shared by ar ai. 'timescale 1ns/ 100ps module fftcomplex_mult_mux (clk, c2, in_ar, in_ai, in_br, in_bi, outcr, outci, out_ovf); parameter parameter parameter wordlength 12; Data wordlength.

c_wordlength 10; Coeffwordlength.

multscale 4; multiplier scalling, /4096, 2 =/2048, =/1024, 4=/512.

input [wordlength-1:0] in_ar, Data input I.

in ai; Data input Q.

input [c_wordlength-1:0] in_br, Coefficient input I.

in_bi; Coefficient input Q.

input clk; //Master clock.

input c2; //Two bit count line.

output out_ovf; Overflow flag.

output [wordlength-1:0] out_cr, Data output I.

outci; Data output Q.

WO 98/19410 PCTIUS97/18911 87 wire [word length-1 in_ar, in-ai, br-tmp, bi tmp, out cr, out-ci* wire [qcword length-i 1:0] inbr, inbi; wire enable_0, enable- 1, enable_2, enable_3; wire c2; reg [word length- 1: 0] inai-tmp, in-artmp, abrtmp, abi-tmp, abri tmpl, abri-tmp2, abri tmp4, coeff tmpl, mpy-tmpl, sum -tmp0, sum -tmpl, sum -tmp2, acc -tmp, store -tmp, cr-tmp, ci-tmp; reg [word length*2-1 abri-tmp3, mpytmp2, coeff tmp2; reg ovf -tmpo, ovf-tmpl, ovf tmp2, ovf-tmp3, ex-regO, ex -regl1, ci, c3, c4; HI Enable signals for registers.

assign enable_-0 -c2[1 assign enable -1 -c2[1] assign enable_2 c2[1] assign enable-3 c2[1] HI Sign extend coefficients from c -wordlength bits to wordlength.

assign br tmp {{(wordlength-c -word length){i nbr[c word length-i 1} i n_br}; assign bi tmp {{(word length-c-word length){i n bi[cword length- 1 in_bi); HI Combinational logic before pipeline register.

always @(inar or br tmp or in_ai or bL tmp or c2) begin WO 98/19410 PCTIUS97/18911 88 cl c2[0] 11c2[1]; c3 c2[1] if (Mc) begin abr-tmp mnar; abi tmp in-ai; endelse begin abr-tmp br-tmp; abi tmp bi-tmp; endif (c3) {exrego,abri-tmp4} abi tmp abr-tmp; else {ex-regQ,abri-tmp4} abi tmp abr-tmp; ovf -tmpO abi -tmp[word length- 1] Overflow check.

(c3 A abr tmp[word length- IIDeals with a -ab ritmp4[word length-l 1I input.

-abi-tmp[wordlength-l] -(3A abr-tmp[word length- abri-tmp4[wordlength-l if (ovf -tmp0) Saturate logic.

abri-tmpl (ex regO) {1'bl.{word length- {1 'bO,{word length- 1 {1 'bl}1} else abri-tmpl =abri-tmp4; end Combinational logic after pipeline register.

always @(inaritmp or in ai tmp or br tmp or c2 or store tmp or abri-tmp2) begin c4 c2[1] case (c2) 2'bOO: begin coeff-tmpl =inartmp; sum -tmpO =store tmp; end 2'b01: begin coeff tmpl =br-tmp; sum -tmpO f wordlength-1{1'b0}}; end 2'bl10: begin coeff-tmpl =inaitmp; sum -tmpO =store~tmp; end 2'bll1: WO 98/19410 PCTIUS97/18911 89 begin coeff-tmpl =in_ar-tmp; sum-tmp0=store-tmp; end endcase abri-tmp3 {{word length{abri tmp2[word length- 1 ]},abri tmp2}; extnd coeff_tmp2= {{wordlength{coeff tmpl [wordlength-1])},coeff tmpl);//extnd mpytmp2 =(abri-tmp3 coeff-tmp2); mpytmp 1 mpyjtmp2 [word length*2-mu It-scale:word length-(mulIt-scale-I if (c4) {ex -regl ,sum-tmp2} sum tmpO- mpy tmpl mpytjmp2 [word le ngth-mulIt-scale]; else {ex~regl,sumtmp2} mpytmpl sum-tmp0 mpytjmp2 [word le ngth-m u Itsca le]; ovf-tmpl1 (c4 A mpy tmpl1[word length- H/Overflow check.

sum-tmpQ[word length- 1] HI Deals with a -sum tmp2[wordiength-1] I I input.

-(4A mpy tmpl1jword length- -sum tm pOfword length- 1] sum tmp2[wordlength-1]; if (ovf-tmpl) HI Saturate logic.

sum-tmpl1 (ex regi1) {1'bl,{word length- 1 {1 'bO,{word length- 1 {1 'b else sum-tmpl sum-tmp2; end HI Pipeline registers for I/Q data paths and intermediate registers.

always @(posedge cik) begin if (enable_2) HI Enable on 2nd clock.

acc-tmp sum-tmpl; HI Temp store.

if (enable_3) HI Enable on 3rd clock.

cr-tmp acc-tmp; HI Pipeline reg cr if (enable_3) HI Enable on 3rd clock.

ci-tmp sum-tmpl; HI Pipeline reg ci if (en ab le 1) store-tmp sum-tmpl; HI Temp store.

if (enable_2) in-ar-tmp in_ar; HI Reg i/p to mpy.

if (enable-1) in-ai-tmp in-ai; HI Reg i/p to mpy.

if (enable 0 I IenableI enable 2) abri-tmp2 <=abri-tmpl; T1 Pipeline reg.

end WO 98/19410 PCT/US97/18911 I/ Register ovf outputs before final OR, else whole complex multiplier is //treated as combinational, and the intermediate pipeline reg is ignored.

always @(posedge clk) if (enable_0 i enable 1 enable_2) ovf_tmp2 ovf_tmp0; always @(posedge clk) ovf_tmp3 ovf_tmpl; assign out_ovf ovf_tmp2 I ovf_tmp3; 'ifdef OVERFLOW_DEBUGLOW LEVEL Debug code to display overflow output of a particular adder.

Concurrently monitor overflow flag and halt on overflow.

always @(posedge clk) if (out_ovf) begin if (ovf_tmp2) $display("ovftmp0 on complex multiplier ",ovf tmp2); if (ovf_tmp3) $display("ovf tmpl on complex multiplier ",ovf tmp3); $stop; end 'else 'endif assign out_cr cr_tmp; assign out ci citmp; endmodule Listing 7 //Sccsld: %G% Copyright 1997 Pioneer Digital Design Centre Limited Author Dawood Alam.

Description: Verilog code for a dual-port FIFO with complex data store. (RTL) Notes A variable bitwidth FIFO shift register for intermediate I/Q calculations.

'timescale 1ns/ 100ps module fft_sriq (clk, enable_3, in_xr, in_xi, out_xr, out_xi); parameter wordlength 1; Data wordlength I/Q.

parameter length Shift reg length.

input clk, Master clock; enable_3; Enable on clock 3.

input [wordlength-1:0] in_xr, SR input data, I.

in xi; SR input data, Q.

WO 98/19410 91 output [wordlength-1:0] out xr, SR output data I.

out_xi; SR output data Q.

PCT/US97/18911 reg [wordlength-l:0] shiftr [length-1:0]; reg [wordlength-1:0] shift_i [length-1:0]; wire [wordlength-1:0] outxr, outxi; wire clk, 0 enable_3; integer i; SR for I data.

SR for Q data/ 1 always (posedge clk) if (enable_3) begin for (i (length-1); i 0; i i 1) begin if (i 0) begin shift_r[0] in_xr; Force shift_i[0] in_xi; For end else begin shift_r[i] shift_r[i-1]; Shift shifti[i] shifti[i-1]; I S end end end input I to SR.

rce input Q to SR.

data I once.

hift data Q once.

assign out_xr shift _r[length-1]; assign out_xi shift_i[length-1]; endmodule Listing 8 //Sccsld: %G% Copyright 1997 Pioneer Digital Design Centre Limited Author Dawood Alam.

Description: Veriiog code for 8 hardwired coefficients in a lookup table, of which 4 are unique values.

Notes Used to store complex Twiddle factors. 8 point FFT twiddle factor coefficients (Radix Coefficients stored as non-fractional bit integers. Real Coefficient (cosine value) is coefficient high-byte. Imaginary Coefficient (sine value) is coefficient low-byte. Coefficient addresses are delayed by a pipeline depth of 5, i.e. equivalent to case table values being advanced by 'timescale 1ns/ 100ps WO 98/19410 PCT/US97/18911 92 module fft_hardwired_lu0 (clk, enable_3, address, out_br, out_bi); parameter parameter c_wordlength 10; romAddressSize Coeff wordlength.

3; //Address bus size.

input clk, enable_3; input [rom_AddressSize-1:0] address; output [c_wordlength-1:0] out_br, out_bi; reg [c_wordlength*2-1:0] b_tmpl, b_tmp2; always @(address) case (address) 3'd6: b_tmpl 20'b0000000000_1000000000; W2 8 +0.000000 -1.000000 btmpl 20'b0101101010_1010010110; W1_8 =+0.707107 -0.707107 3'd2: b_tmpl 20'b1010010110 1010010110; W3_8 =-0.707107 -0.707107 default:b_tmpl 20'b01111111 110000000000;// W0_8 +1.000000 -0.000000 endcase always @(posedge clk) if (enable_3) b_tmp2 b_tmpl; assign outbr b_tmp2[c_wordlength*2-1:c_wordlength]; assign out_bi b_tmp2[c_wordlength-1:0]; endmodule Listing 9 Sccsld: %G% Copyright 1997 Pioneer Digital Design Centre Limited Author Dawood Alam.

Description: Verilog code for 32 hardwired coefficients in a lookup table, of which 16 are unique values.

Notes Used to store complex Twiddle factors. 32 point FFT twiddle factor coefficients (Radix Coefficients stored as non-fractional 10 bit integers. Real Coefficient (cosine value) is coefficient high-byte. Imaginary Coefficient (sine value) is coefficient low-byte. Coefficient addresses are delayed by a pipeline depth of 4, i.e. equivalent to case table values being advanced by 4.

'timescale 1ns/ 100ps module fft_hardwired_lul (clk, enable_3, address, out_br, outbi); WO 98/19410 PCTfUS97/18911 93 parameter c-wordlength =10; IICoeff word length.

parameter romAddressSize 5; Address bus size.

input cik, enable_3; input [romAddressSize-i :01 add ress; output [c _word length-1: out-br, out-bi; reg [cwordlength*2-1 b tmpl, btmp2; always @(address) case (address) 5'd14:b-tmpl 20'bOll110110011100111 100;H/W02 32 +0.923880 -0.382683 5'd6, 5'd16:b tmpl 20'bOl0ll10101010100101 10;H/W04_32 +0.707107 -0.707107 5'd7, 18 t d22:b -tmpl1 20'bOOl1100 100O 1000 100 11 1;H/W06_-32 +0.382683 -0.923880 8: b -tmpl 20'bOOOOOOOOOO_-1 000000000;H/ W08 -32 +0.000000 -1.000000 9: b tmpl1 20O'b110 0l1110_10 0 010 0111;/H/W 10Q3 2= 0.3 8 268 3 -0.9 23 88 0 TOOl, 5'd24:b -tmpl =20'bl 010010110O 1010010110;// W1 2_32 =-0.707107 -0.707107 5'dll1:b -tmpl =20'blOO01lO1lll 1100111100;// W1 432 -0.923880 -0.382683 5'd13:b -tmpl 20'bOll111101101110011100;// WOi132 +0.980785 -0.195090 5'd21:b -tmpl 20'bOll10101010O_1011100100;// W03 32 +0.831470 -0.555570 5'd17:b -tmpl 20'bOlOO0011100O 100101011 O;//W05_32 +0.555570 -0.831470 9:b -tmpl1 20'bOOO 100 100 -100000 1010;!! W07_32 195090 -0.980785 5'd23:b -tmpl1 20'bl1110011100O 100000 10 W09_32 195090 -0.980785 5'd25:b -tmpl 20'bl 000001010 -1110011 100;!Wi5 532 -0.980785 -0.195090 5'd26:b -tmpl 20'blO000100111l 0011000100;//W18_32 =-0.923880 +0.382683 5'd27:b-tmpl 20'b1l111lO100O0110101o10;//W21-32 =-0.555570 +0.831470 default: b -tmpl1 20'bOl 1111111 f1_0000000000;// W(O 32 000000 000000 endcase always @(posedge cik) if (enable_3) b-tmp2 b-tmpl; assign out br b tmp2[c wordlength*2-1 :c wordlength]; assign out bi b-tmp2[cword length- 1: 0]; endmodule Listing II Sccsld: %G% Copyright 1997 Pioneer Digital Design Centre Limited Author Dawood Alam.

WO 98/19410 PCTfUS97/18911 94 Description: Verilog code for 128 hardwired coefficients in a lookup table, of which 64 are unique values.

Notes Used to store complex Twiddle factors. 128 point FIFT twiddle factor coefficients (Radix Coefficients stored as non-fractional 10 bit integers. Real Coefficient (cosine value) is coefficient high-byte. Imaginary Coefficient (sine value) is coefficient low-byte. Coefficient addresses are delayed by a pipeline depth of 3, i.e. equivalent to case table values being advanced by 3.

'timescale 1Ins module ift-hardwired 1u2 (cik, enable_3, address, out-br, out-bi); parameter c-wordlength 10; Coeff wordlength.

parameter romAdd ressSize 7; HI Address bus size.

input cik, enable_3; input [romAddressSize-i address; output [cword length- 1: 0] out-br, out bi; reg [cwordlength*2-1 b-tmpl, b-tmp2; always @(address) case (address) 7'd36:b-tmpl =20'bOll111111l11111100111; //WO1_128=+O.998795 -0.049068 7'd4, 7'd37:b-tmpl =20'bOll11111101111001110; /W02_128=+0.995185 -0.098017 7'd38,_ 7'd68:b-tmpl =20'bOll1l1110101110110101; //W03 128=+0.989177 -0.146730 7'd 7'd39:b tmpl =20Mb11l11l011O11100111100; //W04_-128=+0.980785 -0.195090 7'd40:b-tmpl =20'bOll1l1100011110000100; /W05_128=+0.970031 -0.242980 7'd6,_ TM 41, 7'd69: b_tmpl1 =20'bOl111010l10110 110 10 11; //VVO6 -128=+0.956940 -0.290285 7'd42:b-tmpl =20'bOll111000101101010100; //W07_128=+0.941544 -0-336890 7, 7'd43:b-tmpl =20'bOl1011001_1100111100; /N08_128=+0.923880 -0.382683 7'd44, 7'd70:b-tmpl =20'bOll110011111100100101; I[W09 128=+0.903989 -0.427555 7'd8, 7'd45:b tmpl =20Mb111IOO01001100001111; //W1O_128=+0.881921 -0.471397 7'd46:b-tmpl =20M11ll11l01111011111001; //W11_128=+0.857729-0.514103 7'd9, 7'd47, *7'd71:b tmpl =20'bOll101010101011100100; //W12_-128=+0.831470 -0.555570 7'd48:b-tmpl =20'bOlIOOll1ll_1011001111; //W13_128=+0.803208 -0.595699 Td 1, WO 98/19410 PCT[US97/18911 7'd49:b tmpl =20'b0110001100_1010111011; /W1 4_128=+0.773010 -0.634393 7'd50, 7'd72:btmpl =20'b0101111011_1010101000; I/NV15_128=+0.740951 -0.671559 7'd 11, 7'dl:btmpl =20'b0101101010_1010010110; /NV16 128=+0.707107 -0.707107 7'd52:b-tmpl =20'bOl 01011000_1010000101; /Wi17_128=+0.671559 -0.740951 7

T

d 12, 7'd73, 7'd53:btmpl =20'bOlOlOO 010 1 001110100; /NV18_128=+0.634393 -0.773010 7'd54:b-tmpl =20'bOl001100011001100101; I/NV 9_128=+0.595699 -0.803208 7'd 13, 7'd55:btmpl =20'bOlOO011100_1001010110; /AI20_128=+0.555570 -0.831470 7'd74, 7'd56:btmpl =20'bOl00000111_1001001001; NV21128=+0.514103 -0.857729 7'd14, 7'd57:b tmpl =20'bOO110001 1000111100; INV22_128=+0.471397 -0.881921 7'd58:b-tmpl =20'bOOl 10110111000110001; /NV23 128=+0.427555 -0.903989 7'd15, 7'd75, 7'd59:b tmpl =20'bOO11000100 1000100111; 11W24128=+0.382683 -0.923880 7'd60:b-tmpl =20'bOOl01011001 l000011110; /NV25_128=+0.336890 -0.941544 7'd16, 7'd61: b-tmp 1=20'bOO 10010101_1000010110; INV26 128=+0.290285 -0.956940 7'd76, 7'd62:btmpl =20'bOOO1111100_1000001111; /NV27_128=+0.242980 -0.970031 7'd17, 7'd63:b tmpl =20'bOOOl 100100- 1000001010; /NV28_128=+0.195090 -0.980785 7'd64:btmpl =20'bO01l0010111000000110; /NV29_128=+0. 146730 -0.989177 7'd18, 7'd77, 7'd65:b tmpl =20'bOOOO110010 1000000010; //W30_128=+0.098017 -0.995185 7'd66:b-tmpl =20'bOOOOO 11001 1000000001; /1W31_128=+0.049068 -0.998795 7'dl9:b tmpl =20'bOOOOOOOOOO 000000000; /NV32_128=+0.000000 -1.000000 7'd78:b-tmpl =20'bl 11110011 11000000001; /NV33_128=-0.049068 -0.998795 7'd20:btmpl =20'bl 1110011101000000010; /NV34_128=-0.098017 -0.995185 7'd79, 7'd21:b tmpl =20'bl 110011100 1000001010; /NV36_128=-0.195090 -0.980785 7'd22:btmpl =20'b1101-101011 1000010110; /NV38_128=-0.290285 -0.956940 7'd80:btmpl =20'b110010100 1000011110; /NV39_128=-0.336890 -0.941544 7'd23:b-tmpl =20'bl 1001111001000100111; /NV40_128=-0.382683 -0.923880 7'd81, 7'd24:btmpl =20'bl 100001111_1000111100; NV42 128=-0.471397 -0.881921 7'd25:b tmpl =20'bl 011100100 -001010110; /=W44_128=-0.555570 -0.831470 7'd82:b tmpl =20'bl 011001111 1001100101; /JW45_128=-0.595699 -0.803208 7'd26: b tmpl =20'b1010110ll_1001110100; /NV46_128=-0.634393 -0.773010 7'd83, 7'd27:b tmpl =20'bl010010110 1010010110; //W48_128=-0.707107 -0.707107 7'd28:b-tmpl =20'bl001110100_1010111011; INV50_1128=-0.773010 -0.634393 7'd84:btmpl =20'bl001100101_1011001111; //W51_128=-0.803208 -0.595699 7'd29:b tmpl =20'bl0010101_10101100100; /1W52_128=-0.831470 -0.555570 7Td85, 7'd30:b tmpl =20'bl000111100 1100001111; /NV54_128=-0.881921 -0.471397 7'd31:b tmpl =20'bl00010011100111100; /NV56_128=-0.923880 -0.382683 7'd86:btmpl =20'b1 000011110_1101010100 /NV57_ 128=-0.941544 -0.336890 7'd32:btmpl =20'bl'000ll 101101101011; /NV58_128=-0.956940 -0.290285 7'd87, WO 98/19410 PCTIUS97/18911 96 7'd33:b tmpl =20'b1000001010 1110011100; //W60_1 28=-0.980785 -0.195090 7'd34:b -tmpl =20'blOOOOOO01lO 111100 1110; //W62_1 28=-0.995185 -0.098017 7'd88:b -tmpl =20'blOOOOOOO01ll 1111100111; //W63_128=-0.998795 -0.049068 7'd89:b -tmpl =20'bl 000000010 -0000110010; //W66_128=-0.9951 85 +0.098017 7'd90:b tmpl =20'blO000001111_0001111100; //W69 128=-0.970031 +0.242980 7'd91:b tmpl =20'blO000100111-0011000100; //W72128=-0.923880 +0.382683 7'd92:b -tmpl =20'blOOlO01lOf0100000111; //W75_128=-0.857729 +0.514103 7'd93:b tmpl =20'b1001110100F0101000101; //W78_128=-0.773010 +0.634393 7'd94:b tmpl =20'b1010101OOO 0101111011; //W81_128=-0.671559 +0.740951 7'd95:b -tmpl =20'bl 011100100 011010101; //W84_-128=-0.555570 +0.831470 7'd96:b -tmpl =20'b11lO100101 0111001111; //W87 128=-0.427555 +0.903989 7'd97:b -tmpl =20'b1101101011 0 11110 10 10; //W90_128=-0.290285 +0.956940 7'd98:b tmpl =20'b1110110101 0111111010; //W93_128=-0.146730 +0.989177 default:b -tmpl =20'bOl 111111 11_0000000000; /WOO_128=+1.000000 -0.000000 endcase always @(posedge cik) if (enable_3) b-tmp2 b-tmpl; assign out br b tmp2[c _wordlength*2-1 :c wordlength]; assign out-bi b tmp2[cword length-1: :01; endmod ule Listing 11 ISccsld: %G% Copyright 1997 Pioneer Digital Design Centre Limited Author Dawood Alam.

Description: Verilog code for a lookup table decoder.

Notes Used to generate addresses for each coefficient, based on the in -Address. Addresses are dependent on one of 4 rows (see figures) and on the sequence length (romAddressSize). Each row gives rise to a unique address sequence based on an algorithm. N refers to the index of the twiddle factor, NOT the absolute address. Breakpoints determine where inc values change on line 2.

'timescale i ns /O 0ps module ift-coeff-dcd (clk, enable_3, in_address, out -address, nrst); parameter ramAddressSize 1; HI Twice ROM address.

*parameter break point2 1; 2nd break pt line 2 parameter break point3 1; HI 3rd break pt line 2 input fromAddressSize-i in address; input clk, nrst, WO 98/19410 PCT/US97/18911 97 enable_3; output [rom_AddressSize-2:0] out_address; wire [rom_AddressSize-2:0] out_address; wire line_number; wire nrst; reg [rom_AddressSize-2:0] out_addresstmp; reg inc, count; reg rst; Decode which of the 4 lines are being addressed and assign it a line no.

I/ Only need upper two bits of in_address since 4 lines in sequence length.

assign line_number {in_address[rom_AddressSize-1], in_address[romAddressSize-2}; Check for end of line and force out_address to zero on next clock edge.

always @(in_address) if (in_address[rom_AddressSize-3:0] {rom_AddressSize-2{1'b1}}) rst 0; else rst 1; I/ Check for line number and decode appropriate outaddress using algorithm I/ derived by studying coefficient tables for mpys MO, M1 and M2.

always @(line_number or in_address or count) case (line_number) 2'd0: LINE 0, inc by 2, then run the inc sequence begin if (in_address[rom_AddressSize-3] begin if (count 2'dl I count inc 2'dl; else inc 2'd2; end else inc 2'd2; end 2'd1: LINE 1, inc by 1.

inc 1; 2'd2: LINE 2 inc by 3, (inc by 2 at (inc by 1 at N/2-1).

begin if (in_address[rom_AddressSize-3:0] break_point3) inc 2'dl; Third stage, inc by 1.

else if (in_address[rom_AddressSize-3:0] break_point2) inc 2'd2; Second stage, inc by 2.

else inc 2'd3; First stage, inc by 3.

end 2'd3: LINE 3,fixed at address 0.

WO 98/19410 PCT/US97/18911 98 inc endcase always @(posedge clk) if (enable_3) begin if (!nrst I !rst) I/ out_address=0 at end of line or pwr Reset.

out_address_tmp 0; else out_address_tmp out_address_tmp inc; Only count if at the correct point on line 2.

if (in_address[rom_AddressSize-3] count ((count 2'd2) 2'd0 count 2'd Only count to 2.

else count end assign outaddress out address_tmp; endmodule Listing 12 Sccsld: %G% Copyright 1997 Pioneer Digital Design Centre Limited Author Dawood Alam.

Description: Verilog code for a configurable 2K/8K radix 2^2 2, singlepath-delay-feedback, decimation in frequency, (r22+2sdf DIF) Fast Fourier Transform (FFT) processor. (RTL) Notes This FFT processor computes one pair of I/Q data points every 4 fast clk cycles. A synchronous active-low reset flushes the entire pipeline and resets the FFT. Therefore the next pair of valid inputs are assumed to be the start of the active interval of the next symbol. There is a latency of 2048/8192 sample points 7 slow clock cycles. This equates to (2048/8192 7)*4 fast clk cycles. When the out_ovf flag is raised an overflow has occured and saturation is performed on the intermediate calculation upon which the overflow has occured. If the valid in flag is held low, the entire pipeline is halted and the valid out flag is also held low. validout is also held low until the entire pipeline is full (after the above number of clock cycles).

To Do: RAM control (MUX), ROM lookup (quadrant lookup), Change BF code for unique saturation nets for synthesis.

ovf_detection (correct) register o/p ovf detection (correct) for mpy and BFs ROM/RAM test stuff.

1r I WO 98/19410 WO 9819410PCTIUS97/1891 1 'timescale 1 ns 1 Q0ps module fft-r22sdf (inx inxi, ci, n rst, in_2k8k, valid in, out-xr, out xi, out-ovf, enable_0, enable_1, enable_2, enable_3, valid out, ram address, ram enable, address rom3 address-rom4 z2r_4, z2i_4, z2i_5, z2r6, z2i_6, z2r_7, z2i_7, z2r_-8, z21-8, z2r z2i_9, z2r_10, z2i_1 xlr_4, xli_-4, xiL5, xl1r_6, xl1i_6, xlr 7, xli_7, xlr_8,xli1_8, X1lr_9, Xli_9, xli I br_3, bi_3, br_4, b i_4); IRAM input ports.

HI Output data from this Imodule.

0, HI RAM output ports.

/Input data to this Imodule.

Parameter definitions.

I

parameter parameter parameter parameter parameter parameter parameter H wordlength 12; IIData wordlength.

c wordlength 10; IICoeff wordlength.

Ad-dressSize 13; ISize of address bus.

romAddressSize 13; ROM address bus size.

mult-scale 3; 1/Multiplier scaling: I1 /4096, 2 =/2048, 13=1/1024, 4=1/512.

s12 -wdlength 11; IISectn 12 wordlength.

si lwydength 12; IISectn 11 wordlength.

sl s1 2 >=wordlen rnputIOutput ports.

WO 98/19410 WO 9819410PCTIUS97/1 8911 100 input clk, Master clock.

nrst, HI Power-up reset.

in_2k8k, /12K mode active low.

valid-in; IInput data valid.

0] in-xr, FFT input data, I.

in xi; IIFFT input data, Q.

input [9:1 input [word length- 1: 0] x1lr_4, x1i_4, xlr_6, xl1i_6, xl1r_7, xl1i_7, xlr_8, x1i-8, xlr xl1i_9, xlr_1 0, x1li_1 0; input [c _word length-1: br-3, bi_3, b r_4, b i_4; HI RAM output ports.

output out-ovf, enable_0, enable_1 enable_2, enable_3, valid -out, ram-enable; Overflow flag.

IEnable clock 0.

HI Enable clock 1.

HI Enable clock 2.

HI Enable clock 3.

HI Output data valid.

out xr, FIFT output data, I.

FFT output data, Q.

output [word length-1: :0] out-xi; HI output [word length- 1: 0] z2r-4 z2i_4, z2r z2i_6, z2r_7, z2i_7, z2i_8, z2r z2i_9, z2r_10, z2i_10; RAM input ports.

output [romAddressSize-6:0] address_rom3; output [romAddressSize-4:0] address_rom4; output [AddressSize-1:0] ram_address;

H'

HI

HI

Wire/register declarations.

wire control; HI cik decode.

wire [AddressSize-I address, FFT main address bus.

S, Pipeline SRs to BFs.

ram-address; RAM address bus.

wire [word length-1: :0] xlr_1, xli_1, x1lr_2, xli_2, x1lr_3, x1i3, xl1r_4, xl1i_4, x1 r_0, xl i_0, HI Couples-the IIQ data F1 outputs from the HI memory to the /respective butterfly HI processors, via an WO 98/19410 WO 9819410PCT/UJS97/1891 1 xl1i_5, Iinput register.

xl1r_6, xl1i_6, xl1r_7,xl1i_7, xl1r_8,xl1i-8, xl1r_9, xl1i-9, xlr_1 0, x1L_10, x2i_0, HI Couples the IIQ data x Fr_-1, x2i_I I outputs from BF21 x2r x2i_2, Ito the IIQ inputs of x2r_3, x2i_3, I BF2II. Also connects x2r_4,x2i_4, Ithe I/Q ouputs of the x2i_5, IIcomplex multiplier x2r_-6, x2i_6, /to the inputs of the x2r_7, x2i_7, IInext radix 2 A2 stage.

xfr_-8, xi_8, x2r_9, x2i_9, x2r_10, x2i_10; reg [word length- 1:0] x1lr4 tmp, x1li_4_tmp, Registered inputs x1li_65_imp, from _RAM~.

xlr_-6_-tmp, xli _6_tmp, xlr_-7_-tmp, x1li_7_tmp, xlr_-8_tmp, x1li_8 tmp, xlr_-9_tmp, xl1i_9_tmnp, xli_lf0tmp; wire [sl wdlength-1:0] x1lr 1, x1li_1 1, x2r_1 1, x2i_1 1; /for IIQ lines, wire [s12 wdlength-1:0]xlr_12, xli_12; Different bit-widths but similar to the above.

wire [word length- 1: 0] ar_1, ai_1, a r_2, a i_2, ar_3, ai_3, ar4 a i_-4, ai_5; a r_0, ai_0, Couples the l/Q data I1 outputs of the Iprevious radix 2 A2 Istage into the Icomplex multiplier of the next stage.

wire [cword length- 1:0] brO0, bi_0, Couples the I/O br_1, bi_1, IIcoefficient outputs Ur_-2, bi_2, Ifrom the ROM demnapper br_3, bi_3, /to the complex br_4, bi_4, IImultiplier.

wire [wordlength-1:0] z2rO0, z2 i_0, z2r_1, z2i_1, zfr_2, z2i_2, z2r_3, z2i_3; reg [word length- 1: 0] z2r_4, z2i_4, z2i_5, /to RAM.

z:Fr_6, z2i_6, z2 r_7,z2 i_7, z: r_8, Oi 8, z2r_9, z2i_9; Registered outputs WO 98/19410 WO 9819410PCT[US97/18911 102 wire [word length-1: z2rl1 0, z2i_1 0;iH WILL CHANGE WHEN RAM RIGHT 2 rg wire [word length-1: z2r 4tmp, z2i_4 tmp, Couple the IIQ data z2r 5tmp, z2i_5_tmp, HI outputs of each BF z~r_-6_tmp, z2i_-6_tmp, processor to their z2r_7_tmip, z2i_7_ tmp, HI respective memory z2r_-8_-tmp, z2i_8_tmp, H/inputs via an output z2r_9_tmp, z2i_9_tmp, HI register.

z2i_06_tmp; wire [sl wdlength-1:0] z2r_-11, z2i_1 1; wire [sl2-wdlength-1:0] z2r_12, z2i_12; Different bit-widths I/for the 1 st 2 stages.

wire wire wire wire wire wire wire wire from Add ressSize-8 :0] [rom AddressSize-6:0] [rom-AddressSize-4: 0] [rom-AddressSize-2 :0] from AddressSize-7: 0] from AddressSize-5: 0] from Add ressSize-3 :01 from Add ressSize-1 :0] address rom2; address rom3; address rom4; dcd address2; dcd address3; dcd address4; 1/ Couples the address HI decoders outputs to HI respective ROMs.

HI Couples part of the Iaddress bus to the Icoefficient decoder.

wire ovf_0, ovf_-1, Couples overflow ovf_2, ovf_3, H/flag outputs from ovf_4, ovf_5,I each butterfly ovf_6, ovf_7,I processor and complex ovf_8, ovf_9,I multiplier into one ovf_1 0, ovf_ 11, IIoverflow status flag ovf_ 12, ovf_13, Icalled "out ovf'.

ovf_ 14, ovf_ 16, ovf_ 17, ovf_18; wire clk, nrst, in_2k8k, ovf_2k, out ovf, enable_0, enable_1, enable_2, enable_3, ram-enable; II RAM enable signal.

reg ovf -tmpl, ovf-tmp2, fft_cycle complete, I/End of 1st FF output-valid; IIOutput valid flag.

reg pipeline_count; IICounts pipe reg [AddressSize-1:0] q, t; reg r; reg [word length- 1:0] xlr_0_reg, xli_0_reg, xr-tmp2, bII uput data reg, 1.

xi tmp2; Output data reg, Q.

reg [sl2..wd-length-1:0] in_xr-tmp, in_xi-tmp; rcycle.

line regs.

WO 98/19410 PCTIUS97/18911 103 reg xrjreg, /Input data reg, 1.

xi_reg; H/Input data reg, Q.

reg [word length- 1: 0] x2r- lOtmp2, x2i_10_-tmp2, x2r10-tmp3, x2i_10_tmp3; wire [word length- 1: 0] xr tmpl, /Final BF2(O) out, 1.

xi-tmnpl; II Final BF2I(0) out, Q.

wire [word length- 1: 0] x2 r 10_-tmpl1, x2i_ 10 Otm pl; wire [s12 wdlength-1:0] x2r_1 tmnp, x2Ji_tmp; H HI Address decoders/Quad rant mappers pipeline shift registers.

1* itsr-addr #(rom AddressSize-6, 3) sr addr_2 (cik, enable_3, H/Input.

dcd-address2); HI Output.

ffi -coeff dcd #(romAddressSize-6, 11, 21) coeff-dcd_2 (clk, enable_3, dcd-address2, address-rom2, nrst); ift-sr-addr #(rom AddressSize-4, 2) sr-addr_3 (cik, enable_3, /Input.

dcd-address3); HI Output.

ift -coeff-dcd #(romAddressSize-4, 43, coeff-dcd_3 (clk, enable_3, dcd-address3, address_romn3, nrst); H fisr-addr #(rom AddressSize-2, 1) sr-addr_4 (clk, enable_3, addressilo:0], /Input.

dcd-add ress4); Output.

fit coeff dcd #(rom_ AddressSize-2, 171, 341) coeff-dcd_4 (clk, enable_3, dcd-address4, address-rom4, nrst); H I* ift coeff dcd #(romAdd ressSize, 683, 1.365) (clk, enable_3, address, address-rom5, nrst); HI ROM lookup tables.

ffi-hardwired l uO _word length, rom_ -AddressSize-10)II Case table instance romnO (clk, enable_3, address[2:0I, br_0, biJ); /for a hardwired ROM.

ift -hardwired -lul #(c_word length, rom_ AddressSize-8) HI Case table instance romi (clk, enable_3, address[4:0], br_1, bil1); I/for a hardwired ROM.

WO 98/19410 PCTIUS97/18911 104 fft hardwiredjlu2 -wordlength, rom_-AddressSize-6) Case table instance rorn2 (cik, enable_3, add ress[6: b r_2, b I/for ahardwired ROM.

/*ffl hardwiredjlu3 _word length, romAddressSize-4) Case table instance rornT3 (cik, enable_3, address[8:0], br_3,bi_3); //for a hardwired ROM.*/ ft hardwiredjlu3 _wordlength, romAddressSize-5)/I Case table instance rorn3 (cik, enaibl e_3, add ress_rom3, br_-3, bi_3); I/for ahardwired ROM.*/ /*fft-rom _wordlength, rom_-AddressSize-6, "..I../..Ifft/srcllookup_tables/ lu l0bit l28ptscalel") rom2 (address[6:O], br_2, bi_2);I/ 128 addresses x 20 bits, no decode. I*fft-rom _word length, romAddressSize-7, "..I..I..Ifftlsrcllookup tables/lu l0bit l28ptscalel") rom2 (address-rom2, br_2, 64 addresses x 20 bits, coeff decode. I*fft-rom #(c_word length, rom_-AddressSize-4, '../..I..Ifft/src/lookup tables/lu l0bit 5l2ptscalel") rom3 (address[8:0], br_3, bi_3);I/ 512 addresses x 20 bits, no decode. r* ift rom #(c_word length, ".7./.*./ffi/src/lookup tables/lu -1 Obit 51 2pt scalelI") rom3 (clk, enable_3, address-rom3, br_3, bi_3); 256 addresses x 20 bits.*/ I*fft-rom #(c_wordlength, rom_-AddressSize-2, "..I../../fftlsrc/lookup tables/ lu -l1Obit_-248ptscalel") rom4 (address[1 br_4, bi_4); /2048 addresses x 20 bits, no decode. fft rom _word length, romAddressSize-3, ./fft/src/lookup__tables/lu_ O 1bit 2048pt scale 1") rom4 (clk, enable_3, address-rom'4, br_4, bi_4); //f1024 addresses x 20 bits.*/ /*fft-rom #(c_word length, romAddressSize, "../../../fft/src/lookup tables/lu l0bit 8l92ptscalel') (address, br_5, bi_5); 8192 ad-dresses x 20 bits, no decode. I* Mf rom _word length, romAddressSize-i, LL.. /fft/src/lookup tables/lu_-1 Obit -8 192pt scalel1") rom5 (clk, enable_3, address_romS, br_5, bi_5); 4096 addresses x 20 bits.*/ //Section 12 and 11, tail end of FFT pipeline (input stage).

/Section 12 is 11 bits wide and incorporates the 2K/8K control logic.

always @(xr reg or xi reg or in_2k8k or x2r_10 tmpl or x2ilo 0tmpl or x2r_10 tmp3 or xi_ 0 tmp3) if (!in_2k8k) Configuring for 2K mode.

begin x2r_-10_-tmp2 =x2r 10 tmp3; x2i10_-tmp2 x2ii1o-tmp3; in xr tmp =0; in -xi -tmp =0; end else 1/Configuring for 8K mode.

WO 98/19410 PCTIUS97/18911 105 begin x2r -10 -tmp2 =x2r_10_tmpl; k2il 10tmp2 =x2i_1 0_tmpl; /Sign extend from 10 bits, as section 12 is s12_-wdlength bits.

in-xr-tmp {{(s12 wdlength-9){xr-reg[9]}},xr in -xi -tmp {{(s12..wdlength-9){xireg[9]}},xi-reg[8:0]}; end always @(posedge cik) Pipeline register to enable correct operation in if (enable_3) /2K mode without retiming the entire pipeline since begin 8K mode introduces 1 additional pipeline register.

/Sign extend 10 bit inputs to wordlength bit inputs.

I/for bypass lines into stage x2rI O 0-tmp3 {{(word ength -9){xr -reg[9]}},xr-reg[8:oJ}; x2i_-10_-tmp3 {{(word length -9){xi reg xi_reg end assign x2r1 10 x2r-1l0tmp2; assign x2i1 10 =x2i-1l0tmp2; ISign extend from s12_wdlength bits to si 1_-wdlength bits between Isections 12 and 11. Uncomment below if s -11 >s_12.

assign x2rl1 1 1_wdlength-sl2 wdleigth+1) {x2rl 11tmp[s12 wdlength-1]},x2r_11_tmpsl2 assign x2Ll {(sll- wdlength-sl12 wdlength+1) {x2i-l ltmp[s12wd length- i_1 1 _tmnp[s12-wd length-2: IUncommentf below if-s 1 s_1 2.

1* assign x2r_11 =x2r_11_tmp; assign x2il I x2i_1_1_tmp; fft-bf2l 12_-wdlength) bf2I16 (clk, enable_1, xlr_-12, xli_12, in-xr-tmp, in xi tmp, /Ext In.

s[12], x2r_- 1_tmp, x2i_11_tmp, z2r_12, z2i_12, //Outputs.

ovf_1 8); 1* ffi-r rm 12_-wdlength, 12) ram_12 (clk, enable_1, enable_3, ram -address[1 4096 addrs.

z2r_-12, z2i_12, IInputs.

xlr _12, xli_12); IOutputs. fftbf2ll #(sl1-wdlength)b2l_6 (clk, enable_1, xlr_-11, xli_1 1, x2r_ 1, x2i_1 1, HI Inputs.

s[1ll], s[12], ai_5,z2r_1 1, z2i_11, IOutputs.

ovif_17); ift sr 1lbit sr 1ibit 11 (clk, enable_3, address[l1] s[11]) /SIR 11.

ififsri1bit sr1 ibit 12 (clk, enable_3, address[1 s[1 I/SIR 12.

r* ffi ramn #(sl 1_wdlength, 11) ram_1 1 (clk, enable_-1, enable_3, ram -address[1 H/2048 addrs.

z2r_-11, z2i_1 1, I/Inputs.

X1lr_11, x1li_1 I/Outputs. WO 98/19410 WO 9819410PCTIUS97/1891 1 106 Section 10 and 9.

ificomplex-mult-mux #(wordlength, (cik, control, ai_5, br_5, bi_5, x2rl10-tmpl, x2i_l 0tmnpl, ovf_ 16); c-wordlength, mult-scale) IInputs.

II Outputs.

ffi-bf2l #(wordlength) bf21_5 (cik, enable_1, x1lr_10, xli-1 0, H/Inputs.

x2i_10, s[1 x2r_9, x2i_9, I/Outputs.

z2r_10, z2i_10, fft-bf2ll #(wordlength) bf2l115 (cik, enable_1, x1lr 9tmp, x1 i_9 tmp, IInputs.

x Fr_9, x2i_9, s19], a r_4, ai_4, IIOutputs.

z2r_9_tmp, z2i_9jtmp, OVf 1-4); ift sr 1lbit fftsrl bit sr-1ibit_9 (clk, enable_3, address[91, SIR 9.

sr_I bit- 10 (clk, enable_3, address[1 s[ I/SIR Section 8 and 7.

ffi-complexmult-mux #(wordlength, c-wordiength, multscale) m4 (clk, control, ar 4, ai-4, br 4, bi-4, Inputs.

x2r x2i 8, H Outputs.

ovf-1 3); fft-bf2l #(wordlength) bf2I-4 (clk, x1 r 8 tmp, A i_8 tmp, xfr 8, x2 i_8, s[8], x2r 7, x2i 7, HOu zfr 8 tmp, z2i_8-tmp OVf f-2)7

I

enable 1, Inputs.

tputs.

I

fft-bf2ll #(wordlength) bf2II-4 (clk, enable_1, x1 r 7 tmp, x1 i-7-tmp, Inputs.

x r 7 x2i 7, i[6], ar 3, ai-3, Outputs.

i2r-7 tmp, z2i-7-tmp, OVf 11)7

I

WO 98/19410 PCTIUS97/18911 107 Mf sr 1 bit sri1 bit 7 (cik, enable_3, address[7], IR 7.

ififsrI bit sri1 bit-8 (cik, enable_3, address[8], IR 8.

HI---I II Section 6 and itcomplex_mult mux #(wordlength, c-wordlength, mult scale) m3 (clk, control, ar ai-3, br_3, bi_3, H/Inputs.

x2r_6, x2i_-6, II Outputs.

ovf_ fft-bf2l #(wordlength) bf2l_3 (clk, enable_-1, x1lr 6tmp, x1li 6 tmp, I/Inputs.

x:Fr_6, x2i_6,x2r 5, x2i-5, IIOutputs.

z:Fr_-6_-trp, z2i_6_tmp, ovf_9); fft-bf2ll #(wordlength) bf2ll13 (clk, enable_1, xlr 5 tmp, x1li_5 tmp, H/Inputs.

xfr_-5, s[6], a r_2, a i_2, HI Outputs.

i2 r_-5_-tmp, ovf_8); ift sr 1ibit sr 1ibit 5 (clk, enable_3, address[5], IR ffttsr-1ibit sr1 ibit_6 (clk, enable_3, add ress[6], IR 6.

HI Section 4 and 3.

itcomplex-mult-mux #(wordlength, c-wordlength, mult-scale) m2 (clk, control, ar_2, ai 2, br 2, bi_2, I/Inputs.

x2r_4, x2i_-4, HI Outputs.

ovf_7); ffi-bf2l #(wordlength) bf2l_2 (clk, enable_1, x1lr 4tmp, x1li_4_tmp, H/Inputs.

xfr_-4, x2i_4, x2r_3, x2i_3, HI Outputs.

zfr_4_tmp, z2i_4_tmp, ovf_6)-; ffibf2ll #(wordiength) bf2II_2 (clk, enable_1, x1lr 3, x1 i3, IIInputs.

x2r 3, x2i_3, s[4], ar_1, aiI, H Outputs.

WO 98/19410 WO 9819410PCTIUS97/1891 1 108 z2r_3, z2i_3, Mfi sr i 1bit sr l 1bit -3 (cik, enable_-3, address[3], IR 3.

fftsrl1bit sr1 lbit-4 (cik, enable_3, address[4], IR 4.

fft-sr-iq #(wordlength, 8) sr iq_3 (cik, enable_3, z2r z2i_3, H/Inputs.

xl1r_3, x1i_3); HI Outputs.

Length 8.

Section 2 and 1.

fficomplex -mult mux #(wordlength, c-wordlength, mult-scale) ml (clk, control1, ar_1, ai_1, br_1, x2r_2, x2i_2, ovf_4); bi_1, H/Inputs.

II Outputs.

fft-bf2I #(wordlength) bf2l (clk, enable_1, x1lr_2, xli_2, HI Inputs.

2 2i_2, s[I2], x2r_1, x2i_1, H/Outputs.

2r2, z2i_2, ovfJ3); ffi-sr-iq #(wordlength, 4) z2r_-2, z2i_2, xl1r_2, x i2); sr iq_2 (clk, enable_3, 7Inputs.

IOutputs.

HI Length 4.

fft-bf2ll #(wordlength) bf2Il (clk, enable_1, xlr l,-xi 1, I nputs.

xfr_1, x2i_1, arO, ai_0, /Outputs.

i2 z2i_1, ovf_2); assign s[1] -address[i]; Invert s[1] (see count sequence), SRi not req.

//fft -sr i 1bit sri1bitl (cik, enable_3, address[i s[1 /SIR 1.

ift-srI bit sri1 bit-2 (cIk, enable_3, add ress[2, SIR 2.

ffi-sr-iq #(wordlength, 2) z2r_-1, z2i_1, xlr_1l xliil); sr iqil (cik, enable_3, 7 /Inputs.

HI Outputs.

HI Length 2.

H HI Section 0, front end of FFT pipeline (output stage), mult scale=4.

HI ift complex_mult mux #(wordlength, c-wordlength, 4) mO (cik, control1, ar 0, ai 0, brO0, bi_0, I/Inputs.

x2r 0T x2i_, IIH Outputs.

I WO 98/19410 W098/9410PCTIUS97/1891 1 109 ovf_1); iftbf2l .#(word length) bf2l 0 (clk, enable_1, x1lr 0, xli-0, H/Inputs.

x: r xr tmpl, xi-tmpl, HI Outputs.

ovf_0); assign silo] address[0]; /Invert sEQI (see count sequence), SRO not req.

//fft-sr-1ibit sr1 Ibit-0 (cik, enable_3, address[0], /SR 0.

Last stage should be just a single register as only 1 location needed.

always @(posedge clk) II No reset required as data clocked through registers.

if (enable_3) begin xlr_0_Oreg xli_0_Oreg z2i-O; end assign xlr-O xlr-_reg; assign xliO0 xli-O_reg;

HI

H' Register Inputs/Outputs.

'ifdef BINSHIFT always @(posedge clk) IIRegistered inputs.

if (enable_3 !address[0]) I =freq bin shift by pi.

begin xr-reg in-xr; xi -reg in_xi; end else if (enable_3 add ress[0]) =freq bin shift by pi.

begin xr-reg -in-xr 1'bl- IThis is equivalent to multiplying by xi -reg -in xi 1 'bi; IIexp(-j pi n) )An.

end 'else always @(posedge clk) IIRegistered inputs.

if (enable_3) begin xr-reg in-xr; xi -reg in xi; end endif always @(posedge clk) if (enable_3) begin xr-tmp2 xr-tmpl; xi -tmp2 xi-tmpl;end Registered outputs.

WO 98/19410 WO 9819410PCTIUS97/1891 1 110 assign out xr xr-tmp2; assign out-xi xi_tmp2; always @(posedge cik) II RA~s are latched on outputs so no begin need to enable.

z2r 4 z2r_4_tmp; IIRegister FFT outputs to RAM.

z2i -4 z2i -4 -tmp; z2r -5 z2r -5 tmp; z2i z2i -5 -tmp; z2r-6<= z2r-6tmp; z2i -6 z2i -6 -tmp; z2r-7 z2r-7tmp; z2i -7 z2i_-7_-tmp; z2r-8 z2r-8_-tmp; z2i-8 z2i -8 -tmp; z2r-9 z2r-9tmp; z2i 9 z2i_9_tmp; Izfr_10<=z2r_1 l tmp; Iz2i 10 z2i10 tmp; xlr_'4_-tmp xlr..4; IRegister FFT inputs from RAM.

xli -4 tmp x1L4; xlr 5 -tmp xli -5tmp<= xlr_-6_-tmp xlr6; xli -6 -tmp xli6; xlr -7 tmp x1lr7; xli -7_tmp<= x1 i_7; xlr -8 tmP AlrB8; x1i -8tmp<= x1i_8; xlr_9_-tmp xlr9; xli 9 tmp Xli-9; xI xlr -10 -tmp Alr_1 0; X1 xi -10 -tmp end II Synchronous butterfly controller.

always @(posedge cik) if nrst) IISynchronous power-up reset.

q 0; else if (enable 3) q +1'b1; assign address q II Synchronous RAM address generator.

always @(posedge clk) if (!nrst) IISynchronous power-up reset.

t<=0 else if (enable 2) WO 98/19410 PCTIUS97/18911 111 t t 1'bl; assign ram_address t; assign ram_enable enable_3 11 enable_2; ram enable signal.

H valid_out status flag generation.

always @(posedge clk) if (!nrst) fft_cycle_complete 1'b0; Detect end of 1 st fft cycle i.e. 2K or 8K.

else if ((~in_2k8k &address[10:0]) I (in 2k8k &address[12:0])) fft cycle_complete 1'bl; else fft_cycle_complete fft_cycle_complete; always @(posedge clk) II Account for pipeline and I/O registers.

if (!nrst) pipeline_count 4'b0; Stop at pipeline depth 1.

else if (enable_3 fft cycle_complete pipeline_count 8)//pipe depth=8 pipeline_count pipelinecount 1'bl; always @(posedge clk) Test if the pipeline is full and the input if (!nrst) is valid before asserting valid out.

output_valid else if (enable_2 pipeline_count[3]) output_valid 1'bl; else output_valid assign valid_out output_valid; Fast 40 MHz clock decoder and valid in control.

always @(posedge clk) if (!nrst) //Synchronous power-up reset.

r<=0; else if (valid_in) Count if input data valid.

r r 1'bl; assign control {valid_in r[1],valid_in assign enable_0 valid in //Gate valid in with assign enable_1 valid_in decoded enable signals assign enable_2 valid_in to control all reg's.

assign enable_3 valid in r[1] II Overflow detection, OR overflows from each stage to give overflow flag.

assign ovf 2k ovf_0 I ovf_1 II ovf 2 I ovf 3 )1 ovf_4 II 1 ovf_6 II ovf 7 ovf 81 ovf__9 WO 98/19410 PCT/US97/18911 112 ovf 11 I ovf 12 II ovf 1311 ovf14 11 I/ 2k/8k Overflow flag configuration.

always @(in_2k8k or ovf_16 or ovf_17 or ovf_18 or ovf_2k) if (in_2k8k) ovftmpl ovf_2k I I ovf_16 11 ovf_17 II ovf_18; else ovf_tmpl ovf_2k; always @(posedge clk) Register overflow if (enable_3 fft_cyclecomplete) flag to change when ovf_tmp2 ovf_tmpl; I/Q samples are valid from FFT processor.

assign out_ovf ovf_tmp2; 'ifdef OVERFLOWDEBUG Debug code to display overflow output of a particular instance.

Concurrently monitor overflow flag and halt on overflow.

always @(out_ovf) ovf_x wires are all registered at lower level.

if (out_ovf) begin $display ("Overflow has occurred, type to continue."); $display ("Overflow flag, out_ovf ",outovf); if (ovf_18) $display ("Overflow on port ovf_18"); if (ovf_17) $display ("Overflow on port ovf_17"); if (ovf_16) $display ("Overflow on port ovf_16"); if (ovf_15) $display ("Overflow on port if (ovf_14) $display ("Overflow on port ovf_14"); if (ovf_13) $display ("Overflow on port ovf_13"); if (ovf_12) $display ("Overflow on port ovf_12"); if (ovf_1 1) $display ("Overflow on port ovf_11"); if (ovf_10) $display ("Overflow on port if (ovf_9) $display ("Overflow on port ovf_9"); if (ovf_8) $display ("Overflow on port ovf_8"); if (ovf_7) $display ("Overflow on port ovf_7"); if (ovf_6) $display ("Overflow on port ovf_6"); if (ovf_5) $display ("Overflow on port if (ovf_4) $display ("Overflow on port ovf if (ovf_3) $display ("Overflow on port ovf_3"); if (ovf_2) $display ("Overflow on port ovf_2"); if (ovf 1) $display ("Overflow on port ovf_1"); if (ovf_0) $display ("Overflow on port ovf_0"); $stop; end 'endif endmodule Listing 13 Sccsld: %G% Copyright 1997 Pioneer Digital Design Centre Limited Author Dawood Alam.

Description: Verilog code for the window lookup table, used to determine the WO 98/19410 113 variance of the data and hence the F-ratio.

Notes PCT[US97/1 8911 'timescale 1ins /1Ops module iftwindow-lu (cik, enable_3, in_address, out-data); parameter r-wordlength =10; HI Data word length.

parameter IuAddressSize 13; /Address bus size.

input cik, enable_3; input [lu AddressSize-i in address; output [r _word length-1: out-data; reg [rword length-1: data tmpl, data-tmp2; always @(in_address) casez (in address) 13'bOOOOOOOOOOOOO data-tmpl 13 t b0000000000001: data' tmpl 13'b0000000000010: data-tmpl 13'bOOOOOOOOOOl 1:data-tmpl 13'b0000000000100: data-tmpl 13'b0000000000101: data-tmpl 13'b00000000001 10:data-tmpl 13'bOOOOOOOOOOl11:data-tmpl 13'bOO0000OO0lOOO data-tmpl 13'bOOOOOOOO0lO0l :data-tmpl 13'bOOOOOOOO0l1lO data-tmpl 13'bOOOOOOOll 011data-tmpl 13'bOOOOOOOO0llO 10 data-tmpl 13'bOOOOOOOO 101data-tmpl 13'bOO00OOOO01l110 data-tmpl 13'bOOOOOOOOll 111data-tmpl 10'b10O0000000; 10'b0000000000; 10O'bOOOOl100l11; 10'bOOO01l11110; l0'bOO0lO0lllO; 10'bOO0l0ll0ll; 10'bOO0llO0llO; 10'bOO0ll0lllO; 10'bOO0lll0llO; 1 O'bOO01l111101; 10'bOOlOOOO0ll; 10'b0010001000; 10'bOOlOO0ll0l; 10'bOOlO0lOO0l; 10'bOOlO0l0llO; 10'b0010011010; WO 98/19410 WO 9819410PCTIUS97/18911 114 13'b0000000010000: data-tmpl 13'b0000000010001: data-tmpl 13'b0000000010010: data-tmpl 13'b0000000010011 data-tmpl 13'b0000000010100: data-tmpl 13'bOOOQOOO0l0l0l data-tmpl 13'b0000000010110 data-tmpl 13'b000000001 0111 :data-tmpl 13'bOOOOOOOO 11000 data-tmpl1 13'b000000001 1001 :data-tmpl 13'bOOOOOOOOl110l1 data-tmpl1 13'bOO00O0OO1l1011 data-tmpl 13'b00000000 11100:data-tmpl1 13'b000000001 1101 :data-tmpl 13'bOOOOO00lll111 data-tmpl 13'b000000001 1111 :data-tmpl 13'b00000001 00000 data-tmpl 13'bOOOOOO0l 00001 data-tmpl 13'bOOOOOO0lOO0lO: data-tmpl 13'bOOOOOOlOOl 1:data-tmpl 13'bOOOOOO0l 00100 data_tmpl 13'bOOOOOO0lO0l0l data-tmpl 13'bOOOOOO0lO0llO data-tmpl 13'bOOOOOOOl 00111 data-tmpl 13'bOOOOOOOlOiOaO data-tmpl 13'bOOO000010i0ai data-tmpl 13'bOOOO~oololoio data-tmpl 13'bOOOOOOol oil :data-tmpl 10'bOOlO0lll0l; 10'bOOl0lOOO0l; 10'bOOl0lO0lOO; 10'bOOl0lO0lll; 10'bOOl0l010lO; =10'bOOl0l0ll0l; =10O'b001 0101111; 10'bOOl0llO0lO; 10'bOOl1ll1l 00; 10'bOOl0ll0lll; 10'bOOl0lllO0l; 10'bOOl0lll0ll; 10O'bOOl 0111101; 10'bOOl0llllll; 10O'bOOl1100000l; 10O'bOOl110000l1; 10O'bOOll1000101; 10'bOOllOO0llO; 10O'bOOll100100; 10'bOOllO0l0lO; 10O'bOOll1001011; 10O'bOOll1001101; 10'bOOllO0lllO; 10O'bOOl110 1000; 10O'bOOll1010001; 10O'bOOll1010011; 1 O'bOOll1010100; 10'bOOll010l0l; WO098/19410 13'bOOOOOO01l01100O data-tmpl PCTIUS97/1 8911 13'b00000001 01 101 13'b0000000 10 1110 13'b0000000101 111 13'b0000000 10000 I 3'b0000000 11000 1 I 3'b0000000 110010 13'bOOOOOO0l 10011 1 3'bOOOOOO0l 10100 13'bOOOOOO0l 10101 13'b00000001 10110 13'bOOOOOO0ll1 11 13'bOOOOOOOl 111000 13'bOOOOOOOl 11100 1 13'bOOOOOO0l 11010 13'bOOOOOO0l 11011 13'bOOOOOOOl 111100 13'bOOOOOO01l11101 13'bOOOOOO0l 11110 13'bOOOOOO0l 11111 I 3'bOOOOO0l 000000 I 3'bOOOOO0l 000001 1 3'bOOOOO0l 000010 1 3'bOOOOO0l 000011 1 3'bOOOOO0l 000100 1 3'bOOOOOO 1000101 I 3'bOOOOO0l 000110 13'bOOOOO01l000111 data-tmpl data-tmpl data-tmpl data-tmpl data-tmpl data-tmpl data-tmpl data-tmpl data-tmpl data-tmpl data-tmpl data-tmpl data-tmpl data-tmpl data-tmpl data-tmpl data-tmpl data-tmpl data-tmpl data-tmpl data-tmpl data-tmpl data-tmpl data-tmpl data-tmpl data-tmpl data-tmpl 115 10'bOOll0l0lll; 10O'bOOll1011000; 10'bOOll0llO0l; 10'bOOll0ll0lO; 10O'bOOll1011100; =10O'bOOll1011101; =10O'bOOll1011110; 10'bOOll0lllll; 10O'bOOl11100O00; 10O'bOOl1110000l; 10'bOOll1100010; 10O'bOOll1100011; 10O'bOOll1100100; 10'bOOll1100101; 10ONl1100110; lO'bOOll1100111; 10'bOOll1101000; 10O'bOOll1101001; 10O'bOOll1101010- 10O'bOOll1101011; 10O'bOOll1101100; 10O'bOQ1l1101101; 10O'bOOll1101110; 10O'bOOll1101111; 10O'bOO1 1101111; 1l0'bOOl11110000; 10O'bOOll1110001; =10ONl1110010; 13'bOOOOO0lO0lO0z: data-tmpl 10'bOOl 1110011; WO 98/19410 WO 9819410PCTIUS97/18911 13'b0000001001010: 13'b0000001001011 13'b000000 100 11Oz: 13'bOOOOOO 00111 13'b0000001001111 13'b000000101000z: 13'b0000001010010: 13'b0000001010011 13'b0000001010100: 13'b0000001010101 13'bOOOOO0l0l0llz: 13'bOOOOOOQ1100 13'b0000001011001 13'bOOOOO0l1ll1lO: 13'bOOOOO0l0ll0ll 13'bOOOOO0l0lll0z: 13'bOOOOO01l0111lz: 13'bOOOOOO 1100000: l3 t bOOOOO0llOOO0l 13'bOOOOO0ll100010 13'bOOOOO0llOO0ll 13'bOOOOOOl1100l100 13'bOOOOO0llO0l0l 13'bOOOOOOl11001O0 13'bOO0OO0llO0lll 13'bOOOOO0ll0lO0z: 13'bOOOOO0ll0l0lz: 13'bOOOO0ll0ll0z: 13'bOOOOO0ll0lllz: 13bOOOOOOl111OOOz: 13'bOOOOOO11100 1z: data-tmpl data-tmpl data-tmpl data-tmpl data-tmpl data-tmpl data-tmpl data-tmpl data-tmpl data-tmpl data-tmpl data-tmpl1 data-tmpl data-tmpl data-tmpl data-tmpl data-tmpl data-tmpl data-tmpl data-tmpl data -tmpl data-tmpl data-tmpl data-tmpl data-tmpl data-tmpl1 data-tmpl data-tmpl data-tmpl data-tmpl data-tmpl 116 10O'bOOll1110100; 10O'bOOll1110101; 10'bOOllll0llO; 10O'bOOll1110111; 10O'bOOll1111000; 10'bOOll1111001; 10'bOOll1111010; 10'bOOll1111011; 10O'bOOll1111011; 10'bOO1lllllOO; 10O'bOOll1111101; 10'bOlOOOOOO0l; 10'bOlOOQOO0lO; 10O'bO1lOOOOO1l1; 10'bOlOOOO0l 00; 10'bOlOOOO0l 00; 10'bOlOOOO0l0l; l0 t bOlOOOO0l0l; 10'b010O000110; 10O'bOlO00000110; 10O'bOlO00000111; 10'bOlOQO00lOO; 10'bOlOOO0lO0l; 10'bOlOOO0l0lO; l0 t bOlOOO0l0ll; 10'bOlOOO0llOO; 10'bOlOOQ0ll01; WO 98/19410 W098/9410PCTIUS97/1 8911 117 13'b000000 1110 1Oz :data-tmpl1 13'bOOOOO0lll0llz: data-tmpl 5 13'bOOOOOOl1111OOz :data-tmpl1 13'bO00001 11101lz: data-tmpl 13'b000000 111110Oz data-tmpl1 13'bOOOOOOl111110 data-tmpl1= 13'bOOOOO0ll111111:data-tmpl 13'bOO00O1l0O00OOO data-tmpl 13'b000001 0000001: data-tmpl 13'bO000010000010: data-tmpl 13'b0000010000011: data-tmpl 13'b0000010000100: data-tmpl 13'bOO000lOOO0lzl data-tmpl 13'b0000010000 110:data-tmpl1 13'bOOOO0lOO0lO0z: data-tmpl l3'bOO00lOl0z: data-tmpl 13'b000001000 1100-: data-tmpl1 13'bOOOO01lO01 101 data-tmpl 13'bOOOlOOlll: data-tmpl 13'bOOOOOl0001111l data-tmpl1 13'bQOOO00lO0lOO0z: data-tmpl 13'bOOOO0lO0lO0lz: data-tmpl 13'bOO0O0lO0l0l0z: data-tmpl 13'b0000010010110: data-tmpl 1 Ob~ll0000111; 1 0'bOl 0001000; 00010001; 10'bOlOO0lO0lQ; 10'bOlOO0l 0010; l0'bOl 00010011; 10'bOlOO0lO0l 1; 1 0'bOlOO0l0l 00; 1 0'bOlOO0l1l 00; 10'bOlOO0l0l0l; 10ObOlOOl 0101; 10'bOlOO0l1l 10bOlO00010110; 10'bOlOO0001110; 1 0'bOl 00011000; 10'bOlO00011000; 10'bOlO00011001; 10'bOlO00011001; 1ObOlO00011010; 10'bOlO00011010; 10'bOlO00011011;1 1 Obl001100; 10'bOlOO0l11100; 13'bOOOOOl100l10l11 data-tmpi1 10'bOl1000l1110l; 13'bOOOOOl100 11OOz: data-tmpl1 10'bOlOO01l1101; 13'bOOOO0lO0ll0lz: data-tmpl 10'bOlOO0llllO; 13'bOOOOOl00l111Oz :data-tmpl1 10'bOlOO0lllll; 13'bOOOO0lO0llllO: data-tmpl 13'bOOOO01l0011111l data-tmpl =10'bOl 00100000; 13'bOOOOOI0lOOO0z: data-tmpl l'bOlOOlOOOOO; 13'bOOOO0l0lOO0lz: data-tmpl 10'bOlOOlOOO0l; 13'bOOOO0l0lO0lOO data-tmpl 10'bOlOOlOOO0l; 13'bOOOO0l0lO0lzl data -tmpl =10'bOlOOlOO0lO; 13'bOOOO0l0lO0llO data-tmpl =10'bOlOOlOO0lO; WO 98/19410 WO 9819410PCT/US97/1891 1 13'b000001010100z 13'b0000010101010 13'b000001 010101 1 13'bOOOOOl10l0 11Oz 13'bOOOO01l0101 liz 13'b000001 01 10000 13'bOOOOOl101lO0zl 13'bOOOO0l0l 10010 13'b00000101 101 Oz 13'bOOOO0l1 010110 13'bOOOO0l0l 10111 13'bOOOO0l0l 1 1O0z 13'bOOOO0l0l 1 101z 13'bOOOOOl10l1111Oz 13'bOOOO0l1l 11 liz I 3'bOOOO0l 1000000 1 3'bOOOO0l 1 OOO0zl 1 3'bOOOO0l 1000010 13 'bOOOO0l lOO0lzz 13'bOOOO0l 1001lOOz l3 t bOOOO0l 1001010 13'bOOOO0l 1001011 13'bOOOOO 10011 Oz 13'bOOOO01l1001110 13'bOOOOO 100 1111 I 3'bOOOO0l 101 OOOz 13'bOOOO01l1010010 13'bOOOO0l 1010011 13'bOOOO0l 10101lOz 13'bOOOO0l 101011 z 13'bOOOOOl110 11OOz 13'bOOOO01l0110 l~z 13'bOOOO0l 10111 oz 13'bOOOO01l101111z I13TbOOOOOl 111 OOOoz 13'b000001 110001lz 13'bOOOO01l11001Oz 13'b000001 11100-1 z :data-tmpl data-tmpl data-tmpl data-tmpl data-tmpl data-tmpl data-tmpl data-tmpl data-tmpl data-tmpl data-tmpl data-tmpl data-tmpl data-tmpl data-tmpl data-tmpl data-tmpl data-tmpl data-tmpl data-tmpl data-tmpl data-tmpl data-tmpl data-tmpl data-tmpl data-tmpl data-tmpl data-tmpl data-tmpl data-tmpl data-tmpl data-tmpl data-tmpl data-tmpl data-tmpl data-tmpl data-tmpl data-tmpl 118 10'bOlOOlOO01l1; 10'bOlOOlO00011; 10'bOlOOlO0l 00; 10'bOlOOlO0l 00; 10'bOlOOlO0l0l; 10'bOlOOlO0l0l; 10'bOlOOlO0llO; 10'bOlOOlO0llO; 10'bOlOOlOO1ll; 10'bOlOOlO0lll; 10'bOlOOl1l 000; 10'bOl 00101000; 10'bOlOOl0lO0l; 10'bOlOOl0lO0l; 10'bOlOOl0l0lO; l0 t bOlOOl0l0lO; 10'bOlOOl0l0ll; 10'bOlOOl0l0ll; 10'bOlOOl0llOO; 10'bOlOOl0ll0l; 10'bOlOOl0ll0l; l0'bOlOOl0lllO; 10'bOlOOl0lllO; 10'bOlO0010l11; 10O'bOlO00101111; =10'bOl 00101111; 10'bOlOOl0llll; 10'bOl100l11000; 10'bOlO00110001; 10'bOlO00110001; 10'bOlO0011001; 10'bOlO00110010; 10'bOlOOllO0ll; 10'bOlO00110011; 10'bOlOOll0lOO; 10'bOlOOll0lOO; 10'bOlOOll0l0l; WO 98/19410 119 13'b000001110100z :data-tmpl =10'bOlOOll0l0l; 13'bOOOO01l1101Olz data -tmpl 13'bOO000lll0ll0z: data-tmpl =10'bOlOOll0llO; 13'b000001110111z:data-tmpl =10'bOlOOll0lll; 13'bOOOO0llllOO0z: data-tmpl 10'b0100110111; PCTIUS97/1891 1 13'b000001111001z: data-tmpl 13'bOOQ00llll0lz: data tmpl 13'bOO00O1l1110110 data -tmpl 13'bOOOOOl11110l111:data-tmpl1 13'bOOOO0lllllO0z: dataImpi 13'bOOOO01l1111010 data~tmpl 13'bOOOO0ll1111011 data-tmpl 13'bOOOOOl111111Oz data tmpl1 13'bOOOOOl11111110 data~tmpl1 10O'bOlO00111000; 10'bOlOOll11000; 10'b01001 11000; =1O'bOl100l11100l; 1 O'bOlQ00111001; 10O'bOlQ00111001; 1QO'bOl100l11101; 1 ObOl100l11101; 1QO'b01 00111010; 13'bOOOO0ll1111111:data -tmpl =10'bOlOlO1101; 13'bOOQOOOOOzz: data-tmpl 1 10O'bOl100l1110l1; 13'bOOO0lOOOO0lzz: data-tmpl =10'bOlOOll11100; 13'b0000 10000 1000 data-tmpl 1 1 O'bOl100l11110; 13'bOOO0lOOO0l0zl :data tmpl 13'b0000100001010 data-tmpl 13'b0000100001100 data-tmpl 13'bOOO01l00001lzl data tmpl 13'bOOOOl10000l111 data~tmpl1 13'bOOD0lO00lOQ0z data-tmpl 13'bOO00lOO0lO0z: data-tmpl 13'bOOO0lOO0l0l0z: data -tmpl 13'bOOO0l 00010110: data-tmpl 13'b00001 00010111 data-tmpl 13'bOOO0lOO0ll0zz: data-tmpl 13'bOOO01l00011lzz: data-tmpl 13'bOOO0lO0lOOOOO data-tmpl 13'bOOO0lO0lOO0zl :data -tmpl 13'bOOO0lO0lOO0lO data-tmpl 13'bOOO0lO0lO0l0z data-tmpl =10O'bOlO00111101; 10O'bOl 00111101; 10O'bOl 00111101; 10O'bOl 00111110; 10O'bOl 00111110; 10'bOl 0011111; 10'bOlO0111111; 10O'bOlO0111111 10O'bOl 00111111; 1O0'b0lOOOOO 10O'bOl10l100000; 10'b0 10 100000 1; 10'bOlOlOOOO0l; 10'bOl0lOOO0lO; =10O'bOl 00001 0; =10'b0101000010; 13'bOOO0lO0lO0llz: data-tmpl 10'bOl 0l100001; 13'bOOO0lO0l0lO0z: data -tmpl 101 'bOl 01000011; 13'bOO001l00101010 data-tmpl 10'bOl 01000011; 13'bOO001l001Olzll1 data -tmpl =10'bOlOlQOOl100; 13'bOOOOl100l0 11Oz :data -tmpl =10'bOl 0100010; 13'bOOO0lO00101110:data -tmpl l0'bOlOlOO0lOO; 13'bOOO0lO0llOOOO data- tmpl =10'bOlOlOO0lOO; .0 WO 98/19410 WO 9819410PCTIUS97/1891 1 120 13'bOOOO 011OOz 1:data -tmpl 10'bOl0looolol; 13'bOO0lO0011001 data-tmpl 10'bOlOlOO0i0i; 13'bOOO0lO0ll0l0z: data-tmpl 10'b0101000101; l3'bOOO01l01l101lz: data -tmpl 10'bO10lQQ01lO; 13'bOOO01l00111OOz data_tmpl 10'bOl0lOO0llO, 13'bOO001l00111010 data-tmpl 10'b0101000110; 13'b00001001 1lz1 1 :data-tmpl 10'bOlOlOOoll11; 13'bOOO0lO0llll0z: data tmpl 13'bOOO0lO0lllllO: data-tmpl 10'bOl 01000111; 13'bOO001l1l000OOO data-tmpl 10'b01 01000111; I 3'bOOO0l 01 QOQ0zi 13'bOOO0l0lOO0zlO 13'bOO001010O0l0z data-tmpl data-tmpl data-tmpl 10'bOlOlOO1OOO; 13'bOOO0l 01000111 :data -tmpl 10'b0101Q01001; 13'bOOO0l0lO0l0zz: data-tmpl 13'bO00101001100: data-tmpl 10'bOlOlOOlO0l; 13'bOOO0l0lO0llzl data -tmpl 13'bOOO01l1lO1lllO data-tmpl 13'bOOO0l0l0lOO0z: data-tmpl 13'bOOO0l0l0l0zlz: data-tmpl 13'bOOO0l0l0l0l0z: data-tmpl 13'bOOO01l01011Ozz: data-tmpl 13'bOOO0l0l0lll0z data -tmpl1 13'bOOO01l01011110 data-tmpl 10'bOlOlOOl01O; 10'bOlOlOOl0lO; 10'bOlOlOOl0lO; 10'bOlOlOOl0ll; 10'b0101001011; 10'bOlOlOOllOO;1 13'bOOO0l0l0lllll :data-tmpl =10'bOlOlOOll0l; 13'bOOO01l011OOOzz data-tmpl 1 10bOl 01001101; 13'bOOO01l1l10010O data-tmpl =10'bOlOlOO1 101; 13'bOOO01l011O0lzl :data -tmpl 13'bOOO01l01100110O data-tmpl 13'bOOO0l0ll0lO0z: data -tmpl 13'bOOO0l0ll0l0lO data-tmpl 13'bOOO0l0ll0lzll :data-tmpl 13'bOOO01l011011Oz data -tmpl 13'bOOO0l0ll0lllO data-tmpl 13'bOOOOl0l1110000data-tmpl1 13'bOOOOl0l111OOz 1:data-tmpl1 13'bOOO01l0111OzlO0 data-tmpl 13'bOOO01l011101Oz data -tmpl 13'bOOOOl 01110111:data-tmpl 13'bOOOOl0l1111Ozz data-tmpl1 13'bOOO01l01111lOz data -tmpl 13'bOOO01l01111110 data-tmpl l0'bOlOlOOlllO; 10'bOlOlOOl 110; l0'bOlOlOOi 110; 001111; 10'bOll 0001111; 10'bOlOl 001111; l0'bOlOl 001111; I 0'bOlOl 01100; 1 0b010101 0000; 1 0bOl1l1l 0000; 10'bOl1l 010000; 10'bOl 01010001; 10'bOl1l1l 0001; 10'bOl1l1l 0001; 13'bOOO01l1lllllll data-tmpl 10'bOl0l0lO0lO; WO 98/19410 WO 9819410PCTIUS97/1891 1 121 13'bQOOllOOOO00zz: data-tmpl 10'b101010010; 13'b000011000010z: data-tmpl 10b0101010010; 13'bOOO0llOOO0llz: data -tmpl 10'b101010011; 13'bOOO01l1O001Ozz: data-tmpl 10'b101010011; 13'bOOO0llOQ0llzz: data-tmpl 10%b0101010100; 13 t b00001 1001000z: data -tmpl 1OMb101010100; 13'b0000 1100 100 10 data-tmpl1 1O0'00llO; 13'bOOOO1100 1Ozl 1data-tmpl 1O0'00ll1; 13'bOO0llO0l0l0z: data -tmpl 1QO10l0l0l0l; 13'b00001 10010110 :data -tmpl1 1O0'00ll1; 13'bOOO01l100 11OOz: dataI mpi 10'b101010101; 13'b00001 10011010:data-tmpl 1O0'00ll1; 13'bOOOOl1100 11zll1 data -tmpl 10'b101010110; 13'bOOOOl1100 111Oz: data -tmpl 1O0'00lll; 13'bOOOOl1100l11110data -tmpl 10%b010101011O; 13'bOOO01l01 lOOz: data-tmpl =10'bOl0l0l0llO; 13'bOOO0ll0lO0zlz: data -tmpl 1OMb101010111; 13'bOOO01l101001Oz: data -tmpl 1OWb1l1l1l1ll; 13'bOOO0ll0l0lOOO data-tmpl lOWb1l1l1l1ll; 13'b00001 10101Oz1 :data-tmpl 13'bOO0ll101OlzlO data-tmpl 13'bOOO0ll0l0ll0z: data -tmpl 13'bOOO0ll10101111:data-tmpl 13'b0000 110 110000:data-tmpl1 13'bOOOOl110 11OOz 1:data-tmpl1 1 TbOOOOl110l11 zlO0 data-tmpl1 13'b0000 110 11010Oz data -tmpl 13'bOOO0ll10110111:data-tmpl 13'b00001 10111000 data-tmpl 10%b0101011OOO; 10b0101011000; 1 O'b0101011000; 1OUb1l1l1llOO; 10'b101011000; 1O0'b0llO1; 1O0'b0llO1; 1 O'bOl 01011001; 10O'bOl 01011001; 1 O'bOl 01011001; 13'bOOOOl110l111Ozl data -tmpl 1O0'b0 11; 13'bOOO01l10111zlO0 data -tmpl 10O'b01 010110 13'bOOO01l10l1111 z data -tmpl =0'bWl0l0ll0lO; 13'bQOOll1 1011111 data-tmpl 10O'bOl 01011010; 13'bOOO01ll1OO~zzz: data-tmpl 10O'bOl 01 011011; 13'bOOO0lllO0lzzz: data-tmpl 10b0101011100; 13'bOOOOl1110 1Ozzz: data -tmpl lObWl0l0lll0l; 13'bOO001l11011000 data-tmpl 10'bOl0l0lll0l; 13'bOO001l11011Ozl :data-tmpl 13'bOOOOl1110 11zlO0 data-tmpl1 13'bOOO01l11011l1z: data -tmpl 13'bOOO01l11011111 data-tmpl 13'bOO011100000 data-tmpl 1ObOl 01011110; 10'bOl 01011110; 10'bOl 01011110; 10'bOl 01011110; 13'bOOO01l111OO0zl :data-tmpl 10'bOl 01011111; WO 98/19410 WO 9819410PCTIUS97/1891 1 122 13'b0000 1111 00z 0 13'bOO011l10OlZ: 13'b0000111100111: 13'b000011110100z: data-tmpl data tmpl data-tmpl data-tmpl 1O10'blll; 10'b101011111; 1O10'blll; 1O10l01l1111; 1 0'bOl 01100000; 10O'bOl10l1100000; 10O'bOl10l1100000; l3'bOOO0llll0lzlz: data tmpl 13'bOOO01l111011Oz data -tmpl 13'bOOOOl1111OOOz data-tmpl1 13'bOOO0lllll0zlz: data tmpl 1 'bOl 01100001; 13'bOOO01l111101Oz :data-tmpl 10'bOl 01100001; 13'bOO00llllllO0z: data tmpl 10'bOl0llOOO0l; 13'bOOOOl11110l10data-tmpl 101'bOl 01100001; 13'bOOO01l1111lzl 1:data-tmpl =10'bOl0llOO0lO; 13'bOOO01l111111Oz data -tmpl =10'bOl 01100010; 13'bOOO01l11111110 data -tmpl =10'bOl 01100010; l3bOO0lOOOOOO0zz: data-tmpl 10'bOl 01100010; 13'bOO0lOOOOO0zz: data-tmpl 13'bOO0lOOOO0l0zz: data-tmpl 13'bOO01l000001100O data-tmpl 13'bOO01lOOOO1lzl :data -tmpl 13'bOOO00000 1110: data-tmpl1 13'bOO0lOOO0lO0zz: data-tmpl 13'bOO0lOOO0l0l0z: data -tmpl 13'bOO01l000010110O data-tmpl 10'bOl 01100011; 10'bOl 01100011; 1lObOl 01100011; 10'bOl 01100100; 1O0'b10lO1lO; 10'bOl 01100100; 10'bOl 01100100; 10'bOl 01100100; 13'bOO01lOOO0zll 11data -tmpl 1O0'b 1011; 13'bOOOlO0000 11Ozz: data -tmpl 1O0'b 1011; 13'bOO01l0000111Oz data-tmpl 10'bOl 01100101; 13'bOOOl000011110 data-tmpl 10'bOl 01100101; 13'bOO0lOO0lO0zzz: data -tmpl 13'bOO0lOO0l0lO0z: data-tmpl 10'bOl0llO0llO; 10'bO1011O0llO; l3'bOO0lOO0l0lzlz: data-tmpl 10'bOl0llO0lll; 13'bOO0lOO0l0ll0z: data-tmpl 10O'bOl 01100111; 13'bOO0lOO0llO0zz: data-tmpl =10'bOl 01100111; 13'bOO0lOO0ll0lzz: data-tmpl 10'bOl 01101000; 13'bOO0lOO0lll0zz: data-tmpl 10'bO10ll0lOOO; 13'bOO0lOO0llll0z: data-tmpl 1O0'b 0llOO; 13'bOOO00011111z :data-tmp1 1O0'b 0llO1; 13'bOO0lO0lOO0zzz: data-tmpl 10'bOlOll101001; 13'bOO0lO0lO0lzzz: data -tmpl 10'bOlOll101010; 13'bOO0lO0l0lOO0z: data-tmpl =10'bOlOll101010; 13'bOO0lO0l0l0zlz: data-tmpl 10'bOl 01101011; 13'bOO0lO0l0l0l0z: data-tmpl 10'bOlOll101011; 13'bOOlO0l0ll0zz: data-tmpl 10'bOlOll101011; 13'bOOO001 11100: data-tmpl 10'lbOl0ll0l0ll; WO 98/19410 WO 9819410PCTIUS97/1891 1 123 13'bOO0lO0l0lllzl data-tmpl 1OUb01111100; 13'bOO0lO0l0llllO data-tmpl 1OUb1l1ll1llO; 13'bOO0lO0llOO0zz: data-tmpl 10'bOl0ll0llOO; 13'bOO0lO0llO0l0z: data-tmpl lObUl0ll0llOO; 13'bOO01l001100110O data-tmpl 1QO'bOl 01101100; 13'bOOlO 0011Ozll 11data-tmpl 13'bOOOl10O11lOzz data-tmpl1 13'bOOOl10O111Olz data-tmpl1 13'b000 100 110 1110:data-tmpl1 13'b000 100 111000~z data-tmpl1 1O'b1l1ll1ll1; 10'b101101101; 10M1011ll1101; 1OWb101101101; 1 O'bOl 01101101; 1-3'bOO01l00111Ozl z :data-tmpl 1 10'bOl 0l110111; 13'bOO0lQ0lll0l0z: data-tmpl 110bllllO; 13'bOO01l001111Ozz data -tmpl =1OMb1l1ll11ll; 13'bOO01l001111100 data-tmpl 10'b01 01101110; 13'bOOOl100l11111zl :data-tmpl1 13'bOO01lO1l111110 data-tmpl 13'bOO0l0lOQO0zzz: data-tmpl 13'bOO0l0lOO0lOOO data-tmpl 13'bOO0l01OQ0l0zl data-tmpl l3 t bOO0l0lOO0lzlO data-tmpl 13'bOO01l0100011Oz data -tmpl 13'bOO0l0lOO0llll :data-tmpl 13'bOO0l0lO0lO0zz: data-tmpl 13'bOO10lO0lzlzz: data-tmpl 13'bOO01l010011Ozz :data-tmpl 13'bOO0l0l0lO0zzz: data-tmpl 13'bOO10l0l0l0zz: data-tmpl 1O0' 0llll; =1O'b1l1ll11ll; =10'b0101101111; =O 101110000O; 1 10'b01 01110000; =1QO10lllOOO; 1 10bOl 0l111000; OMb1l1lllOOO; 10bOl0lllOO0l; M010'b 0llO1; =1OWb101110010; 1010blllOO; 13'bOOO101010 11zz :data-tmp1 10'bO1011100l11 13'bOO0l0l0ll0zzz: data-tmpl 1OWb1l1lllO1l; 13'bOOOl10l11zzz: data -tmpl 1O0' 11O; 13'bOO01l011OOOOzz: data-tmpl 10'bOl 01110100; l3'bOOO1011O0zl zz: data-tmpl1 1 ObOl10l110 13'bOO0l0llO0l0zz: data -tmpl 1O0' 111; 13'bOOOl10l110l1000 data-tmpl1 1 O 0 1110ll10l1; 13'bOOOl10l10 1O0zl 13'bOO0l1l l0l0zlO 13'bOO0l1l l0lzlOz 13'bOOOl10l11 10 111 13'bOOOl~ 10011 Ozz data-tmpl data tmpl data -tmpl data -tmpl data-tmpl lObMl0lll0llO; lObMl0lll0llO; 1O0' 11l; 10'01l01110110; 13'bOO01l0110111lz: data -tmpl 1O0' 11l; 13'bOO01l0.11lOOzzz data-tmpl 10'bOl 01110111; 13'bOO0l0lll0lO0z data-tmpl lObWl0lll0lll; 13'bOO01l1lll1l1lO _data tmpl 1O0' 11l; 13'bOO0l0lll0lzll :data_tmpl 1O0' lllOO; WO 98/19410 WO 9819410PCTIUS97/1891 1 13'bOO0l0lll0ll0z: data tmpl 13'b0001 011101110:data-tmpl 1 Tb000 10 11110Ozzz data-tmpl1 10%b0101111000; 1 O'bOl 0111100; 1O0' lllOO; 13'bOO01l1l111lzzz: data-tmpl =10O'bOlOll111001; 13'b0001 1000000zz data tmpl 10 t 'b0101111001; 13'b0001100000100 data~tmpl 10'b101111001; 13'b0001 1000001z1 :data-tmpl 13'b0001 10000z 10:data-tmpl 13'b0001 1000010Ozz: data_tmpl 13'b0001 10000110Oz data -tmpl 13'b000 110000 1111 :data-tmpl1 13'b000 11000 1000z data -tmpl 13'b0001100010010:data-tmpl 13'bOO01l10001Ozl 1:data-tmpl 13'bOO0llOO0lzlOz data -tmpl 13'b0001 10001z1 10 data-tmpl 13'bOO01l100011Ozz data -tmpl 13'b0001 100011111 :data-tmpl 13'b000 1100 100000 data-tmpl1 10O'bOl 01111010; 10O'bOl 1110 10'bUl10 1111010; 1 10 1111010; 10'b0101 1111010; I0'bUl10 1111010; 10O'b0100 1111010; 1 10 1111011; 1 O'bOl 01111011; 1 10 1111011; 10'bOl 01111011; 1 10 1111011; 10'bOl10l11110l1; 1 Tb000 1100 100z 1 :data -tmpl 10'b0 10 1111100; 13'bOO0llO0lO0zlO data-tmpl 10'b0101111100; 13'bOO0llO0l0zl~z: data-tmpl 1O0' llllO; 13'b0O0O1100100111-- data-tmpl =10'bOl 01111100; 13'bOO01l100101Ozz: data-tmpl 10O'bOl 01111100; 13'b0001 100101110:data-tmpl 10bOl 01111100; 13'b0001 100101111 data-tmpl 10O'bOlO01111101; 13'bOO01l10011Ozzz data-tmpl 10'b01 01111101; 13'b000 1100 1110Ozz data-tmpl1 10'bO10lllll10l; 13'bOOOl100l1111Oz data-tmp1= 1'bO 0l11110l; 13'bOO01l1001111lz: data-tmpl 10'bOlOll111110; 13'bOO01l101lOOzzz :data-tmpl 10'bOlOll111110; 13'bOO0llOIO0l0zz: data-tmpl 10'bOl 01111110; 13'bOO0ll0lO0llOO data-tmpl =1O'bOlOllllllO; 13'bOO01l101001lzI data-tmpl 1 10bOl 01111111; 13'bOO0ll0lO0lllO data-tmpl 1 1Ob0101111111; 1 TbOOOl11010 1Ozzz data-tmpl 1 10bOl0l111111; 13'bOO0ll0l0ll0zz data-tmpl =1O'bOlOlllllll; 13'bOO0ll0l0lllzz data-tmpl 1 1ObOl110000000; 13'bOOOll10 11OOzzz: data -tmpl 1 1ObO 110000000; 13'bOO01l101101OOz data-tmpl 1 O'bOl10000000; 13'b0001101101010 data-tmpl 1 OWb110000000; 13'bOO01l101l1lz~l :data-tmpl 1 O'bOl11000000l; 13'bOO01l1011011Oz data-tmpl 1 ObOl11000000l; 13'bOOll 10110111 data-tmpl 1 ObOl 10000001; 13'bOOOll10l111Ozzz: data -tmpl 1 1O'bOl11000000l; 13'bOOOl110l11l1Ooz data-tmpl 1 1 ObOl11000000l; WO 98/19410 WO 9819410PCTfUS97/1891 1 125 13'bOO01l10111lzlz: data-tmpl 13'b000110111110z: data-tmpl 13'bOO01l11OOOOzzz: data-tmpl 13'b000111000100z: data-tmpl 10O'b01 10000010; 1 O'bOl1100000l1; 10O'bOll10000010; 1O'b0110000010; 13'bOO01l11OO0lzlz: data-tmpl 10O'bOll10000011; 13'bOO01l1100011Oz data -tmpl 10'bOll10000011; 13'bOO01l11001Ozzz data-tmpl 1 Ob01 10000011; 13'b0001 11001100~z data-tmpl 1lObOl 10000011; 13'bOO0lllO0llzlz: data-tmpl 10O'bOl110000l10; 13'bOOOl11100 111Oz data-tmpl1 1lObU 110000 100; 13'bOOOl1110 1OOzzz: data-tmpl 101 'bOl110000l10; l3 t bOOOl111010 1OOz data -tmpl 10O'bOll10000100; 13'bOOO11101010Q10data-tmpl 10'bOl110000l10; 13'bOO0lll0l0lzll :data-tmpl 10'bOll10000101; l3 t bOOOl111010 11Oz data-tmpl1 10O'bOl110000101; 13'bOO01l110101110 data-tmpl 10'bOll10000101; 13'bOOO1110 11Ozzz: data-tmpl 1 ObOll10000101; 13'bOOOl1110 111OOz: data-tmpl1 10'bOll10000101; 13'bOO01l110111010 data-tmpl =10bOll10000101; 13'bOO01l11011lzll1 data-tmpl 10'bOllOOO0llO; 13'bOO01l1101111Oz data -tmpl 10O'bOll1000011; 13'bOO01l110l111110data-tmpl =10'bOllOOO0llO; 13'bOOOl1111OOOzzz data-tmpl1 10'bOllOOO0llO; 1 TbOOOl111100 1Ozz data-tmpl1 1QO'bOl110000l11; 13'bOOOl111100 11zz: data-tmpl1 1QbOl110000l11; 13'bOO01l11101Ozzz data-tmpl 1 bOl110000l11; 13'bOOO11110 11Ozz data-tmpl1 10Ol11000 111; 13'bOO01l111011100 data-tmpl =10'bOllOOO0lll; 13'bOO01l111011lzl data -tmpl 1 O'bOl11000l100; 13'bOO01l111011110 data-tmpl 10'b0110001000; 13'bOOOl11111OOzzz: data-tmpl 1 10bOl11000l100; 13'bOOOl111110 1Ozz data-tmpl 1 10bOl11000l100; 13'bOO01l1111011Oz: data-tmpl 1 10bOll10001000; 13'bOO01l1l1101110 data-tmpl 10bOll1000l100; 13'bOO01l111lzll111 data-tmpl 1 10bOll10001001; 1 TbOOOl111111Ozzz data -tmpl =10'bOllOO0lO0l; 13'bOOOll111ll1Ozz data-tmpl 1 1 Ob0 11000 1001; 13'bOO01l111111l1z: data -tmpl 1 10bOll10001001; 13'bOO01l111111110 data-tmpl 10'bOll10001001; 13'b0010000000000 data-tmpl 10'bOllOO0lO0l; 13'bOOlOOOOOOO0zl data-tmpl 1Q'bOllOOl10lO; 13'bOOlOOOOOO0zlO: data -tmpl 1O'bOllOO0l0lO; 13'bOOlOOOOO0zl~z: data -tmpl 10'bOllOO0l 010; 13'bOOlQOOOO00zll11l data-tmpl 1 ObOl110001010; 13'bOOlOOOOO0l0zz: data-tmpl 10'b0110001010; 13'bOOlO0000001110O data-tmpl 10'bOllOO0l0lO; l3'bOOlOOOO0lOO0z: data -tmpl1 10'bOllOO0l0lO; 13'b0010000010010 :data-tmpl 10'b0110001010; WO 98/19410 WO 9819410PCTIUS97/18911 126 13'b0010000010z1 1 data-tmpl 13'b001000001z10z: data tmpl 13'b001000001z110 data-tmpl 13'b00100000110zz: data-tmpl 13'b001 0000011111 data-tmpl 13'b00100001000zz: data-tmpl 13'b001000010010z: data-tmpl 13'b001000010z11z: data-tmpl 13'bOOlOOO0l0l0zz: data -tmpl l3'bOOlO00001011Oz :data-tmpl 13'bOOlOOO0ll0zzz: data-tmpl 13'bOOlOOO0lllzzz: data-tmpl 13'bOOlOO0.lOO0zzz: data -tmpl 13'bOOlOO0lO0l0zz: data-tmpl 13'bOOlOO0lO0llzz: data-tmpl 13'bOOlO000101Ozzz data -tmpl 13'bOOl100010 11Ozz data-tmpl1 13'bOOlOO1011Ollz: data -tmpl 13'bOOlO0001011110O data-tmpl 10'bOllOO0l0ll; 10'b0110001011; 10'bOllOO0l0ll; 10'b0110001011; 10'bOllOO01l11l; l0'bOllOO0l0ll; 10'bOllOO0l0ll; =10'bOllOO0llOO; 1 ObOll10001100; 10'bOllOO0llOO; 10'bOllOO0ll0l; 10'b0110001101; =10'b0110001101; 10'bOllOO0lllO; 1O'b0110001110; 10'b0110001110; 10'bOllOO0lllO; 10'bOllOO01llO; 13'bOOlO0001011111 data-tmpl 10b01 10001111; 13'bOOl1000 1lOzzzz: data -tmpl =10'bOllOO01lll; 13'bOOl1000 111OOOz: d ata -tmpl =10'bOll10001111; 13'bOOlOO01110010: data-tmpl =10'b01 10001111; 13'bOOlO000111 Ozi 1 13'bOO1000 11lzl Oz 13'bOOl1000l11 izI 10 13'bOOl1000l111 lOzz 13'bOOlO0001111111 1 3'bOOl 001 OOOO0zz 13'bOO0lOOlz 13'bOOlO0010000110 data -tmpl data -tmpl 10'bOllO0lOOOO; data -tmpl 10bOl1100l1000; data -tmpl 1 ObOl1100l1000; data -tmpl 1lObOll100l1000; data -tmpl 1 ObOl1100l1000; data -tmpl data-tmpl 13'bOOlO001OO0zll11l data -tmpl 10'bOllOOlOO0l; 13'bOOlO0lO0zlOzz: data -tmpl 10'bOllOOlOO0l; 13'bOOlO0lOO0ll0z: data -tmpl 10'bOllOOlOO0l; 13'bOOlO0010001110O data-tmpl 10bOll10010001; 13'bOOlO0lO0l0zzz: data-tmpl 10'bOllOOlOO0l; 13'bOOlO0lO0lllzz: data -tmpl 10'bOllOOlO0lO; 13'bOOlO0l0l0zzzz: data-tmpl 10'bOllOOlO0lO; 13'bOOlO01l1l10000: data-tmpl =10'bOll1001001; 13'bOOlO0l0llO0zl data-tmpl 13'bOOlO0l0ll0zlO data tmpl1 13'bOOlO0l0llzl~z: data -tmpl 13'b001 00101lz1 11 data -tmpl 13'bOOlO0010111Ozz: data-tmpl 13'b0010010111110 data -tmpl 13'bOOlO0llOOO0zz: data-tmpl 13'bOOlO0llOO0l0z: data-tmpl 10'bOllOOlO0ll; 10'bOl 10010011; 10'bOlIlOOl1; 1 ObOll10010011; 10bOll10010011; 10'bOll10010011; 10'b01 10010011; 10'bOll10010011; WO 98/19410 WO 9819410PCT/US97/1891 1 127 13'bOO1 0011O0zll1z :data-tmpl l3'bOOlO0ll0zlOzz: data-tmpl 13'b001 001100110Oz data-tmpl 13'bOOlO001101Ozzz data-tmpl 13'bOOlO0011011lzz data-tmpl 1 TbOOl100l111Ozzzz data-tmpl1 13'bOOlO001111OOOz data-tmpl1 10'bOllOOl0lOO; 10'bOllOOl0lOO; 1 O'bOll10010100; l0'bOllOOl0l0l; 1O'bOllOOl0l0l; 1O'bOllOOl0l0l; 13'bOOlO0llll0zlz: data -tmpl 13'bOOlO0llllzl~z: data -tmpl 13'bOOlO0lllll0zz: data -tmpl =10'bOllOOl0llO; 13'bOOlQ001111111z data -tmpl 10'bOllOOl0llO; 13'bOOl 0 l0OOzzz data-tmpl bOll10010110; 13'bOOl0lOOO0lzzz: data-tmpl 13'bOO10lOO0l0zzz: data-tmpl 13'bOOlO10011Ozz :data-tmpl 13'bOOl0lOO0lll0z: data-tmpl 13'bOOl 0100011110: data-tmpl l0'bOllOOl0lll; 10'bOllOOl0lll; 10'bOllOOl0lll; 10'bOllOOl0lll; 10'bOll10010111; 13'bOOl 0100011111 data-tmpl 1 10'bOll10011000; 13'bOOl0lO0l0zzzz: data-tmpl =10'bOll10011000; 13'bOOl 01001lOOzz :data-tmpl 1 1Ob~ll10011000; 13'bOOl 01011Oz :data-tmpl 1 10bOll10011000; 13'bOOl01lQ1llzl lz: data-tmpl 13'bOlO l10l11Ozz data-tmpl1 13'bOOl 01001111Oz data-tmpl 13'bOOl0l0lOO0zzz: data -tmpl 13'bOOl0l0lO0l0zz: data tmpl 13'b0011010 100 11 0 data-tmpl1 10'bOll10011001; 10'bOll10011001; 10'bOll10011001; 10O'bOll10011001; 1 ObOll10011001; 10'bOll10011001; 13'bOOl0l0l0zlllz: data-tmpl 10'bOll10011010; 13'bOOl0l0l0l0zzz: data -tmpl1 10'bOllOOll0lO; 13'bOOl 01101Ozz data -tmpl 10O'bOll10011010; 13'bOOl0l0l0lll0z: data -tmpl 10'bOll10011010; 13'bOOl0l0llOO0zz: data -tmpl 10'bOll10011010; 13'bOOl0l0llO0l0z: data-tmpl 10'bOllOOll0lO; 13'bOOl1011Ozl lz: data-tmpl =10O'bOll10011011; 13'bOOl0l0llzl~zz: data-tmpl 10O'bOll10011011; 13'bOOl0l0llzll~z: data-tmpl =10'bOll10011011; 13'bOOl10l1 111Ozzz data -tmpl1 1 Ob~ll10011011; 13'bOOl 0101111110 data-tmpl1 10'bOllOOll0ll; 13'bOOl 0101111111 data-tmpl =10'b0110011100; 13'bOOl 011OOOzzzz data-tmpl 10'bOll10011100; 13'bOOl0llO0l0zzz: data-tmpl 10'b0110011100; 13'bOOl10l100 11zzz data -tmpl1 10O'bOl 10011101; 13'bOOl 01101Ozzzz data -tmpl =10O'bOll1001l101; 13'bOOl01l10110000 data-tmpl 10'bOll10011101; 13'bOOl 011011OOzl :data-tmpl 13'bOOl0ll01l0zlo data-tmpl 10'bOll10011110; WO 98/19410 WO 9819410PCT/US97/1891 1 128 13'bOOl0ll0llzl~z: data tmpl 10'bOll10011110; 13'bOOl 01101lzll :1data-tmpl =1I'bOll1001111; 13'b001 01101110Ozz data -tmpl 13'b001 0110111110 data -tmpl 13'bOOl10111OOOzzz data -tmpl l'bOllO0llllO; 13'bOOl 0111001OOz data -tmpl =1O'bOllOOllllO; 13'b001 0111001010 data-tmpl 3'bO01l0111O0lzll1 data-tmpl 13'bOOl 0111Ozll1Oz data-tmpl 13'bOOl 0111Ozll110 data-tmpl 10'bOll10011111; 13'bO01 011101Ozzz data -tmpl 10'bOll10011111; 13'bOOl 0111011Ozz data -tmpl 13'bOOl0lll0lllll :data -tmpl 13'bOOl 01111OO~zz data-tmpl 13'bOOl 0111100100 data-tmpl 13'bOOl 01111O0lzl :data-tmpl 13'b001 01111Oz 10:data-tmpl 13'bOOl 0111lzl Ozz data-tmpl 13'bOOl01l11lzll10z: data -tmpl1 13'bOOl0llllzllll :data-tmpl 13'bOOl01l111lOzzz: data-tmpl 13'bOOl 0111111110 data-tmpl 10'b110100000; 10Mb110100000; 10'b110100000; 10'b0110100000; 10O'b01 10100000; 10O'b0 110 100000; 1 Ob0 110 100000; 13'bOOll1OOOOOzzzz: data-tmpl 1 Ob01 10100001; 13'bOOllOOO0l0zzz: data-tmpl 10'b0110100001; 13'bOOllOOO0ll0zz: data-tmpl 10'bOll0lOOO0l; 13'bOOl110000 111zz data-tmpl1 13'bOOllOQ0l0zzzz data -tmpl 13'b00 11000 110zz: data-tmpl1 13'b001100011010z: data-tmpl 13'bOOllOO01ll1llO data-tmpl 10 bOl 10100010; 10'Ol 10100010; 10'bOl 10100010; 10'bOl 10100010; 10'bOl 10100010; 13'bOO11000 11z111 data-tmpl1 10'bOll0lOO0ll; 13'bOOO00111Ozz: data-tmpl 10'bOll0lOO0ll; 13'bOOll10001111Oz data-tmpl =10'bOll0lOO0ll; 13'bOOll1000111110 data-tmpl =10'bOll0lOO0ll; 13'bOOl1100 1OOzzzz: d ata -tmpl 10'bOll0lOO0ll; 13'bOlO 10zz: data-tmpl 10'bOll0lOO0ll; 13'bOOllOOI0lzlzz: data-tmpl 10'bOll0lO0lOO; 13'bOOllO0l0ll0zz: data-tmpl 10'bOll0lO0lOO; 13'bOOllO0ll0zzzz: data-tmpl 10'bOll0lO0lOO; 13'bOO1lOlllz7zzz: data -tmpl 10'bOll0lO0l0l; 13'bOOl110l1OOOOzzz :data -tmpl1 10Oll0lO0l0l; 13'bOOll0lOO0l0zz: data-tmpl 10'bOll1lO0l 01; 13'bOOl110l100 1lOz :data-tmpl 10'bOll0lO0l0l; 13'bOOll0lO0zlllz: data-tmpl 10'bOll0lO0llO; 13'bOOll0lO0l0zzz: data tmpl 10'bOll0lO0llO; 13'bOOl110l00 11Ozz data-tmpl1 10'b0110100110; 13'bOOll0lO0lll0z: data-tmpl =10'bOll0lO0llO; 13'bOO1l0l0lO0zzz: data-tmpl 10'bOll0lO0llO; WO 98/19410 W098/9410PCTIUS97/1891 1 129 13'bOOll0l0l0lO0z: data-tmpl 10%b01101O0110; 13'b0011010101010:data-tmpl 10M11ll1lO11; 13'bOOll0l0l01zll data-tmpl 1 O'b0110100111; 13'bOO01lzll~z: data-tmpl 10M11ll1lO111; 13'bOOll0l0lzlllO: data-tmpl 1O'b0110100111; 13'bOOll0l0ll0zzz: data-tmpl 10'bOll10100111; 13'bOOll101011lOzz: data tmpl 13'b0011010111111 data~tmpl 10Oll0lO0lll; 13'bOOll1011OOOzzz data tmpl 10Mb110100111; 13 t b001 101100100z data~tmpl 10Oll0lO0lll; 13'bOOll101lO0lzlz: data-tmpl 10'b110101000; 13'bOOll0ll0zll~z data-tmpl 1O'b1ll1l1lOO; 13'bO~O01Ozzz :data-tmpl1 10Oll0l0lOOO; 13'bOOll0ll0ll0zz: data tmpl =1 O'bOll10101000; 13'bOOll0ll0llllz: data~tmpl 10Oll0l0lOOO; 13'bOOl110l111OOzzz data -tmpl 1OMb1ll1l1lOO; 13'bOOll01lll1lOOO data-tmpl 10Oll0l0lOOO; 13'bOOll0lll0l0zl :data -tmpl 10Oll0l0lO0l; 13'bOOll0lll0lzlO data -tmpl 10'bOll0l01O0l; 13'bOOll1011lzll1Oz data -tmpl =10Oll0l0lO0l; 13'bOOll1011lzll111 data -tmpl 10'bOll0l0lO0l; 13'bOOll101111Ozzz data -tmpl 10Oll0l0lO0l; 13'bOO1l1011111Ozz data -tmpl =10'bOll0l0lO0l; 13'b0011011111110:data-tmpl 1ObOll0l0lO0l; 13'bOOll1l00OOzzz: data-tmpl 10bOll0l0lO0l; 13'bOlOO11 zl zzz data-tmpl1 13'bOOll110001Ozzz data-tmpl 13'bOOlllO0lO0zzz: data-tmpl 13'bOOl11100 1zl zzz: data-tmpl1 13'bOOl11100 11Ozzz data -tmpl 13'bOOl1110 1OOOzzz: data-tmpl1 13'bOOlll0l0zlzzz data -tmpl 13'bOOlll0l0l0zzz: data-tmpl 13'bOOl1110 11OOzzz data -tmpl 13'b0011101101000 data-tmpl 10'bOll0l0l0lO; 10'bOll0l0l0lO; 10Oll0l0l0lO; 10'b0110101011; 10'b01 10101011; 10Oll0l0llOO; =1 ObOll10101100; 10'bOll0l0llOO; 1Q'bOll1010110; 13'bOlO1011zl :data-tmpl 1Q'bOll0l0ll0l; 13'bOOlll0ll0lzlO :data-tmpl =10Oll0l0ll0l; 13'bOlOll0zll~z: data -tmpl =10'bOll0l0ll0l; 13'bOOl1110 11zll111 data-tmpl1 10'bOll0l0ll0l; 13'bOOll11011lOzzz: data-tmpl =10Oll0l0ll0l; 13'bOOlll10l111lOzz data-tmpl 10'lbOll0l0lll; 13'bOOll1101111110 data-tmpl 10'bOll10101101; 13'bOOll11lOOOOzzz data -tmpl =10'bOll0l0ll0l; 13'bOOllllOO0lO0z:data-tmpl 1'Oll10l0lll; 13'bOOll1110001010: data-tmpl 10'bOll0l0ll0l; 13'bOOl1111000 1zl 1:data-tmpl1 13'bOOll111O0zllIOz data -tmpl 13'bOOll111O0zll110 data-tmpl 10'bOll0l0lllO; 10'011l010111O; 10Oll0l0lllO; WO 98/19410 W098/9410PCTIUS97/18911 130 13'bOOl11100 1Ozzz :data-tmpl1 13'bOOllllO0ll0zz: data tmpl 13'b0011110011111 :data-tmpl 13'bOOllll0lO0zzz: data tmpl 13'bOOll1110101Ozz data-tmpl 13'b001 1110101100 data~tmpl 10'bOlll 110; 10'bOlll 110; 10'bOll10101110; 10'b~llOlOl 110; 10'bOll~lOl 110; 10'bOll10l101110; 13'bOOll1110101lzl :data -tmpl 10'b01 10101111; 13'bOOll111Olzll110 data -tmpl 10'bOll0101111; 1 TbOll110 11Ozzz data_tmpl= 10'bOl10l10l111; 13'bOOl1110 111Ozz data-tmpl lO t bOl10l10ll1l; 13'bOOllll01lll10z: data -tmpl 1'Oll0l01lll; 13'bOOll1110111111:data-tmpl 1'Oll0l0llll; 13'bOOll1111007777 data-tmpl 1'Oll0l0llll; 13'bOOll111101zzzz data-tmpl 1'Oll10llOOOO; 13'bOOl111l1Ozzzz: data-tmpl 10'bOll10l11000; 13'bOOll111111OOzz: data-tmpl 10'bOll10l11000; 13'bOOl11l111zl zz data-tmpl1 13'bOOll1111111Ozz data-tmpl 13'bOlOOOOOOOzzzz: data-tmpl 13'bOlOOOOO0l0zzz: data-tmpl 13'bOlO0000001lzzz :data-tmpl 13'bOlOOOO0l0zzzz: data-tmpl 13'bOlOO0O0ll0zzz: data-tmpl l3'bOlOOOO0lll0zz: data-tmpl 13'bOlOOOO01llllOO data-tmpl 13'bOlO00000111lzl :data-tmpl 13'bOlO00000111110 data-tmpl 13'bOlOOO0l0zzzzz: data-tmpl 13'bOlO000011OQOOz: data-tmpl 10'bOll0llOO0l; 10'bOll0llOO0l; 1 'bOll10l11000l; 10'bOl110l11000l; 10'bOll0llQ0lO; 1'Oll0llO0lO; 10'bOll0llQ0lO; 10'bOll0llO0lO; 10'bOll0llO0lO; 10'bOll0llO0ll; 10'bOll0llO0ll; 10bOll0llO0ll; =1'O101lO0ll; 13'bOlO000011O0zl z data-tmpl =10'bOl110l11010; 13'bOl10000 11Ozl Oz data-tmpl 10'b0 110 110 100; 13'bOlO00001lzl Ozz: data- tmpl 10'bOl110l110l10; 13'bO10000 11zllz data-tmp1 10'bOl110l110.10; l3'bOl10000 111Ozzz data -tmpl 10'bOl110l110l10; 13'bO1000011111Oz data-tmp1 10'bOl110l110l10; 13'bOlOO0lOOO0zzz: data-tmpl 10'bOll0ll0lOO; 13'bOlOO0lO0zlzzz: data -tmpl 13'bOlOO0lO0l0zzz: data-tmpl 13'bOlOO0l0lO0zzz: data-tmpl 13'bOlOO0l010l0zz: data-tmpl 13'bOlOO0l0l0ll0z: data-tmpl 13'bOlOO01l1l1llIO data-tmpl 10'bOll0ll0l0l; 10'bOll0ll0l0l; 10M11ll11l1l1; 10'bOll0ll0l0l; 1'Oll0ll0l0l; 10'bOlllll 01; 13'bOlOOl0zllll :data-tmpl lO t bOll0ll0lIO; 13'bOlOOl0ll0zzz: data-tmpl 10'bOll10110110; 13'bOl1000l0 111Ozz data-tmpl1 10'bOl10l110l11; 13'blO00101111Oz data-tmpl 1'Ollollqllo1; 13'bOlOO1l11110: data -tmpl =10'bOll10110110; 13'bOlOO0llO0zzzz: data-tmpl 10'bOll10110110; WO 98/19410PCIS7111 PCT/US97/18911 13'bO1001OOzz: data -tmpl 13'bOlO000110101Oz data -tmpl 13'bOlOO0ll0l0llO data-tmpl 13'bOlOO01l1Olzll 11data-tmpl 1 TbOl1000 11zl11Ozz data-tmpl1 1 'bOl1000 11zl111Oz d ata-tmpl1 1 TbO1000 11z11110 d ata-tmpl1 13'bO 1000 111Ozzzz data-tmpl 1 TbOl1000l1111Ozzzd ata-tmpl1 1Q'bOl110 110 11; 1 ObOl110l110l11; 1 0 110 110 110; 10'bOl110l110l11; 10'bOl110l110l11; 1 0 110l110 111; 10'bOl110l110l11; 10Oll0ll0lll; 10O'b 0 110110l11; 13'bOlOO0llllllll :data-tmpl= 1OWb1ll1lllOO; 13'bOlO001OOOzzzzz :data-tmpl 1 10bOll1011100; 13'bOlOOlO0lO0zzz: data-tmpl 1 10bOll10111000; -13'bOlOOlO0lzlzzz: data-tmpl 10101Q'~ll~; 13'bOl100l00 11Ozzz :data -tmpl 1 10b~Oll1100l; 13'b~lOOl0lO0zzzz: data -tmpl =1O'bOll0lllO0l; 13'bOlOOl01l1lOOOO data-tmpl =10Oll0lllO0l; 13'bOlOOl0l0lO0zl :data-tmpl l3 t bOlOOl01l1lO data-tmpl 13'bOlOOl0l0lzl~z: data-tmpl 13'bOlO00101Olzl 11 data-tmpl 13'bOlOOl0lzllOzz: data -tmpl 13'b~Ol 010111110data-tmpl 13'bOlO0010111Qzzzz~ data-tmpl 13'bOlO0010111Ozzz data-tmpl 1OWb1ll1lll1l; 10'bOll0lll0lO; 1OWb1ll1lll1l; 10'bOll0lll0lO; 10'bOll0lll0lO; 10'011l011101O; =10Oll0lll0lO; 10bOll01ll0lO; 13'bOlOOl0lllllzz: data-tmpl 1'Oll10lllll; 13'bOlOOllO0zzzzz :data-tmpl 10bOll0lll0ll; 13'bOlQ0010OOOzz: data-tmpl =10'bOll0lll0ll; 13'bOlOOO 101z: data-tmpl 10bOll0lll0ll; 13'bOlOOll0lO0llO: data-tmpl =10'Ol10lll0ll; 13'bOlQ001101Ozll11 data-tmpl 1 1ObOll1011110; 13'bOlO0011Olzl Ozz data-tmpl 1 10bOll1Ol1 1100; l3tbOl 001101zllI z data-tmpl 1 10bOll1011110; 13'bOlOOll0lzlllO: data-tmpl 13'bOlOOll0ll0zzz: data -tmpi, 10'bOll10111100; 13'bOlOOll0llllll :data -tmpl 10'bOll0llllOO; 13'bOl100l111OOzzzz :data -tmpl =10'bOll0llllOO; 13'bOlO00110OOOz data -tmpl1 10'bOl110l11110; 13'bOlO00111010010 data-tmpl 1 10bOll10111100; 13'bOlO0011101Ozl 1:data -tmpl 1 1QbOll10111101; 13'bOll101zl Oz data -tmpl 10'bOll10111101; 13'bOll101zll10 data-tmpl 10'bOl110111101; 13'bOlQ0011lzll1Ozz data -tmpl =10'bOl110111101; 13'bOlO00111011111:data-tmpl 1 10bOll10l11110; 13'bOlO001111Ozzzz data -tmpl =10'bOll10111101; 13'bOlO00l11111Ozzz data -tmpl 10'bOl11011110l; 13'bOlO001111111 z data -tmpl=10'bOll0llll0l; 13'bOl 00111111110 data-tmpl 1 1ObOll10111101; 13'bOlO00111111111:data-tmpl 1 10bOll10111110; WO 98/19410 132 13'bOlOlOOOOzzzzz: data-tmpl 10Oll0lllllO; 13'bOlOlOO0lO0zzz: data-tmpl 10'bOll01llll10; 13'bOlOlOO0l0l0zz: data-tmpl 10Oll0lllllO; 13'bOlOlOO0l0llOO: data-tmpl 10Oll0lllllO; 13'bOlOlOO0l0llzl data-tmpl 10Oll0llllll; 13'bOl 01OO0lzll110 data-tmpl 13'b~lOlOO0ll0zzz: data-tmpl 13'bOlOlOOlll0zz: data-tmpl 13'bOlOlOO0llll0z: data -tmpl 13'bOl 01000111111: data-tmpl data-tmpl =10'bOll10111111; 13'bOlOlOOl0l0zzz: data-tmpl 10'bOll10111111; 13'bOl~lOOl0llO0z: data-tmpl 10'bOll0llllll; 13'bOlOlOOl0ll0lO: data-tmpl =10'bOll10111111; 13'bOlOlOOl0llzll :data-tmpl 10bOl111000000; 13'bOl 01001zll11Oz data-tmpl 10bOl111000000; 13'bOlO0lzll1110 data-tmpl 10bOl111000000; 13'bOl10l10 l1Ozzzz data -tmpl 1Q'bOi11100000; 13'bOl10l10 111 zzz data-tmpl1 10'bOl111000000; 13'bOl 01001111Ozz: data-tmpl 10OlllOOOOO0; 13'b0101001111111 :data-tmpl 10'b~l1100000; 13'bOlOlOlOOOOzzz: data-tmpl 10bOl111000000; 13'bOlOlOlOO0lO0z: data-tmpl 10bOll1100000; 13'bOlOlOlOOOlzlz: data-tmpl 13'bOlOlOlOOzll~z: data-tmpl 10OlllOOOO0l; 13'bOlOlOlOzlOzzz: data-tmpl 10bOl11100000l; 13'bOl 01010011Ozz data -tmpl 10'bOlllOOOO0l; 13'bOlOlOlOOllllz: data-tmpl 10'bOlllOOOO0l; 13'bOlOl~lOlOzzzz: data-tmpl 1 10bOl11100000l; 13'bOl0l0l0lllO0z: data-tmpl =10'b~lllOOO00l; 13'bOlOlOlOlllzlz: data -tmpl =10OlllOOO0lO; 13'bOl0l0l0llll0z: data-tmpl 1 10bOll11000010; 13'bOl 01011Ozzzzz :data -tmpl =10OlllOOO0lO; 13'bOlOlOlllOOzzz: data-tmpl =10'bOlllOOO0lO; 13Wb1l1l1lll1lOz: data -tmpl 10'bOlllQOQ0lO; 13'bOl 01011101010 data-tmpl 10'bOlllOOO0lO; 13'bOl 010111Olzl 1:data-tmpl 10'bOlllOOO0ll; 13'bOlOlOlllzll~z: data -tmpl =10'bOll11000011; 13'bOl 010111zll110 data-tmpl 10'bOlll100001l; l3'bOl 0101111Ozzz data -tmpl =1 ObOll11000011; 13'bOl 01011111 zz data -tmpl 10'OlllOO00ll; 13'bOl 01011111111 data-tmpl =10'bOlllOOO0ll; 13'bOl10l11OOOOzzzz: data -tmpl 1 10bOll11000011; 13'bOl10l1100 1 zzz data-tmpl 1 10'bolllOOO0ll; 13'bOlOllOO0ll0zz: data-tmpl =10'bOlllOOQ0ll; 13'bOlOllOOzlllzz: data-tmpl 1 1ObOll11000100; 13'bOlOllOOl0zzzz: data -tmpl =10'b111000100; 13lbOl 0110011Ozzz :data-tmpl 1 O'bol 11000100; 13'bOlOllOOlll0zz: data -tmpl 10'bO111OO0lOO; 13'bOlOllOlOO~zzz: data-tmpl 10'bOlll.OOlOO0; PCT/US97/1891 1 WO 98/19410 W098/9410PCT/US97/1891 1 133 13'bOlOllOlOOl0zz: data-tmpl 10OlllOO0lOO; 13'bOl0ll0lO0l0z: :data-tmpl 10'bOll11000100; 13'b~l 01101001110 data-tmpl 1 O'b~ll1000100; 13'bOl0ll0l0zllll :data-tmpl 10'bOll11000101; 13'bOl 01101zl Ozzz data-tmpl1 10%b0111OO0101; 13'bOlOll~lzllOzz: data-tmpl 1 ObOll11000101; 13'bOl 011 lzll11Oz data-tmpl 10OlllOO0l0l; 13'bOlOll10lzll111O data-tmpl 10'bOll11000101; 13'bOll01lOzzzz data-tmpl =10OlllOO0l0l; 13'bOl 01101111111 data-tmpl 1 10b~ll11000101; 13'bOl 0111OQOOOOz data-tmpl= 1Q'bOlllOO0l0l; l3'bOlOlllOOOOzlz: data-tmpl 1 1ObOll11000110; 13'bOl 0111OO0zl Oz data-tmpl 1 1ObOl 11000110; 13'bOl 0111O0zl Ozz data-tmpl =10OlllOO0llO; 13'bOl 0111O0zll1lz data-tmpl 10O'bOll11000110; 13'bOlOlllOIzzz: data-tmpl 13'bOl0lllO0lll0z: data tmpl =10'bOll11000110; 13'bOlOlllOlOzzzz: data-tmpl 13'bOlOll1101lO0zz: data-tmpl =10'bOlllOOllO0; 13'bOlOlllOllOlOz:data-tmpl =10'bOlllOO0llO; 13'bOl0lll0ll0llO data-tmpl =10OlllOO0llO; 13'bOlOll1101lzll11 data-tmpl 10'bOll11000111; 13'bOlOlllOlllOzz data-tmpl =10'bOlllOO0lll; 13'b~lOlll~llll~z: data tmpl 10'bOll11000111; 13'bOl 01110111110 data-tmpl =10'b~ll11000111; 13'bOl10l1111Ozzzzz data-tmpl1 1O'bOll110001l1; l3'bOl 011111O~zzz data-tmpl =10'bOll11000111; 13'bOl 01111101Ozz data-tmpl 1 ObOll11000111; 13'bOlOll11llzl lzz: data-tmpl 10'b~lOlO000; l3'bOlOllllllOzzz: data tmpl 13'bOlOll11111llzz: data~tmpl 10'bOll11001000; 13'bOllOOOOOzzzzz: data-tmpl =1QOlll00lOQO; 13'bOl110000 1OOOOz data-tmpl 1 10M111llO1000; 13'bOllOOO0lO0zlz data-tmpl =10'b~ll11001001; 13'bOll100001Ozl Oz data-tmpl =10Olll00lO0l; 13'bOllOOOOlzlOzz: data tmpl 101001O'~Ol~; 13'bO110000 1zl11z data-tmpl 1 10'bOlllO0lO0l; 13'bOllOOO0ll0zzz: data-tmpl =10'bOlllOOlO0l; 13'bOl110000 1111Oz data-tmpl 1 10'bOlllO0lO0l; 13'bOllOO0lO0zzzz: data -tmpl =10'bOlllO0lO0l; 13'bOl1100 10 1Ozzz: data-tmpl 1 1 ObOll11001001; 13'bOllOO0l0llOOO data-tmpl =1'OlllO00lO0l; 13'bOll1000101l1zl data -tmpl O'bOlllO0l0lO; 13'bOllOO0l0llzlO: data -tmpl 1 1ObOll11001010; 13'bOllOOOlzlll~z: data -tmpl =1O'bOlllO0l0lO; 13'bOll1000 1zll1111:data-tmpl 1 1 ObOll11001010; 13'bOll100011Ozzzz data -tmpl 1 13bOl11000 111Ozzz data-tmpl1 1OUb1lllO1l1l; 13'bOll1000111lOzz: data -tmpl 1O'bOlllO0l0lO; 13'bOllOOllllllO: data-tmpl 10'bOlllOOl0lO; WO 98/19410 WO 9819410PCTIUS97/1891 1 134 13'bOl1100 1OOOzzzz data-tmpl 1 1Q'b0111001010; 13'b0110010010000 data-tmpl =1O'bOlllOO10lO; 13'b011001001 00z1 data-tmpl =10Olll00l0ll; 13'bOl 1001001OzlQ0 data-tmpl I'b0111001011; 13'b01 1001001z10z data-tmpl =10'b0111001011; 13'b011001 001z1 11 :data tmpl 1 10b01 11001011; 13'bOllOOl0zll~zz: data-tmpl =10'bOlllOOl0ll; 13'b01 10010Ozl11110:data-tmpl 10Olll00l0ll; 13'bOllOOl0l0zzzz: data-tmpl 13'bOl110010 11Ozzz :data-tmpl 10'b~lllOOl0ll; 13'bOllOOl0llll0z: data-tmpl =10'bOll11001011; 13t01l10010111111 data-tmpl =10Olll00l0ll; 13'bOllOOllOO0zzz: data tmpl -10'bOll11001011; 13'bOll10011O0lOOz dataFtmpl =10Olll00l0ll; 13'bOllOOllO0l0lO data7-tmpl =10'bOlllO0l0ll; 13'bOl1100 100 1zll1 data-tmpl 1 13'bOll10011Ozll1 z data-tmpl =10Olll00llOO; 13'bOll10011Ozll110 data-tmpl 10bOll1100110; 13'bOll1001lzl Ozzz data-tmpl 1 10bOll11001100; 13'bOll10011zll1Ozz data-tmpl 13'bOll1001lzl 1111 data-tmpl 1 10bOll11001100; 13'bOl1100 111Ozzzz data-tmpl 1 10'bOlllO01llOO; 13'bOll100111111Oz data-tmpl =10'bOll11001100; 13'bOll10011111110 data-tmpl =10bOlllO0llOO; 13'bOll101 OOOOOzz data-tmpl 1 10bOll11001100; 1 TbOl110l100000l10 data-tmpl 1 10'bOll11001100; 13'bOll10lOOOO0lzl data-tmpl =10'bOlllOO1l0l; 13'bOllOlOOOzlO: data tmpl =10'bOlllOOll0l; 13'bOl110 1OOOzl1Oz: data-tmpl 1 1O'bOlllO0ll0l; 13'bOllOlOOOzlll: :data tmpl 10bOlllO0ll0l; 13'bOll1OOOz111z: data~tmpl 10'bOll11001101; 13'bOllOlOOzllllO :data tmpl =10'bOlllOOll0l; 13'bOllOlOO10zzzz data tmpl =10'bOlllQ0ll0l; 13'bOll10100111Ozz data~tmpl 10'bOlllOO1l0l; 13'bOll10100111l1z: data~tmpl =10'bOlllOOll0l; 13'bOll10100111111 data-tmpl 10'bO1llO0ll0l; 13'bOll1010107777z: data-tmpl 13'bOl110l0 11Ozzzz :data-tmpl1 13'bOllOl~lllOzzz: data-tmpl 13'bOll1010111lOzz :data-tmpl 10'bOlllO0lllO; 10'b0111O01110; 13'bOll10101111lzz data-tmpl 1'bOl 11001111; 13'bOl110 11OOzzzzz data-tmp 11ObOl11100 111; 13'bOll101101Ozzzz data-tmpl 10bOll11001111; 13'bOll101l011Ozzz data-tmpl 10bOll11001111; 13'bOl 10110111000 data-tmpl 1'bOll11001111; 13'bOllOllOlllOzl :data-tmpl 13'bOll1011011lzlO0 data-tmpl 13'bOll101101111Oz data -tmpl 13'bOll10110111111:data-tmpl 1ObOll11010000; 10'bOl 11010000; 1 0'bOl 11010000; 10'bOl 11010000; WO 98/19410 W098/9410PCTIUS97/1891 1 135 13'bOll10111077777: data-tmpl 13'bOll10111llzzzz: data-tmpl 13'bOll011111 zzz :data-tmpl 1 0'b01 11010000; 10'bOl 11010000; 1'Olll10lQOO; 13'bOll011111lzzz: data-tmpl =1'bOl11010001; 13'blO 10OOzzzzz data-tmpl1 1'Olll10lO0l; 1 TbOl111000 1Ozzzz: data-tmpl1 10'bOlll0lOO0l; 13'bOll1100011OOzz: data-tmpl 1Q'Olll10lO0l; 13'bOlllOO0ll0l0z: data -tmpl =1'Olll10lO0l; 13'bOlllOO0ll0llO data-tmpl 1'Olll10lO0l; 13'bOl 110001lzll11 data-tmpl 10'b111010010; 13'bO11000 111Ozz data-tmpl1 1'Olll1lO0lO; 13'bOlllOO0llll0z: data-tmpl =10%b011101O010; 13'b~ll1000l111l1 data-tmpl 1'Olll1lO0lO; 13'bOl11100 1 zzzzz: data-tmpl1 10O'bOl1110l100l1; 13'bOl11100 11Ozzzz: data-tmpl1 1'Olll1lO0lO; 13'bOll1100111 zzz data-tmpl 1Q'Olll1lO0lO; 13'bOll1001111zzz data-tmpl 1'Olll10lQ0ll; 13'bOll1101OOzzzzz: data-tmpl 1Q'Olll0lO0ll; 13'bOl11010O1Ozzzz data-tmpl1 1'Olll10lO0ll; 13'bOll1101011Ozzz data-tmpl =1Olll10lO0ll; 13'bOll1101011l10z: data-tmpl =1 ObOll11010011; 13'bOlllOlOlllzlz: data tmpl 1'Olll10llOO; l3'bOllOlOllll~z: daa-tmpl 1QOlll10l0lOO; 13'bOll11011Ozzzzz data -tmpl 1'Olll10llOO; 1lTbO 1110 111Ozzzz data-tmpl1 1 ObOll11010100; 13'bOll10111lOzzz data-tmpl 1'Olll10llOO; 13'bOlllOlllllOzz: data-tmpl =1'Olll10llOO; 13'bOll1011111100data-tmpl =1'Olll10llOO; 13'bOll1011111lzl data -tmpl 1'Olll0l0l0l; 13'bOll101l111110:data -tmpl =1'Olll0l0l0l; 13'bOl11lOOzzzzzz data -tmpl =1'O1ll0l0l0l; 13'bOll11101000000 data-tmpl =1'Olll0l0l0l; 13'bOll11101 OO0zl data -tmpl =1'Olll0l0llO; 13'bOlll1101OO0zlO0 data -tmpl =1'Olll0l0llO; 13'bOll11101O0zl Oz data -tmpl '1'Olll10l0llO; 13'bOll11101O0zll11 data -tmpl 10'bOll11010110; 13'bOllllOlOzlOzz: data -tmpl 1'Olll10l0llO; 13'bOll1101Ozll110 data -tmpl =1'Olll0l0llO; 13'bOllllOlzlOzzz data -tmpl 1'Olll0l0llO; l3'bOllllOlzlll~z: data -tmpl 1=O10'b 0ll 11ll; 13'bOll1l10zll111 data -tmpl =1'Olll0l0llO; 13'bOllllOll~zzzz: data-tmpl 1'Olll0l0llO; 13'bOll1101111Ozz data-tmpl=10'Olll10l0lO; 13'bOll110111l110 data -tmpl 1'Olll0l0llO; *13'bOllll11OOOOOzz data -tmpl 1'Olll10lO1O; 13'bOll1110000 1Oz: data-tmpl1 lO t b1lll1l1llO; 13'bOll1111OO0zll1z data-tmpl 13'bOll1111O0zl Ozz data -tmpl 13'bOll111O0zll1Oz data-tmpl 1'Olll0l0lll; =10'bOll1010111; WO 98/19410 WO 9819410PCTJUS97/1891 1 136 13'bOll1111Ozl Ozzz data -tmpl=10'bOll11010111; 13lbOll1111Ozll111z data-tmpl 1 10'bOll11010111; 13'bOlllllOlOzzzz: data-tmpl 10'Olll10l0ll; 13'bOll111011lOzz: data-tmpl=10'bOll11010111; 5 13'bOll111101111Oz data-tmpl 1 10'bOll110l1011; 13'bOll11111OOOzzz data-tmpl 10O'bOll110101l1; 13'bOll11111001Ozz data-tmpl =1O'b1lll1l1ll; 13'bOll1111001100 data-tmpl 1Olll10l0ll; 13'bOll1111001lzl data-tmpl 10Olll0llOOO; 13'bOll1111Ozll110 data-tmpl =10'bOlll0llOOO; 13'bOll1111lzl Ozzz data-tmpl1 13'bOll11llzll1Ozz data-tmpl 10O'bOll11011000; 13'bOll1111lzll1l1z data-tmpl 13'bOll111llzll11l1:data-tmpl 10'bOll11011000; 13'bOll111111Ozzzz data -tmpl =10'bOll1101100; 13'bOlllllllllllQ data-tmpl =10Olll0llOOO; 13'blOO000QOOzzzz: data-tmpl 1 10'bOll11011000; 13'blOOOOOO0lQOzz: data-tmpl =10'bOlll0llOOO; 13'blOOOOOQOlzlzz: data-tmpl =10Olll0llO0l; 13'blOOOQO00zll1Ozz :data-tmpl =10'bOlll0llO0l; 13'blOOOOlOzzzz: data-tmpl =10Olll0llO0l; 13'blOOOOOOllOzzz: data -tmpl =1OUb1lll1llO1; 13'blO000000111lzz :data-tmpl =10Olll0llO0l; 13'blOOOO0lOOzzzz: data-tmpl =10Olll0llO0l; 13'blO00000101Ozzz data-tmpl =10Olll0llO0l; 1lTb100001 1Ozz data-tmpl 1 10O'bOl1110l1100l; 13'blO0000010111Oz data-tmpl 10Olll0llO0l; l3 t blOOOOOlzllllz: data-tmpl 10Olll0ll0lO; 13'bl100000 11Ozzzz data-tmpl1 1 Tbl100000 111Ozzz data-tmpl1 10'bOlll0ll0lO; 13'blO000001111Ozz data-tmpl =1OMb1lll1ll1l; 13'blQ0000011111 z data -tmpl =10ObOll1101l01; 13'blOOO0lOOzzzzz data -tmpl 1 1 ObOl1110l110l1; 13'blOOO0l0lOOzzz: data-tmpl 13'blOOQ0l0lzlzzz: data-tmpl =10'bOlll01ll1l1; 1 'bl000010 11Ozzz data -tmpl 10'bOlll0ll0ll; 13'bl10000 11Ozzzzz data-tmpl =1O'bOll11011011; 13'blOOO01lIlOzzzz: data-trnpl =10'bOlll0ll0ll; 13'bl0000 1111OOzz data-tmpl1 10'bO1110ll10ll; 13'bl00001111zl zz data -tmpl1 10O'bOl1110l1110; 13'bl10000l11111Ozz data-tmpl1 10Olll0lllOO; 13'blOO0lOOzzzzzz: data -tmpl 10'bOll11011100; 13'blOO0l0lOOOOOQ data-tmpl =10Ol101llOO; 13'blOO0l0lOOO0zl data -tmpl =1OUb1lll1lll1; 13'blOO0l0lOO0zlO data -tmpl =10Olll0lll0l; 13'blO000101O0zl Oz data -tmpl =10Olll0lll0l; 13'blO000101O0zll 11data -tmpl =1OUb1lll1lll1; 13'blOO0l0l0zlOzz: data-tmpl =10Olll0lll0l; 13'bl 000101Ozll110 data -tmpl =10'Oll10lll0l; 13'blOOOlOlzlOzzz: data-tmpl =10Olll0lll0l; WO 98/19410PCIS7111 PCTIUS97/18911 137 13'blOOOlOlzll1l1z: data-tmpl 13'blOOOlOlzlllll :data-tmpl 13'blO0001011Ozzzz data -tmpl 13'blO000101111 zz data -tmpl 13'blOO00101111110 data-tmpl 13'blOO01llOOzzz: data-tmpl 13'blOO0llOOOlOzz: data-tmpl 13'blOO0llOOOllOz: data-tmpl 13'blO000110001110O data-tmpl =10'b1lll11ll1; lObOll1011101; 10'bOll1011101; 1'Olll0lll0l; =1'Ol101ll0l; =1'Ol101ll0l; =1'Olll0lll0l; =1'Olll0lll0l; =1'Olll0lll0l; 13'blO00011O0zll11:data-tmpl 13'bl1000 11Ozl1Ozzz data-tmpl 1 l3 t blO00011Ozll1Ozz data-tmpl 13'blO00011Ozll1Oz data-tmpl 13'blOOOllOzllllO: data tmpl lObWlll0llllo; 13'blO0001101Ozzzz data -tmpl =10'b0111011110; 13'bl 000110111111 data -tmpl =10'bOll1011110; 13'blOO01lllQOzzzz: data-tmpl 10'bOll1011110; 13'blO00011101Ozzz data-tmpl 13'blO000111011Ozz data -tmpl 13'blOOlll0lll0z: data -tmpl 13'bl 000111011110: data-tmpl 10Olll10llllQ; 13'blQ00011lzll111:data-tmpl 13'blO0001111Ozzzz data -tmpl 13'blO00011111Ozzz data -tmpl 13'blO000111111Ozz data -tmpl 13'bl 0001111111Oz data -tmpl 13'blOO1l11111110 data -tmpl 13'blOOlOOOOzzzzz data_tmpl 13'blOOlOOOlOzzzz: data-tmpl =10'b0111011111; l'bOlllOlllll; =1'bOlllOlllll; =1'O lll0lllll; =1'O l101llll; =10'bO1l0lllll; 13'blOOlO0zllzzzz: data-tmpl 13'bl100l00 1Ozzzzz data-tmpl1 10'bOl111100000; 13'blOOlOOllOzzzz data -tmpl 1 10bOl111100000; 13'blOOl0lOOOOOOz: data -tmpl 1 10bOll11100000; 13'b1001010000010: data-tmpl 1 1ObOl111100000; 13'bl 00101OOO0zll1 data -tmpl 1 10'bOll11100001; 13'bl100l1 1OOzl Oz :data -tmpl lObMllllOOO0l; 13'blOOl0lOO0zllO data -tmpl =10'b111100001; 13'blOOl0lO0zlOzz data -tmpl 1 10'bOll11100001; 13'blO00101O0zll11 data -tmpl 1 1 O'bOll11100001; 13'blOOlOlOzlOzzz data -tmpl1 1 lObOll11100001; 13'blO00101Ozll11Oz data -tmpl 1 10bOll11100001; 13'blO00101Ozll110 data -tmpl =1'OllllQO00l; 13'blOOl0l0l07777 data -tmpl =10'bOll11100001; 13'blO001010111Ozz data -tmpl =10'bOlll1100001; 13'blO001010111111:data -tmpl 1 1ObOll11100001; 13'blO001011OOzzzz data -tmpl 1 10bOll11100001; 13'blO00111OOzz data -tmpl 1 10'bOll11100001; 13'blOOl01l101010z: data tmpl 1 1ObOll11100001; 13'blOOl0ll0l0llO data-tmpl 1 10bOll11100001; 13'blOOl0ll0lzlll data -tmpl =1'OllllOO00l; 13'blO001011zll1Ozz data-tmpl =1'OllllOO00l; WO 98/19410 WO 9819410PCTIUS97/1891 1 138 data-tmpl 10OllllQ00lO; 13'blO001011zll1110 data-tmpl 10'bOllllOO0lO; 13'blOOl0lll07777 data -tmpl 13'blO00101111Ozzz data-tmpl lOtMllllOO0lO; 13'blOOlllllll 111data -tmpl =1OWb1llllOO1l; 1 Tbl100 11OOOzzzzz data -tmpl =10OllllOO0lO; 13'blQ0011001OOzzz data-tmpl =10OllllOO0lO; 13'blO001100101Ozz data-tmpl OtMllllOO0lO; 13'blOOllO0l0llOO data-tmpl =10OllllOO0lO; 13'blOOll100101lzl :data-tmpl =1OWb1llllOO1l; 13'blQ00100zl 110 data-tmpl 1 10bOll11100011; 13'bl00 11Ozl11Ozz data-tmp1 =10OllllO00ll; 13'blOOll0zllllll :data-tmpl 1 10bOll11100011; 13'bl01Ol 11Ozzz data -tmpl 1 10bOll11100011; -13'blOO1llllllz :data -tmpl =10'OllllOO00l; 13'blOOllOllllllO: data tmpl 1OllllQQ00ll; T 10bl110ll11OOzz: data-tmpl 1 13'blOOll101111110: data -tmpl =10'Ollll00lOO; 13'bl001lll0O~zOzz :data-tmpl 1 10'bOll11100011; 13'blOOll1l00zlzz :data-tmpl =10'Ollll00lOO; 13'blO00111l0zlllzz data-tmpl =lObOllllO0lOO; 13'bl 01OllOzzz data-tmpl =10Ollll00lOO; 13'b1001110111Qzz: data-tmpl =10Ollll00loO; 13'blO0011101Ozzzz :data-tmpl 10Ollll00lOO; 13'blO001110111Ozz- data-tmpl 10Ollll00lOO; 3 10 1 11OllOzzzdata -tmpl =10bOllllO0lOO; 13'blO001110OllQ data -tmpl 1 OtMllllQ0lOO; 13'blOOllll0lllzz data-tmpl =10OllllQ00ll; 13'bl 001111011100 data-tmpl 1OMb1llllO1l; 13'bl001110lzzzdata-tmpl 10OllllO00l0l; 13'bl00ll1l10zzdata-tmpl 1'OllllO00l; 13'bl 0011111Ozz data-tmpl 10'bOllllO0l0l; 13'blOOllllllllzz data -tmpl 10bOllllQ0l0l; 13'blOO11ll1llllll data -tmpl 1OMb1llllO1l1; 13'blOOOOO111zzz data -tmpl-=-iQ'OllllO00l0; 13'blOOOO1l1zzzz: data -tmpl 10'bOllllQ0l0l; 13'bl 01OO0lOOzzzdata-tmpl 1ObOll11100l10; 13'blOlOOOOlOz: data-tmpl 10bOllllO0l0l; 13'blOlOOO01ll~llO data-tmpl =1Ollll00l0l; 13'blOlOOOOllzlll :data-tmpl =10'b111100110; 13'bl 01OO0zll11Ozz :data-tmpl =10Ollll00llO; 13'bl 01OO0zll111Oz data -tmpl =1OMb1llllO1ll; 13'bl 01OO0zll11110 data -tmpl 10Ollll00llO; 13'blOlOOOlOzzzzz :data-tmpl =10'bOll11100110; 13'blOlOOOllOzzzz: data -tmpl =10Ollll00llO; 13'bl 01000111Ozzz data -tmpl =10Ollll00llO; 13'bl 010001111111:data -tmpl =10'bOl1ll 13'blOlOOlOOOzzzz: data -tmpl =10OllllQ00ll; 13'blOlOOlO0lOOOz: data -tmpl =10OllllQ00lO; 13'blOlOOlO0lO0lO:data-tmpl =1O'bOlllloollo; WO 98/19410 WO 9819410PCT/US97/1891 1 139 l3'bl 01010Ol 1 data-tmpl 1 ObOll11100111; 13'blOlOOlOOlzlOz: data-tmpl =10'bOllllO0lll; 13'blOlO0lO0lzllO: data-tmpl 10Ollll00lll; 13'blOlOOlOzllOzz:data-tmpl =10'bOllllO0lll; 13'bl 01001Ozll1111:data-tmpl 1010'~l~l; 13'blOlOOlzlO7zzz data tmpl =10'bOll11100111; 13'bl 01001011 Ozzz data~tmpl 10bOll11100111; 13'blOlOO101lll0z:data~tmpl 10Ollll00lll; 13'bl 010010111110:data -tmpl 13'bl 010011Ozzzzz data_ tmpl 10'b111100111; 13'bl 01001111777 data -tmpl 10Ollll0lOOO; 13'blOlOlOOzzzzzz: data tmpl 10'bOllll0lOOO; 13'blOl0l0lO0zzzz data~tmpl 10Ollll0lOOO; 13'blOlOlOlzlzzzz: data-tmpl 1OWb1llll1lO1; l3'blOlOlOllOzzzz: data-tmpl 10Ollll0lO0l; 13'bl10l0 11OOzzzzz data-tmpl1 10bOll11l01001; 13'bl 0101101Ozzzz data-tmpl lOUb1llll1lO1; 13'blOlOllzllzzzz: data-tmpl 10'bOllll0l0lO; 13'bl 01011077z: data tmpl 10'bOllll010lO; 13'bl 0101111Ozzzz data-tmpl 10'b0111101010; 13'bl10l11OQQOOzzzz: data -tmpl 10Ollll0l0lO; 13'blOllOQO0lOO0z: data-tmpl 10bOll11101010; 13'bl 011000010010 data-tmpl 10'Olll10l0lO; 13'blOllOOO0l0zll data-tmpl 10'bOllll0l0ll; 13'blOllOOO0lzl~z: data-tmpl 10'bOll1110101l; 13'bl 01100001zll10 data -tmpl 10'bOllll101011; 13'bl 011QO0zll1Ozz data -tmpl 1O'bOllll0l0ll; 13'bl 011lQ0zl 1111 data-tmpl 10'bOllll0l0ll; -13'bl 011OO0ll zzz datatmpl =10'bOll11101011; 13'blOllOO0llll0z: data -tmpl1 10'bOll11101011; 13'bl 011000l111110data-tmpl 1O'bOll.11Q1011; 13'bl 011001Ozzzzz data-tmpl 1 10bOll11101011; 13'bl 01001OOzz data-tmpl =10'bOll11101011; 13'blOllOOlll0l0z: data-tmpl 10'b0111101011; 13'bl 011001110110 data-tmpl =10'b111101011; l3'blOll10011lzll11 data-tmpl 10'bOll11101100; 13'blOllOOllll0zz: data-tmpl 10Ollll0llOO; 13'blOllOOlllll0z: data-tmpl 1 ObOll11101100; 13'blOllO0lll1110: data -tmpl 10'bOlll1101100; 13'bl10l10 1Ozzzzzz data -tmpl 10Ollll0llOO; 13'bl 011011OOzzzz data-tmpl 010'0lO; 13'bl 011110Ozzz data -tmpl 1 10bOll11101100; 13'bl0l110110 11Ozz data-tmpl1 =10'Olll10llO; 13'blOllOllOlll~z: data-tmpl =10'Olll10llOO; 13'blOllOllzllllz: data -tmpl 1O'bOll11101101; 13'bl 0110111Ozzzz :data-tmpl 10Ollll0ll0l; 13'blOllOllllOzzz: data -tmpl 10Ollll0ll0l; 13'blOllOlllll~zz: data -tmpll1OWb111101101; 13'blOllOllllll-1z: data-tmpl 10'bOl1 lll101; WO 98/19410 WO 9819410PCTIUS97/1891 1 140 13'blOlllOOzzzzzz: data-tmpl 10'b111101101; 13'bl 011101OOOOzz :data tmpl= 1Q'bOll11101101; 13'bl0lll0lQQ0l0z: data~tmpl 10Ollll0ll01; 13'blOlllOlOOzllz: data-tmpl 13'bl 011101Ozl Ozz :data-tmpl 13'blOlllOlOzll~z: data-tmpl 13'blOlllOlzlOzzz: data-tmpl 413'blOll1l1lzll11lz: data-tmpl 13'blOlllOllOzzzz: data-tmpl 13'bl 011101111Ozz :data-tmpl 13'blOll1101111l1z: data tmpl 13'blOllllOOzzzzz: data-tmpl 13'bl101110lOOzzz :data-tmpl1 13'blOllllOlOl~zz: data tmpl 13'blOllllOlOll~z: datatmpl 13'bl 011110101110: data-tmpl =10'bOll11101110; 10Ollll0lllO; 10Ollll0lllO; 10'bOll11101110; 1 ObOll1101110; 1 10b0111101110; 1 10bOll11101110; 1 10bOll1101110; 1 10b01 11101110; 13'blOll11l1lzll111:data-tmpl =10'bOll11101111; 13'bl 01111zllOzzz data-tmpl1ObOll11101l11; 13'blOllllzlllOzz data-tmpl 1O'bOllllOllll; 13'blOllllzllll~z: data tmpl 13'blOll11lzll11110O data~tmpl =10'bOll11101111; 13'blOlllllOzzzzz: data tmpl 10'bOll11101111; 13'bl 0111111Ozzzz data-tmpl 10'bOll11101111; 13'blOlllllllllll :data -tmpl =10Ollll0llll; 13bl11OOOOOOOzzzz: data -tmpl= 13'bll0000001Ozzz data-tmpl=10'bOllll01lll; 13'bl1000000 11OOz data -tmpl 13'bllOOOO0ll0lD:data-tmpl 13'bll10000001lzll1 data -tmpl 13'bl11OOOOOzl111Oz: data -tmpl 10'bO1llllOOOO, 13'bll1O0OO0zll1110 data-tmpl 1 10bOll11110000; 13'bll1OOO0zl Ozzzz data-tmpl 1 10bOll11110000; 13'bl11OOOOzl11Ozzz data-tmpl 1 1 ObOll111l0000; 13'bllOOO00zll11Ozz: data -tmpl= 13'bll1OQO0zll11111:data-tmpl =10'bOll11110000; 13'bl110000 1Ozzzzz: data-tmpl 1 1 Ob01 11110000; 13'bll100001111l1z: data -tmpl 10'bOl111110000; 13'bll10000l111111 data-tmpl 1 1Ob~ll11110000; 13'bllOO0lOOO0zzz: data-tmpl 1 10bOl 11110000; 13'b1100010001000 data-tmpl 1 1ObOll11110000; 13'bllOO0lOO0l0zl :data -tmpl 1 10bOll11110001; 13'bllOO0lOO0lzlO :data -tmpl =10'bOll11110001; 13'bllOO0lO0zll~z: data-tmpl =10'bOll11110001; 13'bll10001O0zll111:data_tmpl 1 1ObOll11110001; 13'bllOO0l0zlOzzz: data -tmpl 1 1ObOll11110001; 13'bll10001Ozll1Ozz data -tmpl 1 10bOll11110001; 13'bll10001Ozll1110 data -tmpl 1 1ObOll11110001; 1 Tbl11000 1zl1Ozzzz data-tmpl 1 1 ObOll11110001; 13'bllOO0l0llll0z: data-tmpl 13'bll10oQ~~ll 11data-tmpl 1 10bOll11110001; 13'bl11000 11Ozzzzz data -tmpl =10OlllllOO0l; 13'bllOO0llll0zzz: data- tmpl =10'bOlllllOO0l; WO 98/19410 141 13'bll10001111lzzz :data-tmpl =1O'bOll11110010; 13'bllOOlOOzzzzzz: data tmpl =1O'bOll11110010; 13'bl110010 1Ozzzzz :data-tmpl 1 10'bOl1111100l1; 13'bll1001011OOzzz data~tmpl 1 10'bOll11110010; 13'b110010110100z: data-tmpl =10'b0111110010; 13'bllOOl0ll0lzlz: data-tmpl =1OUb1lllllO1l; 13'bll1001011zll1Oz :data-tmpl =10'OlllllO00l; 13'bllOOl0lll0zzz: data-tmpl 13'bllOOl0llll0zz: data -tmpl =10'bOlllllO0ll; 13'bllOOl0llllllz: data-tmpl 13'bll1001077zz: data-tmpl =10Olllll00ll; 1 'bl1100 111OOzzzz data-tmp 1 10'b01 11110011; 13'bl1100l110 1Ozzz data-tmpl1 =10'b01111100 11; 13'bll100111011Ozz data-tmpl 1Ob01 11110011; 13'b 1100111011100 data-tmpl 1'b01 111100 11; PCTIUS97/1891 1 13'bll1001110111zl :data-tmpl 13'bll10011lzll1110 data-tmpl 13'bll1001111 zzzz data-tmpl.

13'bll10011111Ozzz data-tmpl 13'bl1100111111Ozz data-tmpl 13'bllOOlllllll0z: data-tmpl 13'bll100111111111:data-tmpl 13'bllOlOOOzzzzzz: data-tmpl 13'bllOlOOlO0zzzz: data-tmpl 13'bll10100101OOOz data-tmpl 13'bllOlOOl0lO0lO data-tmpl 10'bOll11110100; 1 ObOll11110100; 1 Ob01 11110100; 1 ObOll11110100; 10'b01 11110100; 1 'b01 11110100; 1 Ob~ll11110100; 1lO t bOll11110100; 10O'bOll11110100; 10'bOll11110100; 10'bOll11110100; 13'bllOlOOl0l0zll data -tmpl 10bOll11110101; 13'bll10lO0l0lzl~z: data -tmpl =10'bOll11110101 13'bll10lO0l0lzll10 data-tmpl l0'bOll11110101; 13'bllOlOOlzllOzz: data-tmpl 10'bOlllllOl 01; 13'bll10lO0lzll1111:data-tmpl 10'bOlllll0l0l; 13'bll101001lOzzzz: data-tmpl 13'bllOlOOlll0zzz: data -tmpl 10'bOlllll0l0l; 13'bllOlOOlllll0z: data-tmpl 1'bOlllllOlOl; 13'bll101001111110O data-tmpl 10'bOlllll0l0l; 13'bllOlOlOzzzzzz:data-tmpl 10'bOlllll0l0l; 13'bll10101lOOOzzz: data-tmpl 13'bllOlOllOOlO0z: data-tmpl 13'bllOlOllOOlzlz: data-tmpl 10Ollll10llO; 13'bll101011Ozll1Oz data-tmpl 13'bll101011zl Ozzz data -tmpl 10bOll111l011; 13'bllOlOllzllOzz: data-tmpl 13'bllOlOllzllllz:data-tmpl 13'bll1010111Ozzzz data-tmpl 1 ObOl 11110110; 13'bll1010111111oz data-tmpl 10bOlll111011O; 13'bll101lOOzzzzzz data -tmpl 13'bllOllOlOOOOzz: data-tmpl -13'bllOllOlOOzlzz: data-tmpl 13'bllOll0l0zlOzz: data-tmpl 13'bllOllOlzlOzzz: data-tmpl 13'bllOllOlzlllzz: data-tmpl 10'bOll11110111; 10'bOll11110111; WO 98/19410 WO 9819410PCT[US97/18911 142 13'bllOllOllOzzzz: data-tmpl 10'bOll111101l1; 13'bll101101111Ozz :data-tmpl=10'bOll11110111; 13'bll10111Ozzzzz 13'bllOllllzzzzzz:data-tmpl 10O'bOll11111000; 13'bl111OOODOzzzzz: data-tmpl 1 10'b01 11111000; 13'bll1100001Ozzzz data-tmpl =10'b0111111000; 13'b 1110000 11Ozzz data-tmpl 1 10'bOl111111000; 13'bll110000111Ozz data-tmpl 13'bll1100001111Oz data-tmpl 10'b0111111000; 13'blllOOOzlllllz: data-tmpl 13'bll110001Ozzzzz data-tmpl 1 ObOll11111001; 1 31b111000 11Ozzzz data-tmpl1 10'bOll1111100l; 13'bll11000111Ozzz data-tmpl 10'bOll1111l001; 13'bll10001111 zz data-tmpl =l1ObOll11111001; 13'b1 1100011111Oz: data-tmpl 10'b01 11111001; 13'blllOOlO0zzzzz: data-tmpl 10'b01 11111001; 13'blllOOl0l0zzzz: data-tmpl 13'bll11001011Ozzz data-tmpl =l1O t bOll11111001; 13'bll110010111Ozz data-tmpl 10'bOll11111001; 13'bll1100101111Oz data -tmpl 10'bOll11111001; 13'bll10010111110 data-tmpl =10'b0111111001; 13'bll11O0lzll11111 data-tmpl 10'b0111111010; 13'blllOOll0zzzzz: data-tmpl 1 'bll1100 111Ozzzz :data-tmpl1 13'bll1100111lOzzz: data-tmpl= 10'b01 11111010; 13'bll11001111lOzz: data-tmpl =10'bOll11111010; 13'bll100111111Oz data-tmpl =10'b0111111010; 13'bll10011111110 data-tmpl 13'bl1110 1OOzzzzzz: data-tmpl 1 1 O'bOl1111110l1; 13'blllOl~lOOOOOz: data-tmpl 13'bll10101OO0zlz :data -tmpl 10'bOll11111011; 13'blllOlOlOOzl10z: data-tmpl 10'bOllllll0ll; 13'blllOlOlOzlOzz: data-tmpl 13'blllOlOlOzlllz data-tmpl 13'bll110101zl Ozzz data-tmpl =1Q'bOll11111011; 13'bll10101zll1Oz data -tmpl =10'bOll111110l1; 13'blllOlOllOzzzz data -tmpl 10'bOl1111110l1; 13'bll10101111Ozz data-tmpl =10'b0111111011; 13'blllOlOl11111z: data -tmpl 10'bOll11111011; 13'bll1101lOzzzzzz data-tmpl 10O'bOll11111011; 13'bll10111OOOOzz data -tmpl=10'bOllllll0ll; l3 t blllOlllOO0l0z: data-tmpl 13'bll110111000110O data-tmpl 13'blll10111O0zll :1data-tmpl 13'bll110111Ozl Ozz data -tmpl 13'bl11011lzl10z: data-tmpl 13'bll110111Ozil110: data-tmpl 13'blll1011lzl~zzz: data-tmpl 13'bll11011lzll1111:data-tmpl 13'bll110111107777 data -tmpl 13'bll110111111Ozz data-tmpl 1 10bOll11111100; 1 10b01 11111100; =10'b0111111100; WO 98/19410 PCTIUS97/18911 143 13'bll110111111l1z: data-tmpl 10'bOll11111100; 13'b1 110111111110:data-tmpl =10'b01 11111100; 13'bll11OOOzzzzzz data-tmpl=10'bOll11111100; 13'bl1110lOOOzzz data-tmpl 1 10Mb1111111lO; 13'bll1110 100 1Ozz data-tmpl 1 10M1111111llO; 13'bllllO00lO0ll0z: data-tmpl 13'bllllOOl0zllz: data-tmpllO'bOlllllll0l; 13'bll111001z1lOzzz data-tmpl =10'bOlllllll0l; 13'bll11100lz1l1 zz data-tmpl 10'b0111111101; 13'b1lllOOlzlll0z data-tmpl =10'bOlllllll0l; 13'bl1101Olzz: data -tmpl 10'bOlllllll0l; 13'bllllO00llllllz: data -tmpllO'bOlllllll0l; 13'bllllOlOzzzzzz data tmpl =10'bOlllllll0l; 13'bll11011OOzzzz data~tmpl 1Q'bOlllllll01; 13'bll1101101Ozzz data-tmpllO'bOlllllll0l; 13'bl11110 11z1l1zzz data-tmpl 10111'blllll; 13'bll110111Ozzzz data-tmpl 10'bOll1111111; 13'blll1101111Ozzz data-tmpl=1Q'Ollllllll; 13'bl1111OOzzzzzz data -tmpl 10'Ollllllll0; 13'bll11101Ozzzzz data -tmpl 10Mb11111111l; 13'blllll0llQO0zz: data-tmpl 13'blllllOllOzlzz data-tmpl 13'blllllOllzlOzz: data-tmpll=O1'bOlllllllll; 13'bll111lzll1lOzzz data-tmpl 13'bll111lzll111lzz: data-tmpl 13'bl11111Ozzzzzz data-tmpllO1'bOlllllllll; l3'bll111111Ozzzzz data-tmpl 13'bll1111111Ozzzz :data -tmpl1 13'bll11111111Ozz data -tmpl default: data tmpl 1 0'bxxxxxxxxxx; endcasealways @(posedge clk) if (enable_3) data-tmp2 data-tmpl; assign out-data data tmp2; endmodule Listing 14 /I Sccsld: %G% Copyright 1997 Pioneer Digital Design Centre Limited Author Dawood Alam.

Description: Verilog code for windowing algorithm to enable detection of the "lactive interval" of the COFDM symbol for guard values of: 64, 128, 256, 512 and an active interval of 2048. (RTL) Notes This module generates the window signal for the FFT in the form WO 98/19410 PCT/US97/18911 144 of valid in and provides the necessary signals for the I/Q demodulator, sync interpolator and error handler.

To DO: Check between successive symbol acquires for consistency in timing.

Window timing pulse tracking mode, filter peaks IQ and sync interpolator guard pulses.

Override functions for timing.

Gain confidence by comparing symbol_acq vs retrys 'timescale 1ns/ 100ps module fftwindow (in_xr, inxi, clk, nrst, validin, validout, in_resync, out_iqgi, out_sincgi, out_rx_guard, out_acquired, out fft window, enable 3 4, out_test, track ramaddr( xri_tmp1, track ramrnotvw trackramenab ram_addr, ram_enable, ram_rnotw, raml0_in, ram xlr_10, z2r_10, z2i 10, fftramrnotw, fft ram enable, fftram_addr); //To FFT datapath //To FFT datapath From FFT datapath (I) From FFT datapath (Q) From FFT addr gen.

From FFT addr gen.

From FFT addr gen.

II

II

Parameter definitions.

parameter parameter parameter parameter parameter wordlength 12; r_wordlength 10; AddressSize 13; FIFO L 256; FIFOL bits 8; Data wordlength.

/I ROM data wordlength.

Size of address bus.

//Tracking FIFO length.

Track FIFO addr bits WO 98/19410 PCT/US97/18911 145 parameter parameter parameter parameter parameter parameter parameter parameter parameter parameter parameter parameter FIFO N 64; H Acc length S(i-j).

FIFO n 64; H Acc length S(i-n-j).

FIFO A =32; t_offset dly FIFO+1.

FIFO A bits 5; //Track FIFO bits.

luAddressSize 15; H log lu address size.

delta 20; H Gu threshold distance acquired_symbols 2; Acq symbls before trk posthreshold 3; H For info only.

toffsetthreshold 10; t offset valid thresh w_advance= 10; win trig frm boundary sincint latency 2; H Latency to sinc intep iqdemodlatency 168; Latency to IQ demod.

start 3'b000, Search for neg peak.

1 3'b001, 1st pos peak found.

2 3'b010, 2nd pos peak found.

3 3'b011, I 3rd pos peak found.

1 3'b100, Tracking model.

2 3'b101; Tracking model.

parameter 'Ir HI Ii H peak peak peak track track nput/Output ports.

nputlOutput ports.

input clk, Master clock.

nrst, I Power-up reset.

valid_in, I Input data valid.

in resync, Sync FSM into Acqure.

fft ramrn motw, ftram_enable; input [AddressSize-1:0] fft_ram_addr; input [wordlength-3:0] in_xr, FFT input data, I.

in_xi, FFT input data, Q.

Track RAM output.

input [wordlength*2-1:0] raml0_out; input [wordlength-1:0] z2r_10, z2i_10; output [word length*2-1:0] ram10_in; output [wordlength-3:0] xritmpl; H From 1K x 24 bit RAM.

H From FFT datapath.

I To 1K x 24 bit RAM.

Track RAM input.

output [14:0] out_test; output outiqgi, I out sincgi, Sin out acquired, H 1 out fft window, H enable 3 4, validout, track ramrnotw, track ramenable, ramenable, Temp testpin output.

I/Q demod guard info.

c int. guard info.

Symbol acquired flag.

FFT processor st/stp WO 98/19410 PCT/US97/18911 146 ram_rnotw; output [FIFO_L_bits-1:0] track_ram_address; //II Tracking ram address output [1:0] out_rxguard; Acquired gu length.

output [AddressSize-1:0] ram_addr; output [wordlength-1:0] xlr_10, xli_10; II To FFT datapath.

Wire/register declarations.

reg outacquired, II Symbol acquired flag.

outfftwindow, II FFT window signal.

tracking, I Tracking mode data.

accadd, Acc add only flag.

accaddsub, //Acc add/sub flag.

fifoaaddsub, FIFOA add/sub flag.

f ratio valid, F ratio is valid read, Track FIFO read flag.

write, Track FIFO write flag track_mode, Track/Acq status flag dpctlreset, Datapath control rst.

t_reset, Timing counter reset.

g_a_reset, Guard_active cnt rst.

guardvalid, Guard signal is valid tretimeacq, Retime timing counter tretimetrk, Retiming for tracking t offsetvalid, Peak offset valid.

toffsetavg valid, Average offset valid.

pulse, Pulse on states 4 enable_fft, FFT enabled.flag.

out sincgi, Guard int to sincint.

outiqgi, Guard int to iq demod ramenable, ramrnotw; reg [14:0] guard_active; Guard+active length.

reg retry, No failed retry's.

acq symbols; No of acquired symbls reg [wordlength-2:0] xri tmp7; Delayed difference.

reg [wordlength-3:0] xrreg, (10 bits) xi_reg, xritmpl, Sumof II IQI.

xritmp3, Delayed I difference xritmp6; FIFO 2KIL output.

reg [FIFOL bits-1:0] read_address, Track FIFO write_address, Track FIFO write adr.

track_ram_address; Tracking ram address; read addr.

reg [lu AddressSize-1:0)] acc; reg .[word length-4:0] xrtmpl, xi tmpl-;

IQ.

/H Holds input variance.

|1.

WO 98/19410 PCTIUS97/18911 147 reg r; H Clock decode counter.

reg outrx guard; H Determined guard.

reg [r_wordlength:0] f ratio; Statistical F ratio.

reg [10:0] fft validcount; I Counts no of FFT vlds reg [AddressSize-1:0] windowram_addr, //ram add ram_addr; reg [14:0] t_count, H Window timing count.

t_offset; H Peak offset from t ct reg [14:0] g_a_count; H Guard active counter.

reg [14:0] dp_count; H Datapath timing count reg [14:0] toffsetavg; //Averaged offset.

reg state, Acq/Track FSM state.

old_state; H Old tracking state.

reg guard length; H Thresholded guard len ress counter.

reg [FIFOA bits:0] fifo a count; 1 bit more retime reg [r_wordlength-1:0] max peak; Count till fifo a ful H Maximum positive peak reg [wordiength-1:C Isb intmp wire [AddressSizemsb_out tmp, i; even symb 1:0) fftram_addr; Master clock.

Power-up reset.

wire clk, nrst, enable 0 4, H Clock en enable_1 4, H Clock ena enable 2 4, H Clock en enable 3 4, H Clock en enable_0_8, H Clock en enable_1 8, H Clock ena enable_2_8, Clock en enable_3_8, Clock en enable_4_8, H Clock en enable_5_8, Clock ena enable 6_8, H Clock en enable 7_8, H Clock en ramenable_8, H Acq Fl track_ram_enable, Trac track_ram_rnotw, Track evensymbol, valid on in resync, I Resync to pos_peak, +ve peak, dpcontrol, H Datapath toffset_ctl, Trk avera fftram_ rnotw, fftramenable; wire [lu AddressSize-1:0] lu_address; wire [r_wordlength-1:0] lu data, xritmp9; wire [wordlength-3:0] xritmp2, xritmp4, in_q, out_q; H Temporary stores for ols to RAM.

H From FFT RAM addr gen able 0 in 4.

ble 1 in 4.

able 2 in 4.

able 3 in 4.

able 0 in 8.

ble 1 in 8.

able 2 in 8.

able 3 in 8.

able 4 in 8.

ble 5 in 8.

able 6 in 8.

able 7 in 8.

FO enable.

king RAM enable ing RAM rnotw.

even symbols acqn mode.

ref only! acq/trk ctl.

ger dp ctl.

WO 98/19410 WO 9819410PCTIUS97/1891 1 148 wire [wordlength-1:0] ramin; reg [word length-1: lsb...out, msb-out; reg [word length- 1:0] ramout, msb-in, Isb_in; wire [word length*2- 1: 0] ramlO0-out; reg [word length*2- 1: 0)ram10_in; reg [wordlength-1:0] xlr 10, wire [word length- 1:0] z2r 10, z2i_10; wire [14:0] out-test; wire [14:0] tLoffset-duff, IActual +-difference t -offset thresh, IIValid offset (maybe) t -offset-dly, Delayed of above.

t-offset-scalled, Scalled tot toffset.

read pos, IIread trig, +ve offset read -neg, IIread trig, -ye offset write pos, IIwrite trg, +ve offset write neg; IIwrite trg, -ye offset assign out-test t-offset-diff; IIFast 40 MHz clock decoder and valid in control.

H always @(posedge, clk) if (!nrst) IISynchronous power-up reset.

r 0; else if (valid in) IICount if input data valid.

r r +1'bl; assign enable_-0_4 assign enable_1_4 assign enable -2 -4 assign enable_3-4 valid in Gate valid in with valid-in (-nil] rIO]); decoded enable signals valid -in ri] I/to control all reg's.

valid-in r[1] Enables every 4 clk's assign enable 1 8 valid-in assign enable28 valid-in assign enable 3 8 valid-in assign enable48 valid in assign enable 5 8 valid-in assign enable68 valid-in assign enable_7_8 valid-in (-r[21 rnh r[1] -rnh] Enables every 8 r[2] clk's r[2] r[1] -rIO]); r[2] r[1] IThe entire data path incorporating the FIFO's, ROM and comparators.

IRegister the data inputs to the windowing module.

always @(posedge clk) if (in resync 11 !nrst) WO 98/19410 PCTIUS97/18911 149 begin xr-reg in-xr; xi -reg in-xi; end else if (enable_3_4) begin xr-reg in-xr; xi -reg in-xi; end II Take the modulus of in-xr and in-xi and add together (jin xrj lin .xij).

always @(xr-reg or xireg) begin if (xr -reg [word length-3]) IIChecking MSB for negative number.

xr -tmpl -xr-reg; else xr-tmpl xr-reg; if (xi reg [word length-3]) Axitmpl -xi reg; else xi-tmpl xireg; Checking MSB for negative number.

xritmpl xr tmpl xitmnpl; end assign even symbol always @(evensymbol or msb-out-tmp or ram in or 1~ if (even symbol) allow 1 K RAM begin /to act as a 2K ram-out lsb_out; IIFIFO, possible lsb -in -tmp ram_in; since data end IIbitwidth is 2b else IIbits wide in begin the 1 K RAM and ram-out msb_out-tmp; only b bits are msb-in ram-in; required in the end Idata path.

always @(posedge clk) IIDelay even begin symbols by one if (enable 5 8) IIsymbol so that ls i <sb in tmp; Itwo symbols are if (enable_7_8) IIwritten read msb_out tmp mnsb_out; IIto the ram.

end sb-out) Mux MSB/LSB to assign xri tmp2 ram_out; assign ram-in xri-tmpl; II Map RAM Ito dp wires.

always @(ramlo0 out or msb in orlsb in or z2r_10 or z2i or ram enable_8 oren-able_3_8 or fft ram enable orift ram rnotw or window-ram-addr or fft ram addr or tracking) II FFTN\IINDOW FIFO WO 98/19410 PCT/US97/18911 150 begin IIRAM Mux code.

if (tracking) I/In window acq begin IImode.

msb-out ramlI out[2*word length- 1:word length]; lsb out rami 0...out[word length-1: HI Connect window ramlO_inE2*wordlength 1 :word length] =msb in; datapath RAM raml1O_in[word length- 1: 0] lsb-in; I control signals ram-enable ram-enable_8; ram rnotw enable_3_8; ram addr window-ram_addr; end else I n tracking begin mode, therefore ramlO -outI[2*word length- 1:word length]; FFT functional.

xli 10 raml 10outlword length- 1: 0]; rarIFi 0_i n[2 *word length -1 :word length] z2r_10; Connect FFT raml1O_inllword length- 1:0) z2i_10; H/datapath RAM ram-enable ift-ram-enable; IIcontrol signals ram-rnotw =ffl-ram-rnotw; ram-addr fft-ram-addr; end end assign track-ram-rnotw enable_3_4 read; assign track-ram-enable (enable_3_-4 read) I(enable_1_4 write); HI Select which FIFO we read data from depending on tracking or acquire mode.

always @(xri-tmps or xri tmp2 or tracking) if(tracking) xri -tmp6 xri-tmp5; Tracking mode else HI data.

xri-tmp6 xri-tmp2; II Acquisition mode data.

IPerform computation of s(i-j) always @(xri-tmpl or xri-tmp6) xri-tmp7 xri tmpl xri-tmp6; HI Take the modulus of xri-tmp7; always @(xri-tmp7) if (xri -tmp7[wordlength-2]) IICheck MSB for xri -tmp3 -xri-tmp7; HI neg number.

else xri-tmp3 xri-tmp7; IISetup FIFO to perform moving summation of s(i-j) values.

ffi-sr-addr #(wordlength-2, FIFON) srN (clk, dp control, IILength=FIFON.

xri-tmp3, /Input.

xri-tmp4); II Output.

/1Compute the moving summation iLe S(i-j) s(i-1 j-1) s(i-2,j-2) IWe must NOT truncate or round acc as the error will grow across a symbol.

always @(posedge clk) if (in resync I!nrst Idpctlreset) II Clear accumulator at acc 0; IIpower-up or Resync or trk. else if (dp_control acc-add) /Wait until acc data valid.

Subtract as well as add when 2K/BK FIFO is full.

WO 98/19410 PCTIUS97/18911 151 acc acc xri~tmp3 ((acc-add_sub) xri-tmp4 assign lu-address acc; HI Ensure lu -address is large enough to HI accomodate acc number range.

iftwindow lu _word length, luAddressSize) HI Case table instance loglu (cik, dp_control, lu_address, lu-data); Ifor a log lookup.

HI Setup 5 bit FIFO to determine the delayed variance.

ifisr-addr _word length, FIFO n) sn (cik, dp control, Length=FIFO-n.

lu-data, IInput.

xri~tmp9); II Output.

HI Determine difference of logs and hence the f -ratio when it is valid.

always @(lu_data or xri tmp9 or f ratio valid) f ratio (fLratio valid)?l lujdata xri tmp9 H IIPositive threshold (for information only) assign pos peak ratio pos threshold fLratio (1 r-wordlength)) 1'b1 :1'bO); II FFT window datapath control registers.

always @(posedge clk) if (in resync !nrst dpctlreset) IISynchronous reset.

begin f-ratio valid 1'b0; IIInitalise datapath acc -ad-d 1 'b0; IH control registers.

acc-add-sub end else if (enable_3_4 -read) IIAcquisition mode begin Use 2K/8K FIFO.

if (dp count 2047 FIFON FIFO -n 1 1)/I f-ratio only valid f-ratio-valid I'bM; HI after sum of FIFO if (dp..count 2047) +acc+ROM latencys acc-add 1'bl; /Add if acc full.

if (dp count 2047+FIFON) Add/sub when FIFO acc add sub 1'bl; H/N is full.

end else if (enable_3_4 read) H1 Tracking mode begin IIUse FIFO L.

if (dp count FIFOL FIFO_ N FIFO n 1 1) f ratio only valid f ratio valid 1'bl 17 after sum of FIFO if (dp c-ount FIFOL QI +acc+ROM latencys acc-add 1'bl; IH Add if acc full.

if (dp count FIFOL FIFON) II Add/sub when FIFO acc-add-sub i'bi; 7N is full.

end always @(posedge clk) if (in resync I!nrst) Synchronous reset.

WO 98/19410 PCT/US97/18911 152 fifo a add sub 0; else if (enable_3_4 fifo_a_count FIFO A) fifo_a is full fifo a add sub 1; so add and sub.

always @(posedge clk) if (in_resync |I !nrst) Synchronous reset.

t_offset_avg_valid 1'b0; Average value is else if (enable_3 4 fifo a count FIFO A 1) valid one cycle t offset_avgvalid 1'bl; //after add_sub sig.

assign dp_control enable_3_4 Datapath enable (-track_mode I trackmode read); in acq/track mode.

assign t offsetctl enable_3_4 toffsetvalid clock averager pulse !read tracking; dp control signal.

FFT window timing and sync acquisition/tracking timing counters.

always @(posedge clk) if (in_resync I !nrst I t_reset) Synchronous power-up reset.

t_count 0; Reset main timing counter.

else if (enable_3_4 t_retimeacq) Retime to count from last tcount t count guard_active; peak to current time.

else if (enable_3_4 -track_mode) Count if not in track mode t count t count-+ 1'bl; else if (enable_3_4 t_retimetrk) Otherwise must be in track t_count t count guardactive so advance timing for acq (2*FIFO_N FIFO_n FIFO_L read trig point then else if (enable_3_4) begin wrap round t_count at if (tcount 2047+guardlength) end of guard+active length.

t_count 0; Needed as a reference to else track peak movement in t_count t count 1'bl; capture window.

end always @(posedge clk) if (in_resync I !nrst I g_a_reset)- Synchronous power-up reset.

g_a_count 0; Reset guard_active counter.

else if (enable_3_4 f_ratiovalid) g_a count when f ratio vald g_acount ga_count 1'bl; Guard active timing counter always @(posedge clk) Datapath timing counter.

if (in_resync I !nrst I dpctl_reset) Synchronous reset.

dpcount 0; Reset datapath control.

else if (enable_3_4 -track_mode) Always count in acquire dp_count dp_count 1'b; mode on clk 0.

else if (enable_3_4 track_mode read) Count when reading data in dp_count dp_count 1'bl; tracking mode.

always @(posedge clk) if (in_resync I !nrst) Synchronous reset.

fifo a count 0; else if (enable_3_4 toffset ctl) //Only clock averager if Trk WO 98/19410 PCTUS97/18911 153 fifo a count fifo a count 1'bl; and t offset is valid.

always @(posedge clk) Create pulse on entering if (enable 3 4) track 4 or track 5 to clk begin t offset _ctl once per state if ((state trackl transition. We need to old_state trackl) I I clock the averager only (state track2 once on entering state 4 or old state track2)) I state 5 hence t offset ctl 0 pulse 1'bl; I is gated with pulse.

else pulse 1'bO; oldstate state; end always @(posedge clk) if (in resync I I !nrst) tracking 'bO; II Read from 2K/8K FIFO first.

else if (enable_3_4 track_mode !0 dp_count ==FIFO L+1) Check if FIFOL full in trk tracking l'bl; then read tracking FIFO_L.

FFT window timing and sync acquisition/tracking II FFT window timing and sync acquisition/tracking FSM always @(posedge clk) Acquisition mode F if (in resync II !nrst) Synchronous power-up begin state start; FSM starts in resync.

track _mode 1'bO; Start in acquisition rr treset 1'bO; I Reset main timing count dpctl reset 1'bO; dp ctl out of reset.

ga reset 1'bO; I Reset guard active c maxpeak 1'bO; Reset max peak valu retry 0; Reset no of retry's.

acqsymbols 0; I Reset acquired no sy guard valid 1'bO; I Guard data is valid.

tretime acq 1'bO; Do not retime at res t retime trk 1'bQ; I Do not retime at resy end else if (enable_34) case (state) start: begin ga reset 1'bO; g_a_reset out of rst t reset 1'bO; t count out of reset.

guardvalid 1'bO; //Guard invalid.

MUST ACT ON RETRYS TOO!! state peakl; Enter peak1 state.

end 3M.

reset.

ode.

:er.

ounter.

e.

mbols.

ync.

nc.

rs*/ peakl: begin t reset 1'b0; t count out of reset.

if (ga_count 2048+512 Search for pos peaki begin if (fratio-> max _peak WO 98/19410 PCT/US97/18911 154 f ratio (1 rwordlength))// Is new peak larger? begin max peak f ratio; I If so assign max peak t_reset 1; I Reset timing counter.

end end else I First block complete.

begin t reset 'bO; l t count out of reset.

g_areset 1'bl; Reset gacount.

maxpeak 1'bO; Reset max peak value.

state peak2; I Next block search.

end end peak2: begin ga reset 1'b0; Next block start cnt if (g_a_count 2048+512) Search for pos peak2 begin if (fratio maxpeak fratio (1 r_wordlength)) Is new peak larger? begin maxpeak f ratio; H If so assign max peak guard active tcount; Assign guard active.

end end I/ Second block complete else First, one peak per block situation (large guards) (guard_active (2560+delta)&& Test for 2048+512 guard_active (2560-delta))| II pt guard length.

(guard_active (2304+delta)&& Test for 2048+256.

guard_active (2304-delta))I I pt guard length.

(guard_active (2176+delta)&& Test for 2048+128 guard_active (2176-delta)) I pt guard length.

(guard_active (2112+delta)&& Test for 2048+64 guard active (2112-delta))I pt guard length.

Now two peaks per block situation (small guards) (guardactive (5120+delta)&& Test 4096+512+512 guard_active (5120-delta)) I/I /pt guard length.

(guard_active (4608+delta)&& Test 4096+256+256 guard_active (4608-delta))I I pt guard length.

(guard_active (4352+delta)&& Test 4096+128+128 guardactive (4352-delta))I I pt guard length.

(guard_active (4224+delta)&& Test 4096+64+64 guardactive (4224-delta))) pt guard length.

begin state peak3; Next peak search.

ga reset 1'bl; Reset g_acount.

maxpeak 1'bO; Reset maximum peak.

guardvalid 1'bl; WO 98/19410 PCT/US97/18911 155 t_retime_acq 1'bl; end else Acquisition failed so begin jump to start and state start; I/ increment the retry retry retry 1'bl; I/ counter.

t_reset 1'bl; Reset t count.

g_a_reset 1'bl; Reset g_a_count.

max_peak 1'b0; I/ Reset maximum peak.

end end peak3: begin t_retimeacq g_a_reset 1'b0; Next block start cnt if (g_a_count 2048+512) Search for pos peak2 begin if (f_ratio max_peak f_ratio (1 r_wordlength)) Is new peak larger? begin max_peak fratio; I/ If so assign max_peak guard_active t_count; II Assign guard_active.

end end I/ third block complete else if(I/ First, one peak per block situation (large guards) (guard_active (2048+guardlength II Peak test 2048 +delta)&& II guard length.

guard_active (2048+guard_length -delta))|

I

Now two peaks per block situation (small guards) (guard_active (4096+(2*guard_length)// Peak 4096 2 +delta)&& //*guard length.

guard_active (4096+(2*guard_length) -delta))) begin acq_symbols acq_symbols+1'bl;// Another sym acqurd g_a_reset 1'bl; Reset g_a_count.

maxpeak 1'b0; I/ Reset maximum peak.

t retime trk 1'bl; I/ Retime t count to trk trackmode 1'bl; Enter track mode.

dpctl_reset 1'bl; Reset datapath count state trackl; I/ Enter track1 state.

end else Acquisition failed so begin //jump to start and state start; increment the retry retry retry 1'bl; I/ counter.

t reset 1'bl; Reset tcount.

g_a_reset 1'bl; Reset g_a_count.

max_peak 1'b0; I/ Reset maximum peak.

end end trackl: begin t_retime_trk l'b0; tcount out retime.

WO 98/19410 PCTIUS97/18911 156 dpctl_reset 1'b0; dp ctl out of reset.

if (read f_ratio_valid) H Peak detect on rd&vld begin if (f_ratio max_peak f ratio (1 r_wordlength)) Is new peak larger? begin max_peak fratio; If so assign max_peak t offset t_count; I Store peak offset.

end if (read_address FIFO_L-1) If at end of FIFO_L begin I/ move to next state.

state track2; //(read_Addr FIFO_L) max_peak 1'b0; Reset max peak value.

end end else state track1; end else wait in track1.

track2: begin if (read f_ratio_valid) Peak detect on rd&vld begin if (f_ratio max_peak f ratio (1 r_wordlength)) Is new peak larger? begin max_peak f_ratio; If so assign max_peak t offset t_count; Store peak offset end if (read_address FIFO_L-1) At end of FIFO L begin move to next state.

state trackl; (read Addr FIFO_L) max_peak 1'b0; I/ Reset max peak value.

end end else state track2; end I Wait in this state.

default: state 3'bXXX; endcase I, I/ FFT window output decode logic.

H always @(posedge clk) if (in_resync I !nrst) Synchronous reset.

outiqgi 0; else if (enable_3_4 tracking t_count 15'd0 iqdemod_latency) I/ iqgi guard start.

out_iqgi 1'bl; else if (enable_3_4 tracking t_count iqdemod_latency) iqgi guard stop.

outiqgi always @(posedge clk)

L

WO 98/19410 PCTIUS97/18911 157 if (in_resync I I Inrst) //Synchronous reset.

out sincgi 0; else if (enable_3_4 tracking t_count 15'd0 sincintIatency) sincgi guard start.

out sincgi 1'bl; else if (enable_34 tracking TO COMPLETE LATENCY STUFF tcount sincintlatency) sincgi guard stop.

outsincgi 1'bO; always @(posedge clk) I Count over active if (in_resync |I !nrst) H interval to generate enable_fft 1'bO; FFT valid pulse.

else if (enable_3_4 tracking t count guard length FIFOL/2 wadvance) FFT start point is enablefft 1'bl; in middle ofwrite else if (enable_3_4 tracking I into FIFOL advced.

fft_valid_count 2047) FFT stop after 2048 enable_fft 1'bO; samples.

always @(posedge clk) if (in resync I I !nrst) //Synchronous reset.

fft valid count 0; else if (enable_3_4 tracking -enablefft) Valid count 0.

fft valid count 0; until fft is enabled.

else if (enable_3_4 tracking enable fft) fftvalidcount fft_valid_count 1'bl; Count when enabled.

assign valid_out enable_fft validin; //MUST SYNCHROS VId every 3 clks?

I

Synchronous RAM address generators.

always @(posedge clk) Acqsition FIFO address gen.

if (!nrst I Iin resync) //Synchronous reset.

window ramaddr 0; I Address gen for acq mode.

else if (enable_2_8) window ramaddr windowram_addr 1'bl; assign ram enable 8 enable_2_8 enable 3 8 enable4_8 I1 enable5_8; always @(posedge clk begin if (!nrst I in_resync) begin readaddress C writeaddress C write 1'bO; read 1'b; end else if (enable_3_4) begin if (trackmode read 1'bl; H Tracking FIFO address gen.

Reset track FIFO read addr.

H Reset track FIFO write addr //Track FIFO, write disabled.

Track FIFO, read disabled.

t_count 0) trigger poil //Track FIFO read WO 98/19410 PCT/US97/18911 158 if (read) //Read if 'read' begin flag is set.

if (read_address FIFO_L-1) St begin II end of FIFO.

read address 0; read 1'b0; II CIr read flag.

end else read_address readaddress 1'bl; end op read at Inc r address.

if (trackmode t_count guard_length+1) II Write if the write 1'bl; read is guard II depth into FIFO if (write) begin if (write_address FIFO_L-1) II Stop write at begin II end of FIFO.

writeaddress 0; write end else write_address write_address 1'bl; Inc w address.

end end end always @(enable_1_4 or enable_3_4 or read or write or II Assign read and readaddress or write_address) write addresses if (enable_3_4 read) II onto common track ram address readaddress; address bus else if (enable_1_4 write) for tracking track_ram_address write_address; tsyncram RAM.

II

II

II

Thresholding function to determine precise guard interval.

always @(posedge clk) if (enable_3_4 guardvalid) begin First, one peak per block situation (large guards) if (guard_active (2560+delta)&& Test for 2048+512 guardactive (2560-delta)) pt guard length.

begin out_rxguard 2'b11; guardlength 512; end if (guard_active (2304+delta)&& guard_active (2304-delta)) begin out_rx_guard 2'b10; guard_length 256; end Test for 2048+256 pt guard length.

WO 98/19410 PCT/US97/18911 159 a if (guard_active (2176+delta)&& guard_active (2176-delta)) begin out_rx_guard 2'b01; guard_length 128; end if (guard_active (2112+delta)&& guard_active (2112-delta)) begin outrx guard 2'b00; guardlength 64; end Now two peaks per block situatic if (guard_active (5120+delta)&& guard_active (5120-delta)) begin out_rx_guard 2'b11; guard_length 512; end if (guard_active (4608+delta)&& guard_active (4608-delta)) begin out_rx_guard 2'b10; guard_length 256; end if (guard_active (4352+delta)&& guard_active (4352-delta)) begin out_rx_guard 2'b01; guard_length 128; end if (guard_active (4224+delta)&& guard_active (4224-delta)) begin out_rx_guard 2'b00; guard_length 64; end end Test for 2048+128 pt guard length.

Test for 2048+64 pt guard length.

)n (small guards) Test for 4096+512+512 //512 pt guard length.

Test for 4096+256+256 256 pt guard length.

Test for 4096+128+128 //128 pt guard length.

Test for 4096+64+64 64 pt guard length.

Averager for t_offset in tracking mode.

issign t_offset_diff t_offset (2*FIFO_N FIFO_n); //dly 2 for latency? ilways @(posedge clk) if (in_resync I !nrst) //NEED TO ENABLE t offset valid 0; else if ((t_offset_diff (1 14 1) t_offset_threshold Neg t_offset diff (1 14- I| (t_offset_diff t_offset_threshold I/ Pos _W0~1W 98/19410 PCT/US97/18911 160 t_offset_diff (1 14)) //CORRECT TO DETECT vid 1 not 0 t offset valid 0; else t offset valid 1; assign t_offsetthresh (t_offset_valid) toffset_diff: 0; Setup FIFO to perform moving summation of toffset values.

fftsraddr FIFOA) sr_A (clk, t_offset_ctl, t_offset_thresh, Input.

t_offsetdly); II Output.

Compute the moving summation i.e t offset(i-1) toffset(i-2) We must NOT truncate or round acc as the error will grow across a symbol.

always @(posedge clk) if (in_resync I I !nrst) II Clear accumulator at t_offset_avg 0; II power-up or Resync.

else if (toffset_ctl) //Wait until t_offset valid.

Subtract as well as add when averager is full.

t_offset_avg t_offset_avg toffset_thresh ((fifo_a_add_sub) t_offset_dly 0); assign toffset_scalled {{(FIFO_A_bits){toffset_avg[14]}},t_offset_avg[14:FIFOA bits]}; II Code to determine conditions for advancing/retarding tracking window.

II assign read_pos toffsetscalled; +ve (late) so //delay read assign read_neg 2047 guard_length 1 I/ -ve (early) so (~t_offset_scalled II advance read assign write_pos guard_length 1 II +ve (late) so t_offset_scalled; II delay write PROBLEMS WHEN offset guard_length 1 II (should not happen as we range check peaks in acq mode) assign write_neg guard_length 1 -ve (early) so (~t_offset_scalled II advance write endmodule Listing II Sccsld: %G% SCopyright 1997 Pioneer Digital Design Centre Limited Author Dawood Alam.

Description: Verilog code for a structural netlist coupling the Fast Fourier Transform-(FFT) processor to the window acquisition hardware.

WO 98/19410 PCT/US97/18911 161 Notes 'timescale 1ns/ 100ps module fft_top (i_data, q_data, clk, nrst, in_resync, in_2k8k, valid in, ram4_in, ram6_in, ram7_in, ram8_in, ram9_in, i_out, q_out, out_ovf, enable_0, enable_1, enable_2, enable_3, valid_out, ram4_out, ram6_out, ram7_out, ram8_out, ram9_out, raml0_out, ram_addr, ram_enable, ram rnotw, rom3_addr, rom4_addr, rom3_data, rom4_data, trackaddr, track datain, trackdata_out, track_rnw, track_ram_enable, out_rx_guard, outiqgi, out_sincgi, out_test); Param r d Parameter definitions.

HI

WO 98/19410 PCTIUS97/18911 162 parameter parameter parameter parameter parameter parameter parameter parameter parameter parameter parameter parameter parameter parameter parameter parameter parameter parameter parameter parameter wordlength 12; Data wordlength.

c_wordlength =10; Coeff wordlength.

AddressSize 13; II Size of address bus.

rom_AddressSize 13; II ROM address bus size.

multscale 3; Multiplier scalling: /4096, 2 /2048, 1024, 4 =/512.

r_wordlength 10; ROM data wordlength.

FIFO L 256; Tracking FIFO length.

FIFO L bits 8; Track FIFO addr bits FIFO_N 64; //Acc length S(i-j).

FIFO n 64; //Acc length S(i-n-j).

FIFO A 32; I/ toffset delay FIFO.

FIFO A_bits Track FIFO bits.

luAddressSize 15; log rom address size.

delta 20; I/ Gu threshold distance acquired_symbols 2; II Acq symbls before trk pos_threshold 3; //for info only.

t offsetthreshold 10; t offset valid thresh w_advance 10; win trig frm boundary sincint_latency 2; Latency to sinc intep iqdemod_latency 168; II Latency to IQ demod.

II

Input/Output ports.

input clk, nrst, in_2k8k, valid_in, in_resync; input i_data, q_data; Master clock.

Power-up reset.

//2K mode active low.

Input data valid.

FFT input data, I.

FFT input data, Q.

input [wordlength-3:0] track_data_out; input [wordlength*2-1:0] ram4_out, II Couple the I/Q data ram5_out, outputs from the ram6_out, memory to the ram7_out, respective butterfly ram8_out, //processors.

ram9_out, raml0_out; input [c_wordlength*2-1:0] rom3_data, rom4_data; output [rom AddressSize-6:0] rom3_addr; output [romAddressSize-4:0] rom4_addr; output [14:0] out_test; Temp testpin output.

output [1:0] outrx_guard; //Acquired gu length.

WO 98/19410 WO 9819410PCTIUS97/1891 1 163 output [word length-3:0] track-data_in; output [word length*2 1: ram4_in, IICouple the IIQ data IIoutputs of each BF ram6_in, IIprocessor to their ram7_in, IIrespective memory ram8_in, Iinputs.

ram9 in, output [AddressSize-1 ram_addr; RAM address bus.

output out -ovf, I/ Overflow flag.

enable_0, IIEnable clock 0.

enable_1, IIEnable clock 1.

enable_2, IIEnable clock 2.

enable_3, IIEnable clock 3.

valid -out, IIOutput data valid.

ram enable, IIRAM enable.

ram rnotw, track rmw, track-ram-enable, out "iqgi, out sincgi; output [FIFO_L-bits-1:0] track_addr; output [word length- 1:0] i out, EFT output data, 1.

q_out; FFT output data, Q.

II Wire/register declarations.

wire i -data, q_data; FFTANIN input 1.

IFFT/WIN output Q.

wire [word length- 1: 0] i Iout, FFT output data, 1.

,q_out; FFT output data, Q.

wire [word length*2 1: ram4_in, in, ram6_in, ram7_in, ram8_in, ram9_-in, ramlO_in; wire [word lefgth*21: ram4_out, ram5 out, rami6_out, ram7_out,ram8_out, ram9_out, raml1O6out; WO 98/19410 WO 9819410PCTIUS97/1891 1 164 wire [Add ressSize-1 ram_addr, ram-addr_ft_2_win; RAM address bus.

wire clk, nrst, in_2k8k, in_resync, valid-in, out ovf, enable_0, enable_1, enable_2, enable_3, valid out, ram-enable, IIRAM enable signal.

ram -rnotw, valid -win 2 ift, ram -rnotWfft 2 win, ram -enable -ift_-2 -win, trackrmw, track-ram-enable, out-iqgi, out sincgi; wire [word length-I 1:0] z2r_10, z2i-I xlr_1 0, x1L_10, 0; wire [word length- 3: 0] track-data_in, track-data_out; wire [FIFOLbits- 1:01 track-addr; wire [1:01 out-rrxguard; Determined guard.

wire [cwordlength*2-1 rom3_data, rom4_data; wire [romAddressSize-6:0] rom3_addr; wire [romAddressSize-4:0] rom4_addr; wire [14:0] out-test;

HI

Instance FFT processor.

ift-r22sdf #(wordlength, c word length, 7AddressSize, romAdd ressSize, mult -scale) ifi (.in -xr(iLdata), HI FFT input data, I.

.in xi(q data), HI FFT input data, Q .clk(clk), HI Master clock.

.nrst(n rst), Power-up reset.

.in_2k8k(in-2k8k), H 2K active low.

WO 98/19410 WO 9819410PCTIUS97/1891 1 165 .valid -in(valid -win_2_fft),II Input valid.

.out xr(i out), IFT output data, 1.

.out-xi(q_ out), HI FFT output data, Q.

.out -ovf(out-ovf, IIOverflow flag.

.enable0(enable_0), .enabl-e_1(enable_1), .enable_2(enable_2), .enable_3(ram rnotw -ift_-2 -win), .valid -out(valid out), .ram -add ress(ram_addr_ffl2 win), ram -enable(ram-enable ifi_2_win), .add ressrom 3(rom3_addr), .add ressrom4(rom4_add r), H/RAM input ports.

.z2 r_4(ram4_ in[word length-1: .z2i_4(ram4_in~wordIength*2 1 :word length]), in[word length- 1: .z2i_5(ram5_in~wordIength*2-1 :word length]), .z2r_6(ram6_in[word length-1: .z2 i_6(ram6_ in[word length*2 1 :word length]), .z2r_7(ram7_in~wordlength-1 .z2i_7(ram7_in[wordlength*2-1 :wordlength]), .zfr_8(ram8_ in[word length-1: .z2i_8 (ram8_in[wordiength*2-1 :wordlength]), .z2r 9(ram9in [word length-1: .z2 i_9(ram9_ in[word len gth*2- 1 :word le ngth)), .z2r_10(z2r 10),HI Erm FFT datapath to window .z2i_T0(z2i_f0),// Erm FF1 datapath to window HI RAM output ports.

.xlr r4(ram4_o ut[word length-1: .X1 j_(ram4_out[wordlength*2- 1 :word length]), length- 1: .Xl _5 (ram5_out~wordength*2 1 :word length]), .xlr r6(ram6_out~wordlength-1 .x1 i_6(ram6_out~wordlength*2-1 :word length]), .xl r_7(ram7-_out[word length-1: .X1 i_7(ram7_out~wordlength*2-1 :word length]), .xlr_8(ram8_outlword length- 1: .xli i_(ram8_out~~wordlength*2-1 :word length]), .xl- _9(ram9_out[wordlength-1 .xli _9(ram 9_out[wo rd length*2 1: :word length]), 10),IITo FFT datapath frm window .xl _I (xl i_1 0),II To FF1 datapath frm window ROM output ports.

.br_-3(rom3_-data[cword length*2-1 :c -word length)), .bi_-3(rom3_d ata[cword length-1: .br _4(rom4_data[cwordlength*2-1 :c-word length]), bi_4(rom4_d ata[cword length-1: H H Instance FIF1 window processor.

WO 98/19410 PCTIUS97/18911 166 iftwindow #(wordlength, r -wordlength, AddressSize,

FIFO_L,

FIFO L bits, FlF EN, FIFO_n

FIFOA,

FIFOA bits, luAddressSize, delta, acquired symbols, pos threshold, t-offset -threshold, w -advance, sincint latency, iqdemod latency) window (.in xr(i data), .in xi(q data), .clk(clk), .nrst(nrst), -valid -in(valid in), .valid-out(valid-win2fft), inresync(inresync), .out iqgi(out iqgi), .out-sincgi(o-ut sincgi), out rxguard(outrx guard), *out-acquired(out-acq uired), .outift window(out-ift-window), .enable_34(enable 3), .out test(outtest), Atrack- ram address(track-addr), .xritmpl(frack data_in), .xri -tmp5(track~data out), .track -ram rnotfw(track rmw), .track -ram-enable(track ram-enable), .ram -addr(ramaddr), ram_enab le(ram_e nab le), .ram_rnotw(ramrnotw), .raml10_in(raml 1Oin), /To 1 K x 24 bit RAM.

.raml Oout(raml 0_out), From 1 K x 24 bit RAM.

.xlr_-10O(xlr1 10), /To FFT datapath 10), ITo FFT datapath .z2r _10(z2r 10), From FFT datapath (1) .z2i_-10(z2i_10), HI From FFT datapath (Q) .fft ram notw(ram rnotw ffi 2 win), .fft-ram enable(ram-ena~le fft-2_win), .fft-ram addr(ram-addr-fftt2 win)); endmodule Listing 16 I2048 point FFT twiddle factor coefficients (Radix 4+2).

ICoefficients stored as non-fractional 10 bit integers (scale 1) IIReal Coefficient (cosine value) is coefficient high-byte.

IImaginary Coefficient (sine value) is coefficient low-byte.

WO 98/19410 WO 9819410PCTIUS97/1891 I 167 0111111111 0000000000 01111111111111111010 0111111111 1111111100 01111111111111101010 0111111111111111010 0111111111 111110100 01111111111111100101 0111111111 111110001 0111111111 111111010 0011111111011110110010 01111111111111110 0111111111111101001 30011111111111110101 0111111110 111110100 011111111111101110 0111111111 11110100 1011111111111100111 0111111101 11111001000 0111111111 11110010 00111111111111100010 400111111101111100001 011111110110111101 0111111100 111101111 0111111100 1110111101 0111111111 11101110 01111111111110111010 011111110 1111101110 011111110 1111010110 0111111010 11110110101 0111111010 1111010011 0111111010 11110110000 01111111011111001111 011111110111101110 0111111001_111101100 0111111001_1-1110010 IWOOO_2048 1.-000000 IW0001_2048 +0.999995 IW0002_2048 +0-99998 1 IW0003_2048 999958 /W0004_2048 999925 /W0005 2048 +0.999882 IW0006_2048 +0.999831 /W0007_2048 +0.999769 IW0008_2048 +0.999699 /W0009_2048 +0.999619 IW001O_2048 999529 /W001I1_2048 +0.999431 //W0012_2048 +0.999322 /W001 3_2048 +0.999205 /W0014_2048 +0.999078 /W001 5_2048 +0.998941 /W0016_2048 +0.998795 //W0017_2048 +0.998640 //W0018_2048 +0.998476 11W0019_2048 +0.998302 /W0020_2048 +0.998118 /W0021_2048 +0.997925 IW0022_2048 +0.997723 IW0023_2048 +0.997511 /W0024 2048 997290 IW0025_2048 997060 /W0026_2048 996820 /W0027_2048 +0.996571 /W0028_2048 +0.996313 /W0029_2048 +0.996045 IW0030_2048 +0.995767 /W0031_2048 +0.995481 /W0032_2048 +0.9951 85 /W0033_2048 +0.994879 /W0034_2048 +0.994565 /W0035_2048 +0.994240 /W0036_2048 +0.993907 /W0037_2048 +0.993564 /W0038_2048 +0.993212 /W0039_2048 +0.992850 IW0040_2048 +0.992480 /W0041_2048 +0.992099 1W0042_2048 991710 /W0043_2048 +0.991311 /W0044_2048 +0.990903 /W0045_2048 +0.990485 IW0046_2048 +0.990058 /W0047_2048 +0.989622 /W0048_2048 +0.989177 /W0049_2048 +0.988722 /W0050_2048 +0.988258 IW0051 12048 +0.987784 IW0052_2048 987301 /W0053_2048 +0.986809 /W0054_2048 =+0.986308 /W0055_2048 =+0.985798 -0.000000 -0.003068 -0.006136 -0.009204 -0.012272 -0.015339 -0.018407 -0.021474 -0.024541 -0.027608 -0.030675 -0.033741 -0.036807 -0.039873 -0.042938 -0.046003 049068 -0.052132 -0.055195 -0.058258 -0.061321 -0.064383 -0.067444 -0.070505 -0.073565 -0.076624 -0.079682 082740 -0.085797 -0.088854 -0.091909 -0.094963 -0.098017 -0.101 070 -0.104122 -0.107172 -0.110222 -0.113271 -0.116319 -0.119365 -0.122411 -0.125455 -0.128498 -0.131540 -0.134581 -0.137620 -0.140658 -0.143695 -0.146730 -0.149765 -0.152797 -0.155828 -0.158858 -0.161886 -0.164913 -0.167938 WO 98/19410 WO 9819410PCT/US97/1891 1 168 0111111000 1110101000 0111111000 1110100111 0111111000-1110100101 0111111000-1110100100 0111110111 1110100010 0111110111-1110100001 0111110111 1110011111 0111110110 1110011110 0111110110 1110011100 0111110110 1110011011 0111110110 1110011001 0111110101 1110010111 0111110101 1110010110 0111110101 1110010100 0111110100-1110010011 0111110100 1110010001 0111110100 1110010000 0111110011 1110001110 0111110011 1110001101 0111110011 1110001011 011111001 01110001 010 0111110010 1110001000 0111110001 1110000111 0111110001 1110000101 0111110001 1110000100 0111110000 1110000010 01111100001110000001 01111011111101111100 0111101110 1101111010 011110111111011101110 0111101110 1101111010 3501111011111011101001 0111101100711011100111 01111011001110111010 0111101101 11101110100 01111010 1110111011 011110110110110101 011110101111011010000 0111101001 110110110 011110101001101100101 01111010001101101010 011110101 1101100010 01111010111110110000 0111101010110110111 011110101011010101 011110100110101001 011110010111011000 5501111000110 1101011101 550111 100011_1101010110 /W0056_2048 +0.985278 IW0057_2048 +0.984749 /W0058_2048 +0.984210 IW0059_2048 +0.983662 /W0060_2048 +0.983105 /W0061_2048 +0.982539 /W0062_2048 +0.981964 /W0063_2048 +0.981379 IW0064_2048 +0.980785 /W0065_2048 +0.980182 IW0066_2048 +0.979570 IW0067_2048 +0.978948 /W0068_2048 +0.978317 IW0069_2048 +0.977677 IW0070_2048 +0.977028 IW0071_2048 +0.976370 IW0072_2048 +0.975702 IW0073_2048 +0.975025 HI W0074_2048 +0.974339 HI W0075_2048 +0.973644 IW0076_2048 +0.972940 IW0077_2048 +0.972226 /W0078_2048 +0.971504 HI W0079_2048 +0.970772 IW0080_2048 +0.97003 1 IW0081_2048 +0.969281 IW0082_2048 +0.968522 IW0083_2048 +0.967754 IW0084_2048 +0.966976 /W0085_2048 +0.9661 90 HI W0086_2048 +0.965 394 HI W0087_2048 +0.964590 IW0088_2048 =+0.963776 IW0089_2048 +0.962953 /W0090_2048 =+0.962121 /W0091 2048 961280 /W0092_2048 960431 HI W0093_2048 +0.959572 HI W0094_2048 +0-958703 IW0095_2048 +0-957826 IW0096_2048 +0.956940 IW0097_2048 +0.956045 IW0098_2048 +0.955141 HI W0099_2048 +0.954228 HI W0100_2048 +0.953306 //WO1O1_2048 +0.952375 H/WO0102_2048 951435 //W0103_2048 =+0.950486 HI W0104_2048 +0.949528 //W0105_2048 +0.948561 //W0106_2048 =+0.947586 WO0172048 946601 //W0108_2048 +0.945607 //W0109_2048 +0.944605 //WO11O_2048 +0.943593 W0111_2048 +0.942573 -0.170962 -0.173984 -0.177004 -0.180023 -0.183040 -0.186055 -0.189069 -0.192080 -0.195090 -0.198098 -0.201105 -0.204109 -0.207111 -0.210112 -0.213110 -0.216107 -0.219101 -0.222094 -0.225084 -0.228072 -0.231058 -0 .234042 -0.237024 -0.240003 -0.242980 -0.245955 -0.248928 -0.251898 -0.254866 -0.257831 -0.260794 -0.263755 -0.266713 -0.269668 -0.272621 -0.275572 -0.278520 -0.281465 -0.284408 -0.287347 -0.290285 -0.293219 -0.296151 -0.299080 -0.302006 -0.304929 -0.307850 -0.310767 -0.313682 -0.316593 -0.319502 322408 -0.325310 -0.328210 -0.331106 -0.334000 WO 98/19410 PCT/US97/18911 169 0111100010_1101010100 0111100010 1101010010 0111100001 1101010001 0111100000_1101001111 01111000001101001110 01110111111101001100 0111011111 1101001011 01110111101101001001 0111011110 1101001000 01110111011101000110 01110111011101000101 0111011100 1101000011 0111011011-1101000010 01110110111101000000 01110110101100111111 01110110101100111110 01110110011100111100 01110110001100111011 0111011000 1100111001 01110101111100111000 01110101111100110110 01110101101100110101 01110101011100110011 01110100111100110010 0111010100 1100110001 01110100111100101111 0111010011-1100101110 0111010010 1100101100 0111010001 1100101011 0111010001-1100101001 0111010000 1100101000 0111010000 1100100111 0111001111-1100100101 01110011101100100100 0111001101 1100100010 0111001101 1100100001 0111001100-1100011111 0111001011 1100011110 0111001011 1100011101 0111001010 1100011011 0111001001 1100011010 0111001001 1100011000 0111001000 1100010111 0111000111 1100010110 0111000110 1100010100 0111000110 1100010011 0111000101 1100010001 0111000100-1100010000 0111000100-1100001111 0111000011 1100001101 0111000010 1100001100 0111000001-1100001010 0111000001-1100001001 0111000000-1100001000 0110111111 1100000110 0110111110-1100000101 //W0112_2048 +0.941544 //W0113_2048 +0.940506 H W0114_2048 +0.939459 //W0115_2048 +0.938404 H W0116_2048 +0.937339 IIW0117_2048 +0.936266 //W0118_2048 +0.935184 W0119_2048 +0.934093 II W0120_2048 +0.932993 W0121_2048 +0.931884 //W0122_2048 +0.930767 //W0123-2048 +0.929641 //W0124-2048 +0.928506 11W0125-2048 +0.927363 //W0126-2048 +0.926210 //W0127-2048 +0.925049 //W0128_2048 +0.923880 W0129-2048 +0.922701 //W0130-2048 +0.921514 W0131_2048 +0.920318 IIW0132-2048 +0.919114 //W0133_2048 +0.917901 /IW0134_2048 +0.916679 //W0135_2048 +0.915449 //W0136_2048 +0.914210 //W01372048 +0.912962 //W0138 2048 +0.911706 O W01392048 +0.910441 W0140 2048 +0.909168 //W0141 2048 +0.907886 //W0142-2048 +0.906596 W0143-2048 +0.905297 IIW0144-2048 +0.903989 //W0145-2048 +0.902673 IIW0146-2048 +0.901349 //W0147-2048 +0.900016 //W0148-2048 +0.898674 //W0149-2048 +0.897325 /W0150 2048 +0.895966 //W0151 2048 +0.894599 //W0152 2048 +0.893224 //W0153 2048 +0.891841 II W01 54 2048 +0.890449 HWO155 2048 +0.889048 H W0156 2048 +0.887640 H W01 57_2048 +0.886223 //W0158-2048 +0.884797 H/W0159 2048 +0.883363 //W0160-2048 +0.881921 //W0161-2048 +0.880471 //W0162-2048 +0.879012 //W0163-2048 +0.877545 //W0164-2048 +0.876070 W0165 2048 +0.874587 IIW0166-2048 +0.873095 //W0167-2048 +0.871595 -0.336890 -0.339777 -0.342661 -0.345541 -0.348419 -0.351293 -0.354164 -0.357031 -0.359895 -0.362756 -0.365613 -0.368467 -0.371317 -0.374164 -0.377007 -0.379847 -0.382683 -0.385516 -0.388345 -0.391170 -0.393992 -0.396810 -0.399624 -0.402435 -0.405241 -0.408044 -0.410843 -0.413638 -0.416430 -0.419217 -0.422000 -0.424780 -0.427555 -0.430326 -0.433094 -0.435857 -0.438616 -0.441371 -0.444122 -0.446869 -0.449611 -0.452350 -0.455084 -0.457813 -0.460539 -0.463260 -0.465976 -0.468689 -0.471397 -0.474100 -0.476799 -0.479494 -0.482184 -0.484869 -0.487550 -0.490226 WO 98/19410 PCT/US97/18911 170 0110111101 1100000100 0110111101 1100000010 0110111100 1100000001 0110111011 1100000000 0110111010 1011111110 0110111010 1011111101 0110111001 1011111011 0110111000-1011111010 0110110111 1011111001 0110110110 1011110111 0110110110-1011110110 0110110101 1011110101 0110110100 1011110011 0110110011 1011110010 0110110010-1011110001 0110110001 1011101111 0110110001 1011101110 0110110000 1011101101 0110101111 1011101011 01101011101011101010 01101011011011101001 01101011001011100111 01101010111011100110 0110101011 1011100101 0110101010-1011100100 0110101001 1011100010 0110101000-1011100001 0110100111 1011100000 0110100110 1011011110 0110100101 1011011101 0110100100 1011011100 0110100100 1011011010 0110100011 1011011001 0110100010 1011011000 0110100001 1011010111 0110100000-1011010101 011001101 11011010100 0110011110 1011010011 0110011101 1011010010 01100111001011010000 0110011011 1011001111 0110011010-1011001110 0110011001-1011001100 0110011000-1011001011 0110010011 1011001010 0110010111-1011001001 0110010110 1011000111 0110010101 1011000110 0110010100 1011000101 0110010011 1011000100 0110010010 1011000011 0110010001-1011000001 01100100001011000000 0110001111 1010111111 0110001110 1010111110 0110001101 1010111100 H W0168_2048 +0.870087 W0169 2048 +0.868571 fHW0170_2048 +0.867046 //W0171_2048 +0.865514 H W0172_2048 +0.863973 H/W0173_2048 +0.862424 H/W0174_2048 +0.860867 H/W0175 2048 +0.859302 W0176_2048 +0.857729 //W0177 2048 +0.856147 //W0178 2048 +0.854558 O W0179_2048 +0.852961 //W0180_2048 +0.851355 flW0181 2048 +0.849742 //W0182 2048 +0.848120 //W0183_2048 +0.846491 f/W0184_2048 +0.844854 //W0185_2048 +0.843208 //W0186 2048 +0.841555 //W0187-2048 +0.839894 IIW0188-2048 +0.838225 //W0189-2048 +0.836548 flW0190-2048 +0.834863 //W0191-2048 +0.833170 //W0192-2048 +0.831470 //W0193-2048 +0.829761 //W0194-2048 +0.828045 H W0195-2048 +0.826321 //W0196-2048 +0.824589 //W0197-2048 +0.822850 //W0198_2048 +0.821103 //W0199_2048 +0.819348 /W0200 2048 +0.817585 //W0201_2048 +0.815814 H W0202_2048 +0.814036 //W0203 2048 +0.812251 //W0204_2048 +0.810457 //W0205 2048 +0.808656 //W0206-2048 +0.806848 II W0207 2048 +0.805031 //W0208-2048 +0.803208 //W0209 2048 +0.801376 //W0210-2048 +0.799537 IW0211_2048 +0.797691 /W0212-2048 +0.795837 //W0213-2048 +0.793975 //W0214 2048 +0.792107 IIW0215 2048 +0.790230 //W0216 2048 +0.788346 //W02172048 +0.786455 flW0218_2048 +0.784557 //W0219_2048 +0:782651 HI W0220_2048 +0.780737 IIW0221_2048 +0.778817 IW0222_2048 +0.776888 IIW0223_2048 +0.774953 -0.492898 -0.495565 -0.498228 -0.500885 -0.503538 -0.506187 -0.508830 -0.511469 -0.514103 -0.516732 -0.519356 -0.521975 -0.524590 -0.527199 -0.529804 -0.532403 -0.534998 -0.537587 -0.540171 -0.542751 -0.545 325 -0.547894 -0.550458 -0.553017 -0.555570 -0.558119 -0.560662 -0.563199 -0.565732 -0.568259 -0.570781 -0.573297 -0.575808 -0.578314 -0.580814 -0.583309 -0.585798 -0.588282 -0.590760 -0.593232 -0.595699 -0.598161 -0.600616 -0.603067 -0.605511 -0.607950 -0.610383 -0.612810 -0.615232 -0.617647 -0.620057 -0.622461 -0.624859 -0.627252 -0.629638 -0.632019 WO 98/19410 W098/9410PCT/US97/1891 1 171 0110001100_1010111011 0110001011_1010111010 0110001010_1010111001 0110001001_1010111000 0110001000_1010110110 0110000111_1010110101 0110000110_1010110100 0110000101_1010110011 0110000100_1010110010 0110000011_1010110000 0110000010_1010101111 0110000001_1010101110 0110000000_1010101101 0101111111_1010101100 0101111101_1010101010 0101111100_1010101001 0101111011_1010101000 0101111010_1010100111 0101111001_1010100110 0101111000_1010100101 0101110111_1010100100 0101110110_1010100010 0101110101_1010100001 0101110100_1010100000 0101110011_1010011111 0101110010_1010011110 0101110001_1010011101 0101110000_1010011100 0101101110_1010011010 0101101101_1010011001 0101101100_1010011000 0101101011_1010010111 0101101010_1010010110 0101101001_101-0010101 0101101000_1010010100 0101100111_1010010011 0101100110_1010010010 0101100100_1010010000 0101100011_1010001111 0101100010_1010001110 0101100001_1010001101 0101100000_1010001100 0101011111_1010001011 0101011110_1010001010 0101011100_1010001001 0101011011_1010001000 0101011010_1010000111 0101011001_1010000110 0101011000_1010000101 0101010111_1010000100 0101010110_1010000011 0101010100_1010000001 0101010011_1010000000 0101010010_1001111111 0101010001_1001111110 0101010000_1001111101 H/W0224 2048 +0.773010 II W0225 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H/W0981_2048 -0.991311 H/W0982_2048 -0.991710 W0984_2048 -0.992480 II W0986_2048 -0.993212 W0987_2048 -0.993564 HI W0988_2048 -0.993907 W099072048 -0.994565 H/W0992_2048 -0.995185 H/W0993_2048 -0.995481 HI W0994_2048 -0.995767 W0996_2048 -0.996313 HI W0998_2048 -0.996820 W0999_2048 -0.997060 HI Wi 000_2048 997290 H/W1 002_2048 -0.997723 -0.313682 -0.31 0767 -0.307850 -0.302006 -0.296151 -0.293219 -0.290285 -0.284408 -0.278520 -0.275572 -0.272621 -0.266713 -0.260794 -0.257831 -0.254866 -0.248928 -0.242980 -0.240003 -0.237024 -0.231058 -0.225084 -0 .222094 -0.219101 -0.213110 -0.207111 -0.204109 -0.201105 -0.195090 -0.189069 -0.186055 -0.183040 -0.177004 -0.170962 -0.167938 -0.164913 -0.158858 -0.152797 -0.149765 -0.146730 -0.140658 -0.134581 -0.131540 -0.128498 -0.122411 -0.116319 -0.113271 -0.110222 -0.104122 -0.098017 -0.094963 -0.091909 -0.085797 -0.079682 -0.076624 -0.073565 067444 WO 98/19410 WO 9819410PCTIUS97/18911 182 1000000001 1111100001 1000000001 1111100010 1000000001 1111100100 1000000001 1111100111 1000000000 1111101010 1000000000 1111101100 1000000000 1111101101 1000000000-1111110000 10000000001111110011 10000000001111110101 10000000001111110111 1000000000 1111111010 1000000000 1111111101 1000000000 1111111110 1000000000 000000001 1 1 000000000 0000001000 1000000000 0000001101 10000000000000010001 1000000000 00000101 10 1000000001 0000011011 1000000001 0000011111 1000000001 0000100100 1000000010 0000101001 1000000010 0000101101 1000000010F0000110010 1000000011 0000110111 1000000011 0000111100 1000000100 0001000000 1000000101 0001000101 10000001010001001010 1000000110 0001001110 1000000111 0001010011 1000001000 0001011000 10000010000001011100 1000001001 0001100001 1000001010 0001100101 1000001011 0001101010 1000001100 0001101111 10000011010001110011 1000001110 0001111000 1000010101000100 100001001 0001000001 1000010011 0010000110 10000101000010001111 1000010110 0010010011 1000010111 0010011000 1000011000 0010011100 1000011010001l0100001 1000011011 0010100101 1000011101 0010101010 1000011110-0010101110 1000100000-00101 10010 1000100010c0010110111 1000100011 0010111011 10001001010011000000 /W1 004_2048 -0.998118 IWi 005_2048 -0.998302 HI Wi 006_2048 998476 HI W1 008_2048 -0.998795 H/W1010_2048 -0.999078 H/W10I112048 -0.999205 W1012_2048 -0.999322 /HW1014_2048 -0.999529 H/W1 016_2048 -0.999699 I 017_2048 -0.999769 /W1 018_2048 999831 HI Wi 020_2048 -0.999925 HI W1 022248 -0.999981 /W1 023_2048 -0.999995 /W1 026_2048 -0.999981 /W1 029_2048 -0.999882 H/W1 032_2048 -0.999699 H/W1 035_2048 -0.999431 HI Wi 038_2048 -0.999078 /W1 041_2048 -0.998640 /W1 044_2048 -0.998118 IWi 047_2048 -0.997511 /W1 050_2048 -0.996820 HI Wi 053_2048 -0.996045 H/W1 056_2048 995185 /W1 059_2048 -0.994240 /W1 062_2048 -0.993212 IW1 065_2048 -0.992099 /W1 068_2048 =;-0.990903 IWi 071_2048 -0.989622 HI W1 074_2048 -0.988258 II W077_2048 -0.986809 IWI 080_2048 -0.985278 HI WI 083_2048 -0.983662 IW1 086_2048 -0.981964 /W1 089_2048 -0.980182 /W1 092_2048 -0.978317 HI W1 095_2048 -0.976370 H/W1 098_2048 -0.974339 IHWi1101_2048 -0.972226 HI Wi 104_2048 -0.970031 H/W1 107_2048 -0.967754 W110_2048 -0.965394 I Willl 32048 -0.962953 /Wli116_2048 -0.960431 /Wli119_2048 -0.957826 H/W1 122_2048 -0.955141 W1 125_2048 -0.952375 HI Wi 128_2048 -0.949528 H/W1 131_2048 -0.946601 W1134_2048 -0.943593 H/Wi 137_2048 -0.940506 HI Wi 140_2048 -0.937339 HI Wi 143_2048 -0.934093 HI Wi 146_2048 -0.930767 Wi 149_2048 =-0.927363 -0.061 321 -0.058258 -0.055195 049068 -0.042938 -0.039873 -0.036807 -0.030675 -0.024541 -0.021474 -0.018407 -0.012272 -0.006136 -0.003068 +0.006136 +0.015339 +0.024541 +0.033741 042 9 38 +0.052132 +0.061321 +0.070505 +0.079682 +0.088854 +0.098017 +0.107172 +0.116319 +0.125455 +0.134581 +0.143695 +0.152797 +0.161886 +0.170962 +0.180023 +0.189069 +0.198098 +0.207111 +0.216107 +0.225084 +0.234042 +0.242980 +0.251898 +0.260794 +0.269668 +0.278520 +0.287347 +0.296151 +0.304929 +0.313682 +0.322408 +0.331106 +0.339777 +0.348419 +0.357031 +0.365613 +0.374164 WO 98/19410 PCT/US97/18911 183 1000100111 0011000100 10001010010011001000 1000101011 0011001101 10001011010011010001 1000101111 0011010101 1000110000 0011011001 1000110011 0011011110 1000110101-0011100010 1000110111-0011100110 1000111001 0011101010 1000111011 0011101111 1000111101 0011110011 1000111111 0011110111 1001000010 0011111011 1001000100_0011111111 1001000110 0100000011 1001001001 0100000111 1001001011 0100001011 1001001110 0100001111 1001010000 0100010011 1001010011 0100010111 1001010101 0100011011 1001011000 0100011111 1001011011 0100100011 1001011101-0100100111 1001100000-0100101011 1001100011 0100101110 1001100110-0100110010 10011010010100110110 1001101011 0100111010 1001101110-0100111101 1001110001 0101000001 1001110100 0101000101 1001110111 0101001000 1001111010 0101001100 1001111101 0101010000 1010000000 0101010011 1010000100 0101010111 1010000111 0101011010 1010001010 0101011110 1010001101 0101100001 1010010000 0101100100 1010010100 0101101000 1010010111 0101101011 1010011010 0101101110 1010011110 0101110010 1010100001 0101110101 1010100101 0101111000 1010101000 0101111011 1010101100_0101111111 1010101111 0110000010 1010110011_0110000101 1010110110 0110001000 1010111010 0110001011 1010111110 0110001110 1011000001_0110010001 //W1152_2048 -0.923880 //W1155_2048 -0.920318 /Wl158_2048 -0.916679 I Wi161_2048 -0.912962 IIW1164_2048 -0.909168 //W1167_2048 -0.905297 IW 170_2048 -0.901349 /Wi 173_2048 -0.897325 /IW1176_2048 -0.893224 II W 179_2048 -0.889048 /Wi 182_2048 -0.884797 H Wl185 2048 -0.880471 SWI 188_2048 -0.876070 I/W1191 2048 -0.871595 H Wl 194 2048 -0.867046 H Wi 197_2048 -0.862424 W1200-2048 -0.857729 II W1203-2048 -0.852961 //W1206-2048 -0.848120 W1209 2048 -0.843208 //W1212-2048 -0.838225 //W1215_2048 -0.833170 H W1218_2048 -0.828045 II W1221 2048 -0.822850 IIW1224-2048 -0.817585 II W1227-2048 -0.812251 H W1230-2048 -0.806848 W1233-2048 -0.801376 W1236-2048 -0.795837 //W1239-2048 -0.790230 II W1242-2048 -0.784557 IIW1245-2048 -0.778817 //W1248-2048 -0.773010 //W1251-2048 -0.767139 H W1254-2048 -0.761202 H W1257"2048 -0.755201 I W1260-2048 -0.749136 //W1263-2048 -0.743008 /IW1266-2048 -0.736817 //W1269-2048 -0.730563 H W1272-2048 -0.724247 H /W1275-2048 -0.717870 W1278-2048 -0.711432 H W1281-2048 -0.704934 //W1284-2048 -0.698376 IIW1287-2048 -0.691759 I/W1290-2048 -0.685084 II W1293-2048 -0.678350 W1296-2048 -0.671559 //W1299-2048 -0.664711 SWi 302_2048 -0.657807 SWi 305_2048 -0.650847 II W 308_2048 -0.643832 I W1311_2048 -0.636762 //W1314-2048 -0.629638 IIW1317-2048 -0.622461 +0.382683 +0.391170 +0.399624 +0.408044 +0.416430 +0.424780 +0.433094 +0.441371 +0.449611 +0.457813 +0.465976 +0.474100 +0.482184 +0.490226 +0.498228 +0.506187 +0.514103 +0.521975 +0.529804 +0.537587 +0.545325 +0.553017 +0.560662 +_0.568259 +0.575808 +0.583309 +0.590760 +0.598161 +0.605511 +0.612810 +0.620057 +0.627252 +0.634393 +0.641481 +0.648514 +0.655493 +0.662416 +0.669283 +0.676093 +0.682846 +0.689541 +0.696177 +0.702755 +0.709273 +0.715731 +0.722128 +0.728464 +0.734739 +0.740951 +0.747101 +0.753187 +0.759209 +0.765167 +0.771061 +0.776888 +0.782651 WO 98/19410 PCT/US97/18911 184 1011000101 0110010100 10110010010110010111 1011001100 0110011001 1011010000 0110011100 1011010100_0110011111 1011011000_0110100010 1011011100-0110100100 10111000000110100111 1011100100-0110101010 10111001110110101100 10111010110110101111 10111011110110110001 1011110011 0110110100 1011110111 0110110110 1011111011-0110111001 1100000000 0110111011 110000100 0110111101 1100001000 0111000000 1100001100 0111000010 11000101000111000100 1100010100 0111000110 1100011000 0111001001 11000111010111001011 11001000010111001101 1100100101 0111001111 1100101001-0111010001 1100101110-0111010011 1100110010 0111010101 1100110110-0111010111 11001110110111011000 11001111110111011010 11010000110111011100 1101001000 0111011110 11010011000111011111 1101010001 0111100001 11010101010111100011 11010110010111100100 11010111100111100110 1101100010 0111100111 11011001110111101001 11011010110111101010 11011100000111101011 1101110100-0111101101 11011110010111101110 1101111110 0111101111 1110000010-0111110000 11100001110111110001 11100010110111110011 11100100000111110100 1110010100 0111110101 1110011001 0111110110 1110011110-0111110110 1110100010-0111110111 1110100111 0111111000 1110101100 0111111001 1110110000-0111111010 H W1320_2048 -0.615232 IIW1323_2048 -0.607950 //W1326-2048 -0.600616 II Wi 329_2048 -0.593232 //W1332-2048 -0.585798 H /W1335-2048 -0.578314 H W1338-2048 -0.570781 //W1341-2048 -0.563199 //W1344-2048 -0.555570 H W1347-2048 -0.547894 //W1350_2048 -0.540171 //W1353-2048 -0.532403 /Wi 356_2048 -0.524590 //W1359-2048 -0.516732 Wi 362_2048 -0.508830 //W1365-2048 -0.500885 Wi 368_2048 -0.492898 //W1371-2048 -0.484869 II W1374-2048 -0.476799 WI 377_2048 -0.468689 II Wi 380_2048 -0.460539 II Wi 383_2048 -0.452350 H W1386-2048 -0.444122 WI 389_2048 -0.435857 WI 392 2048 -0.427555 //W1395 2048 -0.419217 W1398_2048 -0.410843 H W1401-2048 -0.402435 W1404-2048 -0.393992 H W1407-2048 -0.385516 H W1410-2048 -0.377007 //W1413-2048 -0.368467 H W1416-2048 -0.359895 H W1419-2048 -0.351293 //W1422-2048 -0.342661 II W1425-2048 -0.334000 //W1428-2048 -0.325310 H W1431-2048 -0.316593 //W1434-2048 -0.307850 H /W1437-2048 -0.299080 H /W1440_2048 -0.290285 H /W1443_2048 -0.281465 H W1446_2048 -0.272621 H /W1449_2048 -0.263755 II W1452_2048 -0.254866 H /W1455_2048 -0.245955 II W1458-2048 -0.237024 II W1461-2048 -0.228072 H W1464 2048 -0.219101 //W1467-2048 -0.210112 H W1470-2048 -0.201105 //W1473-2048 -0.192080 H W1476-2048 -0.183040 II W1479-2048 -0.173984 H W1482-2048 -0.164913 H W1485-2048 -0.155828 +0.788346 +0.793975 +0.799537 +0.805031 +0.810457 +0.815814 +0.821103 +0.826321 +0.831470 +0.836548 +0.841555 +0.846491 +0.851355 +0.856147 +0.860867 +0.865514 +0.870087 +0.874587 +0.879012 +0.883363 +0.887640 +0.891841 +0.895966 +0.900016 +0.903989 +0.907886 +0.911706 +0.915449 +0.919114 +0.922701 +0.926210 +0.929641 +0.932993 +0.936266 +0.939459 +0.942573 +0.945607 +0.948561 +0.951435 +0.954228 +0.956940 +0.959572 +0.962121 +0.964590 +0.966976 +0.969281 +0.971504 +0.973644 +0.975702 +0.977677 +0.979570 +0.981379 +0.983105 +0.984749 +0.986308 +0.987784 WO 98/19410 WO 9819410PCTIUS97/1891 1 185 1110110101 0111111010 111011101 00111111011 11101111100111111100 111100001 10111111100 11110010000111111101 11110011000111111101 1111010001 0111111110 1111 01011 0011111111 0 1111100100011111111 1 11111010000111111111 11111 01101 0111111111 H/W1 488_2048 146730 H/W1 491_2048 137620 H/W1 494_2048 128498 H/W1497_2048 -0.119365 HI Wi 500_2048 110222 H/W1 503_2048 10 1070 H/W1 506_2048 -0.091909 HI WI 509_2048 -0.082740 W1 512_2048 -0.073565 H/W1 515_2048 -0.064383 H/W1 518_2048 -0.055195 H/W1 521_2048 -0.046003 Wi 524_2048 -0.036807 HI Wi 527_2048 -0.027608 H/W1 530_2048 -0.018407 H/W1 533_2048 -0.009204 +0.989177 +0.990485 +0.991710 +0.992850 +0.993907 +0.994879 +0.995767 +0.996571 +0.997290 +0.997925 +0.998476 +0.998941 +0.999322 +0.999619 +0.999831 +0.999958 Listing 17 I512 point FFT twiddle factor coefficients (Radix 4+2).

ICoefficients stored as non-fractional 10 bit integers (scale 1) IReal Coefficient (cosine value) is coefficient high-byte.

I/Imaginary Coefficient (sine value) is coefficient low-byte.

0111111111 0000000000 01111111111111111010 30011111111111111000011 0111111111 1111101101 01111111111111100 0111111101111100001 0111111111111011011 0111111101111010101 011111100011101010000 40011111111111010010 0111111101111001100 01111110111110011011 0111111010 111010100 0111111001 01110010101 450111111000111100001000 0011110111 1110111110 01111101101111110111 01111100111110001 0111110100 1110010110 550111111010 111001010 011111001 1110000100 WOOOO_ 0512 +1.000000 //W0001_0512 +0.999925 W0002_0512 999699 H/W0003_0512 +0.999322 W0004_0512 +0.998795 H/W0005_0512 +0.998118 /W0006_0512 +0.997290 /W0007_0512 +0.996313 H/W0008_0512 995185 W0009_0512 +0.993907 H/WO010_0512 +0.992480 H/W001 1_0512 +0.990903 //W0012_0512 +0.989177 //W0013_0512 +0.987301 WOO14_0512 +0.985278 HI WO01l5_0512 +0.983105 //WOO016_0512 980785 /W0017 10512 +0.978317 /WOO018-0512 975702 /WOO019_0512 972940 IW002C0_0512 +0.970031 /W0021_0512 +0.966976 /W0022_0512 +0.963776 H1W00230512 +0.960431 IW0024_0512 +0.956940 /W0025_0512 +0.953306 /W0026_0512 +0.949528 /W0027_0512 +0.945607 /W0028_0512 +0.941544 HI W0029 0512 +0.937339 W0030_0512 +0.932993 H/W0031_0512 +0.928506 -0.000000 -0.012272 -0.024541 -0.036807 -0.049068 -0.061321 -0.073565 -0.085797 -0.098017 -0.110222 -0.122411 -0.134581 -0.146730 -0.158858 -0.170962 -0.183040 -0.195090 -0.207111 -0.219101 -0.231058 -0.242980 -0.254866 -0.266713 -0.278520 -0.290285 -0.302006 -0.313682 -0.325310 -0.336890 -0.348419 -0.359895 -0.371317 WO 98/19410 WO 9819410PCTIUS97/1891 1 186 0111011001-1100111100 01110101111100110110 0111010100 1100110001 0111010001 1100101011 0111001111 1100100101 0111001100T 100011111 0111001001 1100011010 0111000110 1100010100 0111000100 1100001111 0111000001 1100001001 0110111101 1100000100 0110111010 1011111110 0110110111 1011111001 0110110100 1011110011 01101101101 101110110 0110101101 010111001001 0110100110 1011011110 0110100011 11011011001 0110011111 1011010100 0110011011 11011001111 0110010111 1011001010 01 100101 001011000101 01100100001011000000 01100011001010111011 0110001000 1010110110 0110000100 1010110010 0110000000 1010101101 0101111011 11010101000 0101110111 1010100100 0101110011 11010011111 0101101110 1010011010 0101101010 1010010110 0101100110 1010010010 0101100001 1010001101 0101011100F1010001001 0101011000 1010000101 0101010011 1010000000 0101001110 1001111100 0101001010 1001111000 0101000101 1001110100 01010000001001110000o 0100111011 1001101100 0100110110 1001101 001 0100110001 1001100101 0100101100 1001100001 0100100111 1001011101 0100100010T 100101 1010 0100011100 1001010110 0100010111 1001010011 0100010010 10010011 11 0100001101 1001001100 0100000111 1001001001 0100000010 1001000110 0011111100 1001000011 IW0032_0512 +0.923880 IW0033_0512 +0.919114 /W0034_0512 914210 /W0035_0512 +0.909168 IW0036_0512 +0.903989 IW0037_0512 =+0.898674 IW0038_0512 +0.893224 /W0039_0512 +0.887640 /W0040_0512 +0.881921 IW0041_0512 +0.876070 IW0042_0512 870087 IW00430512 +0.863973 IW0044_0512 +0.857729 /W0045_0512 +0.851 355 IW0046_0512 +0.844854 IW0047_0512 +0.838225 /W0048_0512 +0.831470 /W0049_0512 +0.824589 W005 WO_0512 +0.817585 /W0051_0512 +0.810457 IW0052_0512 +0.803208 IW0053_0512 +0.795837 IW0054_0512 +0.788346 /W0055_0512 +0.780737 /W0056_0512 +0.773010 /W0057_0512 +0.765167 IW0058_0512 +0.757209 /W0059_0512 +0.749136 IW0060_0512 +0.740951 IW0061_0512 +0.732654 IW0062_0512 +0.724247 /W0063_0512 +0.715731 /W0064_0512 +0.707107 IW0065_0512 +0.698376 /W0066_0512 =+0.689541 IW0067_0512 +0.680601 IW0068_0512 +0.671559 IW0069_0512 +0.662416 /W0070_0512 +0.653173 IW0071_0512 +0.643832 IW0072_0512 +0.634393 IW0073_0512 +0.624859 IW0074_0512 +0.615232 /W0075_0512 +0.605511 /W0076_0512 +0.595699 IW0077_0512 +0.585798 /W0078_0512 +0.575808 /W0079_0512 +0.565732 IW0080_0512 +0.555570 IW0081_0512 +0.545325 IW0082_0512 +0.534998 IW0083_0512 +0.524590 /W0084_0512 +0.514103 IW0085_0512 +0.503538 IW0086_0512 +0.492898 /W0087_0512 +0.482184 -0.382683 -0.393992 -0.405241 -0.416430 -0.427555 -0.438616 -0.449611 -0.460539 -0.471397 -0.482184 -0.492898 -0.503538 -0.514103 -0.524590 -0.534998 -0.545325 -0.555570 -0.565732 -0.575808 -0.585798 -0.595699 -0.605511 -0.615232 -0.624859 -0.634393 -0.643832 -0.653173 -0.662416 -0.671559 -0.680601 -0.689541 -0.698376 -0.707107 -0.715731 -0.724247 -0.732654 -0.740951 -0.749136 -0.757209 -0.765167 -0.773010 -0.780737 -0.788346 -0.795837 -0.803208 -0.810457 -0.817585 -0.824589 -0.831470 -0.838225 -0.844854 -0.851355 -0.857729 -0.863973 -0.870087 -0.876070 WO 98/19410 PCTIUS97/18911 187 0011110001 1000111100 00111011001 000111010 00111001101 000110111 00111000011000110100 5 00110110111000110001 0011010101_1000101111 0011001111 1000101100 00110010101000101001 0011000100-1000100111 0010111110 1000100101 0010111000-1000100010 00101100101000100000 0010101100_1000011110 0010100111_1000011100 0010100001_1000011010 0010011011_1000011000 0010010101_1000010110 0010001111_1000010100 0010001001_1000010011 0010000010 1000010001 00011111001000001111 00011101101000001110 0001110000-1000001100 00011010101000001011 0001100100 1000001010 00010111101000001001 00010110001000001000 0001010001_1000000111 0001001011_1000000110 0001000101_1000000101 0000111111_1000000100 0000111000 1000000011 00001100101000000010 0000101100 1000000010 0000100110-1000000001 0000011111 1000000001 0000011001_1000000001 0000010011_1000000000 0000001101 1000000000 0000000110 1000000000 0000000000-1000000000 1111111010 1000000000 1111110011 1000000000 1111100111 1000000001 1111011010-1000000001 1111010100 1000000010 1111001110-1000000010 1111000001_1000000100 1110110101-1000000110 1110101111-1000000111 1110101000 1000001000 1110011100-1000001010 1110010000-1000001100 11100010101000001110 1110000100 1000001111 1101110111_1000010011 //W0088 0512 +0.471397 //W0089_0512 +0.460539 //W0090 0512 +0.449611 //W0091 0512 +0.438616 II W0092 0512 +0.427555 //W0093 0512 +0.416430 //W0094-0512 +0.405241 IIW0095 0512 +0.393992 //W0096-0512 +0.382683 /W0097 0512 +0.371317 //W0098 0512 +0.359895 //W0099_0512 +0.348419 //WO100 0512 +0.336890 //W0101 0512 +0.325310 //W0102 0512 +0.313682 //W0103 0512 +0.302006 //W0104 0512 +0.290285 //W0105_0512 +0.278520 //W0106 0512 +0.266713 //W0107 0512 +0.254866 II W0108 0512 +0.242980 //W0109 0512 +0.231058 //W0110 0512 +0.219101 //W011 0512 +0.207111 //W0112 0512 +0.195090 //W0113_0512 +0.183040 /W01 14 0512 +0.170962 /W0115_0512 +0.158858 //W0116 0512 +0.146730 IIW0117_0512 +0.134581 //W0118 0512 +0.122411 //W0119 0512 +0.110222 //W0120_0512 +0.098017 IIW0121 0512 +0.085797 //W0122 0512 +0.073565 //W0123 0512 +0.061321 //W0124 0512 +0.049068 //W0125 0512 +0.036807 //W0126 0512 +0.024541 //W0127 0512 +0.012272 //W0128 0512 +0.000000 I W0129-0512 -0.012272 HIW0130 0512 -0.024541 //W0132 0512 -0.049068 //W0134-0512 -0.073565 //W0135-0512 -0.085797 //W0136 0512 -0.098017 //W0138 0512 -0.122411 //W0140-0512 -0.146730 IIW0141-0512 -0.158858 //W0142-0512 -0.170962 //W0144-0512 -0.195090 //W0146-0512 -0.219101 //W0147 0512 -0.231058 //W0148-0512 -0.242980 //W0150_0512 -0.266713 -0.881921 -0.887640 -0.893224 -0.898674 -0.903989 -0.909168 -0.914210 -0.919114 -0.923880 -0.928506 -0.932993 -0.937339 -0.941544 -0.945607 -0.949528 -0.953306 -0.956940 -0.960431 -0.963776 -0.966976 -0.970031 -0.972940 -0.975702 -0.978317 -0.980785 -0.983105 -0.985278 -0.987301 -0.989177 -0.990903 -0.992480 -0.993907 -0.995185 -0.996313 -0.997290 -0.998118 -0.998795 -0.999322 -0.999699 -0.999925 -1.000000 -0.999925 -0.999699 -0.998795 -0.997290 -0.996313 -0.995185 -0.992480 -0.989177 -0.987301 -0.985278 -0.980785 -0.975702 -0.972940 -0.970031 -0.963776 WO 98/19410 W098/9410PCTIUS97/1 8911 188 1101101011 1000010110 1101100101 1000011000 1101010100 1000011110 1101001000 1000100010 1 10100001 01 0001 00101 11001111001000100111 1100110001 1000101100 1 1001001011000110001 11000111111000110100 11000110101000110111 11000011111 000111100 1100000100100100001 1 1011111110 1001000110 10111110011001001001 10111011101 001001111 10111001001 001010110 10110111101 001011010 10110110011001011101 1011001111 1001100101 10110001011 001101100 10110000001001110000 101011101 110011101 00 10101100101 001111100 10101010001010000101 1010100100 1010001001 10100111111010001101 10100101101010010110 10100011011010011111 10100010011010100100 10100001011010101000 1001111100 1010110010 10011101001010111011 1001110000_1011000000 1001101100 1011000101 10011001011011001111 10010111011011011001 10010110101 011011110 1001010110_1011100100 1001001111 1011101110 1001001001101 1111001 10010001101h011111110 1001000011 1100000100 10001111001h100001111 1000110111 1100011010 1000110001 1100100101 1000101100 1100110001 100010011111011100 50100010010101101000010 100001110 1101001000 10000110110 1100101 551000011010 11010111 100001001111-01110111 //W0152_0512 -0.290285 H/W0153_0512 -0.302006 H/W01 54_0512 -0.313682 H/W0156_0512 -0.336890 //W0158_0512 359895 H/W0159_0512 -0.371317 H/W0160_0512 -0.382683 H/W0162_0512 -0.405241 H/W0164_0512 =-0.427555 //W0165_0512 -0.438616 W0166_0512 -0.449611 HI W0168_0512 -0.471397 H/W0170_0512 -0.492898 H/W0171_0512 -0.503538 H/W0172_0512 -0.514103 HI W0174_0512 -0.534998 HI W0176_0512 -0.555570 H/W0177_0512 -0.565732 W01 780512 575808 H/W0180_0512 -0.595699 H/W0182_0512 -0.615232 //W0183_0512 -0.624859 H/W01 84_0512 -0.634393 H/W0186_0512 -0.653173 H/W0188_0512 -0.671559 H/W0189_0512 -0.680601 H/W0190_0512 -0.689541 H/W0192_0512 -0.707107 //W0194_0512 -0.724247 /W01 95_0512 -0.732654 /W01 96_0512 -0.740951 /W01 98_0512 -0.757209 /W0200_0512 -0.773010 /W0201_0512 -0.780737 /W0202_0512 -0.788346 HI W0204_0512 -0.803208 HI W0206_0512 -0.817585 HI W0207_0512 -0.824589 HI W0208_0512 -0.831470 H/W021 0_0512 -0.844854 H/W0212_0512 -0.857729 W0213_0512 -0.863973 H/W0214_0512 -0.870087 H/W0216_0512 -0.881921 /W0218_0512 -0.893224 /W0219_0512 -0.898674 H/W0220_0512 -0.903989 H/W0222_0512 914210 HI W0224_0512 -0.923880 HI W0225_0512 -0.928506 HI W0226_0512 -0.932993 W0228_0512 -0.941544 H/W0230 0512 -0.949528 H/W0231 0512 =-0.953306 H/W0232_0512 =-0.956940 H/W0234 0512 963776 -0.956940 -0.953306 -0.949528 -0.941544 -0.932993 -0.928506 -0.923880 -0.914210 -0.903989 -0.898674 -0.893224 -0.881921 -0.870087 -0.863973 -0.857729 -0.844854 -0.831470 -0.824589 -0.817585 -0.803208 -0 .788346 -0.780737 -0.773010 -0.757209 -0.740951 -0.732654 -0.724247 -0.707107 -0.689541 -0.680601 -0.671 559 -0.653173 -0.634393 -0.624859 -0.615232 -0.595699 -0.575808 -0.565732 -0.555570 -0.534998 -0.514103 -0.503538 -0.492898 -0.471397 -0.449611 -0.438616 -0.427555 -0.405241 -0.382683 -0.371317 -0.359895 -0.336890 -0.313682 -0.302006 -0.290285 -0.266713 WO 98/19410 WO 9819410PCTIUS97/1891 1 189 1000001111 1110000100 1000001110-1110001010 1000001100 1110010000 lo0o0ololoCh 110011100 1000001000 1110101000 100000111 1110101111 1000000110 1110110101 1000000100 1111000001 1000000010 1111001110 1000000010 1111010100 1000000001 1111011010 1000000001 1111100111 1000000000 1111110011 1000000000 1111111010 1000000000 0000001101 1 000000001 1000001 1111 1000000010 0000110010 1000000101 0001000101 1000001000 0001011000 1000001011 0001101010 1000001111 0001111100 1000010100F0010001111 1000011010 0010100001 1000100000 0010110010 1000100111 0011000100 1000101111 0011010101 1000110111 0011100110 1000111111 0011110111 1001001001 0100000111 1001010011 0100010111 1001011101 0100100111 1001101001 0100110110 1001110100 0101000101 1010000000 0101010011 1010001101 0101100001 1010011010 0101101110 1010101000_0101111011 1010110110 0110001000 1011000101 0110010100 1011010100F0110011111 1011100100 0110101010 1011110011 10110110100 1100000100 0110111101 1100010100 0111000110 1100100101 0111001111 *1100110110 01110101-11 1101001000 0111011110 1101011001 01111001 00 *1101101011 0111101010 1101111110 0111101111 11100100000111110100 1110100010 0111110111 1110110101 0111111010 1111001000F0111111101 1111011010 0111111111 11111 011 01 0 11111111-1 W0236_0512 970031 H/W0231_0512 972940 HI W0238_0512 975702 HI W0240_0512 -0.980785 H/W0242_0512 -0.985278 HI W0243_0512 -0.987301 H/W0244_0512 -0.989177 H/W0246_0512 -0.992480 H/W0248_0512 -0.995185 H/W0249_0512 -0.996313 HI W0250_0512 -0.997290 W0252_0512 -0.998795 H/W0254_0512 -0.999699 W0256_0512 =-0.999925 HI W0258_0512 999699 H/W0261_0512 -0.998118 H/W0264_0512 -0.995185 HI W0267_0512 =-0.990903 II W0270_0512 -0.985278 H/W0273_0512 -0.978317 W0276_0512 -0.970031 H/W0279_0512 -0.960431 /W0282_0512 -0.949528 /W0285_0512 -0.937339 H/W0288_0512 -0.923880 H/W0291_0512 -0.909168 H/W0294_0512 -0.893224 /W0297_0512 876070 /W0300_0512 -0.857729 /W0303 0512 -0.838225 H/W0306_0512 -0.817585 H/W0309_0512 -0.795837 H/W0312_0512 773010 W0315_0512 -0.749136 H/W0318_0512 -0.724247 H/W0321_0512 -0.698376 H/W0324_0512 -0.671559 H/W0327_0512 -0.643832 W0330_0512 -0.615232 H/W0333_0512 -0.585798 H/W0336_0512 -0.555570 /W0339_0512 -0.524590 /W0342_0512 -0.492898 H/W0345_0512 -0.460539 H/W0348_0512 -0.427555 HI W0351_0512 -0.393992 H/W0354_0512 -0.359895 H/W0357_0512 -0.325310 W0360_0512 -0.290285 HI W0363_0512 -0.254866 H/W0366_0512 -0.219101 H/W0369_0512 183040 H/W0372_0512 146730 H/W0376_0512 110222 H/W0378_0512 -0.073565 H/W0381_0512 =-0.036807 -0.242980 -0.231058 -0.219 101 -0.195090 -0.170962 -0.158858 -0.146730 -0.122411 -0.098017 -0.085797 -0.073565 -0.049068 -0.024541 -0.012272 +0.02454 1 +0.061321 +0.098017 +0.134581 +0.170962 +0.207111 +0.242980 +0.278520 +0.313682 +0.348419 +0.382683 +0.416430 +0.449611 +0.482184 +0.514103 +0.545325 +0.575808 +0.605511 +0.634393 +0.662416 +0 .68954 1 +0.715731 74095 1 +0.765167 +0.788346 +0.810457 +0.831470 +0.851355 +0.870087 +0.887640 +0.903989 +0.919114 +0.932993 +0.945607 956940 +0.966976 +0.975702 +0.983105 +0.989177 +0.993907 +0.997290 +0.999322 WO 98/19410 PCT/US97/18911 190 Listing 18 /*FOLDBEGINS 0 0 "Copyright"*/ Copyright Pioneer Digital Design Centre Limited NAME: pilloc_rtl.v PURPOSE: Pilot location CREATED: June 1997 BY: T. Foxcroft

MODIFIED:

USED IN PROJECTS: cofdm only.

/*FOLDENDS*/

/*FOLDBEGINS 0 0 "Defines"*/ 'define FFTSIZE 2048 'define DATABINS 1705 'define SCATNUM 'define SCALEFACTOR64Q 3792 //3x8192/sqrt(42) 'define SCALEFACTOR16Q 3886 //3x8192/sqrt(10)*2 'define SCALEFACTORQPS 2172 //3x8192/sqrt(2)*8 'define AVERAGESF 12'hc49 //0.04x4096x32768/1705 3145

/*FOLDENDS*/

module chanest (clk, resync, in_valid, in_data, constellation, u_symbol, us_pilots, uc_pilots, ct_pilots, out_tps, tps_valid, uncorrected_iq, out_valid, outi, outq, c_symbol, incfreq, wrstrb, ramindata, ramoutdata, ramaddr); /*FOLDBEGINS 0 0 input clk, resync, in_valid; input [23:0] in_data; input constellation; output u_symbol; output us_pilots, uc_pilots, ct_pilots; output outtps, tps_valid; output [23:0] uncorrected_iq; output out valid; output outi; output outq; output c_symbol; output incfreq; output wrstrb; output [23:0] ramindata; input [23:0] ramoutdata; output [10:0] ramaddr;

/*FOLDENDS*/

/*FOLDBEGINS 0 0 "TPS location reg [10:0] tpsloc; reg tpscount; WO 98/19410 WO 9819410PCTIUS97/1891 1 191 always @(tpscount) begin case(tpscount) 5'b00000: tpsloc 34; 5'b00001: tpsloc 5'bOOOl10: tpsloc 209; 1: tpsloc 346; tpsloc 413; 5'b0010 1: tpsloc 569; 5'bOOl110: tpsloc 595; 11: tpsloc 688; 'b01 000: tpsloc 790; tpsloc 901; 5Wb10 10: tpsloc 1073; 5'bOl10l1: tpsloc 1219; 5'bOl1100: tps loc 1262; 5'bOl110l: tpsloc 1286; 5'bOl1110: tpsloc 1469; 5'bOll111: tpsloc 1594; default: tpsloc 1687; endcase end

/*FOLDENDS*/

/*FOLDBEGINS 0 0 "continuous pilot location"*/ reg [10:0] contloc; reg contloccount; always @(contloccount) begin case(contloccount) 6'bOOOOOO: contloc 0; 6'bQOOO00l: contloc 48; 6'bOOOl 10: contloc 54; 1: contloc 87; contloc 141; 6'bOOOl10l: contloc 156; 6'bOO01l10: contloc 192; 6'bOO01l11: contloc 201; 6'bOOl1000: contloc 255; 6'bOOl100l: contloc 279; 6'bOOl10l1: contloc 282; 6'bOO 10 11: contloc 333; 6'bOOl 100: contloc 432; 6'bOO 101: contloc 450; 6'bOOl 110: contloc 483; 6'bOOl 111: contloc 525; 6'bOlOOOO: contloc 531; 6'bOl1000l: contloc 618; 6'bOl100l1: contloc 636; 6'bOI100l1: contloc 714; 6'bOl10I10: contloc 759; 6'bOl10l10I: contloc 765; 6'bOl10l110: contloc 780; 6'bO 10 111: contloc =804; 6'bOI 1000: contloc 873; 6'bO 1100 1: contloc 888; 6'bOll1010: contloc 918; WO 98/19410 PCT[LJS97/18911 192 6'bO 1011: contloc 939; 6'bOl11100: contloc 942; 6'bOl1110l: contloc 969; 6'bOl 11110: contloc 984; 6'bOll111: contloc 1050; 'bl100000: contloc 110 1; 6'b 10000 1: contloc =1107; 6'b 1000 10: contloc 1110; 6'bl1000l1: contloc =1137; 6'bl100l10: contloc 1140; 6'bl100l10l: contloc 1146; 6'b 100 110: contloc 1206; 6'bl100111: contloc 1269; 6'blOlOOO: contloc 1323; 6'bl10l100l: contloc 1377; 6'bl10l10l1: contloc 149 1; 6'bl10l10l1: contloc 1683; default: contloc 1704; endcase end /*FOLDEN DS*I /*FOLDBEGINS 0 0 "continuous pilot location"/ /*reg [10:0] contloc [44:0]; reg contloccount; initial begin contloc[O] 0; contloc[1] 48; contloc[2] 54; contloc[3] =87; contloc[4] =14 1; 156; contloc[6] 192; contloc[7] 201; contloc[8] 255; contloc[9] 279; contloc[10] =282; contlocll] 333; contloc[12] 432; contloc[13] 450; contloc[14] =483; contloc[1 5] =525; contloc[16] 531; contloc[17] 618; contloc[18] 636; contloc[191= 714; =759; contloc[21] 765; contloc[22] 780; contloc[23] 804; contloc[24] 873; =888; contloc[26] =918; contloc[27] 939; contloc[28] 942; contloc[29] =969; 984; contloc[31] 1050; contloc[32] 1101; contloc[33] 1107; contloc[34] =1110; contloc[35] 1137; contlocl36] 1140; contloc[37] 1146; contloc[38] 1206; contloc[39] 1269; =1323; contloc[41 1377; contloc[42J 1491; contloc[43] 1683; contloc[44] =1704; end

/*FOLDENDS*/

/*FOLDBEGINS 0 0 "Control vars"~*/ reg constell; reg resynch; reg valid,valid0,valid 1 valid2, valid 3,valid4,valid 5,va lid 6,valid7,val id 8; reg whichsymbol; reg pwhichsymbol; reg incwhichsymbol; reg [23:0] fttdata; reg [10:0] fftcount; reg [10:0] tapcount; reg countl2; WO 98/19410 WO 9819410PCT/US97/1 8911 193 reg dcountl2; reg ramdatavalid; reg tapinit; reg tapiniti ,tapinit2; reg nscat; reg pilot; reg tapload; //controls when the taps are loaded reg tapload2; reg shiftinnewtap; reg filtgo;

/*FOLDENDS*/

/*FOLDBEGINS 0 0 "Channel Est vars*/ reg Eli1:0] tapi reg [11:0] tapq reg [27:0] sumi; reg [27:0] sumq; reg [11:0] chani; reg [11:0] chanq; wire [27:0] chani_; wire [27:0] chanq_; reg [11:0] idata; reg [11:0] qdata;

/*FOLDENDS*/

I*FOLDBEGINS 0 0 "RAM varss*/ reg [10:0] ramaddr; reg [10:0] pilotaddr; wire [10:0] ramaddr_; wire [10:0] ramaddrrev_; reg [23:0] ramindata; wire [23:0] ramoutdata; reg [23:0] ramout; reg [23:0] ramot; reg wrstrb; reg rwtoggle; reg framedata, framedatao; reg fray, firstfrav; reg [23:0] avchannel; reg [11:0] avchan; reg avlow; wire [23:0] avchan_;

I*FOLDENDS*/

I*FOLDBEGINS 0 0 "Channel calc varsl*I reg chanval; reg chan valO,chan-vall,chan_val2,chan-val3,chan_val4,out-valid; reg [23:0] sum; reg [11:0] sumsq; reg [11:0] sumsqtemp; reg [11:0] topreal; reg [11:0] topimag; reg outi; reg outitemp; reg outitem; reg outq; reg [10:0] prbs; I/integer intsumi, intsumfq,intsumsq,intoutjintoutq;

/*FOLDENDS*/

WO 98/19410 WO 9819410PCT/US97/1891 1 194 /*FOLDBEGINS 0 0 "uncorrected pilot vars"*/ reg u symbol; reg us -pilots; reg uc-pilots; reg [23:0] uncorrected_iq; reg tps_pilots; reg tpsmajcount; wire tpsmajcount_; reg ct-pilots; reg out tps, tps_valid; reg pilotdata; /*FOLDEN DS*/ /*FOLDBEGINS 0 0 "pilot locate vars"l*/ wire which symbol; wire [10:0] cpoffset; -wire [10:0] pilotramaddr_; wire [23:0] pilotramin_; wire pilotwrstrb_; wire found pilots; reg pilotlocated;

/*FOLDENDS*/

/*FOLDBEGINS 0 0 "sync function arrays-~/ reg [11:0] syncO; reg [11:0] synci; reg [11:0] sync2; reg syncoffset; always @(dcountl 2 or validi1 or valid2) begin if(validl Ivalid2) syncoffset 4'hc-dcountl2; else syncoffset dcountl2; /*FOLDBEGINS 0 2 case(syncoffset) 4'hl1: begin syncO 4046; synci 272; sync2 end 4'h2: begin syncO 3899; synci 476; sync2 168; end 4'h3: begin syncO 3661; synci 614; sync2 217; end 4'h4: begin syncO =3344; synci 687; sync2 243; end begin syncO 2963; synci 701; sync2 248; end 4'h6: WO 98/19410 WO 9819410PCT/US97/1891 1 195 begin syncO 2534; synci 665; sync2 234; end 4'h7: begin syncO 2076; synci 590; sync2 205; end 4'h8: begin syncO 1609; synci 486; sync2 167; end 4'h9: begin syncO 1152; synci 364; sync2 123; end 4'ha: begin synoD 722; syncl 237; sync2 78; end default begin syncO 334; synci 113; sync2 36; end endcase

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end

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always @(posedge cik) begin /*FOLDBEGINS 0 2 "Control I constell constellation; resynch resyno; if(resynch) begin /*FOLDBEGINS 0 2 valid 1bO; validO bO; validi valid2 1bO; valid3 1'bO; valid4 1'bO; 1'bO; valid6 1'bO; valid7 bO; valid8 1'bO; fftcount 11'bO; ramdatavalid chan-val 1'bO; tapinit 1'bO; tapinit2 1'bD; rwtoggle 1'bO;

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end else- WO 98/19410 WO 9819410PCTIUS97/18911 196 begin /*FOLDBEG INS 0 2 SI* valid in-valid; validO valid&&pilotlocated; valid 1 validO; valid2 validi; valid3 valid2; valid4 valid3; valid4; valid6 valid7 valid6; valid8 validT if(valid2) ffcount fftcount 1'bl; chan val valid4&&filtgo&&framedata; incwhichsymbol valid 1 &&(fftcount QFFTSIZE-1 if(incwhichsymbol) begin rwtoggle !rwtoggle; tapinit 1'bl; ramdatavalid 1bl; end else if(valid6) tapinit 1'bO; tapiniti tapinit; tapinit2 tapiniti;

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end ffidata in-data; /*FOLDBEGTNS 0 0 "frame averager'~*/ if(resynch) begin fray 1'bO; firstfrav 1'bO; end else begin if(chan_val&&framedata) fray 1'bl; else if(!framedata&&framedata0) fray 1'bO; if(cha n_val&&framed ata&&!frav) firstfrav <=1'bl; else if(chan-val) firstfrav 1'bO; P*FOLDBEGINS 0 2 "calculate 0.2 x me if(chanval0) begin an channel amplitude"~*/ if(firstfrav) begin avchannel avmult(sumsqtemp); avchan avchan_[11:0]; end WO 98/19410 PCT/US97/18911 197 else avchannel avmult(sumsqtemp) avchannel; end

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if(chan vail) aviow (sumsqtemp~avchan)? end

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if(resynch) begin framedata 1'bO; framedata0 1'bO; tapload 1'bO; end else begin framedata0 framedata; if(incwhichsymbol&&(cpoffset==0)) framedata 1; else if(ramdatavalid&&valid2&&(fftcount ==(cpoffset framedata 1; else if(valid2&&(fficount (cpoffset 'DATABINS))) framedata 0; tapload framedata; end filtgo <=ramdatavalid&&( valid2? tapload :filtgo); tapload2 valid&&tapload&&(countl 11 )&&(fftcount!=0); pilot (count12=0); dcountl2 countl2; shiftinnewtap !((nscat 139)11 I(nscat 140)11 (nscat ==14 if(i ncwh ic hsymbol) begin if( 'ramdatavalid) begin whichsymbol pwhichsymbol; tapcount pwhichsymbol*2 1 b1 1 cpoffset; end else begin whichsymbol whichsymbol 1 bi; tapcount {whichsymbol[1 ]A which symbol[OI, Iwhichsymbo[]}*2'b 11+ cpoffset; end end else if(framedata) begin if(fftcount==cpoffset) begin /*FOLDBEGINS 0 4 "set up the counters"I/ //countl 2 ((4-whichsymbol)&4'bOOl 1)*3; counti 2 {whichsymbolll ]A wh ichsymbol[OI,whichsymbol[]*2 1 1; if(valid0) WO 98/19410 WO 9819410PCTIUS97/1891 1 198 nscat 8'bO;

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end else begin /*FOLDBEGINS 0 4 if(va lid) begin countl2 (countl2==11)? 4'bO: countl2 1bl; tapcount tapcount 1'bl if(countl 11) nscat nscat 1'bl; end

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end end else begin nscat 8'bO; if(tapinit) begin if(valid3l I valid4l valid 5&&(wh ichsymbol==2'bO)) tapcount tapcount 4'hc; else if(valid6) tapcount tapcount {whichsymbol[1 ]A whichsymbolE0],whichsymbol[I}*2'b 11 1 'b 1 end end

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/*FOLDBEGINS 0 2 "Channel Estimation"l/ if(tapinit2) begin /*FOLDBEGINS 0 4 "Read in first 3 or 4 taps"~*/ if(va lid prbs alphal12(alpha(whichsymbol)); else if(valid6l I valid7l I (valid 8&&(whichsymnbol==2'bO))) prbs alphal2(prbs); begin tapi[O] pseudo(ramout[23: 12], 1'bI); tapi[1 pseudo(ramout[23: 12], 1 bi); tapi[2] pseudo(ramout[23: 12],l1'bi); tapi[3] pseudo(ramout[23: 12], 1'bi); tapq[0] pseudo(ramout[1 1 bi); tapq[1 pseudo(ramout[1 1'bl); tapq[2] pseudo(ramout[1 1:01, ibi); tapq[3] pseudo(ramout[1 1 bi); end else if( !((whichsymbol!=2'bO)&&valid8)) begin tapi[5] tapi[4]; tapi[4] <=tapi[3]; WO 98/19410 W098/9410PCTIUS97/18911I 199 tapi[l] tapi[0]; tapi[O] <=pseudo(ramout[23:12],prbs[O]); tapq[5] tapq[4]; tapq[4] tapq[3]; tapq[3] tapq[2]; tapq[21 tapq[1]; tapq[1] tapq[0]; tapq[0] pseudo(ramout[1 :0],prbs[0]); end I*FO LDEN DS*I end else if(framedata) begin /*FOLDBEGINS 0 4 "update taps in normal ojp."*/ if (tap load2) begin prbs alphal2(prbs); tapi[3] tapill2]; tapi[1] tapi[0]; if(shiftinnewtap) tapi[0] pseudo(ramout[23:12],prbs[0]); tapq[4]; tapq[4] tapq[3]; tapq[3] tapq[2]; tapq[1] tapq[0]; if(shiftinnewtap) tapq[0] pseudo(ramout[1 1 :O],prbs[0]); end

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/*FOLDBEGINS 0 4 "Channel interpolate"*/ if(pilot) begin if(valid4) begin chani tapi[3]; chanq tapq[3]; end if(valid3) begin idata ramot[23:12]; qdata ramot[1 end end else begin if(validl) begin sumi mult(tapi[0],sync2) mult(tapi[1],syncl); sumq mult(tapq[0],sync2); WO 98/19410 PCTIUS97/18911 200 end else if(v alid2) begin sumi sumi mult(tapi[2],syncO); sumq sumq mult(tapq[2],syncO) mult(tapq[1],syncl); end else if(valid3) begin sumi sumi mult(tapi[3],syncO) mult(tapi[4],syncl); sumq sumq mult(tapq[3],syncO) 12'h800; //2048 for final rounding idata ramot[23:12]; qdata ramot[l end else if(valid4) begin chani chani-[23:12]; chanq chanq_[23:12]; end end //intsumni (chani[1 {20'hfffff,chani[1 1 :0]):chani; //intsumq (chanq[1 {20'hfffff,chanq[1 1 :0]:chanq; //if(chan vat) $d isplay(intsumi*intsumi+intsumq*intsumq);

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end end assign chani- sumi mult(tapi[5],sync2) 12'h800; assign chanq_ sumq mult(tapq[5],sync2) mutt(tapq[4],syncl); assign avchan_ avchannel 24'h000800; FO LDE NDS*I /*FOLDBEGINS 0 2 "Calculate channel"l*/ always @(posedge cik) begin if(resynch) begin chan valO lbO; chan vail 1'bW; chan va12 1'bO; chan va13 1bO; chan va14 ibO; out valid I 'bO; end else begin chan -valO chan-vat; chan vail chan valO; chan val2 chan vall; chan va13 chan -val2; chan val4 chan-val3; flout -valid chan-val4; out-valid chan-val4&&ramdatavalid&&!pilotdata[l]; end if(chan -val) sumsqtemp sum[22:l 1] if(chan-valO) WO 98/19410 WO 9819410PCTIUS97/1 8911 201 topreal sum[23:12]; if(chan-vail) topimag sum[23:121; if(chan -val2) sumsq sum[23:12]; if(chan -val3) begin outitemp divider(topreal ,sumsq ,(constell==0)); outitem d ivpl ussoft(topreal1, sumsq, con stell); end if(chanval4) begin outq divider(topimag ,sumsq,(constell==0)); outi outitemp; end Ilintouti (outill7])? {24'hffffff,outi[7:0]}:outi; //intoutq {24'hffffff,outq[7:0]}:outq; Ilif(chan_val&&ramdatavalid) $d isplay(intsumi); //if(cha n_val4&&ramd atava lid) $displayb(outitemp,,outitem); end always @(chan val or chan valO or chan vail or chani or chanq or consteli or idata or qdata orsumsqtemp) begin if(chan-val) sum smult(chani,chani,1) smult(chanq,chanq,1) 24'h000400; else if(chanval0) sum smult(idata,chani,1) smult(qdata,chanq,1) 24'h000800; else if(chan vail) sum smult(qdata,chani,1) smult(idata,chanq,1) 24'h000800; else //chan-va12 begin case(constell) 2'b00: sum smu lt(sumsqtemp,'SCALE FACTO RQ PS,o) 24'h000800; 2b01: sum sm ult(su msqtemp,'S CALE FACTOR 1 6Q,Q) 24'11000800; default: sum smu lt(sumsqtemp,'SCALE FACTO R64Q,o0) 24'h000800; endcase end end

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/*FOLDBEGINS 0 2 "Extract Continual and scattered pilots for Freq Sampling Error Block"*/ always @(posedge clk) begin if(resynch) contloccount 6'bO; else if(ramdatavalid&&valid2&&(pilotadd r==contloc)) contloccount (contloccount 44)? 6Wb contloccount 1 'bi; if(ramdatavalid&&valid2&&((pilotaddr==contloc) pilot)) uncorrectediq ramot; uc-pilots ramd atavaI d&&framed ata&&(p i Iotadd r==co ntloc) &Ma id2&&! resynch; WO 98/19410 PCTIUS97/18911 202 us-pilots ramd atava lid&&framed ata&&p lot&&va lid 2W&resynch; u symbol Iresynch&&ramdatavalid&&(valid2? (pilotaddr==O) usymbol); /T$display(pilotaddr, ,ramot[23: 12], ,valid2, ,contloccount, ,uncorrected iq[ 23:1 2],,uncorrected iq[1 1: uc-pilots, ,us-pi lots); end I*FOLDEN DS*I /*FOLDBEGINS 0 2 "Extract TPS pilots always @(posedge cik) begin if(resynch) begin tpscount tps _pilots 3bO; tps _valid 1'bO; ct-pilots 1'bD; end else begin if(ramdatavalid&&valid2&&(pilotaddr==tpsloc)) tpscount (tpscount[4])? 5'bO tpscount 1'bl; tpspilots[0] valid2? ramdatavalid&&framedata&&(pilotadd r==tpsloc): tpspilots[0]; tpspilots[l (chan val? tps pilots[0] tps pilots[ tpspilots[2] tps pilots[1]&&chan_va13; tps valid (tpcOLuntIE==)&&tpspilOtS[2]; ct-pilots tpspilots[2]; end if(resynch) tpsmajcount 6'bO; else begin if(tpspi lots[2]) begin if(tpscount==0) begin tpsmajcount 6'bO; out-tps tpsmajcount end else tpsmajcount tpsmajcount_; end end if(resynch) pilotdata 2'bO; else begin if(valid2) pilotdata[0] ramdatavalid&&framedata&&( (pilotaddr==tpsloc)II (pilotaddr==contloc) pilot pilotdata[1I chan valO? pilotdata[0] pilotdata[1]; end WO 98/19410 PCTIUS97/18911 203 //$display(pilotaddr,, ramot.[23:12], ,valid2, ,contloccount,, uncorrected_iq[2 3:12],,uncorrectediq[1 1: uc-pilots,, us_p ilots); II$display(valid2, ,pilotdata[0], ,pilotdata[1 ,pilotdata[2], ,ct pilots,,,, ,,out-valid,,pilotaddr); end assign tpsmajcount- tps(topreal[1 ],tpscount,tpsmajcount);

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/*FOLDBEGINS 1 2 "pilot locate control 1* always @(posedge cik) begin if(resynch) pilotlocated 1'bO; else if(found pilots) begin pilotlocated 1'bl; pwhichsymbol which symbol 2'bl 0; end end

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PFOLDBEGINS 0 2 "RAM"I/ always @(posedge cik) begin if(pilotlocated) begin wrstrb !valid0; if(valid) ramindata fttdata; pilotaddr ramaddr- cpoffset; ramaddr rwtoggle? ramaddr_: ramaddrrev-; ramot ramout; end else begin /*FOLDBEGINS 0 4 wrstrb pilotwrstrb_; ramindata pilotramin_; ramaddr pilotramaddr_;

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end ramout ramoutdata; end assign ramaddr_ (tapiniti framedata&& (valid 2&&(countl 2==1 tapcount: fftcount; assign ramaddrrev {ramaddr_(0], ramaddr [1 ramadd ramadd rj3], ramaddr [4],ramaddr ramaddr16, ramaddr_[7], ramaddr [8],ramadd ramaddr-[1

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assign c symbol whichsymbol[0]; /*FOLDBEGINS 0 0 always @(posedge clk) begin WO 98/19410 PCT/US97/18911 204 II$d isplay(chan val, ,framedata, ,frav, ,firstfrav,....valid2, ,valid4, ,out-valid ,,avchannel,,avchan,,sumsqtemp...avlow, ,chan -vallI); //$display(tpsvalid, ,out tps,jpscount,Jpsplos[2) is pIay~in-datailItg o, ,valIid4,, tap load ,nscat, ,countl 2, ,fftcount, ,incw hichsymbol.,, I/ta pco unt, ra mad dr, ,wrstrb, rwtogg le /I(resynch, ,valid, ,fftcount,, ramadd ram indata[23: ramoutdata[23: 12], ,t apinit, ,tapinit2, ,tapcount, ,ramout[23: 12],, //tapi[0],,tapi[1 ],,tapi[2],,tapi[3],,tapi[4],,tapi[]); //$display(tapcount, ,tapinit2, ,valid4, ,valid, ,valid2, ,wrstrb, ,fftcount, ,fram edata, ,countl 2, ,tapi[0], ,tapi[1 ,,tapi[2], ,tapi[3], ,tapi[4], //$display(, intouti,, intoutq,, out valid, valid4, ,valid2, ,chan_val,,filt go,,framedata, ,fftcount, ,ramindat-a[23: 12]); I/if (whichsymbol==1) $d isp lay(tapinit, ,tapcou nt, ,fftcou nt,, ram indata[2 3: 12], tapcount, ,tapi[0] ,,tapi[1 ],,tapi[2],,tapi[3], ,tapi[4], ,tapi[5],,intsumi, ,intsumq,,idata,,qda ta); //$display(framedata, ,pilotaddr, ,fftcount, ,tapcount, ,ramaddr,,ramout[23: 12], ,ramindata[23: 12], ,prbs,,us pilots,,uc-pilots,,ct-pilots,,out-valid, contl occount,, Iltpspilots[0], ,tps _pi lots[ 1~ ],tps__pilots[2]); end

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pilloc pilloc (.clk(clk), .resync(resync), .in valid(in -valid), .in_data(in data), .found pilots(found pilots), .which symbol(which symbol), .cpoffset(cpoffset), incfreq(incfreq), .ramaddr(pilotramaddrj .ramin(pilotraminj, .ramout(ramout), .wrstrb(pilotwrstrbj)); /*FOLDB EG INS 0 2 "functions"I/ /*FOLDBEGINS 0 0 "tps demod function tps; input tpssign; input tpscount; input [5:01 tpsmajcount; reg tpsflip; begin case(tpscount) ,5'bOO0l 1 ,5'bOOl 00,5'bOOl 1 0,5'bOll 01,5'bOl 110: tpsflip 0; I/added 1 since tpscount already incremented default: tpsflip =1; endcase tps (tpSflipAtpSSign)? tpsmajcount 1'bl :tpsmajcount 1'bl; end endfu nction

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/*FOLDBEGINS 0 0 "pseudo function"l*/ function [11:0] pseudo; input [11:0] data; input flip; begin pseudo =flip? -data +1'bl data; end endfu nction

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/*FOLDBEG INS 0 0 "averager multiplier"l/ WO 98/19410 WO 9819410PCTfUS97/1 8911 205 function [11:0] avmult; input [11:01 i; reg [23:0] res; begin res (i*AVERAGESF) 23'h000800; //multiply and round avmult res[23:12]; end endfunction

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/*FOLDBEGINS 0 0 "filter tap multipier'~*/ function [27:0] mult; input [11:0] i; input [11:0] j; reg [23:0] res; reg [11:0] modi; reg [11:0] invi; begin modi i[l1 invi res (modi*j); //multiply and round mult i[1 {4'hf,-res} 1'bl res; end endfunction

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/*FOLDBEGINS 0 0 "signed multiplier"/* function [23:0] smult; input [11:0] i; input [11:0] j; input signedj; reg [23:0] res; reg [11:0] modi; reg [11:0] modj; begin modi -i+1'bl i modj 0j[1 1]&&signedj)? -j 1'bl j; res (modi*modj); smult (i~jll]AOj11&&signedj))? -res 'bl :res;, end endf unction

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/*FOLDBEGINS 0 0 "divider function"'/ function divider; input [11:0] dividend; input [11:0] divisor; input qpsk; reg [11:0] moddividend; reg signresult; reg [12:0] intval; reg [12:0] carry; reg divide; reg signeddivide; integer i; begin signresult dividendill1]; moddividend dividendill1]? -dividend 1'bl :dividend; WO 98/19410 PCTfLJS97/18911 206 divide 0 carry qpsk? {1 'bO,moddividend}:{moddividend,l1'bO); /*FOLDBEGINS 0 2 for(i=0;i<8;i=i+1) beginintval carry divisor; divide[7-i] !intval[12]; carry (intval[12])? {carry[1 {intval[1 1:0],1'bO); end

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//signeddivide signresult? -divide 2'b10 divide 1'b1 signeddivide signresult? {1'bl,-dividel 2'b10 1'b,divide} 1bl; //$displayb(signeddivide, ,d ivide, ,signresult, ,constellation,,); divider signeddivide[8:1]; end endfunction

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/*FOLDBEGINS 0 0 "divider function with soft decisions added"l/ function divplussoft; input [11:01 dividend; input [11:0] divisor; input constellation; reg [i11:0] moddividend; reg signresult; reg [12:0] intval; reg [12:0] carry; reg divide; reg [10:0] signeddivide; reg [11:0] fracdivide; integer i; begin signresult dividendll 1] moddividend =dividend[l1]? -dividend 'bl 1 dividend; divide 0 carry (constellation== {1 'bO,moddividendl:{moddividend,l1'bO}; /*FOLDBEGINS 0 2 for(i=0;i<9;i=i+1) begin intval carry divisor; divide[8-i] lintval[12]; carry (intval[12])? {carry[1 1:0],1'bO} {intval[1 1:0],1'bO); end

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signeddivide signresult? {2'bl 1,-dividel 1 'b1 {2'bO,divide}; //$displayb(signedd ivide, ,divide, ,sig nresult,, constellation,,); /*FOLDBEGINS 0 2 "qpsk"*/ if(constellation==2'bO) begin //$writeh(,,signeddivide,,,,) signeddivide signeddivide 8'h80; //$writeh(signeddivide, if(signeddivide[1 0]) fracdivide 9'hO; else if(signeddivide[9]1 sig neddivide[8]) WO 98/19410 WO 9819410PCTIUS97/1891 1 207 fracdlivide 12'h700; else begin fracdivide =signeddivide[7:0] {signeddivide[7:0],1'b0}+ {signeddivide[7:01,2'bO}; fracdlivide fracdlivide 8'h80; end divplussoft {3'bO,fracdivide[10:8]}; end else /*FOLD EN DS*I /*FOLDBEGINS 0 2 "16qamh*/ if(constellation==2'bOl) begin $writeh(,,signeddivide,,,j; signeddivide signeddivide 8'hcO; $writeh(, ,signeddivide.,,,) if(signeddivide[1 0]) begin signeddivide fracdlivide 9'hO; end else if(signeddivide[9]1 I (signedd ivide[8:7]==2'b 1)) begin fracdivide 12'h380; signeddivide 1 O'h 100; end else begin fracdlivide signeddivide[6: 01 {sig nedd ivide[6 1'bO} {signeddivide[6:0],2'bO}; fracdlivide fracdivide 8'h40; end divplussoft {1 'bO,signeddivide[8:7],fracdivide[9:7]}; end

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/*FOLDBEGINS 0 2 II32qamI*/ else begin signeddivide signeddivide 8'heO; if(signeddivide[1 0]) begin signeddivide fracdivide 9'hO; end else if(signeddivide[9]1 I (signeddivide[8:6]==3'b1 11)) begin signeddivide 10O'h 180; fracdivide 9'hlcO; end else begin WO 98/19410 PCTIUS97/18911 208 fracdivide signeddivide[5:0] {signeddivide[5:0],2'bQ}; M/7 fracdivide fracdivide 8'h20; end d ivplussoft {signedd ividell8:6],fracdivide[8:6]}; end /*FO LDEN DS*/ end endfu nction

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/*FOLDBEGINS 0 0 "PRBS alpha31619112 multiplier"*/ function [10:0] alpha; input which symbol; begin case (wh ich symbol) 2'bO: alpha 11'b1111111111; 2'bOl: alpha 1 1'bOO01l1111111; 2'bl10: alpha 1 l'bOOOOO01l1111; 2'bll1: alpha 11l'b0000000001 1; endcase end endfunction /*FOLDENDS*/ /*FOLDBEGINS 0 0 "PRBS alphal2 multiplierh"*/ function [10:01 alphal2; input [10:0] prbsin; reg [10:0] prbsO; reg [10:0] prbsl; reg [10:0] prbs2; reg [10:0] prbs3; reg [10:0] prbs4; reg [10:0] reg [10:0] prbs6; reg [10:0] prbs7; reg [10:0] prbs8; reg [10:0] prbs9; reg [10:0] prbslO; begin prbsO {prbsin[0] Aprbsin[2],prbsin[10:1]); prbsl ={prbsO[0] Aprbs0[2] ,prbsO[10:1]); prbs2 {p rbsl1[0] Aprbsl[2] ,prbsl[10:1]}; prbs3 {prbs2[0] Aprbs2[2] ,prbs2[10:1]1; prbs4 {prbs3[0] A prbs3[2] ,prbs3[1 {prbs4[0] A prbs4[2] ,prbs4[1 prbs6 {prbs5[0] A1 prbs5[2] ,prbs5[10:1]1; prbs7 {prbs6[0] A prbs6[2] ,prbs6[10:1]1; prbs8 {prbs7[0] A prbs7[2] prbs7[1 0:1 ]J; prbs9 {prbs8[0] A prbs8[2] ,prbs8[10:1]1; prbsl 0 {prbS9[0] A prbs9[2] ,prbs9[10:1]1; alphal2 {prbslO[0] A1 prbs10[2],prbs10[10:1]}; end WO 98/19410 PCT/US97/18911 209 endfunction

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endmodule Listing 19 /*FOLDBEGINS 0 0 "Copyright"*/ Copyright Pioneer Digital Design Centre Limited NAME: pilloc_rtl.v PURPOSE: Pilot location CREATED: June 1997 BY: J. Parker (C code) MODIFIED: BY: T. Foxcroft USED IN PROJECTS:_cofdm only.

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'define FFTSIZE 2048 'define SCATNUM module pilloc (clk, resync, in_valid, in_data, found_pilots, which_symbol, cpoffset, incfreq, ramaddr, ramin, ramout, wrstrb); /*FOLDBEGINS 0 0 input clk, resync, in_valid; input [23:0] in_data; output found_pilots; output which_symbol; output [10:0] cpoffset; output incfreq;

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/*FOLDBEGINS 0 0 "ram output [10:0] ramaddr; reg [10:0] ramaddr_; output [23:0] ramin; input [23:0] ramout; output wrstrb; reg [10:0] ramaddr; reg [23:0] ramin; reg wrstrb;

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/*FOLDBEGINS 0 0 "vars"*/ reg found_pilots; reg which_symbol; reg which_symbolcount; reg which_symbol_; reg [10:0] cpoffset; reg incfreq; WO 98/19410 WO 9819410PCTJUS97/1891 1 210 reg found_pilot; reg [19:0] v; reg [19:0] sum; reg splocoffset; wire [10:0] carrier -number; reg [10:0] continual pilot offset; reg resynch; reg valid; reg [23:0] ffidata; reg [10:0] fftcount; reg contcomplete; reg firstcontsearch; reg finishedsearch; reg firstscatcomplete; reg failedtolock; reg spmax; reg spmaxfirst; reg [10:0] pilot offset; reg splocizero; reg [10:0] splocO; reg sploci; reg [10:0] splocmaxcount; reg spoffset; reg [19:0] sumnscat [11:0]; reg [19:0] sumscatmax; reg sumscatmaxno0; reg sumscatmaxnol; wire [19:0] sumscatl; wire [19:0] sumscat3; wire [19:0] reg [11:0] sumscatfirst; reg fftfinished; reg ramnwritestop; I/botch for development purposes wire modl2fftcount;

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/*FOLDBEGINS 0 0 "continuous pilot location"*/ reg [10:0] contloc; always @(splocl) begin case(sptocl) 6'bQOOOOO: contloc 0; contloc 48; 6'bOOOOI10: contloc 54; 6'bOOOOI 1: contloc 87; 6'bOO01l00: contloc =141; 6'bOOOl10l: contloc =156; 6'bOOOl110: contloc 192; 6'bOO0l 11: contloc 201; 6'bOOlOOO: contloc 255; contloc 279; 6'bOOl10l1: contloc 282; 6'bOOl 011: contloc 333; 6'bOOl 100: contloc =432; 6'bOOll101: contloc 450; WO 98/19410 WO 9819410PCTIUS97/1891 1 211 6'bOOl 110: contloc 483; 6'bOOl 1111: contloc .525; 6'b01 0000: contloc 531; contloc 618; 6'bOl100I1: contloc 636; 6'bOl100l11: contloc 714; 6'b010 100: contloc 759; 6'bOl10l10l: contloc =765; 6'bOl10l110: contloc 780; 6'bOl10l11: contloc 804; 6'bOl 1000: contloc 873; 6'bOll100l: contloc 888; 6'bOl 1010: contloc 918; 6'bOl110l1: contloc 939; 6'bOll1100: contloc 942; 6'bOl1110l: contloc 969; 6'bOll1110: contloc 984; 6'bOll1111: contloc 1050; 6'blO00000: contloc 1101; 6'bI10000l: contloc 1107; 6'b 100010: contloc =1110; 6'bl1000l1: contloc 1137; 6'bl100l10: contloc 1140; 6'bl100l10l: contloc 1146; 6'bl100l11: contloc 1206; 6'blO00l11: contloc 1269; 6'blOlOOO: contloc 1323; 6'b 10 100 1: contloc 1377; 6'bl10l10l1: contloc 149 1; 6'bI10l10l1: contloc 1683; default: contloc =1704; endcase end

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always @(posedge clk) begin resynch resync; if(resynch) begin valid 4'bO; fficount 1 1'bO; firstscatcomplete sum splocO 1l1bO; sploci 6'bO; contcomplete 1'bO; faiiedtolock spmax 1 'bO; spmaxflrst 1'bO; ramnwritestop 1'bO; found_pilots; 1'bO; found_pilot 1'bO; firstcontsearch 1'bO; finishedsearch 1'bO; which symbolcount 2'bO; WO 98/19410 WO 9819410PCTIUS97/1891 1 212 incfreq 1bO; end else begin incfreq <=!failedtolock[1 ]&&failedtolock[0]&&fftfinished[4]; found pilots Ifou nd pilot&&fi n ished search; found pilot finishedsearch; valid[O] in-valid; valid[1] valid[0]; valid[2] valid[11; valid[3] valid[2]; ffdata in-data; if(valid[]&&!finishedsearch) fftcount fftcount 1'bl; Iif (fftfinished IH $display("frame",,fftcount); IHif(incfreq) $display("tweek"); P*FQLDBEGINS 0 4 "locate continual pilots"/ spmax[1] spmax[0]; spmax[2] spmax[1]; spmaxfirst[1 spmaxfirst[0]; spmaxfirst[2J spmaxfirst[1]; IHif(fftfinished[3]) HI $display(spoffset,,which symbol); if(fftfi n ished -begin failedtolock[1] failedtolock[0]; failedtolock[2] failedtolock[1]; failedtolock[3J failedtolock[2]; failedtolock[41 failedtolock[3]; if(failedtolock[0]) begin /*FOLDBEGINS 0 2 if(failedtolock[4]) failedtolock[0] 1 bO; firstscatcomplete ramnwritestop I bO; firstcontsearch 1 bO;

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end else begin /*FOLDBEGINS 0 4 firstscatcomplete[0] 1'bl; firstcontsearch Ifirstscatcomplete[0]; ramnwritestop Iramnwritestopj finishedsearch; contcomplete ramnwritestop; df( !fi nis hed search &&fi rstscatcom plete[p]&&ramwritestop) '4begin finishedsearch firstcontsearch? 1 'bO (cpoffset==continual pilot offset); cpoffset continual-I pilot offset; WO 98/19410 PCTIUS97/1891 1 213 failedtolock[0I Ifirstcontsearch&&(cpoffset!=continual pilot-offset); end

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end end else begin firstscatcomplete[1] firstscatcomplete[0]&& !contcomplete; firstscatcomplete[2] firstscatcomplete[ 1]; if(firstscatcomplete[01&&!fi nished search &&!contcomp lete&&!finishedsearc h &&(splocl 4 4)&&(splocO==splocmaxcount)) contcomplete 1'bl; end if(fou nd pi lots) $d isplay(wh ich symbol,, cp offset,, sp offset); //$display(sum, ,contcomplete, ,ramwritestop, ,which symbol,, spoffset, splo cO,,splocmaxcount,, fftfinished(3],,finishedsearch); //$display(fficount, ,firstscatcomplete[0],, ramwritestop, ,spoffset, ,sumsca tmaxnol ,finishedsearch,,found pilots,, I/pilot -offset,,which_symbol cpoffset, ,failedtolock) sploclzero[0] (sploci 0); sploclzero[1] sploclzero[0]; if(flrstscatcomplete[Q]&& !finishedsearch&& !contcomplete&&!finishedsearch) begin if(splocl ==44) begin /*FOLDBEGINS 0 4 ~S //$display(splocO, ,splocmaxcount); pilot-offset splocO splocoffset; which-symbol which -symbol_ which symbolcount; if(splocO=splocmaxcount) begin splocO 11'b0; //contcomplete 1 'bi; which-symbolcount end else begin splocO splocO 2'bl 1 which-symbolcount which-symbolcount 'bl; end if(splOC0==0) spmaxfirst[0] 1l'bl; sploci 6'bO; spmax[0] <=1'bl;

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end else begin I*FOLDBEG INS 0 4 sploci sploci 1'bl; spmax[0] 1'bO; spmaxfirst[0] 1'bO; WO 98/19410 PCTfUS97/18911 214

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end end if(fi rstscatcomplete begin if(splocl zeroll]) sum mod ulus(ramout[23:1I2], ramout[ 11:01); else sum mod ulus(ramout[23:12], ramout[1 11:0]) sum; end /*FOLDE NDS*I end /FOLDBEGINS 0 2 "search for largest continous pilot correlation"I/ if(spmax[2]) begin if(spmaxfirst[2]) begin v sum; continual pilot-offset pilot-Offset; end else begin if(sum>v) begin v <=sum; continual_pilot offset pilot-Offset; end end II$d isplay(sum, ,continual pilot -offset,,contcomplete,, ramwritestop, ,which -symbol, ,spoffset, ,,splocO, ,splocmaxcount, //$display(sum); end /*FOLDEN DS*I end assign carrier number contloc splocO splocoffset; /*FOLDBEG INS 0 0 "scattered pilot offset mod 3*/ always @(spoffset) begin splocoffset splocmaxcount =342; which-symbol 2'bO; ca se (s5poff set) 4'bOOOO,4'bOOl 1 ,4'bOl 1 0,4'bl 001: begin splocoffset 2'bO; splocmaxcount 342; end ,4bOlOO,4'bOl 1 1,4'blOlO: begin splocoff set 2'bOl; splocmaxcount 339; end //4'bOOl 04'bOl 01 ,4'bl 000,4'bl 011: default: begin WO 98/19410 PCTIUS97/18911 215 splocoffset 2'bO; splocmaxcount 339; end endcase case(spoffset) 4'bOOOO,4'bOO0l ,4'bOOl 0: which-symbol_ 2'bO; 4'bOOl1 1,4'bOl1O,4'bOl10l: which symbol-= 2'bOl; 4'bOl 1 TO,'bO 11 1,4'b 1000: which-symbol- 2'bl10; //4'bl100l,4'bl10l1O,4'bl 10 1: default: which-symbol- 2'b 1; endcase

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PFOLDBEGINS 1 0 "Search for scattered pilots"~*/ always @(posedge cik) begin if(resynch) sumscaffirst 12'hfff; else begin if(valid[0]&& !finishedsearch) /*FOLDBEGINS 1 2 "do the accumulations"~*/ case (mod 1 2fftcou nt) 4'hO: begin sumscat[0] (sumscatfirst[0I)? mod ulus(ffldata[23:12],fftdatall 11:0]): sumscat[0] moduius(fftdata[23: 12],fftdata[1 sumscatfirst[0] 1'bO; end 4'hl1: begin sumscat1 I (sumscafirst[1 mod uIus(fftdata[23: 1 2,fftdata[1 sumscat[1 I mod ulus(fftd ata[23: 12],fftdata 11:0]); sumscatfirst[1] 1'bO; v end 4'h2: begin sumscat[2] (sumscatfirst[2])? mod ulus(fftdata[23:1 2],ffidatafl1 sumscat[2] mod ulus(fftdata[23: 12],fftdata[ 11:0]); sumscatfirst[2] 1bO; end 4'h3: begin sumscat[3] (sumscatfirst[3])? mod ulus(fftdata[23:12],ffidata[1 sumscat[3] mod ul us(fftdata[23: 1 2],fftdata sumscatfirst[3] 1'bO; end 4'h4: begin WO 98/19410 PCT/US97/18911 216 sumscat[4] (sumscatfirst[4])? mod ulus(fftdata[23: 12],fftdata sumscat[4] mod ulus(fftdata[23: 1 2],ffidata 11:0]); sumscatfirst[4] 1 t bO; end begin (sumscatfirst[5])? mod u lus(fftdata[23: 1 2],fdata[1 1:01): mod ulus(ffldata[23:1I2],fftdata[ 1 'bO; end 4'h6: begin sumscat[61 (sumscatfirst[6])? modulus (fftdata[2 3:12],ffldata[ 11:0]): sumscat6] mod ulus(ffdata[23: 12],fftdata[ sumscatfirst[6] 1'bO; end 4'h7: begin sumscat7] (sumscatfirst[7])? mod ulus(fftdata[23:1I2],fftdata[1 sumscat[7] mod ulus(fftdata[23:1I2],fftdata[ sumscafirst[7] 1'bO; end 4'h8: begin sumscat[8] (sumscatfirst[8])? mod ulus(fftdata[23: 12] ,ffldata[ 11:0]): sumscat[8] mod ulus(fttdata[23: 12],fftdata sumnscatfirst[8] 1 'bO; end 4'h9: begin sumscat[9] (sumscatfirst[9])? mod ulus(fftdata[23: 12],fftdata[1 sumscat[9] mod ulus(ffldata [23: 1 2,fftdatal sumscatfirst[9] 1bO; end 4'ha: begin sumscat[1 0] (sumscatfirst[1 modulus(fftdata[23:1I2],ffdata[1 sumscat[1 0] mod ul us(fftd ata[23: 12],fftdata[1 11:0]); sumscatfirst[10] 1'bO; end default: begin sumscat[1 1] (sumscatfirst[1 modulus(fftdata[23: 1 2,fftdatall sumscat[1 1] modulus(ffidata[23: 12],ffldata[1 sumscatfirst[11] 1'bO; end endcase

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else if(fftfinished[0]) sumnscatfirst 12'hfff; end /*FOLDBEGINS 1 0 "Find offset"*/ if(resynch) fftfinished else WO098/19410 PCTJUS97/1891 1 217 begin fftffnished[0] validlo0]&&!fi nishedsea rch&&(Mfco unt==2047); fftfinished[1J fftfinished[0]; fftfinished[2] fftfinished[1]; ffifinished[3] fftfinished[2]; fftfinished[4] fftfinished[3]; end if(!ramwritestop) begin if(fftfinished[0]) begin sumscat[0] (sumscat[0] sumscat[1])? sumscat[0] sumscat[1]; sumscat[1] (sumscat[0] sumscat(1])? 0: 1; sumscat[2] (sumscat[2] sumscat[3])? sumscat[2] :sumscat[3]; sumscat[3] (sumscat[2] sumscat[3])? 2 3; sumscat[4] (sumscat[4] sumscat[5])? sumscat[4] (sumscat[4] sumscat[5])? 4 sumscat[6] (sumscat[6] sumscat[7])? sumscat[6] :sumscat[7]; sumscat[7] (sumscat[6] sumscat[7])? 6 7; sumscat[8) (sumscat[8] sumscat[9])? sumscat[8] :sumscat[9]; sumscat[9] (sumscat[8] sumscatf 8 9; sumscatl0] (sumscat[1 0]>sumscat[1 sumscat[1 0] sumscat[1 1] sumscat[l1 (sumscat[1 0]>sumscat[1 10 :11; end if (fftfin ished( I]) begin sumscat[O] (sumscat[0] sumscat[2])? sumscat[0] :sumscat[2]; sumscat[1] (sumscat[0] sumscat[2])? sumscat[1] :sumscat[3]; sumscat[2] (sumscat[4] sumscat[6])? sumscat[4] :sumscat[6]; sumscat[3] (sumscat[4] sumscat[6])? sumscat[5] sumscat[7]; sumscat[4] (sumscat[8] sumscat[1 sumscat[8] :sumscat[1O]; (sumscat[8] sumscat[l sumscat[9] :sumscat[1 1] end if(fftfnished[2]&&!ramwritestop) spoffset sumscatmaxnol; end if(fftfinished[0]) begin $display(sumscat[0]); $display(sumscat[1 $display(sumscat[2]); $display(sumscat[3]); $display(sumscat4]); $display(sumscat[6]); $display(sumscat[7]); $display(sumscat[8]); $display(sumscat[9]); $display(sumscat[1 $d isplay(sumscat[ 1]) $displayo; end end WO098/19410 PCTIUS97/1891 1 218 always @(sumscat[0] or sumscat[1 or sumscat[2] or sumscat[3] or sumscat[4] or or sumscatl or sumscat3 or begin sumscatmax =(sumscat[0] sumscat[2])? sumscat[0] sumscat[2]; sumscatmaxno0 (sumscat[0] sumscat[2])? sumscatl sumscat3[3:0]; sumscatmaxnol (sumscatmax sumscat[4])? sumscatmaxno0 sumscat5[3:0]; end assign mod l2fficount mod 12(fftcount); assign sumscatl sumscat[1]; assign sumscat3 sumscat[3]; assign sumscat5

/*FOLDENDS*/

/*FOLDENDS*/

/*FOLDBEGINS 0 0 "~ram"I*/ always @(posedge cik) ramaddr_ ramaddr; always @9(ramwritestop or valid or finishedsearch or fftcount or carrier-number or ramnwritestop, or ramaddr_ or fftdata) begin ramaddr ramaddr_; if( !ramwrite stop) begin if(valid[0]&&!fi nished search) ramaddr {fftcount[0],fficount[l1],fftcount[2] ,fftcou nt[31,fftcount[4],fftcount[ 5],fftcount[6], ffcount[7],ffcount[8],fficount[9],fftcount[ 1 end else ramaddr carfier -number; ramin =fttdata; wrstrb ramwritestop&&valid[1 end

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/*FOLDBEGINS 0 0 "modulus approximation function"*/ function [11:0] modulus; input [11:0] i; input [11:0] j; reg [11:0] modi; reg [11:0) modj; begin modi (i[1 -i iii 1]; modj Uj[11]? -j +j[1 1]; modulus modi modj; end endfu nction

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/*FOLDBEGINS 0 0 "mod 12"*/ function modl2; input [10:0] count; reg [14:0] onetwelfth; reg modulusl2; parameter TWELFTH 12'haab; WO 98/19410 PCTIUS97/18911 219 begin onetwelfth {count[0],count[1 ],count[2], count[3],count[4],count[5] count count[7] count[8], count[9J, count[ 10]) TWELFTH; modulusl12 {onetwelfth[ 14:9],1'bO) onetwelfth[l 4:9] 4'h8; X/12 modl2 modulusl2[7:4]; end

/*FOLDENDS*/

endfunction endmodule Listing ISccsld: @(#)bchidecode.v 1.2 8/22/97 PFOLDBEGINS 0 0 "copyright"*/ ICopyright 1997 Pioneer Digital Design Centre Limited INAME: BCH-rtl.v IIPURPOSE: BCH decoder for TPS pilots. Flags up to two error IIpositions using search technique.

rFOLDENDS*/ 'define DATAO SIZE 7'b0110100 'define DATA1_SIZE 7'bOll 1011 module bch decode (cik, resync, in_data, in_valid, in-finalwrite, out-valid, out-data); /*FOLDBEGINS 0 0 e"/OsH*I input clk, resync; input in data, in-valid, in-finalwrite; output out-valid; output out-data; reg out data; reg out valid;

/*FOLDENDS*/

/*FOLDBEGINS 0 0 "variables"/ reg resynch; reg valid; reg finalwrite; reg indata; reg SO; reg S1; reg S2; reg count; reg searchierror, found2error, oneerror, twoerror; wire twoerror_; reg noerrors; reg delay0, delay 1, delay2; reg GsO; reg Gsl; reg 16:0] Gs2;

/*FOLDENDS*/

always @(posedge cik) begin WO 98/19410 WO 9819410PCTIUS97/18911 220 /*FOLDBEGINS 0 2 "read in data and calculate syndromes"~/ resynch resync; if(resynch) begin valid I'b0; SO 7bO; SI 7'bO; S2 7'bO; end else begin valid in valid; if(delayl &&twoerrorj begin /*FOLDBEGINS 0 4 "update after one in two errors found"/I So SQA GsO; SI S1AGsI; S2 S2 AGs2;

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end else if(valid) begin SO indata A MULTAl (SO); S1 indata A MULTA2(S1); S2 indata A MULTA3(S2); end end indata in-data;

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/*FOLDBEGINS 0 2 "out-valid control"~*/ if(resynch) begin delayO 1'bO; delayl 1'bO; delay2 1bO; out valid 1'bO; final1write 1bO; end else begin finalwrite in finalwrite;if(valid&&finalwrite) delayO 1'bI; else if(count 'DATAlSIZE-4) delayO 1'bO; delayl delayO; delay2 delay 1; out -valid delay2; end /*FOLDEN DS*/ /*FOLDBEGINS 0 2 "error search algorithm"~/ if(delayO&&!delayl) begin noerrors, (SO 7'bO); WO 98/19410 WO 9819410PCT/US97/1891 1 221 searchierror (GFULL(SO,S1) found2error l'bO; twoerror 1'bO; count 7bO; GsO Gsl Gs2 7h3d; end else if(delayl) begin oneerror ((SOAGsO) ==7'bO)&&searchl1error; twoerror twoerror_; if(twoerrorj) begin searchi error lbl; found2error Pb 1; end GsO DlVi (GsO); Gsl DIV2(Gsl); Gs2 DIV3(Gs2); count count 1'bl; end out-data (twoerror I I oneerror)&&!noerrors;

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end assign twoerror_ GFULL((SOA GsO),(SJA Gs1)) (S2 AGs2))&&!found2error&&!twoerror; /*FOLDB EG INS 0 0 ~Iunctionsh*/ /*FOLDBEGINS 0 0 "GFULL function"~/ function GFULL; input X; input Y; reg AO, Al, A2, A3, A4, A5, A6; integer i; begin AO =X; Al {AO[5],AO[4],AO[3],AO[2] A AO[61,AO[1 A2 {A1 [5],A1 [4],AI [3],Al A Al [6],Al [1 ],Al [OJAl A3 {A2[5] ,A2[41,A2[3] ,A2[2] A A2[61,A2[ 1 A4 {A3[5] ,A3[4] ,A3[3] ,A3[2] A A3[6J,A3[ 1 {A4[5],A4[4],A4[3],A4[2] A A4[6],A4[l A6 {A5[5] ,A5[4] ,A5[3] ,A5[2] A A5[6],A5[l 1 ,A5[0I,A5[6]1; for(i=0;i<7;i=i+l) begin AO[i] AO[i] Y[0]; AlI[i] Al Y[1J]; A2[i) A2[i] Y[2]; A3[i] A3[i] Y[3]; A4[i] A4[i] Y[4]; A5[i] A6[i] A6[i] Y[6]; end GFULL AO A Al A A2 A A3 A A4 A A5 A A6; WO 98/19410 PCTIUS97/18911 222 end endfunction

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/*FOLDBEGINS 0 0 "MULTAl function"'/ funhction 01 M ULTAl; input X; begin MULTA1 A X[6],X[1 end endfunction /*FOLDEN DS*I /*FOLDBEGINS 0 0 "MULTA2 function"l/ function MULTA2; input X; begin MULTA2 ,X[2]A X[6] 1]A X[5] end endfunction

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/*FOLDBEGINS 0 0 "MULTA3 function"I*/ function MULTA3; input X; begin MU LTA3 X[6],X[1 ]A X[5] X[O]A X[4] end endfunction /*FOLDENDS*/ /*FOLDBEGINS 0 0 "DlVi function"*/ function DlVi; input X; begin DIVi X[2],X[1 end endfu nction

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/*FOLDBEGINS 0 0 "DIV2 function"*/ function DIV2; input X; begin DIV2 {X[1 I,X[01,X[6],X[5],X[4]AX[1 I,X13]AX[O],X[2]}; end endfunction

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/*FOLDBEGINS 0 0 "DIV3 function"l*/ function DIV3; input X; begin DIV3 ],X[01,X[61,X[5]A X[2],X[4]AX[1 I,X[3AX[0]1; end endfunction

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/*FOLDBEGINS 0 0 I/always @(posedge cik) $display(in -valid,,in data,,in-finalwrite,....out-valid,,out-data,...SO,,S1,,S2 I/always @(psedge cik) WO 98/19410 PCTIUS97/18911 223 II$d isplay(resynch,, in-va lid, in_data,,out-valid SO,, Si count,.., delay0, ,del ayl ,,delay2,,,, ,delay2,,noerrors, ,oneerror, ,twoerror,,out-data, ,out-valid); I/always @(posedge cik) $display(in-valid,,in_data out-valid,,out-data,..,SO,,S1,,S2,,.); I/always @(posedge clk) $display(in valid,,in-data__..out-valid,,out-data,...SO,,S1 /*FOLDEND9S*/ endmodule Listing 21 /Sccsld: 1.2 9/15/97 /*FOLDBEGINS 0 0 "~copyright"*/ ICopyright 1997 Pioneer Digital Design Centre Limited HI NAME: tps_rtl.v IIPURPOSE: Demodulates TPS pilots using DPSK. Finds sync bits.

IICorrects up to two errors using BCH.

HI (DPSK produces two errors for each transmission error)

IHISTORY:

1/9/97 PK Added scan 10 ports, te, Wdin tdlout

HI

I*FOLDENDS*I

'define SYNCSEQO 16'bOlllOllll00lOO 'define SYNCSEQ1 16'blOO0lOOO0l0lO0ll module tps (resync, clk, tps-valid, tps_pilot, tps-sync, tps_data, upsel, upaddr, uprstr, lupdata, te, tdin, tdout); I*FOLDBEGINS 0 0 'ViosII/ input resync, clk, tps -valid, tps_pilot, upsel, uprstr, te, tdin; input upaddr; inout lupdata; output tps sync, tdout; output [30:0] tps data;

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/*FOLDBEGINS 0 0 "registers"*/ reg resynch; reg foundsync; reg [66:0] tpsreg; reg [15:0] syncreg; reg tpsvalid; reg pilot; reg tps sync; reg bch count; reg bch go; reg bch-finalwrite; wire bch-data; wire bch-valid; wire bch-error; integer i; wire upselO; wire upsell; WO 98/19410 PCTIUS97/18911 224 wire upsel2; wire upsel3;

/*FOLDENDS*/

always @(posedge elk) begin P*FOLDBEG INS 0 2 "Synch ronise to TPS"I*/ resynch resync; if(tpsval id (found sync[0] I Ifoundsync[1]l I tps sync)) begin tpsreg[66] pilot 1 ]Apilot[0]; for(i=0;i<66;i=i+1) tpsreg[i] tpsreg[i+1]; end else if(bch-valid&&bch-error) tpsreglbch count] !tpsreg[bch count]; if(tpsvalid[O]&&(foundsync[0]l I foundsync[1 I)) begin pilot[ 1]A pilot[0I; for(i=0;i<1 5;i=i+1) syncreg[i] syncreg[i+1]; end pilot[0] tps pilot; pilot[1] Pilot[0]; if(resynch) begin tpsvalid 2'bO; tps sync 1'bO; bch-go 3'bO; bch-finalwrite 1'bO; bch-count 8'bO; foundsync end else begin tpsvalid[O] tps valid; tpsvalid[1] tpsvalid[0]; bch_go[1] bchgo[0]; bch_go[2] bchgo[1]; bch finalwrite (bch-count 65)&&bch_go[2]; if((b-ch_count 52)&&bch_valid) tps sync 1'bl; /*FOLDBEGINS 0 2 "lcounter"~*/ if(bch_count 66) bch-count 8'bO; else if(tpsvalid[1 (foundsync[0] IIfoundsync[ begin if(tpsreg[15:0] 'SYNOSEQ1) bch count 8'hfe; if(tpsreg[15:0] 'SYNCSEQO) bch-count 8'hfe; /1-2 end else if(tpsvalid[1 ]&&(bch-count== 15)&&(fou ndsync[0] I foundsync[ WO 98/19410 PCTIUS97/18911 225 bch -count 8'hfe; else begin if(bch -valid bchgo[0] I((foundsync[0] Ifoundsync[1 ])&&tpsvalid[0])) bch -count bch-count 1'bl; end I*FO LDEN DS*I I*FOLDBEGINS 0 2 "BCH second SYNC reg control"/ if(bch count 66) begin bch-go 3bO; end else if(tpsvalid[1I)begin if(foundsync[0] Ifoundsync[1]) begin if(bchcount== begin if(((syncreg[1 5:01 'SYNC SEQO) &&fou ndsync[ 1) ((syncreg[1 SYNCSEQ1)&&foundsync[Q])) bchgo[01 1'bl; else foundsync 2'bO; end end else begin if(tpsreg[15:0] 'SYNCSEQ1) foundsync[1] 1bl; if(tpsreg[15:0] 'SYNOSEQO) foundsync[01 1'bl; end end

/*FOLDENDS*/

end

/*FOLDENDS*/

end assign bch data tpsregllbch count]; /*FOLDBEGINS 0 0 I/always @(posedge clk) //begin I$write (tps_valIid, tps_syn c,,tps_p ilot,, tpsva lid[ 1],,pilot Ibch -finalwrite bch_go[2],,bch-data,,bch-valid,,bch_error,,bch-count,,tps $d isplayb(tpsreg,,syncrego u nd sync); I/end

/*FOLDENDS*/

/*FOLDBEGINS 0 0 "micro access"~*/ assign upselO upsel&&uprstr&&!upadd !upaddr[0J; assign upset 1 upsel&&uprstr&&' upaddr[1 upaddr[0]; assign upsel2 upsel&&uprstr&& upaddr[1 !upaddr[01, assign upsel3 upsel&&uprstr&& upaddr[1]&& upaddr[0]; assign lupdata upselO? {1'bO,tps data[30:24]} 8'bz, lupdata upsell tpsdata[23:16] 8'bz, lupdata upsel2? tpsdata[15:8]: 8'bz, WO 98/19410 PCT/US97/18911 226 Iupdata upsel3? tpsdata[7:0] :8'bz; rFOLDENDS*/ assign tps data tpsreg[52:22]; bch decode bch 1 (.clk(clk), resync(resync), .in-valid(bchgo[2]), .in-:finalwrite(bch-finalwrite), .in data(bch data), .out -valid(bch -valid), .out-data(bch error)); endmodule Listing 22 //SccsID %G%g //FOLDBEGINS 0 0 "Copyright 1997 Pioneer Digital Design Centre Limited r Copyright 1997 Pioneer Digital Design Centre Limited NAME: sydint-rtl-v PURPOSE: <a one line description> CREATED: Thu 14 Aug 1997 BY: Paul(Paul McCloy) MODIFICATION HISTORY: 15/9/97 PK Increased width to 13 to allow for bad-carrier flag

//FOLDENDS

//FOLDBEG INS 0 0 "module symdint top level" module symdint //FOLDBEGINS 0 0 "pins out data, valid, d-symbol, valid-in, demap data, odd symbol, symbol, carrierO, constellation, /FOLDBEGINS 0 3 "ram pins." ram a, ram -di, ram -do, ram wreq,

//FOLDENDS

IIFOLDBEG INS 0 3 "scan pins." tdin, tdout, WO 98/19410 PCTJUS97/1891 1 227 te,

//FOLDENDS

nrst, clk

//FOLDENDS

parameter WIDTH 13; /Modified by PK 15/9/97; 12->1 3 parameter ADDR_WIDTH 11; //FOLDBEGINS 0 2 "outputs output tdout; output valid; output [1 7:0]out data; output dlsymbl; output [ADDRWIDTH-i :0]ram_a; output [WIDTH-i :0]ram di; output ram wreq;

//FOLDENOS

//FOLDBEGINS 0 2 "inputs input valid_in; input [WIDTH-i :0]demap data; input odd symbol; input symbol; input carrierO; input [WIDTH-1:Qlram_do; input [1 :0]constellation; input tdin, te;_ input nrst, clk;

/FOLDENDS

/FOLDBEG INS 0 2 "regs I/wires /FOLDBEGINS 0 0 "inputs regs." reg valid_in_reg; reg [WIDTH-I :Ojdemap data reg; reg odd symbol reg; reg symribol reg; reg [WIDTH-1:0]ram -do_reg; reg Ii :Olconstellationreg;

/IFOLDENDS

/IFOLDBEGINS 0 0 "output regs..

reg valid; reg [I 7:0]out data; reg dsymbol; reg [ADDRWIDTH-i :Ojram_a; reg [WIDTH-1:0]ram di; WO 98/19410 228 reg ram-wreq;

//FOLDENDS

//FOLDBEGINS 0 0 "instate reg parameter INSTATE WAITSYMBOL 2'dO; parameter INSTATE WAITVALID 2'dl; parameter INSTATE-WRITE 2'd2; parameter INSTATEWRITERAM 2'd3; reg

//FOLDENDS

//FOLDBEGINS 0 0 "outstate reg parameter OUTSTATE WAIT-WRITEFINISHED 3dO; parameter OUTSTATE-WAITO 3'dl; parameter OUTSTATE-WAIT1 3'd2; parameter OUTSTATE READRAM 3'd 3; parameter OUTSTATE-WAIT2 3'd4; parameter OUTSTATE-OUTPUTDATA Td parameter OUTSTATE-WAIT3 =3'd6; reg [2:0]outstate -reg;

/FOLDENDS

reg reg reg next-read-reg, next-write-reg; reg frist -data reg; reg oddF read -reg, odd -write reg; reg sym-rst-readjreg, sym-rst-write reg; reg [17:01 demnapped; reg 13:0] iminus; reg qminus; reg outi; reg outq; reg demap; //FOLDBEGINS 0 0 "wires wire [ADDRWIDTH-i :0]address read, address-write; wire finished read, finished-writewire valid-read, write-valid; wire [5:Q]ini, inq;

IIFOLDENDS

IIFOLDENDS

ag #(ADDRWIDTH) r //FOLDBEGINS 0 2 "pins." .add ress(add ress-read), .finished(finished read), .next(next-read_reg), PCTIUS97/1891 1 WO 98/19410 W098/9410PCTIUS97/1891 1 229 .random(oddreadjreg), .sym_rst(sym rst-read-reg), .nrst(nrst), .clk(clk)

//FOLDENDS

ag #(ADDR WIDTH) w //FOLDBEGINS 0 2 "pins add ress(address write), .finished(finished write), .next(next-write-reg), rand om(-odd-writereg), .sym_rst(sym-rst-write-reg), .nrst(nrst), .clk(clk)

//FOLDENDS

//FOLDBEGINS 0 2 "latch inputs." always @(posedge clk) begin valid-in-reg valid-in; demapdatajreg demap data; odd-symbolreg odd -symbol; symbol reg symboI; ram-do-reg ram-do; constellation-reg constellation; end

//FOLDENDS

always @(posedge clk) begin if( -nrst) I/FOLDBEGINS 0 4 "reset begin instate-reg INSTATE WAIT SYMBOL; outstate reg OUTSTATEWAITWRITEFINISHED; next -read reg 0; end

//FOLDENDS

else begin //FOLDBEGINS 0 4 "input state machine." //$write("DB(%Od instate-reg=%Od fw=%b\n", II $time, instate-reg, finished-write); case (instate reg) INSTATEWAITSYMBOL: begin sym_rst iwrite reg 1; next -write -reg 0; ram-Wreq 0; if( symbolreg) begin WO 98/19410 PCTIVS97/18911 230 //$write("DB(%Od GOT %x (NEW SYMBOL)\n", $time, demap_data_reg); $write("DB(%Od START WRITIEWn, $time); odd -write-reg odd-symboi-reg; data-reg demap data -reg; instate-reg INSTATEWRITE; end end INSTATE_-WAIT_-VALID: begin ram wreq 0; next -write -reg 0; if( finished-Write) begin $write("DB(%Od END(1) WRITE\n", $time); instate reg INSTATEWAITSYMBOL; end else begin if( valid-in-reg) begin data reg demap_data_reg; instate reg INSTATEWRITE; end end end INSTATEWRITE: begin symrsti'write-reg 0; next-Write reg 1; ram a aiddress write; II$write("DB(%Od RWritef%xI $time, address-write, data reg); ram -di Z=data reg; ram-wreq 1; if( finished-write) begin $write("DB(%Od END(2) WRITE\n", $time); instate-reg INSTATEWAITSYMBOL; ram -wreq 0; end else instate-reg INSTATEWAITVALID' end endcase

//FOLDENDS

//FOLDBEGINS 0 4 "output state machine." //$write("DB(%Od outstatereg=%Od nr:%b r: HI $time, outstate_reg, next-read reg, odd_symbol_reg); case (outstate Treg) OUTSTATEWAITWRITEFINISHED: begin sym-rst read reg 1; frist data reg 1; valid'< (T0; if( finished-Write) begin -odd-read-reg odd write reg; WO 98/19410 PCTIUS97/18911 231 outstate-reg OUTSTATE WAITO; $write("DB(%Od START READ~n", $time); //$write("DB(%Od Read (NEW SYMBOL)\n", $time, address-read); end end OUTSTATEWAITO: begin sym_rst -read reg 0; outstate-reg OUTSTATEWAITI; end OUTSTATEWAITI: begin outstatereg OUTSTATEREADRAM; end OUTSTATE READRAM: begin //$write("DB?'/o~d Read $time, address-read); ram -a address read; ram wreq 0; next- read reg 1; outstate-reg OUTSTATEWAIT2; end OUTSTATEWAIT2: begin next read-reg 0; outstate-reg OUTSTATEOUTPUTDATA; end OUTSTATEOUTPUTDATA: begin out data {outi[8:6], outq[8:6], outi[5:3], valid 1; d-symbol frist-data -reg; frist data-reg 0; outstate-reg OUTSTATEWAIT3; end OUTSTATE_-WAIT3: begin valid 0; if( finished-read) begin outstate-reg OUTSTATE WAITWRITEFINISHED; $write("DB(%Od END READ\n', $time); end else outstate-reg OUTSTATEWAITO; end endcase

//FOLDENDS

end end always @(constellation -reg or ini or inq) //FOLDBEGINS 0 2 "dernapper...

begin IIFOLDBEGINS 0 2 "coarse demnapping" iminus ini[5:31,1'bO} -2'd3; qminus ={inq[5:3],1'bO} -2'd3; if(constellationreg==2'bo1) begin WO 98/19410 WO 98/ 9410PCTIUS97/1891 1 232 demnap 2'bO, im in us[2], qm in us[2], !(iminus[2]A iminus~l !(qminus[2]A qrinus[1]) //$writeb(demap,,); //$dispiay(iminus,,ini[5:31); end else if(constellation reg==2'bl 0) begin iminus ={inhi[5:3],1'bO} -3'd7; qminus ={inq[5:3],1'bO} -3'd7; demnap ={iminus[31, qminus[3], I(iminus[3]A iminus[2]), !(qminus[3]A qminus[2]), (iminus[2lA iminus[1 I), (qminus[2]A qrinus[l]) end else demnap =6'bO;

//FOLDENDS

if(constellationreg==2'bOl) begin //FOLDBEGINS 0 4 I16QAM' begin outi[8:6] outi[5:3] end else begin outi[8:6] outi[5:3] 3'bO; demap[31? 3'bl 11 3'bQ; iminus[2]? ini[2:0] 3'bO; 3'bll1; end if(!qminus[1 ]&&qminus[0]) begin outq[8:6] 3'bO; outq[5:3] demap[2]? 3'bl 11 3'bO; qminus[2]? inq[2:0] end else begin outq[8:6] 3'bO; outq[5:3] end

//FOLDENDS

'bll11; WO 98/19410 WO 9819410PCT/US97/1891 1 233 end else if(constellation-reg==2'blO) begin //FOLDBEGINS 0 4 "64QAM" if(!iminuslll]) begin outi[8:6] demap[5]? 3'bl 11: 3bO; outi[5:3] demap[3]? 3'bl 11: 3'IbO; iminus[2]? '-ini[2:0] end else if(!iminus[2]) begin outill8:6] demap[5]? 3bl 11 3'bO; outi[5:3] iminus[3]? ini[2:0]: outi[2:0] demap[1 3'blll1 3'IbO; end else begin outi[8:6] outi[5:3] demapl3]? 3'bl 11: 3bO; demapill? 3'bl 11: 3bO; end if( !qminus[ 1]) begin outq[8:6] demap[4]? 3'bl 11: 3bO; outq[5:3] =demap[2]? 'bl 11 3'bO; qminus[2]? -inq[2:0] end else if(!qminus[2]) begin outq[8:6] demap[4]? 3'bl 11: 3bO; outq[5:3] qminus[3]? inq[2:0] demap[O]? 3'bl 11: 3bO; end else begin outq[8:6] outq[5:3] demap[2]? 3'bl 11: 3bO; demap[0]? 3'bl 11: 3bO; end

//FOLDENDS

end else begin //FOLDBEGINS 0 4 "QPSK" outi ={6'bQ,-inil2:0}; outq 6'bO,-inq[2:0]};

//FOLDENDS

end end

//FOLDENDS

assign ini ram-do regll 1:6]; assign inq WO 98/19410 W098/9410PCTIUS97/18911 234 endmodule

//FOLDENDS

//FOLDBEGINS 0 0 "module ag (address gereration)..."

IIIIII/IIIIIIIIIIIII/IIII///II/IIIII

module ag //FOLDBEGINS 0 0 "pins." address, finished, next, random, sym _rst, n rst, cik

//FOLDENDS

parameter ADDRWIDTH =12; //FOLDBEGINS 0 2 "outputs output [ADDRWIDTH-i address; output finished-,

//FOLDENDS

//FOLDBEGINS 0 2 "inputs input next; input random; input symrst; input nrst, cik;

//FOLDENDS

//FOLDBEGINS 0 2 "regs integer i; reg finished; reg prsr-reg; reg [11:0) count-reg; wire address-valid;

//FOLDENDS

always @(posedge cik) begin if( -nrst) begin count-reg 0; prsr -reg end else begin if(symrst) begin finished 0; WO 98/19410 PCT[US97/18911 235 count-reg 0; end else if( next I (!address-valid random)) begin II$write("DB(%Od Next(r: $time, random); if( random //FOLDBEGINS 0 8 "do the random stuff bgn if( !address-valid) begin //FOLDBEGINS 0 4 "drive the prsr." if( count reg 11'dO prsr -reg else if( count -reg 11'dl) prsr-reg else begin for(i=0;i<9;i=i+1) prsr reg[i] prsr reg[i+1]; prsrreg[9] prsr -reg[0] A prsr-reg[3]; end

//FOLDENDS

count reg count reg 1; II$write("DB(%Od count=%Od Rand(Retry)\n", $time, count-reg); end else begin if( count -reg 1 1'd2047) begin II$write("DB(%Od **FINISHED Rand\n", $time); finished 1; count -reg 0; prsr-reg end else begin //FOLDBEGINS 0 6 "drive the prsr..

if( count reg 1 1'dO prsr -reg else if( count reg 11'dl 1 prsr-reg else begin for(i=0;i<9;i=i+1) prsr -reg[i] prsr-reg[i+1]; prsrreg[9] prsr reg[0] A prsr-reg[3]; end

IFOLDENDS

count-reg count reg 1; WO 98/19410 PCTIUS97/18911 236 //$write("DB(%Od count=%Od Rand\n", $time, count-reg); finished 0; end end end

//FOLDENDS

else //FOLDBEGINS 0 8 "do the sequential stuff bgn if( count -reg 11'd1511) begin II$write("DB(%Od count=%Od Sequ\n", $time, count-reg); count reg count-reg +1; finished 0; end else begin //$write("DB(%Od FINISHED Sequ\n", $time); finished 1; count-reg 0; end end

/IFOLDENDS

end end end //FOLDBEGINS 0 2 "assign address assign address =(random) ({count reg[0], prsr reg[2], //9 //8 prsr -reg[8], H17 prsrrjeg[3], //6 prsr -reg[7], prsrreg[0], H14 prsr -reg[1], 3 prsrreg[4], /H2 prsr -reg[6], H11 prsrreg[9]}): 0 count reg; //FOLD ENDS assign address-valid =(address 11'd1 512); endmodule

I/FOLDENDS

Listing 23 //SccslD: "@(#)bitdeint.v 1.4 9/14/97" //FOLDBEGINS 0 0 "Copyright 1997 Pioneer Digital Design Centre Limited" Copyright 1997 Pioneer Digital Design Centre Limited NAME: bitdeint-rtl.v PURPOSE: bit deinterleaver WO 98/19410 PCTIUS97/1891 1 237 CREATED: Wed 23 Jul 1997 BY: Paul(PauI McCloy) MODIFICATION HISTORY:

//FOLDENDS

module bitdeint //FOLDBEGINS 0 2 "pins." _-data, q_data, discardi, discard_q, valid, H/ output //FOLDBEGINS 0 2 "ramO pins." ramO-a, ramO-di, ramO-do, ramO_wreq, ramO-ce,

//FOLDENDS

//FOLDBEGINS 0 2 "rami pins." rami-a, rami di, rami1 do, rami_ wreq, rami ce,

//FOLDENDS

//FOLDBEGINS 0 2 "ram2 pins." ram2-a, ram2_di, ram2_do, ram2_-wreq, ram2 ce,

//FOLDENDS

bad-carrier, valid-in, data-in, symbol, constellation, HI constellation alpha, HI does not do anything yet //FOLDBEGINS 0 2 "scan pins." td in, tdout, te,

//FOLDENDS

n rst, WO 98/19410 WO 9819410PCTIUS97/18911 238 olk

//FOLDENDS

parameter SBW 3; soft bit width //FOLDBEGINS 0 2 "outputs." //FOLDBEGINS 0 0 "ramO outputs...

output [6:0]ramO a; output [((SBW+1)«1l)-1:0]ram0_d[; output ramO-ce; output ramO wreq;

//FOLDENDS

//FOLDBEGINS 0 0 "rami outputs output [((SBW'1)«1l)-1:0]raml_di; output rami1_ce; output rami wreq;

//FOLDENDS

//FOLDBEGINS 0 0 "ram2 outputs output [6:Q]ram2_a; output [((SBW+1 :0]ram2_di; output ram2_ce; output ram2 wreq;

//FOLDENDS;

output tdout; output [SBW-1 :0]i_data; output output discard-i; output discard-q; output valid;

//FOLDENDS

//FOLDBEGINS 0 2 "inputs." input [((SBW+1)«1l)-1:0]ramO-do; input [((SBW-i1)«1l)-1:0]raml-do; input [((SBW+1)«1l)-1:0]ram2_do; input bad-carrier; input valid_in; input [((SBW«<2)+(SBW«1l))-1:0]data_in. I 6*SBW bits input symbol; input constellation; input alpha; input tdin, te; input nrst,- clk;

/FOLDENDS

//FOLDBEG INS 0 2 "reg wire //FOLDBEGI NS 0 0 "outputs." WO 98/19410 PCTIUS97/18911 239 //FOLDBEGINS 0 0 "ramO regs." reg reg [((SBW+l)«<l)-:0]ramO-di; reg ramOce; 5 reg ramO wreq;

//FOLDENDS

/FOLDBEGINS 0 0 "rami regs." reg reg [((SBW+1)<<1)-1:0]ram1_di; reg rami_ce; reg rami wreq;

//FOLDENDS

//FOLDBEGINS 0 0 "ram2 regs reg [6:0]ram2_a; reg :0]ram2_di; reg ram2_ce; reg ram2 wreq;

/FOLDENDS

reg [SBW-1 :0]i data; reg reg discard_i reg discardq; reg valid;

/FOLDENDS

//FOLDBEGINS 0 0 "inputs." reg valid in_reg; reg :0]datainreg; //6*SBW bits reg symbol reg, b.ad-carrier reg; reg constellation reg; reg alpha reg; reg [((SBW+1)<1)-1:0]ramO-do_reg; reg [((SBW+1)«1l)-1:0]raml-do_reg; reg [((SBW+1 :0]ram2_do_reg;

//FOLDENDS

reg [6:0]i0_adr -reg; reg [6:0]il_adr -reg; reg [6:0]i2_adr -reg; reg [6:0]i3_adr-reg; reg [6:0]i4_-adr -reg; reg [6:0]i5_adr-reg; reg mode_reg; reg BW<<2)+(SBW< 1 Ol]data reg; HI 6*(SBW) bits reg [((SBW+1)«1l)+SBW:0]i out buf-reg, q_out-buf-reg; HI 3*(SBW+1) bits reg ramjfilled reg, out-buf full reg, bad_car-reg; wire [SBW:0] iD_in, qO_in, ii_in, qi_in i2_in q2_in; wire [SBW:0] iO ram, qO_ram, il_ram, qi_ram ,i2_ram ,q2_ram;

//FOLDENDS

WO 98/19410 PCTIUS97/18911 240 //FOLDBEGINS 0 2 "latch inputs always @(posedge cik) begin bad-carrier-reg bad_carrier; valid-in-reg valid -in.

data-in-reg <=data in; symbol reg symbol; constellation-reg constellation; alphareg alpha; ramO-do-reg <=ram0_do; rami-do-reg rami-do; ram2_do-reg ram2_do; end

//FOLDENDS

always @(posedge clk) begin if( -nrst) //FOLDBEGINS 0 4 "reset." begin mode-reg Z'OO; valid 0; iQ adr -reg 0; il -adr -reg 63; i2 -adr -reg 105; B adr -reg 42; i4 adr -reg 21; 84; _-out-buf-reg 0; qout buf reg 0; ram- filled-reg 0; out -buf -full1-reg 0; end

//FOLDENDS

else begin if( valid in reg) //FOLDBEGINS 0 6 "start cycle...

begin data-reg data-in-reg; bad car-reg bad -carrier -reg; II$write("DB(%Od data reg=%X(%b. $time, data_inreg, IIbad Icarrier, bad -carrier -reg, bad_car -reg); //FOLDBEGINS 0 2 logic to read iO,1 ,2 ramO-a iO-adr -reg; ramO-wreq 0; rami -a il adr -reg; rami-wreq 0; ram2_-a Qi2_adr -reg; ram2 wreq 0;

//FOLDENDS

WO098/19410 PCTIUS97/1891 1 241 ramO-ce rami-ce (constellation-rag 2'b (constellation reg 2'bOl); ram2_ce (constellation reg ==2'bl 0); //FOLDBEGINS 0 2 "output il and q1 if( out-buf-full reg (constellation rag 2'bOO)) begin valid 1; idata i out but dfiscard-i i-out_buf-reg[((SBW+1)«1l)-1]; qdata q out but reg[((S BW+ 1 (SBW+ discardq qout buf-reg[((SBW+1)<<1)-1]; //$write("DB(%Od OUT(l1):%x $time, ii i out buf reg[((SBW-i1 q- qoufbufreg[((SBW-i-i)<1 (SBW+1 end

//FOLDENDS

mode -reg end

//FOLDENDS

else begin //$write("DB(%Od $time, mode rag); case( mode reg //FOLDBEGINS 0 8 begin //FOLDBEGINS 0 4 "logic to read qO, 1,2 ramO-a i3_adr-reg; ramO-wreq 0; ram- a<=i4-adr rag; raml-wreq 0; ram2_a i5-adr rag; ram2-wreq 0;

//FOLDENDS-

valid 0; mode-rag 3bOlO; end

//FOLDENDS

//FOLDBEGINS 0 8 "3'bOlO:." 3'bOlO: begin mode reg 3'bOl 1; //FOLDBEGINS 0 4 "output i2 and q2..

if( out -buf -full rag (constellation-rag ==2'blO)) begin valid 1; i data i out buf discard i i-o-ut-b uf regSBW]; WO 98/19410 PCTIUS97/18911 242 qdata q-out-buf reg[SBW-1 discardq qoutbufre[SBW]; //$write("DB(%Od OUT(2): %x $time, i iout buf reg[SBW-1 :01, I end

//FOLDENDS

end

//FOLDENDS

//FOLDBEGINS 0 8 "3'b01 1: 3'bOll1: begin valid 0; //$write(" DB(%Od ram read iO:%x il:%x i2:%x\n", II $time, II ramO -do reg[((SBW+1)«1l)-1 :SBW+1], II rami -doreg[((SBW+1 :SBW+1], II ram2_do reg[((SBW+1)<<1)-1 :SBW+1]); iout -buf -reg {ram0 do reg[((SBW+1 :SBW+1], ramldoreg[((SBW+1 :SBW+1, ram2-doreg[((SBW+1 :SBW+1]} /IFOLDBEGINS 0 4 "logic to write new iO,1,2 ramO -a 10_-adr -reg; ramO-wreq 1; ramO-di {iO_in, qoram}; rami a ii adr -reg; raml -wreq 1; rami-di fii_in, qi_ram}; ram2_-a i2_ adr -reg; ram2 -wreq ram2-di {i2_in, q2_ram};

//FOLDENDS

mode-reg 3'blOO; end

//FOLDENDS

//FOLDBEGINS 0 8 "3'blOO:

I

3'blOO: begin II$write("DB(%Od ram read qo:%/x ql:%x q2:%x\n", II $time, ramO -do -reg[SBW:0], II rami-doreg[SBW:0], II qout -buf -reg {ramO -do oreg [S BW: 0], ramildoreg[SBW:0], ram2-do-reg [SBW: out buf full reg ram -filled reg; //FOL-DEINS 0 4 "logic to write inew qO, 1,2 WO 98/19410 PCTfUS97/18911 243 ramO-a i3-adr-reg; ramO-wreq 1; ramO-di {iO ram, q0_in); rami i4-adr reg; raml-wreq 1; rami-di {il-ram, qi_in); ram2_a ram2 -wreq 1; ram2 di {i2ram, q2_in); //FOLDEN DS //FOLDBEGINS 0 4 "output iO and qO if( out buf fullreg) begin valid 1; _-data i-out-buf-reg[((SBW+1)<<1)+SBw-1:((SBW+1J)<1)]; discardi i-out-buf-reg[((SBW+1)«1l)+sBW]; qdata q out buf reg[((SBW-'1 )+SBW-1 :((SBW+1 )I; discardq q ou u reg[((SBW+ 1 1)+SBW]; //$write("DB(%Od OUT(0):%x $time, ii iout-buf reg[((SBW+1 )+SBW-1 :((SBW+1 I- q out-buf reg[((SBW+ 1 )«1)+SBW-1 :((SBW+1 end //FOLDEN DS mode-reg end

//FOLDENDS

//FOLDBEGINS 0 8 "3'bl101 3'bl 01 :begin valid 0; //FOLDBEGINS 0 4 "increment ram address...

if( 10 adr reg 7'd125) begin iO-adr-reg //FOLDBEGINS 0 2 "do il -adr reg (63 offset)..." iladr-reg (iladr -reg 7'd20) Td84: (ii adr -reg T=7d41) T'd105: (ii adr reg T=7d62) 7'dO (ii adr -reg T=7d83) Td21 (i 1 adr rreg T=7d 104) 7'd42: Td63; //FOLDBEGINS 0 2 "do i2_adr reg (105 offset)..." i2-adr-reg (i2_adr-reg 'd120) 7'd42 (i2_adr-reg T=7d41) 7'd63: (i2_adr-reg T=7d62) T'd84: (i2_adr-reg 7'd83) 7'd105: (i2_adr-reg ==7d104) 7 7'dO Td121

//FOLDELNDS

WO 98/19410 PCTIUS97/18911 244 //FOLDBEGINS 0 2 "do i3_adr reg (42 offset)...

i3-adr-reg (13_adr reg d20) 7'd105: (1 3_ad r-reg T=7d4 1) (13_adr -reg Tc17'62) 7'd21 (13_adr reg Tc17'83) 7'd42 i3-adr-reg Tcl 7104) 7'd63: 7'd 84;

//FOLDENDS

//FOLDBEGINS 0 2 "do i4_adlr reg (21 offset)..." i4-adr-reg (i4-adr reg Td20) 7'dO (14_adr -reg T=7d41) 7'd21 (i4_adr-reg Tc17'62) 7'd42: (i4_adr reg ==7d83) 7 7'd63: (14_adr-reg Tcl7'104) 7cd84: T'd105;

//FOLDENDS

//FOLDBEGINS 0 2 "do i5_-adr reg (84 offset)..." (i5_adr-reg 7'd20) 7'd63 -adr -reg T=7d41) Tcd84: (i5 -adr~reg Tc17'62) T'd105: -adr -reg T=7d83) 7'dO Tcl 7104) 7'd21 7'd42;

//FOLDENDS

ram -filled reg 1; end else begin iO-adr -reg i0 adr -reg 1; il-adrrjeg (il adr -reg T=7d125) 0: il_adr reg +1; i2-adr -reg (12-adlrreg T=7d125) 0: Q 2adr reg +1; i3-adrreg (i3 adr-reg ==7d125) 0 :i3_-adr -reg +1; i4_adr -reg (i4_adr -reg TcI'd125) 0: i4_-adr -reg +1; ('5-adr-reg T=7d125) 0 :15 adr-reg +1; end

//FOLDENDS

end

//FOLDENDS

endcase end end end assign iOin ={bad car reg, data reg[(SBW«<2)(SBW<1 assign qoin bad car reg, data reg[(SBW.'<2)VS BWT-1 SBW«<2]}; assign ilun bad_car-reg, data reg[(SBW<<2)-1 (SBW« 1 )+SBW]}I; assign qlin f bad_car-reg, data reg[(SBW«1l)+SBW-1 assign i2_in bad-car-reg, datajeg[(SBW<<1)-l

:SBW]};

assign q2_in-= bad_car-reg, WO 98/19410 WO 9819410PCTIUS97/1891 1 245 data reg[SBW-1 assign 10rm i out Ibut assign qO ram =q_out_but reg[((SBW+ 1 )«1)+SBW:((SBW+1 assign ii_ram =i-out -but Ireg[((SBW+)«1J)-1:sBw+1]; assign qi ram q_out_but reg[((SBW+1)<c<1)-1:SBW+1]; assign Q2_ram i out buf reg[SBW:0]; assign q2 ram q out_bu-freg[SBW:0]; endmodule Listing 24 Sccsld: %G% Copyright 1997 Pioneer Digital Design Centre Limited module acc prod (clk, resync, load, symbol, new-phase, old phase, xcount, acc-out); input olk, resync, load, symbol; input [10:0] xcount; input [13:0] new-Phase, old_phase; output [29:0] acc out; reg [29:0] acc -out; reg [29:0] acc_int; reg [14:0] diff; reg [25:0] xdliff; reg sign; reg [14:0] mod_diff; reg [25:01 mod_xdiff; always (posedge clk) begin if (resyno) begin acc-out 0; acc int 0; end else begin if (load) acc-imt acc mnt {xdiff[25], xdiff[25], xdiff[25], xdlitf); if (symbol) begin acc-out acc-int; acc imt 0; end I/sign extend WO 98/19410 PCTIUS97/18911 246 end end always (new-Phase or old-phase or xcount) begin duff ={new-phase[1 new-phase} sign extend up to allow {old phase[13], old_phase}; differences up to 360 sign diff[14]; mod diff sign (-diff 1) diff; mod-xdiff mod -duff {4'bO, xcount}; xdiff sign (-mod xdiff 1: o_xif end 1:mdxif endmodule Listing iSccsld: %G%g Copyright 1997 Pioneer Digital Design Centre Limited module acc-simple (clk, resync, load, symbol, new-Phase, old_phase, accOout); input clk, resync, load, symbol; input [13:0] new-Phase, old_phase; output [20:0] acc out; reg [20:0] acc -out; reg [20:0] acc -it; reg [14:0] duff; always (posedge clk) begin if (resync) begin acc-out 0; acc int 0; end else begin if (load) acc-imt acc m it {diff[14], diff[14], diff[14], diff[ 14], difff[14), diff[14], diff}; if (symbol) begin acc-out acc-int; acc int 0; end end sign extend WO 98/19410 PCTIUS97/18911 247 end always (new_phase or old_phase) diff {new_phase[13], new_phase} sign extend up to allow {old_phase[13], old_phase}; differences up to 360 always (diff or load) begin: display reg[14:0] real_diff; if (load) begin if (diff[14]) begin realdiff (diff 1); $display ("diff real_diff); end else $display ("diff diff); end end display endmodule Listing 26 Sccsld:

%G%

Copyright 1997 Pioneer Digital Design Centre Limited module addrgen (clk, resync, u_symbol, uc_pilot, got_phase, en, load, guard, addr, xcount, guard_reg, symbol); input clk, resync, u_symbol, uc_pilot, got_phase; input guard; output en, load, symbol; output guard_reg; output addr; output [10:0] xcount; reg en, load, load_p, inc_count2, symbol; reg guard_reg; reg reg [10:0] xcount; reg addr; always (posedge clk) begin if (resync) begin 0; WO 98/19410 WO 9819410PCT/US9711891 1 248 load-p 0; load 0; inc-count2 0; symbol 0; guard reg 0; end else begin if (u symbol) begin inc-count2 1; guard reg guard; end if (inc count2 uc-pilot) begin inc count2 0; 0; end if (got phase) count45 1; load-p en; load load-p; symbol (inc count2 uc-pilot); addr en got-Phase !resync (count45 45); H!H 45 end end always case 1: xcount =1; 2: xcount 49; 3: xcount 4: xcount 88; xcount 142; 6: xcount 157; 7: xcount 193; 8: xcount 202; 9: xcount =256; xcount= 280; 11: xcount= 283; 12: xcount =334; 13: xcount 433; 14: xcount =451; xcount 484; 16: xcount 526; 17: xcount 532; 18: xcount =619; 19: xcount 637; xcount 715; 21: xcount 760; 22: xcount 766; 23: xcount =781; 24: xcount 805; WO 98/19410 W098/9410PCTIUS97/1891 1 249 xcount 874; 26: xcount 889; 27: xcount =919; 28: xcount 940; 29: xcount 943; 30: xcount= 970; 31: xcount 985; 32: xcount 1051; 33: xcount 1102; 34: xcount 1108; xcount 1111; 36: xcount 1138; 37: xcount 1141; 38: xcount 1147; 39: xcount 1207; xcount 1270; 41: xcount =1324; 42: xcount 1378; 43: xcount 1492; 44: xcount 1684; xcount 1705; default: xcount 0; endcase endmodule Listing 27 ISccsld: %G% Copyright 1997 Pioneer Digital Design Centre Limited module avg_8 (elk, resync, symbol, in-data, avg out); parameter phase-width 12; input clk, resync, symbol; input [phase-width-2:0] in data; output [phase-width-2:0) avg_out; reg [phase-width-2:0] avg out; reg [phase-width-2:0] store [7:01; wire [phase width-2:0] store7 store[7]; wire [phase width-2:0] store6 store[6]; wire [phase-width-2:0] store5 wire [phase-width-2:0] store4 store[4]; wire [phase width-2:0] store3 store[3]; wire [phase width-2:0] store2 store[2]; wire [phase-width-2:0] storel store[1]; wire [phase width-2:0] store0 store[0]; WO098/19410 PCTJUS97/1891 1 250 wire [phase-width+1 sum ({store 7[p hase width-2], store7[phase width-2], store7[phase width-2], store7} {store6[phase-width-21, store6[phase-width-2], store6[phase-width-2], store6} {store5[phase-width-2], store5[phase-width-2], store5[phase-width-2], {store4[phase-width-2], store4[phase-width-2], store4[phase -width-2], store4} {store3[phase-width-2], store3[phase-width-2], store3f phase -width-2], store3} {store2[phase-width-2], store2[phase-width-2], store2[phase -width-2], store2) {store 1 [phase-width-2], store 1 [phase-width-2], storel1[phase -width-2], storelI {storeO[phase-width-2], storeO[phase-width-2], store0[phase-width-2], store0}); always (posedge cik) begin if (resync) begin store[7] 0; store[6] 0; 0; store[4] 0; store[3] 0; store[2] 0;store[1] 0; store[0] 0; avg-out 0; end else if (symbol) begin store[7] store[6]-; store[6] store[4]; store[4] store(3]; store[3] store[2]; store[2] storef 1]; store[1] store[0];store[0] in-data; avg-out sum 3; end end endmodule Listing 28 ISccsld: %G% Copyright 1997 Pioneer Digital Design Centre Limited module twowire26 (clk, rst, in-valid, din, out-accept, out-valid, in_accept, WO 98/19410 PCT/US97/18911 251 dout, set); input clk, rst, set, in_valid, outaccept; input [25:0] din; output in_accept, out_valid; output [25:0] dout; reg in_accept, out_valid, acc_int, acc_intreg, in_valid_reg, val_int; reg [25:0] dout, din_reg; always (posedge clk) begin if (rst) out_valid 0; else if (acc_int 1 set) out_valid val_int; if (in_accept) begin invalid_reg invalid; din_reg din; end if (acc_int) dout inaccept din din_reg; if (set) accint_reg 1; else acc intreg acc_int; end always (out_accept or out_valid or accint_reg or in valid or invalid_reg) begin acc int out_accept I !outvalid; inaccept acc int reg I !in_valid_reg; val int inaccept in valid: invalid_reg; end endmodule module buffer (clk, nrst, resync, u_symbol_in, ucpilot in, uidata_in, uq_data_in, u_symbol_out, uc_pilot_out, ui_data_out, uqdataout, got_phase); input clk, nrst, resync, u_symbol_in, uc_pilot in, got_phase; input [11:0] uidata_in, uq_datain; output u_symbol_out, uc_pilot out; output [11:0] ui data out, uq_data_out; reg u_symbolout, uc_pilotout, accept; wire u symbol_o, uc_piloto; reg [11:0] ui data out, uq_dataout; wire [11:0] uidata_o, uq_data_o; wire a, v; WO 98/19410 PCT[US97/18911 252 wire [25:0] d; wire- in -valid u symbol_in! uc-pilot-in; wire rst !nrst II resync; twowire26 twi (.clk(clk), .rst(rst), .in-valid(in-valid), .din({u-symbol_in, uc-pilot-in, ui-data-in, uq data .out accept(a), .out-valid(v), .in accepto, .dout(d), .set(1 10twowire26 tw2 (.clk(clk), .rst(rst), .in valid(v), .din(d), .out accept(accept), .out valid(out valid), .in_accept(a), .dout({u symbol o, uc~plto ul atao, uq data .set(1 _io -,u-aa always (u symbol-o or uc pilot o or ui-data a or uq_data-o or out-valid or accept) begin if (out -valid accept) begin u symbol_out u_symbol a; uc pilot out =uc pilot-a; ui-data-out =ui-data_o; uq data out uq data-o; endelse begin u symbol-out 0; uc-pilot -Out =0; ui data-outo0; uq-data-out =0; end end always (posedge clk) begin if (rst Igot-Phase) accept 1 else if (uc -pilot -out) accept 0; end endmodule Listing 29 HI Sccsld: %G% Copyright 1997 Pioneer Digital Design Centre Limited module divide (clk, go, numer, denom, answ, got); WO 98/19410 PCT/US97/18911 253 this divider is optimised on the principal that the answer will always be less than 1 ie denom numer input clk, go; input [10:0] numer, denom; output got; output [10:0] answ; reg got; reg [10:0] answ; reg [20:0] sub, internal; reg dcount; always (posedge clk) begin if (go) begin dcount 0; internal numer sub denom 9; end if (dcount 11) begin if (internal sub) begin internal internal sub; answ[10 dcount] 1; end else begin internal internal; answ[10 dcount] 0; end sub sub 1; dcount dcount 1; end got (dcount end endmodule Listing Sccsld: %G% Copyright 1997 Pioneer Digital Design Centre Limited module fserr_str (clk, nrst, resync, usymbol, uc_pilot, ui_data, uq_data, guard, WO 98/19410 PCT[US97/18911 254 freq sweep, sr-sweep, Iupdata, upaddr, upwstr, uprstr, upsell, upsel2, ram-di, te, tdin, freq_err, samp err, ram_rnw, ram-addr, ram-do, tdout); input cik, nrst, resync, u_symbol, uc-pilot, upwstr, uprstr, te, tdin, upsell, upsel2; input guard; input freq sweep, sr sweep, upaddr; input [11:01]ui_data, uqd-cfata; input [1370] ram do; output ram_mnw, tdout; output ram addr; output [12:0] freq__err, samp_err; output [13:0] ram di; inout lupdata; wire got-Phase, en, load, symbol, u-symbol buf, uc-pilot-buf; wire fmeq open, sample open; wire guard meg; wire [10:0] xcount; wire [11:0] ui_data_buf, uq_data_buf; wire [13:0] phase-in, phase-out; wire [20:0] acc -out -simple; wire [29:0] acc-out-prod; wire [12:0] freq erm uf, samp__err uf; wire [12:0] freq err -fil, samp_err-fil, freq _twiddle, sample-twiddle; buffer buffer (.clk(clk), nrst(nrst), resync(resync), u_symbol in(u symbol), .uc-pilot-in(uc-pilot), .ui_data_in(ui data), uq_data in(uq_data), u symbolout(usymbolbuf), .uc_pilot out(uc pilot buf, .ui data out(ui_data_buf), uq data out(uq data buf), .go phs- pae) tan taylor phase extr (.clk(clk), n rst(nrst), resync(resync), .uc-pilot(uc-pilotbu), .ui-data(ui data_buf), .uqdata(uqjdata_buf), .phase(phase in), .got phase(got phase)); addrgen addrgen (.clk(clk), resync(resync), u_symbol(u symbol_buf), uc-pilot(uc pilot buf), got-Phase(got-phase), .en(en), *load(load), .guard(guard), .addr(ram addr), .xcount(xcount), .guardreg(g uard reg), .symbol (symbol)); pilot-Store pilot-store (.clk(clk), .en(en), .ram_do(ram do), phase -in(phase ram_rnw(ramrnw), ramd i(ramdi), .phase-out(phase-out)); acc simple acc-simple (.clk(clk), resync(resync), .load (load), .symbol(symbol), new-Phase(phase-in), .oldjphase(ph-ase out), .acc-Out(acc-out -simple)); acc prod acc prod (.clk(clk), resync(resync), load(load), *symbol(symbol), .new -phase(phase in), old_phase(phase-out), .xcount(xcount), WO 98/19410 PCTIUS97/189 11 255 .acc Out(acc0 out- prod)); slow-arith slow arith (.acc-simple(acc-out-simple), .acc-prod(acc-out-prod), guard (guard reg), .freq err uf(freq e rr-uf), .samp__err-uf(samp err-uf)F; avg_8 #(14) lpffreq (.clk(clk), resync(resync), .symbol (symbol), in_data (freq err u4) avg out(f req err-fil)); avg_8 #(14) lpfsamp (.clk(clk), resync(resync), .symbol(symbol), .in-data(samp erruf), .avg_out(samp err-fl)); median-filter #(14) lIpffreq (.clk(clk), .nrst(nrst), .in -valid(symbol), *din(freq err uf), .dout(freq err-fil)); median-filter #(14) lpfsamp (.clk(clk), .nrst(nrst), in_valid (symbol), .din(samp err uf), .dout(samp err-fil)); sweep-twiddle sweep twiddle (.freq err -fi l(f req err fil), .samp err -fil(samp err -fil), .freq sweep (f req sweep), .sr -sweep(sr sweep), freq_open (freqo open), sample open(sample open), .freq -twiddle(freqtwiddle), .sample -twiddle(sample twiddile), .freqerr-out(freqerr), .samp err out(samp err)); lupidec lupidec -(.clk(clk), .nrst(nrst), .resync(resync), .upaddr(upaddr), .upwstr(upwstr), .uprstr(uprstr), .lupdata(iupdata), .freq_open(freq open), .sample -open(sample -open), .freq_twiddle(freq twiddle), sample twiddle(sample twiddle), sample loop bwo, .freq loop bwO, freq e rr(freq err), .samperr(samp_err), Lferr-updateo, .s_err-Updateo); endmodule HI Sccsld: Lsig3 Copyright 1997 Pioneer Digital Design Centre Limited module lupidec (clk, nrst, resync, upaddr, upwstr, uprstr, lupdata, freq open, sample -open, freq-twiddle, sample-twiddle, sample loop bw, freq loop_bw, freq err, samp err, f-err-update, s-err-update); input clk, nrst, resync, upwstr, uprstr, f err update, s-err-update; WO098/19410 PCTIUS97/1891 1 256 input upaddr;.

input [12:0] freq_err, samp err; inout lupdata; output freq_open, sample open; output [12:0] freq twiddle, sample-twiddle, sample loop bw, freq loop bw; reg freq__open, sample -open; reg [12:0] freq twiddle, sample-twiddle, sample loop bw, freq_loop bw; wire wr str; wire [3:06] wr -addr; wire wr_data; /*FOLDBEGINS 0 2 "address decode*/ /*FOLDBEGINS 0 0 "read decodeh"/ wire f err h-ren (upaddr 4'he); wire ferrI-ren =(upaddr 4'hf); wire s-err-h-ren =(upaddr 4'hc); wire s -err_-I -ren (upaddr 4'hd); wire f twd h ren =(upaddr 4'h4); wire f-twdI ren =(upaddr 4Mh); wire s-twd-h-ren =(upaddr wire s-twdlIren =(upaddr 4'h9); wire f lbw bren =(upaddr ==4Mh); wire f-lbwI ren =(upaddr 4Wh); wire s-lbw-h-ren =(upaddr 4'ha); wire s lbwlIren (upaddr 4'hb);

/*FOLDENDS*/

/*FOLDBEGINS 0 0 "write decode"~/ wire f twd h wen =(wr addr wire f-twd I -wen =(wr addr 4Mh); wire s twd h wen =(wr -addr 4Vh); wire s-twd I wen =(wr addr 4Mh); wire f lbw hFwen =(wr addr wire f-lbwl wen =(wr -addr 4Wh); wire s-lbw-h-wen =(wr addr 4'ha); wire s lbw I wen =(wr addr 4'hb);

/*FOLDENDS;*/

/*FOLDENDS*/

/*FOLDBEGINS 0 2 "upi regs"I*/ /*FOLDBEGINS 0 0 "freq error status reg"I upi-status_reg2 fr-err (.clk(clk), .nrst(nrst), .status value({3'bO, freq__err}), .capture strobe(f err -update), read_strobe(uprstr), reg_select_I (ferrlren), reg_select_h (Lerrhren), .lupdata(lupdata));

/*FOLDENDS*/

/*FOLDBEGINS 0 0 "sample error status reg"l/ upi-status_reg2 sr-err (.clk(clk), .nrst(nrst), .status value({3'b0, samperr}), .captu reStrobe(serr-u pd ate), read_strobe(up rstr), .reg_select l(s err I ren), *re9_select_h(serrhren),

/*FOLDENDS*/

WO 98/19410 PCTIUS97/18911 257 /*FOLDBEGINS 0 0 "control regs write latch"l/ upi write -latch write_lat (.clk(clk), .nrst(nrst), .lupdata(lupdata), .upaddr(upaddr), write -strobe(upwstr), .write_data(wr-data), .write add ress(wr add write-sync(wr-Str));

/*FOLDENDS*/

/*FOLDBEGINS 0 0 "freq twiddle etc rdbk regs"~*I upird bkreg freqj...upper (.control_value({freq oe, 2'bO, freq twidldle[1 2: read strobe(up rstr), reg_select(fUwdhren), .lupdata(Iupdata)); upirdbk-reg freqrlower (.control_value(freq__twidd Ie[7 read_strobe(uprstr), reg select(Ltwdlren), lupdata(lupdata));

/*FOLDENDS*/

/*FOLDBEGINS 0 0 "samp twiddle etc rdbk regsl*/ upirdbkreg samprupper (.control value({sa mple open, 2'bO, sample twiddle[1 S ead strobe(u prstr), reg select(stwdhren), *lupdata(lupdata)); upirdbk-reg samp_r_lower (.control value(sample-twiddle[7: read-strobe(uprstr), reg select(stwdlren), .1updata(lupdata)); /*FOLDENDS*/ /*FOLDBEGINS 0 0 "freq loop bw rdbk regs 9 upirdbkreg fr Ipr upper (.control value({3'bO, freq_loop bw[1 readsroeu rsrrgselect(flbw-hren), .lupdita(lupdata)); upirdbkreg fr lprlower (.control value(freq loop bw[7: read strobe(uprstr), .reg_select(Llbw-lren), *lupdata(lupdata));

/*FOLDENDS*/

/*FOLDBEGINS 0 0 "samp loop bw rdbk regs"I/ upirdbk-reg sr Ipr upper (.control value({3'bO, sample loop bw[ readstrobe(u prstr), reg selIect(slbwhren), .Iupdata(lupdata)); upirdbk-reg sr Ip r_lower (.control value(sample read !strobe(uprstr), regselect(slbw-lren), .lupdata(lupdata));

/*FOLDENDS*/

I*FO [DEN DS*I /*FOLDBEGINS 0 2 "control regsl*/ always (posedge clk) begin if (!nrst) begin freq open 0; sample-Open 0; WO 98/19410 W098/9410PCTIUS97/1891 1 258 freq twiddle 0; sample -twiddle 0; sample loop bw 0; freqloopbw 0; end else begin if (wr-str) begin if (f-twd -h wen) begin freq open wr data[7]; freqt widdle[1 2:81 end if (f twdlIwen) wr-data[7 if (s-twd-hwen) begin sample open wr data[7]; sample twiddle[12:8] end if (si- wdl-I-wen) sample twiddle[7:0] if (flbw-hwen) freq loop bw[1 2:8] if (flbwl-I-wen) freq loop_bw[7: 01 if (slbw-hwen) sample loop bw[1 2:8] if (slbwl-I-wen) sample loop bw[7: 0] wr data[7: 0]; end end end

/*FOLDENDS*/

endmodule Listing 32 HI Sccsld: %G% Copyright 1997 Pioneer Digital Design Centre Limited WO 98/19410 PCT/US97/18911 259 module pilotstore (clk, en, ramdo, phase_in, ram_rnw, ram_di, phase_out); input clk, en; //input addr; input [13:0] phase_in; input [13:0] ram_do; output ram_rnw; output [13:0] ram_di, phase_out; wire ram_rnw; reg en_dl; reg addrreg; //reg [13:0] mem [579:0]; reg [13:0] phase_out; phasein_reg; wire [13:0] ram_di; always (posedge clk) begin //en_dl en; if (en) begin phase in_reg phasein; addrreg addr; phase_out ram_do; I/ phase_out mem[addr]; end //if (en_dl) mem[addrreg] phase_in_reg; end assign ram_di phase_in; assign ramrnw !en; endmodule Listing 33 Sccsld: %G% Copyright 1997 Pioneer Digital Design Centre Limited module slow_arith (acc simple, acc_prod, guard, freq_err_uf, samp_erruf); input guard; input [20:0] acc_simple; input [29:0] acc_prod; output [12:0] freq_erruf, samp_erruf; reg [12:0] freq_erruf, samp erruf; reg [20:0] freq scale; reg [38:0] interfreq; WO 98/19410 WO 9819410PCTfUS97/18911 260 reg sign; reg [20:0] mod-acc; reg [38:0] mod 7trunc-sat; reg [41:0] mod; reg sign a, sign_b, sign inter-sr; reg [20:0] mod_acc_s; reg [29:0] mod_acc-p; reg [35:0] a, mod-a; reg [35:0] b, mod_b; reg [36:0] mod-dff, duff; reg [46:0] inter-sr, mod-inter-sr; parameter sp =45, acc-x 33927, samp scale= 1 V1'bl0lO0lO always (guard) case (guard) Z'OO: freq_scale =21'bOlll11010011l110001011; Iguard =64 2'bOl: freq_scale =21'bOll1101101110001000011; Iguard ==128 2'blO: freq_scale =21'bO110000010001110101; IIguard ==256 2'bl1: freq scale 21bO1001010000110011111;/guard 512 endcase always (acc simple or freq scale) begin sign acc mod -acc sign (-acc simple 1) acc_simple; mod (freq_scale mod- acc); /inter freq sign ?Q(-mod 1) mod; if (mod[41 :38] 0) begin mod trunc sat 39'h3fffffffff $display("fr-eq err saturated"); end else mod-trunc-sat mod[38:0]; inter-freq sign (-mod-trunc-sat mod-trunc-sat; freqerr-uf inter-freq 26; end always (acc simple or acc prod) begin sign a acc-prod[29]; mod -accj, sign a (-acc prod acc-prod; mod-a sp *mod-acc-p; a signa a? (-mod a 1) mod_a; signb mod -acc -s sign b (-acc simple 1) acc-simple; mod-b =acc-x WO 98/19410 PCTIUS97/18911 261 b signb b? (-mod_b 1) mod_b; duff a) sign extend sign inter sr diff[36]; mod -duff sign-intersr (-duff 1) duff; mod -inter-sr (mod-duff samp scale); inter-sr signintersr (-mod_inter-sr mod-inter-sr; samp -err -uf inter-sr 34; II! scaling!! end endmodule Lsig3 ISccsld: Lsig3 Copyright 1997 Pioneer Digital Design Centre Limited module sweep__twiddle (freq err -fil, samp err -fil, freq_sweep, sr -sweep, freqopen, sample open, freqjtwiddle, sample twiddle, freq err-out, samp err out); input freq open, sample -open; input freq sweep, sr -sweep; input [12:0] freq err fil, samp_err-fil, freq twiddle, sample-twiddle; output [12:0] freq err-out, samp err out; reg [12:0] freq err out, samp-err -out; reg [12:0] freq__err-swept, samp err swept; always (freq sweep or freq err fil) case (freq sweep) 4'bOOOO: freq err -swept freq err -fil; freq err -swept freq__err -fil 500; 4'bOOl10: freq err -swept freq_ err fil 1000; 4'bOO 11: freq err -swept freq err fil 1500; 4'bOl100: freq err -swept freq err fil 2000; 4'bOlOl: freq err -swept freq err -fil 2500; 4'bO 110: freqe err -swept freq -err -fil 3000; 4'bOl 11: freq err -swept freq -err -fil 3500; default: freq_err-swept freq-err il; endcase always (sr -sweep or samp err fil) case (sr sweep) 4'bOOOO: samp err -swept samp err fil; 4'b001: samp__.err-swept samp er~il 500; samperr swept samp__err~fil 500; 4'bOOll1: samnperr-swept samp err~fil 1000; 4'bOlOO: samperr swept samp err~fil 1000; samp~err -swept samp err-fil 1500; 4'bOll10: samperr swept samp err-fil 1500; 4'bOl 11: sam perr-swept samp err~fil 2000; WO 98/19410 PCT/US97/18911 262 4'b1000: samp err swept samp errfil 2000; default: samp_errswept samp_err fil; endcase always (freq_errswept or freq_open or freq_twiddle) if (freq_open) freq_errout freq_twiddle; else freq_errout freq_err_swept freq twiddle; always (samp_err_swept or sample_open or sample_twiddle) if (sample_open) samperr_out sample_twiddle; else samperrout samp_errswept sample_twiddle; endmodule Listing Sccsld: %G% Copyright 1997 Pioneer Digital Design Centre Limited module tan_taylor (clk, nrst, resync, uc_pilot, ui_data, uq_data, phase, got_phase); input clk, nrst, resync, uc_pilot; input [11:0] ui_data, uq_data; output got_phase; output [13:0] phase; reg got_phase; reg [13:0] phase; reg add, qgti, modqeqi, i_zero_reg, q_zero_reg, go; reg quadrant; reg count, count_dl; reg [10:0] mod_i, mod_q, coeff, numer, denom; reg [21:0] x_sqd, x_pow, next_term, sum, flip, next_term_unshift, prev_sum, x_sqd_unshift, x_powunshift; wire got; wire [10:0] div; parameter pi 6434, pi_over2 3217, minus_pio2 13167, pi_over4 1609; divide div1 (clk, go, numer, denom, div, got); always (posedge clk) begin if (!nrst I resync) count 7'b1111111; WO 98/19410 W098/9410PCT/US97/1891 1 263 else begin if (uc pilot) begin mod -i ui-data[l11]? (-ui data[1 :ui -data[1 0:0]; modq uq data[l11]? (-uq data[1 0:0] uq_data(1 quadrant {uq data[l1 ul data[1 1]} count 0; go 0; end else begin if (count 0) begin qgti (modq mod_i); modqeqi (modq mod i); _-zero -reg (modi 0); qzeroreg (modq 0); add 0; go 1; count 1; end if ((count 3) (count 71)) count count 2; if (count 1) begin go if (got) begin sum div; x-pow div; x-sqd xsqd_unshift 11; count 3;: end end if ((count 1) (count 69)) x-pow x-pow-unshift 11; if ((count 3) (count 69)) next-term next-term-unshift 12; if ((count 5) (count 69)) begin prey sum sum; sum add (sum next-term) :(sum next-term); add ladd; end end if (count 67) sum (prey sum sum) 1; if (count 69) casex ({i-zero_reg, q zero reg, qgti, modqeqi, quadrant})) 6'bl1xxO Ox: phase piover2; lx: phase minus-pi-o2; WO 98/19410 W09819410PCTIUS97/1891 1 264 phase 0; 6'bOlxO-xl: phase <=pi 6'b00 10_00: 6'b0010_01: 6'bOOlO_10: 6'b00 10_11: 6'bOOOO_00: 6'bOOOO_01: 6'bOOOO_1 0: 6'bOOOO_1 1: 6'bxxxl1_0 0: 6'bxxxl_01: 6'bxxxl_10: 6'bxxxl_1 1: endcase phase {2'b00, flip[1 1 phase pi {2'bOO, flip[1 1 phase 0 {2'bOO, flipfl 1 phase {2'bOO, flip[1 1 pi; phase phase phase phase {2'bOO, sum[1 1:0]1; pi {2'bOO, sum[1 1 0 {2'bOO, sum[1 1 {2'bOO, sum[1 1 pi; phase piover4; phase pi piover4; phase 0 pi_over4; phase piover4 pi; count-dl count; got -phase (count 69); end end always (dlv) x-sqd-unshift div *div; had to do this in order to stop synthesis throwing away! always (xpow or coeff) next-term-unshift (xpow coeff); compass dp cell mult-booth-csum always (xpow or xsqd) xpow-unshift (xpow x-sqd); always (count dl) case (count -d1) 3: coeff 11'b10101010101; coeff 1 1'bOll100110011; 7: coeff 11'bMlO0lO0lO0l; 9: coeff 1 1'bOOll11000111; 11: coeff =1 1'b001 011101001 13: coeff 11l'bOOlO01l11011; coeff 11l'bOOlOO01l0001; 17: coeff 1 1'bOO01l111000l; 19: coeff 1 1'bOO01l1010111; 2 1: coeff 1 1'bOOOl110000l1; 23: coeff 1 1'bOOOl10l1100l1; coeff 1 1'bOOOl10l1000 11; 27: coeff 1 1'bOOOl100l10l11; 29: coeff 1 1'bOOOl1000l110l; 3 1: coeff 1 1'bOOOl10000l10; 33: coeff 1 1'bOOO01l111100; coeff 1 1'bOOOOl11l0 37: coeff 1 1'bOOOOl110l111; 39: coeff 1 1'bOOOO 110l100l; 4 1: coeff 1 1'bOOOOl1100l10; 43: coeff 1 1'bOOOOl10l1111; HI compass dp cell mult-booth-csum WO 98/19410 WO 9819410PCT/US97/1891 1 265 47: 49: 51: 53: 57: 59: 61: 63: //67 //69 //71 //73 75 //77 coeff =11'bOOO01l011011; coeff 11'bOOO0l0l0lll; coeff 1 1'b0000 10 100 11; coeff 11 'bOO0l 010000; coeff 11'bOOO0lO0ll0l; coeff 11'bOOO0lO0l0lO; coeff 11'bOOO0lOO0lll; coeff 11'bOOO0lOO0l0l; coeff 1 1'bOOO0l 000011; coeff 11 'bOOl 000001; coeff 11l'bOOOO01l11111; coeff =1 1'bOOOOOl11110l; coeff 1 1'bOOOOOl1110l1; coeff 11'bOOOO0lllO0l; coeff 1 1'bOOOOOl11100; coeff 1 1'bOOOOOl110l11; coeff 1 1'bOOOOOl110l10l; default: coeff 1 1'bx; endcase always (modq or mod-i or qgti) begin numer =qgti mod-i mod-q; denom =qgti mod_q mod_i end always (sum) flip piover2 sum; HI always (got) I/if (got) HI $display('numer was denom was div then numer, denom, div); HI always (count) I/if (count 68 $display("as far as x to the %Od term, approx (count-6), sum); always (gotphase) begin: display reg (13:0] real phase; if (phase[1 3]) begin real phase (-phase 1); if (got ~phase) $display("%t: got phase, phase $time, real phase); end else begin if (got-Phase) $display("%t: got phase, phase $time, phase); end end HI display endmod ule P:\OPERXDBWM5147-98 spmi.dmc-19 Oober. 2000 266 While this invention has been explained with reference to the structure disclosed herein, it is not confined to the details set forth and this application is intended to cover any modifications and changes as may come within the scope of the claims.

Throughout this specification and the claims which follow, unless the context requires otherwise, the word "comprise", and variations such as "comprises" and "comprising", will be understood to imply the inclusion of a stated integer or step or group of integers or steps but not the exclusion of any other integer or step or group of integers or steps.

The reference to any prior art in this specification is not, and should not be taken as, an acknowledgment or any form of suggestion that that prior art forms part of the common general knowledge in Australia.

Claims (32)

1. A digital receiver for multicarrier signals comprising: an amplifier accepting an analog multicarrier signal, wherein said multicarrier signal comprises a stream of data symbols having a symbol period T S wherein the symbols comprise an active interval, a guard interval, and a boundary therebetween, said guard interval being a replication of a portion of said active interval; an analog to digital converter coupled to said amplifier; an I/Q demodulator for recovering in phase and quadrature components from data sampled by said analog to digital converter; an automatic gain control circuit coupled to said analog to digital converter for providing a gain control signal for said amplifier; a low pass filter circuit accepting I and Q data from said I/Q demodulator, wherein said I and Q data are decimated; a resampling circuit receiving said decimated I and Q data at a first rate and outputting resampled I and Q data at a second rate; an FFT window synchronization circuit coupled to said resampling circuit for locating a boundary of said guard interval; a real-time pipelined FFT processor operationally associated with said FFT window synchronization circuit, wherein said FFT processor comprises at least one S: stage, said stage comprising: a complex coefficient multiplier; and a memory having a lookup table defined therein for multiplicands being multiplied in said complex coefficient multiplier, a value of each said multiplicand being unique in said lookup table; and a monitor circuit responsive to said FFT window synchronization circuit for 25 detecting a predetermined event, whereby said event indicates that a boundary between an active symbol and a guard interval has been located.

2. The receiver according to claim 1, wherein said FFT window synchronization circuit comprises: a first delay element accepting currently arriving resampled I and Q data, and outputting delayed resampled I and Q data; a subtracter, for producing a difference signal representative of a difference between said currently arriving resampled I and Q data and said delayed resampled I and Q data; WO 98/19410 PCT/US97/18911 268 8 a first circuit for producing an output signal having a unipolar magnitude that is 9 representative of said difference signal of said subtracter; a second delay element for storing said output signal of said first circuit; 11 a third delay element receiving delayed output of said second delay element; and 12 a second circuit for calculating a statistical relationship between data stored in 13 said second delay element and data stored in said third delay element and having an 14 output representative of said statistical relationship. 1 3. The receiver according to claim 2, wherein said statistical relationship 2 comprises an F ratio. 1 4. The receiver according to claim 1, wherein said FFT processor operates in an 2 8K mode. 1 5. The receiver according to claim 1, wherein said wherein said FFT processor 2 further comprises an address generator for said memory, said address generator 3 accepting a signal representing an order dependency of a currently required multipli- 4 cand, and outputting an address of said memory wherein said currently required multiplicand is stored. 1 6. The receiver according to claim 5, wherein each said multiplicand is stored in 2 said lookup table in order of its respective order dependency for multiplication by said 3 complex coefficient multiplier, said order dependencies of said multiplicands defining an 4 incrementation sequence, and said address generator comprises: an accumulator for storing a previous address that was generated by said 6 address generator; 7 a circuit for calculating an incrementation value of said currently required 8 multiplicand; and 9 an adder for adding said incrementation value to said previous address. 1 7. The receiver according to claim 6, wherein said lookup table comprises a 2 plurality of rows, and said incrementation sequence comprises a plurality of 3 incrementation sequences, said multiplicands being stored in row order, wherein 4 in a first row a first incrementation sequence is O; in a second row a second incrementation sequence is 1; 6 in a third row first and second break points B1, B2 of a third incrementation 7 sequence are respectively determined by the relationships WO 98/19410 PCT/US97/18911 269 8 8 N-1 Bi MN 4NB1iN E 4 n n=O 9 9 N B 2 M N E4 n n=O ;and 11 in a fourth row a third break point B3 of a third incrementation sequence is 12 determined by the relationship 13 13 B3MN 2 x 4 N 2 MN 14 wherein MN represents the memory of an Nth stage of said FFT processor. 1 8. The receiver according to claim 1, further comprising channel estimation and 2 correction circuitry comprising: 3 pilot location circuitry receiving a transformed digital signal representing a frame 4 from said FFT processor for locating pilot carriers therein, wherein said pilot carriers are spaced apart in a carrier spectrum of said transformed digital signal at intervals K and 6 have predetermined magnitudes, said pilot location circuitry comprising: 7 a first circuit for computing an order of carriers in said transformed digital signal 8 modulo K; 9 K accumulators coupled to said second circuit for accumulating magnitudes of said carriers in said transformed digital signal, said accumulated magnitudes defining 11 a set; and 12 a correlation circuit for correlating K sets of accumulated magnitude values with 13 said predetermined magnitudes, wherein a first member having a position calculated 14 modulo K in each of said K sets is uniquely offset from a start position of said frame. 1 9. The receiver according to claim 8, wherein said pilot location circuitry further 2 comprises a bit reversal circuit for reversing a bit order of said transformed digital signal. 1 10. The receiver according to claim 7, wherein said magnitudes of said carriers 2 and said predetermined magnitudes are amplitudes. 1 11. The receiver according to claim 7, wherein said magnitudes of said carriers 2 and said predetermined magnitudes are absolute values. WO 98/19410 PCT/US97/18911 270 1 12. The receiver according to claim 7, wherein said correlation circuitry further 2 comprises a peak tracking circuit for determining a spacing between a first peak and a 3 second peak of said K sets of accumulated magnitudes. 1 13. The receiver according to claim 7, wherein said channel estimation and 2 correction circuitry further comprises: 3 an interpolating filter for estimating a channel response between said pilot 4 carriers; and a multiplication circuit for multiplying data carriers output by said FFT processor 6 with a correction coefficient produced by said interpolating filter. 1 14. The receiver according to claim 7, wherein said channel estimation and 2 correction circuitry further comprises 3 a phase extraction circuit accepting a data stream of phase-uncorrected I and Q 4 data from said FFT processor, and producing a signal representative of a phase angle of said uncorrected data, said phase extraction circuit including an accumulator for 6 accumulating the phase angles of succeeding phase-uncorrected I and Q data. 1 15. The receiver according to claim 14, said channel estimation and correction 2 circuitry further comprises: 3 an automatic frequency control circuit coupled to said phase extraction circuit 4 and said accumulator, comprising; a memory for storing an accumulated common phase error of a first symbol 6 carried in said phase-uncorrected I and Q data; 7 wherein said accumulator is coupled to said memory and accumulates a 8 difference between a common phase error of a plurality of pilot carriers in a second 9 symbol and a common phase error of corresponding pilot carriers in said first symbol; an output of said accumulator being coupled to said I/Q demodulator. 1 16. The receiver according to claim 15, wherein said coupled output of said 2 accumulator is enabled in said I/Q demodulatoronly during reception of a guard interval 3 therein. 1 17. The receiver according to claim 14, said channel estimation and correction 2 circuitry further comprises an automatic sampling rate control circuit coupled to said 3 phase extraction circuit, comprising: WO 98/19410 PCT/US97/18911 271 4 a memory for storing accumulated phase errors of pilot carriers in a first symbol carried in said phase-uncorrected I and Q data; 6 wherein said accumulator is coupled to said memory and accumulates 7 differences between phase errors of pilot carriers in a second symbol and phase errors 8 of corresponding pilot carriers in said first symbol to define a plurality of accumulated 9 intersymbol carrier phase error differentials, a phase slope being defined by a difference between a first accumulated intersymbol carrier phase differential and a second 11 accumulated intersymbol carrier phase differential; 12 an output of said accumulator being coupled to said I/Q demodulator. 1 18. The receiver according to claim 17, wherein said sampling rate control circuit 2 stores a plurality of accumulated intersymbol carrier phase error differentials and 3 computes a line of best fit therebetween. 1 19. The receiver according to claim 17, wherein said coupled output signal of said 2 accumulator is enabled in said resampling circuit only during reception of a guard 3 interval therein. 1 20. The receiver according to claim 17, wherein a common memory for storing 2 output of said phase extraction circuit is coupled to said automatic frequency control 3 circuit and to said automatic sampling rate control circuit. 1 21. The receiver according to claim 14, wherein said phase extraction circuit 2 further comprises: 3 a pipelined circuit for iteratively computing the arctangent of an angle of rotation 4 according to the series X 3 X 5 X 7 X 9 tan-l(x) x- Ixl<1 3 5 7 9 6 wherein x is a ratio of said phase-uncorrected I and Q data. 1 22. The receiver according to claim 21, wherein said pipelined circuit comprises: 2 a constant coefficient multiplier; and 3 a multiplexerfor selecting one of a plurality of constant coefficients of said series, 4 an output of said multiplexer being connected to an input of said constant coefficient multiplier. WO 98/19410 PCT/US97/18911 272 1 23. The receiver according to claim 21, wherein said pipelined circuit comprises: 2 a multiplier; 3 a first memory for storing the quantity x 2 said first memory being coupled to a 4 first input of said multiplier; a second memory for holding an output of said multiplier; and 6 a feedback connection between said second memory and a second input of said 7 multiplier. 1 24. The receiver according to claim 21, wherein said pipelined circuit further 2 comprises: 3 a third memory for storing a value of said series; 4 a control circuit, coupled to said third memory, wherein said pipeline circuit computes N terms of said series, and said pipeline circuit computes N+1 terms of said 6 series, wherein N is an-integer; 7 an averaging circuit coupled to said third memory for computing an average of 8 said N terms and said N+1 terms of said series. 1 25. The receiver according to claim 1, wherein data transmitted in a pilot carrier 2 of said multicarrier signal is BCH encoded according to a code generator polynomial 3 further comprising: 4 a demodulator operative on said BCH encoded data; an iterative pipelined BCH decoding circuit, comprising: 6 a circuit coupled to said demodulator for forming a Galois Field of said 7 polynomial, and calculating a plurality of syndromes therewith; 8 a plurality of storage registers, each said storage register storing a 9 respective one of said syndromes; a plurality of feedback shift registers, each said feedback shift register 11 accepting data from a respective one of said storage registers and having an 12 output; 13 a plurality of Galois field multipliers, each said multiplier being connected 14 in a feedback loop across a respective one of said feedback shift registers and multiplying the output of its associated feedback shift register by an alpha value 16 of said Galois Field; 17 an output Galois field multiplier for multiplying said outputs of two of said 18 feedback shift registers; WO 98/19410 PCT/US97/18911 273 19 an error detection circuit connected to said feedback shift registers and said output Galoisfield multiplier, wherein an ouput signal of said error detection 21 circuit indicates an error in a current bit of data; and 22 a feedback line enabled by said error detection circuit and connected to 23 said storage registers, wherein outputs of said feedback shift registers are written 24 into said storage registers. 1 26. The receiver according to claim 25, wherein said output Galois field multiplier 2 comprises: 3 a first register initially storing a first multiplicand A; 4 a constant coefficient multiplier connected to said register for multiplication by a value a, an output of said constant coefficient multiplier being connected to said first 6 register to define a first feedback loop, whereby in a kth cycle of clocked operation said 7 first register contains a Galois field product Aak; 8 a second register for storing a second multiplicand B; 9 an AND gate connected to said second register and to said output of said constant coefficient multiplier; 11 an adder having a first input connected to an output of said AND gate; 12 an accumulatorconnected to a second input of said adder; wherein an output of 13 said adder is connected to said accumulator to define a second feedback loop; 14 whereby a Galois field product AB is output by said adder. 1 27. A method for estimation of a frequency response of a channel, comprising the 2 steps of: 3 receiving from a channel a multicarrier signal having a plurality of data carriers 4 and scattered pilot carriers, said scattered pilot carriers being spaced apart at a first interval N and being transmitted at a power that differs from a transmitted power of said 6 data carriers; 7 converting said multicarrier signal to a digital representation thereof; 8 performing a Fourier transform on said digital representation of said multicarrier 9 signal to generate a transformed digital signal; reversing a bit order of said transformed digital signal to generate a bit-order 11 reversed signal; S12 cyclically accumulating magnitudes of carriers in said bit-order reversed signal 13 in N accumulators; 14 correlating said accumulated magnitudes with said power of said scattered pilot carriers; WO 98/19410 PCT/US97/18911 274 16 responsive to said step of correlating, generating a synchronizing signal that 17 identifies a carrier of said multicarrier signal. 1 28. The method according to claim 27, wherein said step of accumulating 2 magnitudes comprises the steps of: 3 adding absolute values of a real component of said bit-order reversed signal to 4 respective absolute values of imaginary components thereof to generate sums; respectively storing said sums in said accumulators. 1 29. The method according to claim 27, wherein said step of correlating said 2 accumulated magnitudes further comprises the step of: 3 identifying a first accumulator having a highest value stored therein representing 4 a first carrier position. 1 30. The method according to claim 29, wherein said step of correlating said 2 accumulated magnitudes further comprises the steps of: 3 identifying a second accumulator having a second highest value stored therein 4 representing a second carrier position; and determining an interval between said first carrier position and said second carrier 6 position. 1 31. The method according to claim 27, further comprising the steps of: 2 comparing a position of a carrier of a first symbol in said bit-order reversed signal 3 with a position of a carrier of a second symbol therein. 1 32. The method according to claim 27, further comprising the steps of: 2 interpolating between pilot carriers to determine correction factors for respective 3 intermediate data carriers disposed therebetween; and 4 respectively adjusting magnitudes of said intermediate data carriers according to said correction factors. 1 33. The method according to claim 27, further comprising the steps of: 2 determining a mean phase difference between corresponding pilot carriers of 3 successive symbols being transmitted in said transformed digital signal; and 4 generating a first control signal responsive to said mean phase difference; and responsive to said first control signal adjusting a frequency of reception of said 6 multicarrier signal. P:\OPER\DBW\51471-98 speci.doe-19 Octobr 2000O

34. The method according to claim 33, further comprising the steps of: determining a first phase difference between a first data carrier of a first symbol in said transmitted data carrier and said first data carrier of a second symbol therein; determining a second phase difference between a second data carrier of said first symbol and said second data carrier of said second symbol; and determining a difference between said first phase difference and said second phase difference to define a phase slope between said first data carrier and said second data carrier; generating a second control signal responsive to said phase slope; and responsive to said second control signal adjusting a sampling frequency of said multicarrier signal. The method according to claim 34, wherein said step of determining a difference between said first phase difference and said second phase difference comprises computing a line of best fit.

36. A modulated multicarrier receiver comprising: a demodulator accepting digitized data representing modulated multicarrier symbols; carrier recovery circuitry; a microprocessor interface; a Viterbi decoder; channel estimation circuitry; an FFT processor; wherein the multicarrier receiver produces an output comprising demodulated video data; and wherein the multicarrier receiver is implemented in a single chip.

37. The receiver of claim 36 wherein the output complies with a digital video standard. PNOPERDBWU547 1 98 Speci.doc-19 Ocobe. 2000 276

38. The receiver of claim 36 wherein the produced output comprises MPEG compliant video data.

39. The receiver of claim 38 wherein the demodulator demodulates COFDM symbols. The receiver of claim 39 wherein the produced output comprises MPEG-2 compliant video data.

41. The receiver of claim 36 further comprising: an I/Q demodulator; timing recovery circuitry; a reed-solomon decoder; a symbol deinterleaver; 15 a clock source for controlling an analog-to-digital converter; and an automatic gain control signal generator.

42. The receiver of claim 36 wherein recovered carriers from the carrier recovery circuitry that fail to meet predetermined quality standards are ignored by 20 the Viterbi decoder.

43. The receiver of claim 42 wherein the recovered carriers have an interpolated channel response and wherein the predetermined quality standard is a function of the interpolated channel response.

44. The receiver of claim 36 wherein the carriers failing to meet a defined strength threshold are flagged; and wherein the Viterbi decoder is used to decode data from flagged carriers.

45. The receiver of claim 44 wherein the strength threshold is. 0.2 of a 7 Z. detected mean value. P\OPEXDBMS1471.99 spei.doc-19 October, 2000 277

46. The receiver of claim 44 wherein the strength threshold is varied through the microprocessor interface.

47. A receiver for receiving modulated symbols that have an active interval and a guard interval separated by a boundary, the receiver having a guard interval detector comprising: a measurement block; a delay block, the delay being approximately equal to the active interval; a subtractor generating a difference sample corresponding to the difference in measured signal strength between a first symbol and a second delayed symbol; a storage block storing N difference samples; a processing block applying a mathematical operation to the stored N difference samples.

48. The receiver of claim 47 wherein the processing block performs a statistical analysis.

49. The receiver of claim 47 wherein the delay block comprises 20 addressable RAM.

50. The receiver of claim 47 wherein the delay block comprises a FIFO.

51. The receiver of claim 47 wherein the processing block comprises a dispersion measurement.

52. The receiver of claim 47 wherein the guard interval detector measures a first dispersion over a first block of N difference samples and a second dispersion over a second block of N difference samples, the first and second block of difference samples being separated by at least one sample. P:\OPERIDBVW51471-98 speci.doc-19 October, 2000 278

53. The receiver of claim 52 wherein the first and second blocks of difference samples are not contiguous.

54. The receiver of claim 52 wherein the guard interval detector generates a signal based on a statistical relationship between the two dispersion calculations, the statistical relationship having a known probability function. The receiver of claim 54 wherein the probability function is an F ratio.

56. The receiver of claim 52 wherein the dispersion calculations are submitted to a peak detector having statistical tests of significance. 0000*

57. The receiver of claim 36 further comprising a synchronizer that synchronizes to a signal having an active interval and a guard interval, the 15 synchronizer comprising: a first digital delay of period L; a subtractor coupled to the input and output of the digital delay; unipolar output coupled to the output of the subtractor; an adder/subtractor coupled to the unipolar output; 20 a second digital delay of period M coupled to the adder/subtractor.

58. The receiver of claim 57 wherein the synchronizer further comprises a RAM storing logarithm lookup tables, the lookup tables being addressed as a function of the output of the adder/subtractor.

59. The receiver of claim 36 further comprising a synchronizer that synchronizes to a signal having an active interval and a guard interval, the synchronizer comprising a digital delay having an input and an output defining a synchronizing interval, the synchronizer having an acquisition mode with a first synchronizing interval and a tracking mode with a second synchronizing interval, the first and second intervals being unequal. P:\OPER\DBW l471-98 Spedodoc-19 October, 2000 279 The receiver of claim 59 wherein the FFT processor has an FFT window and wherein the first synchronizing interval is equal to the FFT window.

61. The receiver of claim 60 wherein the second synchronizing interval is smaller than the FFT window.

62. The receiver of claim 59 wherein memory allocated to the FFT processor during FFT calculations is allocated to the synchronizer during synchronization.

63. The receiver of claim 59 wherein the synchronizer further comprises: a correlator having an input coupled to the input and output of the digital delay and output coupled to a peak detector, wherein the peak detector generates an output when the output of the correlator exceeds a threshold.

64. The receiver of claim 36 wherein the receiver has a synchronizer that detects boundaries of received symbols, the synchronizer comprising: a threshold detector; a statistical peak detector; wherein the synchronizer's choice between the threshold detector and the statistical peak detector is a function of the signal to noise ratio of the received signal.

65. The receiver of claim 36 wherein the FFT processor comprises constant coefficient multipliers and multiplexers.

66. The receiver of claim 36 wherein the FFT processor performs a radix 2A2A+2 FFT.

471-98 spmi.doc-l9 OdobC. 2000 280 67. The receiver of claim 36 wherein the FFT processor comprises: RAM storing FFT coefficients; and an address generator mapping addresses of redundant entries onto a single address. 68. The receiver of claim 67 wherein the FFT processor has a predefined breakpoint and wherein the address generator maps an address above the breakpoint onto an address below the breakpoint. 69. The receiver of claim 68 wherein the FFT processor has a plurality of .breakpoints, each breakpoint defining a change in an address increment for the FFT processor. j 9 15 70. The receiver of claim 67 wherein the RAM stores a power of four table. 71. A method of processing a modulated multicarrier signal comprising: receiving digitized data representing modulated multicarrier symbols comprising an active interval and a guard interval; passing the received data through an 1/Q demodulator; synchronising an FFT window to the active interval; performing an FFT on the active interval; estimating the channel characteristics; producing an output comprising unmodulated digitized video data corresponding to the received modulated multicarrier signal; and wherein the passing, synchronising, performing, applying, estimating, and producing are performed within a single chip. 72. The method of claim 71 wherein the producing produces an MPEG encoded output. PAOPER\DBW'31471-98 spwi.doc.I9 Oclbe. 281 73. The method of claim 71 further comprising: extracting pilot carriers from the received digitized data; determining phase differences in the pilot carriers; applying feedback to the I/Q demodulation as a function of the determined phase differences in the pilot carriers. 74. A method for synchronizing an FFT window to a modulated multicarrier signal having symbols comprising: choosing a pair of blocks of symbols; measuring a characteristic of a first symbol of a first block of the pair; measuring a characteristic of a first symbol of a second block of the pair; determining the difference between the first symbol of the first block and the first symbol of the second block; 15 repeating the measuring steps and the determination step for successive symbols in each block; and applying a statistical test to the determined differences between the first and second blocks. 20 75. The method of claim 74 wherein the statistical test is an F ratio test. 76. The method of claim 74 further comprising: choosing a second pair of blocks; performing the measuring, determining, repeating, and applying on the second pair. 77. A method for synchronizing an FFT window to a modulated multicarrier signal having symbols comprising: receiving a digital signal corresponding to the multicarrier signal; producing a delayed signal by delaying the received signal by L symbols; determining the difference between the delayed signal and the received P:\OPERDBW\51471-98 spci doc-19 October. 2(000 282 signal and producing a difference signal; delaying the difference signal by N symbols; inputting the difference signal and the delayed difference signal into an adder/subtractor; delaying the output of the adder/subtractor; feeding back the delayed output of the adder/subtractor as an additional input into the adder/subtractor. 78. A method for synchronizing an FFT window to a modulated multicarrier signal having symbols comprising: receiving a digital signal corresponding to the multicarrier signal; delaying the digital signal producing a delayed; i" correlating the delayed signal to the received signal; accessing data in a lookup table stored in memory as a function of the 15 correlating. 79. A method for synchronizing an FFT window to a modulated multicarrier signal having symbols comprising: receiving a digital signal corresponding to the multicarrier signal; 20 measuring the signal to noise ratio of the digital signal; choosing a synchronization technique of a plurality of synchronization techniques as a function of the measured signal to noise ratio. The method of claim 79 wherein the plurality of techniques comprising use of a threshold detector and alternatively use of a statistical peak detector. 81. A digital receiver substantially as hereinbefore described with reference to the drawings. 71.98 speci.doc-19 OctobC, 283 82. A method substantially as hereinbefore described with reference to the drawings. 83. A modulated multicarrier receiver substantially as hereinbefore described with reference to the drawings. DATED this 19th day of October 2000 Discovision Associates By its Patent Attorneys DAVIES COLLISON CAVE *e oeoo o