EP0931347A1 - Memoire a semiconducteurs integree avec electrode a plaque enterree - Google Patents

Memoire a semiconducteurs integree avec electrode a plaque enterree

Info

Publication number
EP0931347A1
EP0931347A1 EP97912027A EP97912027A EP0931347A1 EP 0931347 A1 EP0931347 A1 EP 0931347A1 EP 97912027 A EP97912027 A EP 97912027A EP 97912027 A EP97912027 A EP 97912027A EP 0931347 A1 EP0931347 A1 EP 0931347A1
Authority
EP
European Patent Office
Prior art keywords
electrode
source region
semiconductor body
memory arrangement
semiconductor memory
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP97912027A
Other languages
German (de)
English (en)
Inventor
Günther SCHINDLER
Carlos Mazure-Espejo
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Infineon Technologies AG
Original Assignee
Siemens AG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Siemens AG filed Critical Siemens AG
Publication of EP0931347A1 publication Critical patent/EP0931347A1/fr
Withdrawn legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/37—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells the capacitor being at least partially in a trench in the substrate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B53/00—Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors

Definitions

  • the invention relates to an integrated semiconductor memory arrangement which consists of a multiplicity of memory cells of the same type, each having the following features:
  • a selection transistor having a drain region, a source region and a gate
  • the source region and the drain region are arranged in a semiconductor body, the gate in an insulation layer arranged above the semiconductor body;
  • a storage capacitor which has a first electrode, a second electrode and a storage dielectric arranged between the two electrodes;
  • the first electrode is conductively connected to the source region of the selection transistor
  • the second electrode is conductively connected to a common plate which is located below the source region
  • Such a memory arrangement is known from DE 38 40 559 AI.
  • the memory arrangement described there has a NEN storage capacitor arranged below a source region, which is conductively connected to the source region with a first electrode.
  • a second electrode of the storage capacitor is connected to a common plate, which is arranged below the source region.
  • DE 39 31 381 AI describes a memory arrangement with switching elements arranged in a substrate below selection transistors. These switching elements can be designed, for example, as memory capacitors, which are connected with a first electrode to a source region of a selection transistor and with a second electrode to a common plate designed as a buried wiring level.
  • a memory arrangement which has a number of selection transistors, each of which is connected to a source region with a first electrode of a storage capacitor.
  • the storage capacitor is located in a substrate below the source region, the second electrode of the source region is formed by a conductive substrate region which is electrically insulated from the source region.
  • US 53 09 008 describes a memory arrangement with a number of selection transistors, each of which has a source region which is connected to a first electrode of a storage capacitor.
  • the storage capacitors are located in a substrate in which the source regions are also arranged.
  • a second electrode of the storage capacitors is connected to a common plate arranged below the source regions.
  • a disadvantage of the known memory arrangements is the spatial arrangement of the storage capacitors, which must be manufactured during the manufacturing process before the selection transistors are manufactured. Especially with the Using special memory dielectrics, such as ferroelectric memory dielectrics, these memory dielectrics can contaminate the semiconductor process used to manufacture the selection transistors.
  • the aim of the invention is to provide a semiconductor memory device in which additional space is available on the first main surface for wiring, in which the above-mentioned problems in particular do not arise and which can be easily produced using known methods. Furthermore, the aim of the invention is to specify a method for producing such a semiconductor memory arrangement.
  • the storage capacitor is arranged on side surfaces of a cutout in the insulation layer above the source region.
  • the semiconductor memory arrangement described it is possible in a simple manner to use prefabricated arrangements from selection transistors for producing the memory arrangement.
  • the production of the storage capacitors can take place spatially distant from the production of the selection transistors; The risk of contamination of the semiconductor process used to manufacture the selection transistors is thus avoided.
  • WeicerbiiPHgen of the invention are the subject of the dependent claims.
  • ferroelectric materials are used as the storage dielectric.
  • Ferroelectric materials of this type offer the advantage that those in the form of electrical charge in the memory stored information is retained after the loss of a supply voltage or that the information does not have to be refreshed at regular intervals, which is necessary in conventional semiconductor memory devices that use a dielectric with paraelectric properties due to leakage currents occurring.
  • ferroelectric properties of most of the previously known ferroelectric materials that are suitable for such storage dielectrics are temperature-dependent. These ferroelectric materials behave ferroelectrically below a temperature which is characteristic of them, while they behave paraelectrically above this characteristic temperature, the dielectric constant in the paraelectric state being substantially higher than the dielectric constant of previously used storage dielectrics.
  • the temperature below which ferroelectric properties are established is very low in some ferroelectric materials, so that from a technical point of view the use of these ferroelectric materials is only possible in the paraelectric state, the dielectric constant of which in the paraelectric state is in each case more than 10, preferably more than Is 100.
  • the storage dielectric has a dielectric constant greater than 10.
  • Materials for such storage dielectrics are, for example, the ferroelectric materials mentioned above, which are used above the temperature that is characteristic of them.
  • the storage dielectric is an oxidic dielectric.
  • the class of oxidic dielectrics includes, for example, SBTN SrBi 2 (Ta 1 _ ⁇ Nb ⁇ ) 2 0 9 , SBT SrBi 2 Ta 2 0 9 , PZT (Pb, Zr) Ti0 3 , BST
  • the formula (Pb, Zr) Ti0 3 stands for Pb x Zr 1 _ ⁇ Ti0 3 .
  • the proportion of Pb and Zr in this substrate may vary, where the ratio of Pb and Zr, the temperature behavior of this dielectric significantly determ m t, that is, determines the temperature below which the substrate ferro- electrical properties or above which the substrate has paraelectric properties.
  • the formula (Ba, Sr) Ti0 3 stands for Ba x Sr 1 _ ⁇ Ti0 3 , with this substrate
  • Temperature behavior can be significantly determined via the ratio of Ba to Sr.
  • the list of substances mentioned is by no means exhaustive. The selection of one of the substances as the storage dielectric depends to a large extent on processing factors during the manufacturing process but also on factors during the use of the semiconductor storage arrangement, for example the ambient temperature.
  • the cutout in the insulation layer is preferably arranged centrally above the source region, as is proposed in a further embodiment of the invention.
  • the second electrodes of the respective memory cells are connected to the common plate by a conductive connection which extends downward through the source region and the semiconductor body.
  • the storage dielectric extends downward through the source region and the semiconductor body to the common plate and the conductor.de ver bond surrounds.
  • the second electrode can also follow between the conductive connection and the storage dielectric O 98/15007
  • a further embodiment of the invention provides for the conductive connection to be insulated from the source region and the semiconductor body by means of an insulation collar, which can consist, for example, of a semiconductor oxide.
  • the common plate which runs below the selection transistors, can be a region of the semiconductor body, this region being doped in order to have sufficient electrical conductivity.
  • a method for producing a semiconductor memory arrangement according to one of the above-mentioned embodiments is the subject of claims 12 to 15.
  • the invention is explained in more detail below in connection with exemplary embodiments with reference to figures. Show it:
  • FIG. 1 shows a first embodiment of a semiconductor memory device according to the invention in cross section
  • FIG. 2 shows a second exemplary embodiment of a semiconductor memory arrangement according to the invention in cross section
  • Fig. 3 shows a semiconductor memory device according to the invention in plan view.
  • Fig. 1 shows a cross section through a section of a semiconductor memory device 1 according to the invention.
  • a memory cell of the semiconductor memory arrangement 1 is shown in the figure.
  • the memory cell has a selection transistor, which has a source region 4 and a drain region 6, which are arranged in a semiconductor body 12.
  • Above the semiconductor body 12 there is an insulation layer 10 in which a gate 8 of the selection transistor is arranged, a thin region of the insulation layer 10 being located between the gate 8 and the semiconductor body 12.
  • the source and drain regions 4, 6 can, for example, consist of regions of the semiconductor body 12 doped complementarily to the conductivity type of the semiconductor body 12, while the gate can be made of polysilicon, for example.
  • Silicon dioxide SiC * 2 or silicon nitride Si3N4, for example, can be used as the material for the insulation layer 10.
  • a common plate 14 is located below the source and drain regions 4, 6 in the semiconductor body 12, it being possible for the common plate 14 to be a doped region of the semiconductor body 12.
  • the recess 26 extends in the insulation layer 10 as far as the source region 4, so that the first electrode 16 is electrically conductively connected to the source region 4.
  • a second recess 29 extends from a second main compartment 30 of the semiconductor body downward through the source region 4 and the semiconductor body 12 to the common plate 14.
  • a storage dielectric 20 is applied over the first electrode 16 and on side surfaces of the second recess 29. over which a second electrode 18 is in turn located.
  • the first electrode 16, the storage dielectric 20 and the second electrode 18 form a storage capacitor in the region of the recess 26 of the insulation layer 10, while in the region of the second recess 29 the storage dielectric 20 insulates the second electrode 18 from the source region 4 and the semiconductor body 12 .
  • the barrier layer is particularly useful when using ferroelectric materials as the storage dielectric 20.
  • the barrier layer can consist, for example, of TiN, W, WTiN or TaN.
  • the second electrode 18 is electrically conductively connected to the common plate 14, an interspace located within the second electrode 18 is filled with a conductive material that forms a conductive connection 24 and improves charge transport from the common plate 14 to the second electrode 18.
  • the conductive connection 24 can, for example, be made of lysilicon exist, a possible material for the production of the two electrodes 16, 18 is platinum.
  • regions of a first main surface 2 of the insulation layer 10 are exposed at the top, so that these regions can be used in particular for wiring the semiconductor memory arrangement 1.
  • the representation of word and bit lines, which are an example of wiring within semiconductor memory arrangements, and of the representation of further wiring are omitted in the example shown.
  • FIG. 2 shows a section of a further exemplary embodiment of a semiconductor memory arrangement 1 in cross section.
  • a memory cell shown in FIG. 2 has a storage capacitor which is arranged on side surfaces of a cutout 26 in an insulation layer 10 above a source region 4 of a selection transistor.
  • a first electrode 16 of the storage capacitor is electrically conductively connected to the source region 4.
  • a storage dielectric 20 is applied over the first electrode 16, over which a second electrode 18 is applied, the storage dielectric 20 isolating the first electrode 16 and the second electrode 18 and the second electrode 18 and the source region 4 from one another.
  • a barrier layer may be located between the first electrode 16 and the source region 4 and between the storage dielectric 20 and the source region 4, which protects the source region 4 from oxidation during the production of such a semiconductor memory arrangement when the storage dielectric 20 is applied.
  • the barrier layer is particularly useful when using ferroelectric materials as the storage dielectric 20.
  • the barrier layer can consist, for example, of TiN, WN, WTiN or TaN.
  • a second cutout 29 extends from a second main surface 30 of a semiconductor body 12 through the source region 4 and the semiconductor body 12 down to a common plate 14. On the side surfaces of the second recess 29, an insulation collar 28 is applied, which extends upwards into a recess formed by the second electrode 18 and covers regions of the second electrode 18.
  • An intermediate space formed within the second electrode 18 and the insulation collar 28 is filled with a conductive material, so that a conductive connection 24 is created.
  • the conductive connection 24 is insulated from the source region 4 and the semiconductor body 12 by the insulation collar 28.
  • the second electrode 18 is connected to the common plate 14 by means of the conductive connection 24.
  • FIG. 3 shows the semiconductor memory arrangement 1 shown in FIG. 1 or FIG. 2 in a top view.
  • the insulation layer 10 is shown, in which there is the rectangular recess 26 in the present example, on the side surfaces of which the first electrode 16 is applied.
  • the dielectric layer 20 is attached to the first electrode 16, and the second electrode 18 is attached to the latter.
  • the space formed within the second electrode 18 is filled by the conductive connection 24.

Landscapes

  • Semiconductor Memories (AREA)
  • Dram (AREA)

Abstract

Mémoire à semiconducteurs présentant une pluralité de transistors de sélection qui sont connectés chacun à une première électrode (16) d'un condensateur de mémorisation. Une deuxième électrode (18) du condensateur de mémorisation est raccordée à une plaque commune (14) placée sous les transistors de sélection dans un corps à semiconducteurs. Le condensateur de mémorisation est placé sur les faces latérales d'un évidement (26) de la couche isolante (10) au-dessus de la zone de source (4). Le diélectrique de mémorisation (20) présente de préférence des propriétés ferroélectriques.
EP97912027A 1996-09-30 1997-09-26 Memoire a semiconducteurs integree avec electrode a plaque enterree Withdrawn EP0931347A1 (fr)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
DE19640215 1996-09-30
DE19640215A DE19640215C1 (de) 1996-09-30 1996-09-30 Integrierte Halbleiterspeicheranordnung mit "Buried-Plate-Elektrode"
PCT/DE1997/002219 WO1998015007A1 (fr) 1996-09-30 1997-09-26 Memoire a semiconducteurs integree avec electrode a plaque enterree

Publications (1)

Publication Number Publication Date
EP0931347A1 true EP0931347A1 (fr) 1999-07-28

Family

ID=7807380

Family Applications (1)

Application Number Title Priority Date Filing Date
EP97912027A Withdrawn EP0931347A1 (fr) 1996-09-30 1997-09-26 Memoire a semiconducteurs integree avec electrode a plaque enterree

Country Status (8)

Country Link
US (1) US6627934B1 (fr)
EP (1) EP0931347A1 (fr)
JP (1) JP3898766B2 (fr)
KR (1) KR100291565B1 (fr)
CN (1) CN1160793C (fr)
DE (1) DE19640215C1 (fr)
TW (1) TW364202B (fr)
WO (1) WO1998015007A1 (fr)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9305929B1 (en) * 2015-02-17 2016-04-05 Micron Technology, Inc. Memory cells
US10134982B2 (en) 2015-07-24 2018-11-20 Micron Technology, Inc. Array of cross point memory cells
US10396145B2 (en) 2017-01-12 2019-08-27 Micron Technology, Inc. Memory cells comprising ferroelectric material and including current leakage paths having different total resistances
US11170834B2 (en) 2019-07-10 2021-11-09 Micron Technology, Inc. Memory cells and methods of forming a capacitor including current leakage paths having different total resistances
CN117337029A (zh) * 2022-06-24 2024-01-02 长鑫存储技术有限公司 一种半导体结构及其形成方法

Family Cites Families (17)

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KR900001836B1 (ko) * 1985-07-02 1990-03-24 마쯔시다덴기산교 가부시기가이샤 반도체기억장치 및 그 제조방법
DE3780840T2 (de) * 1986-03-03 1993-03-25 Fujitsu Ltd Einen rillenkondensator enthaltender dynamischer speicher mit wahlfreiem zugriff.
US4794434A (en) * 1987-07-06 1988-12-27 Motorola, Inc. Trench cell for a dram
JPH0797626B2 (ja) * 1987-10-31 1995-10-18 日本電気株式会社 Ｍｉｓ型半導体記憶装置
JPH01146354A (ja) * 1987-12-02 1989-06-08 Mitsubishi Electric Corp 半導体記憶装置
JPH0262073A (ja) * 1988-08-26 1990-03-01 Mitsubishi Electric Corp 半導体記憶装置
JPH0272663A (ja) * 1988-09-07 1990-03-12 Fujitsu Ltd 半導体記憶装置
US5225698A (en) * 1989-08-12 1993-07-06 Samsung Electronics Co., Inc. Semi-conductor device with stacked trench capacitor
DE3931381A1 (de) * 1989-09-20 1991-03-28 Siemens Ag Halbleiterschichtaufbau mit vergrabener verdrahtungsebene, verfahren fuer dessen herstellung und anwendung der vergrabenen verdrahtungsebene als vergrabene zellplatte fuer drams
JPH0513676A (ja) 1991-07-02 1993-01-22 Toshiba Corp 半導体装置
JP2994110B2 (ja) * 1991-09-09 1999-12-27 株式会社東芝 半導体記憶装置
JP3151684B2 (ja) * 1992-04-24 2001-04-03 株式会社日立製作所 半導体装置及びその製造方法
JPH06216336A (ja) * 1992-10-27 1994-08-05 Sanyo Electric Co Ltd 半導体装置の製造方法
JP3224916B2 (ja) 1993-09-10 2001-11-05 株式会社東芝 半導体装置の製造方法
JPH0786427A (ja) 1993-09-10 1995-03-31 Toshiba Corp 半導体装置およびその製造方法
KR0123751B1 (ko) * 1993-10-07 1997-11-25 김광호 반도체장치 및 그 제조방법
JPH07193141A (ja) * 1993-12-27 1995-07-28 Toshiba Corp 半導体記憶装置

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Also Published As

Publication number Publication date
KR20000036160A (ko) 2000-06-26
US6627934B1 (en) 2003-09-30
CN1231767A (zh) 1999-10-13
KR100291565B1 (ko) 2001-05-15
WO1998015007A1 (fr) 1998-04-09
JP3898766B2 (ja) 2007-03-28
TW364202B (en) 1999-07-11
CN1160793C (zh) 2004-08-04
JP2000503814A (ja) 2000-03-28
DE19640215C1 (de) 1998-02-19

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