Classifications

• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
  • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
  • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
  • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
  • H03H3/00—Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators
  • H03H3/007—Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators for the manufacture of electromechanical resonators or networks
  • H03H3/08—Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators for the manufacture of electromechanical resonators or networks for the manufacture of resonators or networks using surface acoustic waves
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L23/00—Details of semiconductor or other solid state devices
  • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
  • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
  • H01L23/3157—Partial encapsulation or coating
  • H01L23/3171—Partial encapsulation or coating the coating being directly applied to the semiconductor body, e.g. passivation layer
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
  • H01L2924/0001—Technical content checked by a classifier
  • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
  • H01L2924/30—Technical effects
  • H01L2924/301—Electrical effects
  • H01L2924/3025—Electromagnetic shielding

Definitions

• the present invention relates to a method for producing contacts of electrical components suitable for flip-chip mounting according to the preamble of patent claim 1.
• Component system selectively solderable layers with bumps - are provided, so that a number of process steps are required, which are particularly problematic for SAW components, because the likelihood of short circuits is greater because of overlapping flat finger structures.
• the present invention is based on the object of specifying a method in which the production of solderable layers suitable for flip-chip assembly is possible without impairing component structures.
• FIG. 1 shows a schematic illustration of an SAW component produced by the method according to the invention.
• Figure 2 is a schematic partial representation of the component of Figure 1 in supervision.
• an SAW component generally consists of a piezoelectric substrate 1 and conductive structures 3 provided thereon, which can be, for example, electrode fingers of interdigital transducers, resonators or reflectors.
• the electrically conductive structures 3 are covered by a cap 2, which protects the structures against environmental influences, and the component can be used directly with the cover 2 and the substrate 1 as a "housing".
• suitable contacts for the electrical contacting of the conductive structures 3 are now provided for a flip-chip assembly. As can be seen schematically from FIG.
• a window 6 is provided in the cover 2, through which a solderable layer 4 is applied, which is in contact with a pad (not shown) of the electrically conductive structures 3.
• the solderable layer 4 also lies on parts of the cover 2, as can be seen from FIG. 2.
• the solderable layer 4 can be, for example, a chromium / chromium copper / copper / gold layer.
• solderable layers a layer of solderable material can first be used over the entire surface, ie. H. are also vapor-deposited onto the entire cover 2, which is then structured so that individual solderable layers 4 result, each of which is in contact with pads of the electrically conductive structures 3.
• the electrically solderable layers 4 can also be vapor-deposited by means of masks which define the layer dimensions.
• bumps 7 which come into contact with the solderable layers 4 are introduced into the windows 6 and are soldered to the layers 4.
• the component can be mounted in an electrical circuit via these bumps 7.
• the method according to the invention has the advantage that the solderable layers 4 and the bumbs 7 are produced only after the cover 2, which protects the component structures against environmental influences, is produced. Therefore, the device structures can inherently result from the process steps in the manufacture of the solderable layers and the bumps resulting influences are no longer impaired. Another advantage can be seen in the fact that the solderable layers can be produced over a large area and their dimensions can therefore be large compared to that of the pads (not shown).
• the windows 6 in the cover 2 can be designed in such a way that they act as masks for the conductive layers 4 and at the same time are not steamed on their edges.

Landscapes

• Engineering & Computer Science (AREA)
• Physics & Mathematics (AREA)
• Condensed Matter Physics & Semiconductors (AREA)
• General Physics & Mathematics (AREA)
• Computer Hardware Design (AREA)
• Microelectronics & Electronic Packaging (AREA)
• Power Engineering (AREA)
• Manufacturing & Machinery (AREA)
• Acoustics & Sound (AREA)
• Surface Acoustic Wave Elements And Circuit Networks Thereof (AREA)
• Wire Bonding (AREA)

Applications Claiming Priority (3)

Publications (1)

Family

ID=7780957

Family Applications (1)

Country Status (8)

Families Citing this family (19)

Family Cites Families (10)

• 1995
  • 1995-12-21 DE DE19548046A patent/DE19548046C2/de not_active Expired - Lifetime
• 1996
  • 1996-12-16 CA CA002241037A patent/CA2241037A1/en not_active Abandoned
  • 1996-12-16 CN CN96199161A patent/CN1105397C/zh not_active Expired - Lifetime
  • 1996-12-16 KR KR10-1998-0704406A patent/KR100445569B1/ko not_active IP Right Cessation
  • 1996-12-16 WO PCT/DE1996/002412 patent/WO1997023904A1/de not_active Application Discontinuation
  • 1996-12-16 EP EP96946147A patent/EP0868744A1/de not_active Ceased
  • 1996-12-16 JP JP52321297A patent/JP4413278B2/ja not_active Expired - Lifetime
• 1998
  • 1998-06-22 US US09/103,163 patent/US6057222A/en not_active Expired - Lifetime

Non-Patent Citations (1)

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