CN1205800A - 适于倒装法组装的电气元件触极的制作方法 - Google Patents
适于倒装法组装的电气元件触极的制作方法 Download PDFInfo
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- CN1205800A CN1205800A CN96199161A CN96199161A CN1205800A CN 1205800 A CN1205800 A CN 1205800A CN 96199161 A CN96199161 A CN 96199161A CN 96199161 A CN96199161 A CN 96199161A CN 1205800 A CN1205800 A CN 1205800A
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- 238000000034 method Methods 0.000 title claims abstract description 24
- 239000000758 substrate Substances 0.000 claims abstract description 4
- 238000010276 construction Methods 0.000 claims description 7
- 230000008020 evaporation Effects 0.000 claims description 7
- 238000001704 evaporation Methods 0.000 claims description 7
- 239000000463 material Substances 0.000 claims description 3
- 238000003466 welding Methods 0.000 claims description 2
- 238000010897 surface acoustic wave method Methods 0.000 claims 1
- 238000005538 encapsulation Methods 0.000 description 4
- 238000004519 manufacturing process Methods 0.000 description 3
- VYZAMTAEIAYCRO-UHFFFAOYSA-N Chromium Chemical group [Cr] VYZAMTAEIAYCRO-UHFFFAOYSA-N 0.000 description 1
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 229910052804 chromium Inorganic materials 0.000 description 1
- 239000011651 chromium Substances 0.000 description 1
- ZTXONRUJVYXVTJ-UHFFFAOYSA-N chromium copper Chemical compound [Cr][Cu][Cr] ZTXONRUJVYXVTJ-UHFFFAOYSA-N 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000007613 environmental effect Effects 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- 239000011435 rock Substances 0.000 description 1
- 238000007789 sealing Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
- H03H3/00—Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators
- H03H3/007—Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators for the manufacture of electromechanical resonators or networks
- H03H3/08—Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators for the manufacture of electromechanical resonators or networks for the manufacture of resonators or networks using surface acoustic waves
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3157—Partial encapsulation or coating
- H01L23/3171—Partial encapsulation or coating the coating being directly applied to the semiconductor body, e.g. passivation layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/3025—Electromagnetic shielding
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Acoustics & Sound (AREA)
- Surface Acoustic Wave Elements And Circuit Networks Thereof (AREA)
- Piezo-Electric Or Mechanical Vibrators, Or Delay Or Filter Circuits (AREA)
- Wire Bonding (AREA)
Abstract
用于制作适于倒装法组装的OFW元件触极的方法,在OFW元件的基底(1)上设置的导电结构(3)用一个覆盖层(2)封住,在制作完成覆盖层(2)之后,敷上与导电结构(3)的焊盘接触连接的可焊接层(4)。
Description
本发明涉及权利要求1前序部分的、适于倒装法组装的电气元件触极的制作方法。
在较早期的德国专利登记P 444 15 411.9中描述了一种电子元件的封装,该封装具有封住基底上的元件结构的密封罩,其中该罩由一个设置在基底上的覆盖层构成,它在元件结构区域内具有容纳这些元件结构的凹槽。这样的一种封装保护元件结构不受环境影响,因此这样封装的电子元件不需要另外的外壳而可直接投入使用。
随着元件趋于更小型化,要求最小的外壳体积和具有低矮的结构高度。这种要求适用于例如电子元件用于芯片卡比如电话卡或信用卡。具有根据上述较早期的德国专利登记的封装的元件极好地满足了这些要求。它还特别适于,实现在一种适于倒装法组装的结构中。
至今适于倒装法组装的元件安装在一种特别是陶瓷的外壳内。在此在元件系统的连接面(焊盘Pads)处必须有选择地设置具有隆起(Bumps)的可焊接层,于是为此需要一系列工艺步骤,这些步骤特别是对于OFW元件是十分棘手的,因为由于相互重叠的平面指状结构短路的可能性会增大。
本发明的任务在于,提出一种可适于倒装法组装的触极而不妨碍元件结构的制作可焊接层的方法。
该任务在开始时所述的那种方法中根据本发明通过权利要求1特征部分的特征得以解决。
本发明的其它结构在附属要求中说明。
本发明依据一实施例借助附图进一步予以解释。如图所示:
图1根据本发明制作OFW元件的方法的示意图;和
图2根据图1的、元件的部分俯视示意图。
根据图1一个OFW元件通常由一个压电基底1及在其上面设置的导电结构3构成,其中涉及比如叉指式变换器、谐振器或反射器的指状电极。就像在开始所述的较早期的德国专利登录中所描述的,导电结构3被覆盖层2盖住,保护结构不受环境影响,而有覆盖层2和基底1作为“外壳”的元件可以直接投入使用。
根据本发明在此设计适于倒装法组装的触极用于制作与导电结构3的电气接触。如图1所示可清楚看到,覆盖层2上设置了一个窗口6,通过它敷上可焊接层4,它与导电结构3的连接面(焊盘Pad)(未示出)接触。如图2清楚地示出,可焊接层4在此也放在覆盖层2的部分上。可焊接层4可以比如是一个铬/铬铜/铜/金的薄层。
可以根据本发明的一种实施形式来制作可焊接层,首先可以在整个平面上构成一层可焊接材料,即在整个覆盖层2上蒸发此种材料,然后使其这样结构化,使产生各个分别与导电结构3的焊盘相接触的可焊接层4。
根据另一种实施形式电气可焊接层4也可以通过掩模蒸发确定层的尺寸。
制作可焊接层之后,在窗口6中放入与可焊接层4相接触的隆起7,并与层4焊在一起。经这些隆起7可将元件装配在电路内。
根据本发明的方法的优点在于,在敷上保护元件结构防止环境影响的保护覆盖层2之后,再制作可焊接层4和隆起7。因此通过这种方法步骤在制作可焊接层和隆起的过程中使元件结构不受任何损害影响。另一个优点在于,可以大面积制作焊接层,而且它的大小可以大于焊盘(未示出)。
为了避免整个面积所蒸镀的层4的结构化,在覆盖层2中的窗口6可以这样构造,把它用作导电层4的掩模且同时不在它的边缘蒸镀。
Claims (6)
1.用于制作适于倒装法组装的电气元件触极的方法,特别是用声表面波工作的元件(OFW元件),在它的基底(1)上设置的导电结构(3)由一个罩形的覆盖层(2)紧密地封住而不受环境影响,其特征在于,在制作完成覆盖层(2)之后,通过覆盖层(2)内的窗口(6)敷上与导电结构(3)的连接面(焊盘Pads)接触连接的可焊接层(4)。
2.根据权利要求1的方法,其特征在于,首先在整个平面上蒸镀上一层由可焊接的材料构成的层和这样使整个层结构化,使产生各个分别与导电结构(3)的焊盘相接触的可焊接层(4)。
3.根据权利要求1的方法,其特征在于,经掩模蒸镀导电层(4)。
4.根据权利要求1至3之一的方法,其特征在于,导电层(4)的尺寸比导电结构(3)的焊盘尺寸大。
5.根据权利要求1至4之一的方法,其特征在于,在覆盖层(2)中的窗口内放入与可焊接层(4)接触的隆起(7)。
6.根据权利要求1至5之一的方法,其特征在于,在整个平面上蒸镀上可导电层(4),在此覆盖层(2)作为掩模这样来应用,可导电层(4)上的蒸镀层与覆盖层(2)上的那层不连接导通。
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
DE19548046.5 | 1995-12-21 | ||
DE19548046A DE19548046C2 (de) | 1995-12-21 | 1995-12-21 | Verfahren zur Herstellung von für eine Flip-Chip-Montage geeigneten Kontakten von elektrischen Bauelementen |
Publications (2)
Publication Number | Publication Date |
---|---|
CN1205800A true CN1205800A (zh) | 1999-01-20 |
CN1105397C CN1105397C (zh) | 2003-04-09 |
Family
ID=7780957
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN96199161A Expired - Lifetime CN1105397C (zh) | 1995-12-21 | 1996-12-16 | 适于倒装法组装的电气元件触极的制作方法 |
Country Status (8)
Country | Link |
---|---|
US (1) | US6057222A (zh) |
EP (1) | EP0868744A1 (zh) |
JP (1) | JP4413278B2 (zh) |
KR (1) | KR100445569B1 (zh) |
CN (1) | CN1105397C (zh) |
CA (1) | CA2241037A1 (zh) |
DE (1) | DE19548046C2 (zh) |
WO (1) | WO1997023904A1 (zh) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN101286456B (zh) * | 2007-04-13 | 2012-03-21 | 新光电气工业株式会社 | 布线板制造方法、半导体器件制造方法以及布线板 |
Families Citing this family (18)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE19806550B4 (de) * | 1998-02-17 | 2004-07-22 | Epcos Ag | Elektronisches Bauelement, insbesondere mit akustischen Oberflächenwellen arbeitendes Bauelement - OFW-Bauelement |
DE19806818C1 (de) * | 1998-02-18 | 1999-11-04 | Siemens Matsushita Components | Verfahren zur Herstellung eines elektronischen Bauelements, insbesondere eines mit akustischen Oberflächenwllen arbeitenden OFW-Bauelements |
DE19822794C1 (de) | 1998-05-20 | 2000-03-09 | Siemens Matsushita Components | Mehrfachnutzen für elektronische Bauelemente, insbesondere akustische Oberflächenwellen-Bauelemente |
KR100687548B1 (ko) * | 1999-01-27 | 2007-02-27 | 신꼬오덴기 고교 가부시키가이샤 | 반도체 웨이퍼 제조 방법, 반도체 장치 제조 방법 및 칩 사이즈의 반도체 웨이퍼 패키지 제조 방법 |
US6747298B2 (en) | 2001-07-23 | 2004-06-08 | Cree, Inc. | Collets for bonding of light emitting diodes having shaped substrates |
US6888167B2 (en) * | 2001-07-23 | 2005-05-03 | Cree, Inc. | Flip-chip bonding of light emitting devices and light emitting devices suitable for flip-chip bonding |
DE10142542A1 (de) * | 2001-08-30 | 2003-03-27 | Infineon Technologies Ag | Anordnung eines Halbleiterchips in einem Gehäuse, Chipkarte und Chipmodul |
DE10302298A1 (de) | 2003-01-22 | 2004-08-05 | Henkel Kgaa | Hitzehärtbare, thermisch expandierbare Zusammensetzung mit hohem Expansionsgrad |
US6992400B2 (en) * | 2004-01-30 | 2006-01-31 | Nokia Corporation | Encapsulated electronics device with improved heat dissipation |
US7608789B2 (en) * | 2004-08-12 | 2009-10-27 | Epcos Ag | Component arrangement provided with a carrier substrate |
DE102005008512B4 (de) | 2005-02-24 | 2016-06-23 | Epcos Ag | Elektrisches Modul mit einem MEMS-Mikrofon |
DE102005008514B4 (de) * | 2005-02-24 | 2019-05-16 | Tdk Corporation | Mikrofonmembran und Mikrofon mit der Mikrofonmembran |
DE102005008511B4 (de) * | 2005-02-24 | 2019-09-12 | Tdk Corporation | MEMS-Mikrofon |
JP4585419B2 (ja) | 2005-10-04 | 2010-11-24 | 富士通メディアデバイス株式会社 | 弾性表面波デバイスおよびその製造方法 |
DE102005053765B4 (de) * | 2005-11-10 | 2016-04-14 | Epcos Ag | MEMS-Package und Verfahren zur Herstellung |
DE102005053767B4 (de) * | 2005-11-10 | 2014-10-30 | Epcos Ag | MEMS-Mikrofon, Verfahren zur Herstellung und Verfahren zum Einbau |
DE102013106353B4 (de) * | 2013-06-18 | 2018-06-28 | Tdk Corporation | Verfahren zum Aufbringen einer strukturierten Beschichtung auf ein Bauelement |
US10431533B2 (en) * | 2014-10-31 | 2019-10-01 | Ati Technologies Ulc | Circuit board with constrained solder interconnect pads |
Family Cites Families (11)
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JPS59172756A (ja) * | 1983-03-22 | 1984-09-29 | Nec Corp | 半導体装置 |
GB2171850B (en) * | 1985-02-22 | 1988-05-18 | Racal Mesl Ltd | Mounting surface acoustic wave components |
JPS62173814A (ja) * | 1986-01-28 | 1987-07-30 | Alps Electric Co Ltd | 弾性表面波素子搭載ユニツト |
JP2563652B2 (ja) * | 1990-07-17 | 1996-12-11 | 株式会社東芝 | 半導体装置及びその製造方法 |
EP0475139A3 (en) * | 1990-09-04 | 1992-03-25 | Motorola, Inc. | Method and apparatus for saw device passivation |
JPH0590872A (ja) * | 1991-09-27 | 1993-04-09 | Sumitomo Electric Ind Ltd | 表面弾性波素子 |
JP2718854B2 (ja) * | 1992-06-10 | 1998-02-25 | 株式会社東芝 | 半導体装置 |
EP0590780B1 (en) * | 1992-08-28 | 1997-06-25 | Dow Corning Corporation | Method for producing an integrated circuit with hermetic protection based on a ceramic layer |
DE4302171A1 (de) * | 1993-01-22 | 1994-07-28 | Be & We Beschaeftigungs Und We | Verfahren zur Herstellung von Oberflächenwellenbauelementen |
EP0645807B1 (en) * | 1993-04-08 | 2003-06-25 | Citizen Watch Co. Ltd. | Semiconductor device |
WO1995030276A1 (de) * | 1994-05-02 | 1995-11-09 | Siemens Matsushita Components Gmbh & Co. Kg | Verkapselung für elektronische bauelemente |
-
1995
- 1995-12-21 DE DE19548046A patent/DE19548046C2/de not_active Expired - Lifetime
-
1996
- 1996-12-16 WO PCT/DE1996/002412 patent/WO1997023904A1/de not_active Application Discontinuation
- 1996-12-16 EP EP96946147A patent/EP0868744A1/de not_active Ceased
- 1996-12-16 CA CA002241037A patent/CA2241037A1/en not_active Abandoned
- 1996-12-16 KR KR10-1998-0704406A patent/KR100445569B1/ko not_active IP Right Cessation
- 1996-12-16 JP JP52321297A patent/JP4413278B2/ja not_active Expired - Lifetime
- 1996-12-16 CN CN96199161A patent/CN1105397C/zh not_active Expired - Lifetime
-
1998
- 1998-06-22 US US09/103,163 patent/US6057222A/en not_active Expired - Lifetime
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN101286456B (zh) * | 2007-04-13 | 2012-03-21 | 新光电气工业株式会社 | 布线板制造方法、半导体器件制造方法以及布线板 |
Also Published As
Publication number | Publication date |
---|---|
KR19990072096A (ko) | 1999-09-27 |
JP4413278B2 (ja) | 2010-02-10 |
US6057222A (en) | 2000-05-02 |
KR100445569B1 (ko) | 2004-10-15 |
JP2000502238A (ja) | 2000-02-22 |
DE19548046A1 (de) | 1997-06-26 |
WO1997023904A1 (de) | 1997-07-03 |
CA2241037A1 (en) | 1997-07-03 |
DE19548046C2 (de) | 1998-01-15 |
EP0868744A1 (de) | 1998-10-07 |
CN1105397C (zh) | 2003-04-09 |
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