EP0868744A1 - Process for producing contacts on electrical components suitable for a flip-chip assembly - Google Patents

Process for producing contacts on electrical components suitable for a flip-chip assembly

Info

Publication number
EP0868744A1
EP0868744A1 EP96946147A EP96946147A EP0868744A1 EP 0868744 A1 EP0868744 A1 EP 0868744A1 EP 96946147 A EP96946147 A EP 96946147A EP 96946147 A EP96946147 A EP 96946147A EP 0868744 A1 EP0868744 A1 EP 0868744A1
Authority
EP
European Patent Office
Prior art keywords
cover
layers
solderable
pads
electrically conductive
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
EP96946147A
Other languages
German (de)
French (fr)
Inventor
Wolfgang Pahl
Alois Stelzl
Hans Krüger
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
TDK Electronics AG
Original Assignee
Siemens Matsushita Components GmbH and Co KG
Epcos AG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Siemens Matsushita Components GmbH and Co KG, Epcos AG filed Critical Siemens Matsushita Components GmbH and Co KG
Publication of EP0868744A1 publication Critical patent/EP0868744A1/en
Ceased legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H3/00—Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators
    • H03H3/007—Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators for the manufacture of electromechanical resonators or networks
    • H03H3/08—Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators for the manufacture of electromechanical resonators or networks for the manufacture of resonators or networks using surface acoustic waves
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3157—Partial encapsulation or coating
    • H01L23/3171—Partial encapsulation or coating the coating being directly applied to the semiconductor body, e.g. passivation layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3025—Electromagnetic shielding

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Acoustics & Sound (AREA)
  • Surface Acoustic Wave Elements And Circuit Networks Thereof (AREA)
  • Wire Bonding (AREA)

Abstract

In a process for producing contacts on SW components suitable for a flip-chip assembly, in which electrically conductive structures (3) on a substrate (1) are encapsulated by a cover (2), after the cover (2) has been produced, solderable layers (4) in contact with pads of the electrically conductive structures (3) are applied.

Description

Beschreibungdescription
Verfahren zur Herstellung von für eine Flip- Chip-Montage ge¬ eigneten Kontakten von elektrischen BauelementenMethod for producing contacts of electrical components suitable for flip-chip assembly
Die vorliegende Erfindung betrifft ein Verfahren zur Herstel¬ lung von für eine Flip- Chip-Montage geeigneten Kontakten von elektrischen Bauelementen nach dem Oberbegriff des Patentan¬ spruches 1.The present invention relates to a method for producing contacts of electrical components suitable for flip-chip mounting according to the preamble of patent claim 1.
In der älteren deutschen Patentanmeldung P 444 15 411.9 ist eine Verkapselung für elektronische Bauelemente mit einer Bauelemente-Strukturen auf einem Substrat verschließenden Kappe beschrieben, bei der die Kappe durch eine auf dem Substrat vorgesehene Abdeckung gebildet ist, welche in Berei¬ chen der Bauelemente-Strukturen diese aufnehmende Ausnehmun¬ gen besitzt. Eine derartige Verkapselung schützt die Bauele¬ mente-Strukturen gegen Umwelteinflüsse, so daß derartig ver¬ kapselte elektronische Bauelemente ohne ein weiteres Gehäuse direkt weiterverwendbar sind.In the older German patent application P 444 15 411.9, an encapsulation for electronic components is described with a cap closing the component structures on a substrate, in which the cap is formed by a cover provided on the substrate, which cover is in areas of the component structures has these receiving recesses. Such encapsulation protects the component structures against environmental influences, so that encapsulated electronic components of this type can be used directly without an additional housing.
Mit zunehmender Miniaturisierung werden Bauelemente ange¬ strebt, die ein minimales Gehäusevolumen beanspruchen und eine niedrige Bauhöhe besitzen. Derartige Anforderungen stel- len sich beispielsweise bei der Anwendung von elektronischenWith increasing miniaturization, components are striven for that require a minimal housing volume and have a low overall height. Such requirements arise, for example, when using electronic ones
Bauelementen in Chipkarten, wie beispielsweise Telefonkarten oder Kreditkarten. Bauelemente mit einer Verkapselung nach der oben genannten älteren deutschen Patentanmeldung erfüllen diese Anforderungen optimal. Dies gilt insbesondere dann, wenn sie in einer für eine Flip- Chip-Montage geeigneten Aus¬ gestaltung realisiert sind.Components in chip cards, such as telephone cards or credit cards. Components with an encapsulation according to the older German patent application mentioned above optimally meet these requirements. This applies in particular if they are implemented in a configuration suitable for a flip-chip assembly.
Bisher werden für eine Flip- Chip-Montage geeignete Bauele¬ mente in einem Gehäuse, insbesondere einem Keramikgehäuse, montiert. Dabei müssen an den Anschlußflächen - Pads - desSo far, suitable components for a flip-chip assembly have been mounted in a housing, in particular a ceramic housing. The pads - pads - des
Bauelementesystems selektiv lötfähige Schichten mit Höckern - Bumps - vorgesehen werden, so daß dazu eine Reihe von Prozeß- schritten erforderlich sind, die insbesondere für OFW-Bauele- mente sehr problematisch sind, weil wegen sich überlappender flächiger Fingerstrukturen die Wahrscheinlichkeit von Kurz¬ schlüssen größer wird.Component system selectively solderable layers with bumps - are provided, so that a number of process steps are required, which are particularly problematic for SAW components, because the likelihood of short circuits is greater because of overlapping flat finger structures.
Der vorliegenden Erfindung liegt die Aufgabe zugrunde, ein Verfahren anzugeben, bei dem die Herstellung von lötfähigen Schichten für eine Flip- Chip-Montage geeignete Kontakte ohne Beeinträchtigung von Bauelemente-Strukturen möglich ist.The present invention is based on the object of specifying a method in which the production of solderable layers suitable for flip-chip assembly is possible without impairing component structures.
Diese Aufgabe wird bei einem Verfahren der eingangs genannten Art erfindungsgemäß durch die Merkmale des kennzeichnenden Teils des Patentanspruches 1 gelöst.This object is achieved according to the invention in a method of the type mentioned at the outset by the features of the characterizing part of patent claim 1.
Weiterbildungen der Erfindungen sind Gegenstand von Unteran¬ sprüchen.Further developments of the inventions are the subject of subclaims.
Die Erfindung wird nachfolgend anhand eines Ausführungsbei¬ spiels gemäß den Figuren der Zeichnung näher erläutert. Es zeigt:The invention is explained in more detail below using an exemplary embodiment according to the figures of the drawing. It shows:
Figur 1 eine schematische Darstellung eines nach dem erfin¬ dungsgemäßen Verfahren hergestellten OFW-Bauelementes; undFIG. 1 shows a schematic illustration of an SAW component produced by the method according to the invention; and
Figur 2 eine schematische Teildarstellung des Bauelementes nach Figur 1 in Aufsicht.Figure 2 is a schematic partial representation of the component of Figure 1 in supervision.
Gemäß Figur 1 besteht ein OFW-Bauelement generell aus einem piezoelektrischen Substrat 1 und darauf vorgesehenen leiten- den Strukturen 3, bei es sich beispielsweise um Elektroden¬ finger von Interdigitalwandlern, Resonatoren oder Reflektoren handeln kann. Wie in der eingangs genannten älteren deutschen Patentanmeldung beschrieben, sind die elektrisch leitenden Strukturen 3 durch eine Kappe 2 abgedeckt, welche die Strukturen gegen Umwelteinflüsse schützt und das Bauelement ist mit der Abdeckung 2 und dem Substrat 1 als "Gehäuse" di¬ rekt weiterverwendbar. Erfindungsgemäß ist nun vorgesehen für eine Flip-Chip-Montage geeignete Kontakte für die elektrische Kontaktierung der lei¬ tenden Strukturen 3 herzustellen. Wie aus Figur 1 schematisch ersichtlich, ist in der Abdeckung 2 ein Fenster 6 vorgesehen, durch das hindurch eine lötfähige Schicht 4 aufgebracht wird, welche mit einer (nicht dargestellten) Anschlußfläche - Pad - der elektrisch leitenden Strukturen 3 in Kontakt steht. Die lötfähige Schicht 4 liegt dabei auch auf Teilen der Abdeckung 2 auf, wie dies aus Figur 2 ersichtlich ist. Bei der lötfähi¬ gen Schicht 4 kann es sich beispielsweise um eine Chrom/Chromkupfer/Kupfer/Gold-Schicht handeln.According to FIG. 1, an SAW component generally consists of a piezoelectric substrate 1 and conductive structures 3 provided thereon, which can be, for example, electrode fingers of interdigital transducers, resonators or reflectors. As described in the earlier German patent application mentioned at the outset, the electrically conductive structures 3 are covered by a cap 2, which protects the structures against environmental influences, and the component can be used directly with the cover 2 and the substrate 1 as a "housing". According to the invention, suitable contacts for the electrical contacting of the conductive structures 3 are now provided for a flip-chip assembly. As can be seen schematically from FIG. 1, a window 6 is provided in the cover 2, through which a solderable layer 4 is applied, which is in contact with a pad (not shown) of the electrically conductive structures 3. The solderable layer 4 also lies on parts of the cover 2, as can be seen from FIG. 2. The solderable layer 4 can be, for example, a chromium / chromium copper / copper / gold layer.
Zur Herstellung von lötfähigen Schichten kann gemäß einer Ausführungsform der Erfindung zunächst eine Schicht aus löt- fähigem Material ganzflächig, d. h. auch auf die die gesamte Abdeckung 2 aufgedampft werden, die sodann so strukturiert wird, daß sich einzelne lötfähige Schichten 4 ergeben, die jeweils mit Pads der elektrisch leitenden Strukturen 3 in Kontakt stehen.To produce solderable layers, according to one embodiment of the invention, a layer of solderable material can first be used over the entire surface, ie. H. are also vapor-deposited onto the entire cover 2, which is then structured so that individual solderable layers 4 result, each of which is in contact with pads of the electrically conductive structures 3.
Gemäß einer anderen Ausführungsform können die elektrisch lötfähigen Schichten 4 auch durch Masken aufgedampft werden, welche die Schichtabmessungen festlegen.According to another embodiment, the electrically solderable layers 4 can also be vapor-deposited by means of masks which define the layer dimensions.
Nach der Herstellung der lötfähigen Schichten werden in die Fenster 6 mit den lötfähigen Schichten 4 in Kontakt tretende Bumps 7 eingebracht und mit den Schichten 4 verlötet. Über diese Bumps 7 kann das Bauelement in einer elektrischen Schaltung montiert werden.After the solderable layers have been produced, bumps 7 which come into contact with the solderable layers 4 are introduced into the windows 6 and are soldered to the layers 4. The component can be mounted in an electrical circuit via these bumps 7.
Das erfindungsgemäße Verfahren bietet den Vorteil, daß die lötfähigen Schichten 4 und die Bumbs 7 erst nach der Aufbrin¬ gung der die Bauelementestrukturen gegen Umwelteinflüsse schützenden Abdeckung 2 hergestellt werden. Daher können die Bauelementestrukturen durch sich aus den Vefahrensschritten bei der Herstellung der lötfähigen Schichten und der Bumps ergebenden Einflüsse nicht mehr beeinträchtigt werden. Ein weiterer Vorteil ist darin zu sehen, daß die lötfähigen Schichten großflächig hergestellt werden können und ihre Ab¬ messungen daher groß gegen die der (nicht dargestellten) Pads sein können.The method according to the invention has the advantage that the solderable layers 4 and the bumbs 7 are produced only after the cover 2, which protects the component structures against environmental influences, is produced. Therefore, the device structures can inherently result from the process steps in the manufacture of the solderable layers and the bumps resulting influences are no longer impaired. Another advantage can be seen in the fact that the solderable layers can be produced over a large area and their dimensions can therefore be large compared to that of the pads (not shown).
Um die Strukturierung einer ganzflächig aufgedampften Schicht 4 zu vermeiden, können die Fenster 6 in der Abdeckung 2 so gestaltet sein, daß sie als Masken für die leitfähige Schich- ten 4 wirken und gleichzeitig an ihren Rändern nicht bedampft werden. In order to avoid the structuring of a layer 4 which has been vapor-deposited over the entire surface, the windows 6 in the cover 2 can be designed in such a way that they act as masks for the conductive layers 4 and at the same time are not steamed on their edges.

Claims

Patentansprüche claims
1. Verfahren zur Herstellung von für eine Flip- Chip-Montage geeigneten Kontakten von elektrischen Bauelementen, insbeson- dere von mit akustischen Oberflächenwellen arbeitenden Bau¬ elementen - OFW-Bauelemente - , bei denen auf einem Substrat1. Method for producing contacts suitable for a flip-chip assembly of electrical components, in particular components working with acoustic surface waves - SAW components - in which on a substrate
(1) vorgesehene elektrisch leitende Strukturen (3) durch eine kappenförmige Abdeckung (2) dicht gegen Umwelteinflüsse ver¬ kapselt sind, dadurch gekennzeichnet , daß nach der Herstellung der Abdeckung (2) lötfähige Schichten (4) aufgebracht werden, die durch Fenster (6) in der Abdeckung(1) provided electrically conductive structures (3) are encapsulated tightly against environmental influences by a cap-shaped cover (2), characterized in that after the cover (2) has been produced, solderable layers (4) are applied, which through windows (6 ) in the cover
(2) hindurch mit Anschlußflächen - Pads - der elektrisch lei¬ tenden Strukturen (3) in Kontakt stehen.(2) are in contact with pads - pads - of the electrically conductive structures (3).
2. Verfahren nach Anspruch 1, dadurch gekennzeich¬ net , daß zunächst eine Schicht aus lötfähigem Material ganzflächig aufgedampft wird und daß die ganzflächige Schicht so strukturiert wird, daß sich einzelne lötfähige Schichten (4) ergeben, die jeweils mit Pads der elektrisch leitenden Strukturen (3) in Kontakt stehen.2. The method according to claim 1, characterized gekennzeich¬ net that first a layer of solderable material is evaporated over the entire surface and that the entire surface layer is structured so that individual solderable layers (4) result, each with pads of the electrically conductive structures ( 3) are in contact.
3. Verfahren nach Anspruch 1, dadurch gekennzeich¬ net , daß elektrisch leitfähige Schichten (4) durch Masken aufgedampft werden.3. The method according to claim 1, characterized gekennzeich¬ net that electrically conductive layers (4) are deposited by masks.
4. Verfahren nach einem der Ansprüche 1 bis 3, dadurch gekennzeichnet , daß die Abmessungen der leitfähigen Schichten (4) groß gegen die Abmessungen der Pads der leiten¬ den Strukturen (3) sind.4. The method according to any one of claims 1 to 3, characterized in that the dimensions of the conductive layers (4) are large compared to the dimensions of the pads of the conductive structures (3).
5. Verfahren nach einem der Ansprüche 1 bis 4, dadurch gekennzeichnet , daß in die Fenster in der Abdeckung (2) mit den lötfähigen Schichten (4) in Kontakt tretende Bumps (7) eingebracht werden.5. The method according to any one of claims 1 to 4, characterized in that in the window in the cover (2) with the solderable layers (4) contacting bumps (7) are introduced.
6. Verfahren nach einem der Ansprüche 1 bis 5, dadurch gekennzeichnet , daß leitfähige Schichten (4) ganzflächig aufgedampft wird, wobei die Abdeckung (2) derart als Maske verwendet wird, daß die aufgedampfte Schicht auf den leitfähigen Schichten (4) mit jener auf der Abdeckung (2) nicht leitend verbunden ist. 6. The method according to any one of claims 1 to 5, characterized in that conductive layers (4) are evaporated over the entire surface, the cover (2) being used as a mask such that the evaporated layer on the conductive layers (4) is not conductively connected to that on the cover (2).
EP96946147A 1995-12-21 1996-12-16 Process for producing contacts on electrical components suitable for a flip-chip assembly Ceased EP0868744A1 (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
DE19548046A DE19548046C2 (en) 1995-12-21 1995-12-21 Method for producing contacts of electrical components suitable for flip-chip assembly
DE19548046 1995-12-21
PCT/DE1996/002412 WO1997023904A1 (en) 1995-12-21 1996-12-16 Process for producing contacts on electrical components suitable for a flip-chip assembly

Publications (1)

Publication Number Publication Date
EP0868744A1 true EP0868744A1 (en) 1998-10-07

Family

ID=7780957

Family Applications (1)

Application Number Title Priority Date Filing Date
EP96946147A Ceased EP0868744A1 (en) 1995-12-21 1996-12-16 Process for producing contacts on electrical components suitable for a flip-chip assembly

Country Status (8)

Country Link
US (1) US6057222A (en)
EP (1) EP0868744A1 (en)
JP (1) JP4413278B2 (en)
KR (1) KR100445569B1 (en)
CN (1) CN1105397C (en)
CA (1) CA2241037A1 (en)
DE (1) DE19548046C2 (en)
WO (1) WO1997023904A1 (en)

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DE19806550B4 (en) 1998-02-17 2004-07-22 Epcos Ag Electronic component, in particular component working with surface acoustic waves - SAW component
DE19806818C1 (en) * 1998-02-18 1999-11-04 Siemens Matsushita Components Method for producing an electronic component, in particular an SAW component working with acoustic surface waves
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KR100687548B1 (en) * 1999-01-27 2007-02-27 신꼬오덴기 고교 가부시키가이샤 Semiconductor wafer and semiconductor device provided with columnar electrodes and methods of producing the wafer and device
US6888167B2 (en) * 2001-07-23 2005-05-03 Cree, Inc. Flip-chip bonding of light emitting devices and light emitting devices suitable for flip-chip bonding
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US6992400B2 (en) * 2004-01-30 2006-01-31 Nokia Corporation Encapsulated electronics device with improved heat dissipation
US7608789B2 (en) * 2004-08-12 2009-10-27 Epcos Ag Component arrangement provided with a carrier substrate
DE102005008512B4 (en) 2005-02-24 2016-06-23 Epcos Ag Electrical module with a MEMS microphone
DE102005008511B4 (en) * 2005-02-24 2019-09-12 Tdk Corporation MEMS microphone
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US10431533B2 (en) * 2014-10-31 2019-10-01 Ati Technologies Ulc Circuit board with constrained solder interconnect pads

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Also Published As

Publication number Publication date
CA2241037A1 (en) 1997-07-03
DE19548046A1 (en) 1997-06-26
KR100445569B1 (en) 2004-10-15
JP2000502238A (en) 2000-02-22
CN1105397C (en) 2003-04-09
CN1205800A (en) 1999-01-20
KR19990072096A (en) 1999-09-27
DE19548046C2 (en) 1998-01-15
US6057222A (en) 2000-05-02
JP4413278B2 (en) 2010-02-10
WO1997023904A1 (en) 1997-07-03

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